aboutsummaryrefslogtreecommitdiff
path: root/llvm/include/llvm/CodeGen/TargetSchedule.h
diff options
context:
space:
mode:
Diffstat (limited to 'llvm/include/llvm/CodeGen/TargetSchedule.h')
-rw-r--r--llvm/include/llvm/CodeGen/TargetSchedule.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/include/llvm/CodeGen/TargetSchedule.h b/llvm/include/llvm/CodeGen/TargetSchedule.h
index bfab9cb92a38..bfe4234abf8e 100644
--- a/llvm/include/llvm/CodeGen/TargetSchedule.h
+++ b/llvm/include/llvm/CodeGen/TargetSchedule.h
@@ -46,7 +46,7 @@ class TargetSchedModel {
unsigned computeInstrLatency(const MCSchedClassDesc &SCDesc) const;
public:
- TargetSchedModel() : SchedModel(MCSchedModel::GetDefaultSchedModel()) {}
+ TargetSchedModel() : SchedModel(MCSchedModel::Default) {}
/// Initialize the machine model for instruction scheduling.
///
@@ -90,7 +90,7 @@ public:
bool hasInstrSchedModelOrItineraries() const {
return hasInstrSchedModel() || hasInstrItineraries();
}
- bool enableIntervals() const { return SchedModel.EnableIntervals; }
+ bool enableIntervals() const;
/// Identify the processor corresponding to the current subtarget.
unsigned getProcessorID() const { return SchedModel.getProcessorID(); }