diff options
Diffstat (limited to 'llvm/lib/CodeGen/PeepholeOptimizer.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/PeepholeOptimizer.cpp | 20 |
1 files changed, 9 insertions, 11 deletions
diff --git a/llvm/lib/CodeGen/PeepholeOptimizer.cpp b/llvm/lib/CodeGen/PeepholeOptimizer.cpp index 31e37c4cd7e3..c3458be0f883 100644 --- a/llvm/lib/CodeGen/PeepholeOptimizer.cpp +++ b/llvm/lib/CodeGen/PeepholeOptimizer.cpp @@ -66,7 +66,6 @@ //===----------------------------------------------------------------------===// #include "llvm/ADT/DenseMap.h" -#include "llvm/ADT/Optional.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallSet.h" #include "llvm/ADT/SmallVector.h" @@ -273,11 +272,11 @@ namespace { : MI(MI), CommutePair(std::make_pair(Idx1, Idx2)) {} MachineInstr *getMI() const { return MI; } - Optional<IndexPair> getCommutePair() const { return CommutePair; } + std::optional<IndexPair> getCommutePair() const { return CommutePair; } private: MachineInstr *MI; - Optional<IndexPair> CommutePair; + std::optional<IndexPair> CommutePair; }; /// Helper class to hold a reply for ValueTracker queries. @@ -696,7 +695,7 @@ bool PeepholeOptimizer::findNextSource(RegSubRegPair RegSubReg, do { CurSrcPair = SrcToLook.pop_back_val(); // As explained above, do not handle physical registers - if (Register::isPhysicalRegister(CurSrcPair.Reg)) + if (CurSrcPair.Reg.isPhysical()) return false; ValueTracker ValTracker(CurSrcPair.Reg, CurSrcPair.SubReg, *MRI, TII); @@ -744,7 +743,7 @@ bool PeepholeOptimizer::findNextSource(RegSubRegPair RegSubReg, // constraints to the register allocator. Moreover, if we want to extend // the live-range of a physical register, unlike SSA virtual register, // we will have to check that they aren't redefine before the related use. - if (Register::isPhysicalRegister(CurSrcPair.Reg)) + if (CurSrcPair.Reg.isPhysical()) return false; // Keep following the chain if the value isn't any better yet. @@ -1191,7 +1190,7 @@ bool PeepholeOptimizer::optimizeCoalescableCopy(MachineInstr &MI) { "Coalescer can understand multiple defs?!"); const MachineOperand &MODef = MI.getOperand(0); // Do not rewrite physical definitions. - if (Register::isPhysicalRegister(MODef.getReg())) + if (MODef.getReg().isPhysical()) return false; bool Changed = false; @@ -1242,8 +1241,7 @@ bool PeepholeOptimizer::optimizeCoalescableCopy(MachineInstr &MI) { MachineInstr & PeepholeOptimizer::rewriteSource(MachineInstr &CopyLike, RegSubRegPair Def, RewriteMapTy &RewriteMap) { - assert(!Register::isPhysicalRegister(Def.Reg) && - "We do not rewrite physical registers"); + assert(!Def.Reg.isPhysical() && "We do not rewrite physical registers"); // Find the new source to use in the COPY rewrite. RegSubRegPair NewSrc = getNewSource(MRI, TII, Def, RewriteMap); @@ -1301,7 +1299,7 @@ bool PeepholeOptimizer::optimizeUncoalescableCopy( while (CpyRewriter.getNextRewritableSource(Src, Def)) { // If a physical register is here, this is probably for a good reason. // Do not rewrite that. - if (Register::isPhysicalRegister(Def.Reg)) + if (Def.Reg.isPhysical()) return false; // If we do not know how to rewrite this definition, there is no point @@ -1460,7 +1458,7 @@ bool PeepholeOptimizer::foldRedundantNAPhysCopy( Register DstReg = MI.getOperand(0).getReg(); Register SrcReg = MI.getOperand(1).getReg(); - if (isNAPhysCopy(SrcReg) && Register::isVirtualRegister(DstReg)) { + if (isNAPhysCopy(SrcReg) && DstReg.isVirtual()) { // %vreg = COPY $physreg // Avoid using a datastructure which can track multiple live non-allocatable // phys->virt copies since LLVM doesn't seem to do this. @@ -2110,7 +2108,7 @@ ValueTrackerResult ValueTracker::getNextSource() { // If we can still move up in the use-def chain, move to the next // definition. - if (!Register::isPhysicalRegister(Reg) && OneRegSrc) { + if (!Reg.isPhysical() && OneRegSrc) { MachineRegisterInfo::def_iterator DI = MRI.def_begin(Reg); if (DI != MRI.def_end()) { Def = DI->getParent(); |