diff options
Diffstat (limited to 'llvm/lib/CodeGen/RegisterClassInfo.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/RegisterClassInfo.cpp | 19 |
1 files changed, 16 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/RegisterClassInfo.cpp b/llvm/lib/CodeGen/RegisterClassInfo.cpp index 65a65b9cae95..374fcc9a6014 100644 --- a/llvm/lib/CodeGen/RegisterClassInfo.cpp +++ b/llvm/lib/CodeGen/RegisterClassInfo.cpp @@ -19,7 +19,6 @@ #include "llvm/ADT/SmallVector.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/CodeGen/TargetFrameLowering.h" #include "llvm/CodeGen/TargetRegisterInfo.h" #include "llvm/CodeGen/TargetSubtargetInfo.h" #include "llvm/MC/MCRegisterInfo.h" @@ -44,9 +43,11 @@ void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) { bool Update = false; MF = &mf; + auto &STI = MF->getSubtarget(); + // Allocate new array the first time we see a new target. - if (MF->getSubtarget().getRegisterInfo() != TRI) { - TRI = MF->getSubtarget().getRegisterInfo(); + if (STI.getRegisterInfo() != TRI) { + TRI = STI.getRegisterInfo(); RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); Update = true; } @@ -68,6 +69,18 @@ void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) { } CalleeSavedRegs = CSR; + // Even if CSR list is same, we could have had a different allocation order + // if ignoreCSRForAllocationOrder is evaluated differently. + BitVector CSRHintsForAllocOrder(TRI->getNumRegs()); + for (const MCPhysReg *I = CSR; *I; ++I) + for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) + CSRHintsForAllocOrder[*AI] = STI.ignoreCSRForAllocationOrder(mf, *AI); + if (IgnoreCSRForAllocOrder.size() != CSRHintsForAllocOrder.size() || + IgnoreCSRForAllocOrder != CSRHintsForAllocOrder) { + Update = true; + IgnoreCSRForAllocOrder = CSRHintsForAllocOrder; + } + RegCosts = TRI->getRegisterCosts(*MF); // Different reserved registers? |