diff options
Diffstat (limited to 'llvm/lib/Support/X86TargetParser.cpp')
| -rw-r--r-- | llvm/lib/Support/X86TargetParser.cpp | 82 |
1 files changed, 65 insertions, 17 deletions
diff --git a/llvm/lib/Support/X86TargetParser.cpp b/llvm/lib/Support/X86TargetParser.cpp index c9530659caad..ab49ac548f89 100644 --- a/llvm/lib/Support/X86TargetParser.cpp +++ b/llvm/lib/Support/X86TargetParser.cpp @@ -11,7 +11,9 @@ //===----------------------------------------------------------------------===// #include "llvm/Support/X86TargetParser.h" +#include "llvm/ADT/StringSwitch.h" #include "llvm/ADT/Triple.h" +#include <numeric> using namespace llvm; using namespace llvm::X86; @@ -137,8 +139,8 @@ constexpr FeatureBitset FeaturesNocona = // Basic 64-bit capable CPU. constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | Feature64BIT; constexpr FeatureBitset FeaturesX86_64_V2 = FeaturesX86_64 | FeatureSAHF | - FeaturePOPCNT | FeatureSSE4_2 | - FeatureCMPXCHG16B; + FeaturePOPCNT | FeatureCRC32 | + FeatureSSE4_2 | FeatureCMPXCHG16B; constexpr FeatureBitset FeaturesX86_64_V3 = FeaturesX86_64_V2 | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureF16C | FeatureFMA | FeatureLZCNT | FeatureMOVBE | FeatureXSAVE; @@ -151,7 +153,7 @@ constexpr FeatureBitset FeaturesCore2 = FeaturesNocona | FeatureSAHF | FeatureSSSE3; constexpr FeatureBitset FeaturesPenryn = FeaturesCore2 | FeatureSSE4_1; constexpr FeatureBitset FeaturesNehalem = - FeaturesPenryn | FeaturePOPCNT | FeatureSSE4_2; + FeaturesPenryn | FeaturePOPCNT | FeatureCRC32 | FeatureSSE4_2; constexpr FeatureBitset FeaturesWestmere = FeaturesNehalem | FeaturePCLMUL; constexpr FeatureBitset FeaturesSandyBridge = FeaturesWestmere | FeatureAVX | FeatureXSAVE | FeatureXSAVEOPT; @@ -201,11 +203,11 @@ constexpr FeatureBitset FeaturesTigerlake = FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B | FeatureCLWB | FeatureMOVDIRI | FeatureSHSTK | FeatureKL | FeatureWIDEKL; constexpr FeatureBitset FeaturesSapphireRapids = - FeaturesICLServer | FeatureAMX_TILE | FeatureAMX_INT8 | FeatureAMX_BF16 | - FeatureAVX512BF16 | FeatureAVX512VP2INTERSECT | FeatureCLDEMOTE | - FeatureENQCMD | FeatureMOVDIR64B | FeatureMOVDIRI | FeaturePTWRITE | - FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureUINTR | - FeatureWAITPKG | FeatureAVXVNNI; + FeaturesICLServer | FeatureAMX_BF16 | FeatureAMX_INT8 | FeatureAMX_TILE | + FeatureAVX512BF16 | FeatureAVX512FP16 | FeatureAVX512VP2INTERSECT | + FeatureAVXVNNI | FeatureCLDEMOTE | FeatureENQCMD | FeatureMOVDIR64B | + FeatureMOVDIRI | FeaturePTWRITE | FeatureSERIALIZE | FeatureSHSTK | + FeatureTSXLDTRK | FeatureUINTR | FeatureWAITPKG; // Intel Atom processors. // Bonnell has feature parity with Core2 and adds MOVBE. @@ -254,16 +256,17 @@ constexpr FeatureBitset FeaturesBTVER1 = FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_A | FeatureSAHF; constexpr FeatureBitset FeaturesBTVER2 = - FeaturesBTVER1 | FeatureAES | FeatureAVX | FeatureBMI | FeatureF16C | - FeatureMOVBE | FeaturePCLMUL | FeatureXSAVE | FeatureXSAVEOPT; + FeaturesBTVER1 | FeatureAES | FeatureAVX | FeatureBMI | FeatureCRC32 | + FeatureF16C | FeatureMOVBE | FeaturePCLMUL | FeatureXSAVE | FeatureXSAVEOPT; // AMD Bulldozer architecture processors. constexpr FeatureBitset FeaturesBDVER1 = FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B | - FeatureCMPXCHG16B | Feature64BIT | FeatureFMA4 | FeatureFXSR | FeatureLWP | - FeatureLZCNT | FeatureMMX | FeaturePCLMUL | FeaturePOPCNT | FeaturePRFCHW | - FeatureSAHF | FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | - FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A | FeatureXOP | FeatureXSAVE; + FeatureCMPXCHG16B | FeatureCRC32 | Feature64BIT | FeatureFMA4 | + FeatureFXSR | FeatureLWP | FeatureLZCNT | FeatureMMX | FeaturePCLMUL | + FeaturePOPCNT | FeaturePRFCHW | FeatureSAHF | FeatureSSE | FeatureSSE2 | + FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A | + FeatureXOP | FeatureXSAVE; constexpr FeatureBitset FeaturesBDVER2 = FeaturesBDVER1 | FeatureBMI | FeatureFMA | FeatureF16C | FeatureTBM; constexpr FeatureBitset FeaturesBDVER3 = @@ -276,9 +279,9 @@ constexpr FeatureBitset FeaturesBDVER4 = FeaturesBDVER3 | FeatureAVX2 | constexpr FeatureBitset FeaturesZNVER1 = FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO | - FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT | FeatureF16C | - FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT | FeatureMMX | - FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT | + FeatureCMPXCHG8B | FeatureCMPXCHG16B | FeatureCRC32 | Feature64BIT | + FeatureF16C | FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT | + FeatureMMX | FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT | FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA | FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC | @@ -470,6 +473,7 @@ constexpr FeatureBitset ImpliedFeaturesCLZERO = {}; constexpr FeatureBitset ImpliedFeaturesCMOV = {}; constexpr FeatureBitset ImpliedFeaturesCMPXCHG16B = {}; constexpr FeatureBitset ImpliedFeaturesCMPXCHG8B = {}; +constexpr FeatureBitset ImpliedFeaturesCRC32 = {}; constexpr FeatureBitset ImpliedFeaturesENQCMD = {}; constexpr FeatureBitset ImpliedFeaturesFSGSBASE = {}; constexpr FeatureBitset ImpliedFeaturesFXSR = {}; @@ -576,6 +580,8 @@ constexpr FeatureBitset ImpliedFeaturesAMX_BF16 = FeatureAMX_TILE; constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE; constexpr FeatureBitset ImpliedFeaturesHRESET = {}; +static constexpr FeatureBitset ImpliedFeaturesAVX512FP16 = + FeatureAVX512BW | FeatureAVX512DQ | FeatureAVX512VL; // Key Locker Features constexpr FeatureBitset ImpliedFeaturesKL = FeatureSSE2; constexpr FeatureBitset ImpliedFeaturesWIDEKL = FeatureKL; @@ -660,3 +666,45 @@ void llvm::X86::updateImpliedFeatures( if (ImpliedBits[i] && !FeatureInfos[i].Name.empty()) Features[FeatureInfos[i].Name] = Enabled; } + +uint64_t llvm::X86::getCpuSupportsMask(ArrayRef<StringRef> FeatureStrs) { + // Processor features and mapping to processor feature value. + uint64_t FeaturesMask = 0; + for (const StringRef &FeatureStr : FeatureStrs) { + unsigned Feature = StringSwitch<unsigned>(FeatureStr) +#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \ + .Case(STR, llvm::X86::FEATURE_##ENUM) +#include "llvm/Support/X86TargetParser.def" + ; + FeaturesMask |= (1ULL << Feature); + } + return FeaturesMask; +} + +unsigned llvm::X86::getFeaturePriority(ProcessorFeatures Feat) { +#ifndef NDEBUG + // Check that priorities are set properly in the .def file. We expect that + // "compat" features are assigned non-duplicate consecutive priorities + // starting from zero (0, 1, ..., num_features - 1). +#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) PRIORITY, + unsigned Priorities[] = { +#include "llvm/Support/X86TargetParser.def" + std::numeric_limits<unsigned>::max() // Need to consume last comma. + }; + std::array<unsigned, array_lengthof(Priorities) - 1> HelperList; + std::iota(HelperList.begin(), HelperList.end(), 0); + assert(std::is_permutation(HelperList.begin(), HelperList.end(), + std::begin(Priorities), + std::prev(std::end(Priorities))) && + "Priorities don't form consecutive range!"); +#endif + + switch (Feat) { +#define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \ + case X86::FEATURE_##ENUM: \ + return PRIORITY; +#include "llvm/Support/X86TargetParser.def" + default: + llvm_unreachable("No Feature Priority for non-CPUSupports Features"); + } +} |