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Diffstat (limited to 'llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp')
-rw-r--r--llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp257
1 files changed, 208 insertions, 49 deletions
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
index 76663b563150..bd938d829953 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -120,14 +120,6 @@ void AMDGPUInstPrinter::printAddr64(const MCInst *MI, unsigned OpNo,
printNamedBit(MI, OpNo, O, "addr64");
}
-void AMDGPUInstPrinter::printMBUFOffset(const MCInst *MI, unsigned OpNo,
- raw_ostream &O) {
- if (MI->getOperand(OpNo).getImm()) {
- O << " offset:";
- printU16ImmDecOperand(MI, OpNo, O);
- }
-}
-
void AMDGPUInstPrinter::printOffset(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
@@ -152,7 +144,7 @@ void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo,
if (IsFlatSeg) { // Unsigned offset
printU16ImmDecOperand(MI, OpNo, O);
} else { // Signed offset
- if (AMDGPU::isGFX10Plus(STI)) {
+ if (AMDGPU::isGFX10(STI)) {
O << formatDec(SignExtend32<12>(MI->getOperand(OpNo).getImm()));
} else {
O << formatDec(SignExtend32<13>(MI->getOperand(OpNo).getImm()));
@@ -191,6 +183,13 @@ void AMDGPUInstPrinter::printSMEMOffset(const MCInst *MI, unsigned OpNo,
O << formatHex(MI->getOperand(OpNo).getImm());
}
+void AMDGPUInstPrinter::printSMEMOffsetMod(const MCInst *MI, unsigned OpNo,
+ const MCSubtargetInfo &STI,
+ raw_ostream &O) {
+ O << " offset:";
+ printSMEMOffset(MI, OpNo, STI, O);
+}
+
void AMDGPUInstPrinter::printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
@@ -206,13 +205,15 @@ void AMDGPUInstPrinter::printCPol(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O) {
auto Imm = MI->getOperand(OpNo).getImm();
if (Imm & CPol::GLC)
- O << " glc";
+ O << ((AMDGPU::isGFX940(STI) &&
+ !(MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::SMRD)) ? " sc0"
+ : " glc");
if (Imm & CPol::SLC)
- O << " slc";
+ O << (AMDGPU::isGFX940(STI) ? " nt" : " slc");
if ((Imm & CPol::DLC) && AMDGPU::isGFX10Plus(STI))
O << " dlc";
if ((Imm & CPol::SCC) && AMDGPU::isGFX90A(STI))
- O << " scc";
+ O << (AMDGPU::isGFX940(STI) ? " sc1" : " scc");
if (Imm & ~CPol::ALL)
O << " /* unexpected cache policy bit */";
}
@@ -309,8 +310,8 @@ void AMDGPUInstPrinter::printSymbolicFormat(const MCInst *MI,
if (AMDGPU::isGFX10Plus(STI)) {
if (Val == UFMT_DEFAULT)
return;
- if (isValidUnifiedFormat(Val)) {
- O << " format:[" << getUnifiedFormatName(Val) << ']';
+ if (isValidUnifiedFormat(Val, STI)) {
+ O << " format:[" << getUnifiedFormatName(Val, STI) << ']';
} else {
O << " format:" << Val;
}
@@ -362,27 +363,26 @@ void AMDGPUInstPrinter::printRegOperand(unsigned RegNo, raw_ostream &O,
}
void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI,
- raw_ostream &O) {
+ const MCSubtargetInfo &STI, raw_ostream &O) {
auto Opcode = MI->getOpcode();
auto Flags = MII.get(Opcode).TSFlags;
-
if (OpNo == 0) {
- if (Flags & SIInstrFlags::VOP3) {
+ if (Flags & SIInstrFlags::VOP3 && Flags & SIInstrFlags::DPP)
+ O << "_e64_dpp";
+ else if (Flags & SIInstrFlags::VOP3) {
if (!getVOP3IsSingle(Opcode))
O << "_e64";
- } else if (Flags & SIInstrFlags::DPP) {
+ } else if (Flags & SIInstrFlags::DPP)
O << "_dpp";
- } else if (Flags & SIInstrFlags::SDWA) {
+ else if (Flags & SIInstrFlags::SDWA)
O << "_sdwa";
- } else if (((Flags & SIInstrFlags::VOP1) && !getVOP1IsSingle(Opcode)) ||
- ((Flags & SIInstrFlags::VOP2) && !getVOP2IsSingle(Opcode))) {
+ else if (((Flags & SIInstrFlags::VOP1) && !getVOP1IsSingle(Opcode)) ||
+ ((Flags & SIInstrFlags::VOP2) && !getVOP2IsSingle(Opcode)))
O << "_e32";
- }
O << " ";
}
- printOperand(MI, OpNo, STI, O);
+ printRegularOperand(MI, OpNo, STI, O);
// Print default vcc/vcc_lo operand.
switch (Opcode) {
@@ -400,7 +400,16 @@ void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
- printDefaultVccOperand(1, STI, O);
+ case AMDGPU::V_ADD_CO_CI_U32_e32_gfx11:
+ case AMDGPU::V_SUB_CO_CI_U32_e32_gfx11:
+ case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx11:
+ case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx11:
+ case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx11:
+ case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx11:
+ case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx11:
+ case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx11:
+ case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx11:
+ printDefaultVccOperand(false, STI, O);
break;
}
}
@@ -412,7 +421,7 @@ void AMDGPUInstPrinter::printVINTRPDst(const MCInst *MI, unsigned OpNo,
else
O << "_e32 ";
- printOperand(MI, OpNo, STI, O);
+ printRegularOperand(MI, OpNo, STI, O);
}
void AMDGPUInstPrinter::printImmediateInt16(uint32_t Imm,
@@ -533,7 +542,7 @@ void AMDGPUInstPrinter::printImmediate64(uint64_t Imm,
STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
O << "0.15915494309189532";
else {
- assert(isUInt<32>(Imm) || Imm == 0x3fc45f306dc9c882);
+ assert(isUInt<32>(Imm) || isInt<32>(Imm));
// In rare situations, we will have a 32-bit literal in a 64-bit
// operand. This is technically allowed for the encoding of s_mov_b64.
@@ -548,6 +557,18 @@ void AMDGPUInstPrinter::printBLGP(const MCInst *MI, unsigned OpNo,
if (!Imm)
return;
+ if (AMDGPU::isGFX940(STI)) {
+ switch (MI->getOpcode()) {
+ case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_acd:
+ case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_vcd:
+ case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_acd:
+ case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_vcd:
+ O << " neg:[" << (Imm & 1) << ',' << ((Imm >> 1) & 1) << ','
+ << ((Imm >> 2) & 1) << ']';
+ return;
+ }
+ }
+
O << " blgp:" << Imm;
}
@@ -571,26 +592,73 @@ void AMDGPUInstPrinter::printABID(const MCInst *MI, unsigned OpNo,
O << " abid:" << Imm;
}
-void AMDGPUInstPrinter::printDefaultVccOperand(unsigned OpNo,
+void AMDGPUInstPrinter::printDefaultVccOperand(bool FirstOperand,
const MCSubtargetInfo &STI,
raw_ostream &O) {
- if (OpNo > 0)
+ if (!FirstOperand)
O << ", ";
- printRegOperand(STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ?
- AMDGPU::VCC : AMDGPU::VCC_LO, O, MRI);
- if (OpNo == 0)
+ printRegOperand(STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64]
+ ? AMDGPU::VCC
+ : AMDGPU::VCC_LO,
+ O, MRI);
+ if (FirstOperand)
O << ", ";
}
+void AMDGPUInstPrinter::printWaitVDST(const MCInst *MI, unsigned OpNo,
+ const MCSubtargetInfo &STI,
+ raw_ostream &O) {
+ uint8_t Imm = MI->getOperand(OpNo).getImm();
+ if (Imm != 0) {
+ O << " wait_vdst:";
+ printU4ImmDecOperand(MI, OpNo, O);
+ }
+}
+
+void AMDGPUInstPrinter::printWaitEXP(const MCInst *MI, unsigned OpNo,
+ const MCSubtargetInfo &STI,
+ raw_ostream &O) {
+ uint8_t Imm = MI->getOperand(OpNo).getImm();
+ if (Imm != 0) {
+ O << " wait_exp:";
+ printU4ImmDecOperand(MI, OpNo, O);
+ }
+}
+
+bool AMDGPUInstPrinter::needsImpliedVcc(const MCInstrDesc &Desc,
+ unsigned OpNo) const {
+ return OpNo == 1 && (Desc.TSFlags & SIInstrFlags::DPP) &&
+ (Desc.TSFlags & SIInstrFlags::VOPC) &&
+ (Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
+ Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO));
+}
+
+// Print default vcc/vcc_lo operand of VOPC.
void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
- // Print default vcc/vcc_lo operand of VOPC.
- const MCInstrDesc &Desc = MII.get(MI->getOpcode());
- if (OpNo == 0 && (Desc.TSFlags & SIInstrFlags::VOPC) &&
+ unsigned Opc = MI->getOpcode();
+ const MCInstrDesc &Desc = MII.get(Opc);
+ int ModIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers);
+ // 0, 1 and 2 are the first printed operands in different cases
+ // If there are printed modifiers, printOperandAndFPInputMods or
+ // printOperandAndIntInputMods will be called instead
+ if ((OpNo == 0 ||
+ (OpNo == 1 && (Desc.TSFlags & SIInstrFlags::DPP)) ||
+ (OpNo == 2 && (Desc.TSFlags & SIInstrFlags::DPP) && ModIdx != -1)) &&
+ (Desc.TSFlags & SIInstrFlags::VOPC) &&
(Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC) ||
Desc.hasImplicitDefOfPhysReg(AMDGPU::VCC_LO)))
- printDefaultVccOperand(OpNo, STI, O);
+ printDefaultVccOperand(true, STI, O);
+
+ printRegularOperand(MI, OpNo, STI, O);
+}
+
+// Print operands after vcc or modifier handling.
+void AMDGPUInstPrinter::printRegularOperand(const MCInst *MI, unsigned OpNo,
+ const MCSubtargetInfo &STI,
+ raw_ostream &O) {
+ const MCInstrDesc &Desc = MII.get(MI->getOpcode());
if (OpNo >= MI->getNumOperands()) {
O << "/*Missing OP" << OpNo << "*/";
@@ -710,12 +778,24 @@ void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10:
case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10:
case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10:
+ case AMDGPU::V_CNDMASK_B32_e32_gfx11:
+ case AMDGPU::V_ADD_CO_CI_U32_e32_gfx11:
+ case AMDGPU::V_SUB_CO_CI_U32_e32_gfx11:
+ case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx11:
+ case AMDGPU::V_CNDMASK_B32_dpp_gfx11:
+ case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx11:
+ case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx11:
+ case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx11:
+ case AMDGPU::V_CNDMASK_B32_dpp8_gfx11:
+ case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx11:
+ case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx11:
+ case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx11:
case AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7:
case AMDGPU::V_CNDMASK_B32_e32_vi:
if ((int)OpNo == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
AMDGPU::OpName::src1))
- printDefaultVccOperand(OpNo, STI, O);
+ printDefaultVccOperand(OpNo == 0, STI, O);
break;
}
@@ -732,6 +812,10 @@ void AMDGPUInstPrinter::printOperandAndFPInputMods(const MCInst *MI,
unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
+ const MCInstrDesc &Desc = MII.get(MI->getOpcode());
+ if (needsImpliedVcc(Desc, OpNo))
+ printDefaultVccOperand(true, STI, O);
+
unsigned InputModifiers = MI->getOperand(OpNo).getImm();
// Use 'neg(...)' instead of '-' to avoid ambiguity.
@@ -754,7 +838,7 @@ void AMDGPUInstPrinter::printOperandAndFPInputMods(const MCInst *MI,
if (InputModifiers & SISrcMods::ABS)
O << '|';
- printOperand(MI, OpNo + 1, STI, O);
+ printRegularOperand(MI, OpNo + 1, STI, O);
if (InputModifiers & SISrcMods::ABS)
O << '|';
@@ -767,10 +851,14 @@ void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI,
unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
+ const MCInstrDesc &Desc = MII.get(MI->getOpcode());
+ if (needsImpliedVcc(Desc, OpNo))
+ printDefaultVccOperand(true, STI, O);
+
unsigned InputModifiers = MI->getOperand(OpNo).getImm();
if (InputModifiers & SISrcMods::SEXT)
O << "sext(";
- printOperand(MI, OpNo + 1, STI, O);
+ printRegularOperand(MI, OpNo + 1, STI, O);
if (InputModifiers & SISrcMods::SEXT)
O << ')';
@@ -784,7 +872,7 @@ void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI,
case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10:
if ((int)OpNo + 1 == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
AMDGPU::OpName::src1))
- printDefaultVccOperand(OpNo, STI, O);
+ printDefaultVccOperand(OpNo == 0, STI, O);
break;
}
}
@@ -1203,9 +1291,9 @@ void AMDGPUInstPrinter::printVGPRIndexMode(const MCInst *MI, unsigned OpNo,
void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
- printOperand(MI, OpNo, STI, O);
+ printRegularOperand(MI, OpNo, STI, O);
O << ", ";
- printOperand(MI, OpNo + 1, STI, O);
+ printRegularOperand(MI, OpNo + 1, STI, O);
}
void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
@@ -1262,15 +1350,16 @@ void AMDGPUInstPrinter::printSendMsg(const MCInst *MI, unsigned OpNo,
uint16_t MsgId;
uint16_t OpId;
uint16_t StreamId;
- decodeMsg(Imm16, MsgId, OpId, StreamId);
+ decodeMsg(Imm16, MsgId, OpId, StreamId, STI);
+
+ StringRef MsgName = getMsgName(MsgId, STI);
- if (isValidMsgId(MsgId, STI) &&
- isValidMsgOp(MsgId, OpId, STI) &&
+ if (!MsgName.empty() && isValidMsgOp(MsgId, OpId, STI) &&
isValidMsgStream(MsgId, OpId, StreamId, STI)) {
- O << "sendmsg(" << getMsgName(MsgId);
- if (msgRequiresOp(MsgId)) {
- O << ", " << getMsgOpName(MsgId, OpId);
- if (msgSupportsStream(MsgId, OpId)) {
+ O << "sendmsg(" << MsgName;
+ if (msgRequiresOp(MsgId, STI)) {
+ O << ", " << getMsgOpName(MsgId, OpId, STI);
+ if (msgSupportsStream(MsgId, OpId, STI)) {
O << ", " << StreamId;
}
}
@@ -1423,6 +1512,76 @@ void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
}
}
+void AMDGPUInstPrinter::printDepCtr(const MCInst *MI, unsigned OpNo,
+ const MCSubtargetInfo &STI,
+ raw_ostream &O) {
+ using namespace llvm::AMDGPU::DepCtr;
+
+ uint64_t Imm16 = MI->getOperand(OpNo).getImm() & 0xffff;
+
+ bool HasNonDefaultVal = false;
+ if (isSymbolicDepCtrEncoding(Imm16, HasNonDefaultVal, STI)) {
+ int Id = 0;
+ StringRef Name;
+ unsigned Val;
+ bool IsDefault;
+ bool NeedSpace = false;
+ while (decodeDepCtr(Imm16, Id, Name, Val, IsDefault, STI)) {
+ if (!IsDefault || !HasNonDefaultVal) {
+ if (NeedSpace)
+ O << ' ';
+ O << Name << '(' << Val << ')';
+ NeedSpace = true;
+ }
+ }
+ } else {
+ O << formatHex(Imm16);
+ }
+}
+
+void AMDGPUInstPrinter::printDelayFlag(const MCInst *MI, unsigned OpNo,
+ const MCSubtargetInfo &STI,
+ raw_ostream &O) {
+ const char *BadInstId = "/* invalid instid value */";
+ static const std::array<const char *, 12> InstIds = {
+ "NO_DEP", "VALU_DEP_1", "VALU_DEP_2",
+ "VALU_DEP_3", "VALU_DEP_4", "TRANS32_DEP_1",
+ "TRANS32_DEP_2", "TRANS32_DEP_3", "FMA_ACCUM_CYCLE_1",
+ "SALU_CYCLE_1", "SALU_CYCLE_2", "SALU_CYCLE_3"};
+
+ const char *BadInstSkip = "/* invalid instskip value */";
+ static const std::array<const char *, 6> InstSkips = {
+ "SAME", "NEXT", "SKIP_1", "SKIP_2", "SKIP_3", "SKIP_4"};
+
+ unsigned SImm16 = MI->getOperand(OpNo).getImm();
+ const char *Prefix = "";
+
+ unsigned Value = SImm16 & 0xF;
+ if (Value) {
+ const char *Name = Value < InstIds.size() ? InstIds[Value] : BadInstId;
+ O << Prefix << "instid0(" << Name << ')';
+ Prefix = " | ";
+ }
+
+ Value = (SImm16 >> 4) & 7;
+ if (Value) {
+ const char *Name =
+ Value < InstSkips.size() ? InstSkips[Value] : BadInstSkip;
+ O << Prefix << "instskip(" << Name << ')';
+ Prefix = " | ";
+ }
+
+ Value = (SImm16 >> 7) & 0xF;
+ if (Value) {
+ const char *Name = Value < InstIds.size() ? InstIds[Value] : BadInstId;
+ O << Prefix << "instid1(" << Name << ')';
+ Prefix = " | ";
+ }
+
+ if (!*Prefix)
+ O << "0";
+}
+
void AMDGPUInstPrinter::printHwreg(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O) {
unsigned Id;
generated by cgit v1.3 (git 2.53.0) at 2026-03-10 12:37:12 +0000