diff options
Diffstat (limited to 'llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 33 |
1 files changed, 19 insertions, 14 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 51fd45034534..9caef9f09ea9 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -19,10 +19,10 @@ #include "llvm/MC/MCInstrDesc.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/SubtargetFeature.h" +#include "llvm/MC/TargetRegistry.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MathExtras.h" -#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" #include <algorithm> #include <cassert> @@ -227,10 +227,12 @@ static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeQQPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); -static DecodeStatus DecodeQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); +static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, @@ -852,12 +854,15 @@ ARMDisassembler::AddThumbPredicate(MCInst &MI) const { VCCI = MI.insert(VCCI, MCOperand::createImm(VCC)); ++VCCI; if (VCC == ARMVCC::None) - MI.insert(VCCI, MCOperand::createReg(0)); + VCCI = MI.insert(VCCI, MCOperand::createReg(0)); else - MI.insert(VCCI, MCOperand::createReg(ARM::P0)); + VCCI = MI.insert(VCCI, MCOperand::createReg(ARM::P0)); + ++VCCI; + VCCI = MI.insert(VCCI, MCOperand::createReg(0)); + ++VCCI; if (OpInfo[VCCPos].OperandType == ARM::OPERAND_VPRED_R) { int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint( - VCCPos + 2, MCOI::TIED_TO); + VCCPos + 3, MCOI::TIED_TO); assert(TiedOp >= 0 && "Inactive register in vpred_r is not tied to an output!"); // Copy the operand to ensure it's not invalidated when MI grows. @@ -6154,9 +6159,9 @@ static const uint16_t QQPRDecoderTable[] = { ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7 }; -static DecodeStatus DecodeQQPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder) { +static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { if (RegNo > 6) return MCDisassembler::Fail; @@ -6170,9 +6175,9 @@ static const uint16_t QQQQPRDecoderTable[] = { ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7 }; -static DecodeStatus DecodeQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder) { +static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { if (RegNo > 4) return MCDisassembler::Fail; |