diff options
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td | 6032 |
1 files changed, 3829 insertions, 2203 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td index a49051888c77..ccc3f98d8378 100644 --- a/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td +++ b/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td @@ -5,14 +5,14 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// -// Automatically generated file, please consult code owner before editing. +// Automatically generated file, do not edit! //===----------------------------------------------------------------------===// def A2_abs : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = abs($Rs32)", -tc_cf8126ae, TypeS_2op>, Enc_5e2823 { +tc_d61dfdc3, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10001100100; let hasNewValue = 1; @@ -23,7 +23,7 @@ def A2_absp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = abs($Rss32)", -tc_cf8126ae, TypeS_2op>, Enc_b9c5fb { +tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10000000100; let prefersSlot3 = 1; @@ -32,7 +32,7 @@ def A2_abssat : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = abs($Rs32):sat", -tc_cf8126ae, TypeS_2op>, Enc_5e2823 { +tc_d61dfdc3, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000101; let Inst{31-21} = 0b10001100100; let hasNewValue = 1; @@ -44,15 +44,15 @@ def A2_add : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = add($Rs32,$Rt32)", -tc_5a2711e5, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel { +tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110011000; let hasNewValue = 1; let opNewValue = 0; +let BaseOpcode = "A2_add"; let CextOpcode = "A2_add"; let InputType = "reg"; -let BaseOpcode = "A2_add"; let isCommutable = 1; let isPredicable = 1; } @@ -60,7 +60,7 @@ def A2_addh_h16_hh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = add($Rt32.h,$Rs32.h):<<16", -tc_679309b8, TypeALU64>, Enc_bd6011 { +tc_01d44cb2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101010; @@ -72,7 +72,7 @@ def A2_addh_h16_hl : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = add($Rt32.h,$Rs32.l):<<16", -tc_679309b8, TypeALU64>, Enc_bd6011 { +tc_01d44cb2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101010; @@ -84,7 +84,7 @@ def A2_addh_h16_lh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = add($Rt32.l,$Rs32.h):<<16", -tc_679309b8, TypeALU64>, Enc_bd6011 { +tc_01d44cb2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101010; @@ -96,7 +96,7 @@ def A2_addh_h16_ll : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = add($Rt32.l,$Rs32.l):<<16", -tc_679309b8, TypeALU64>, Enc_bd6011 { +tc_01d44cb2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101010; @@ -108,7 +108,7 @@ def A2_addh_h16_sat_hh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = add($Rt32.h,$Rs32.h):sat:<<16", -tc_779080bf, TypeALU64>, Enc_bd6011 { +tc_8a825db2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101010; @@ -121,7 +121,7 @@ def A2_addh_h16_sat_hl : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = add($Rt32.h,$Rs32.l):sat:<<16", -tc_779080bf, TypeALU64>, Enc_bd6011 { +tc_8a825db2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101010; @@ -134,7 +134,7 @@ def A2_addh_h16_sat_lh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = add($Rt32.l,$Rs32.h):sat:<<16", -tc_779080bf, TypeALU64>, Enc_bd6011 { +tc_8a825db2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101010; @@ -147,7 +147,7 @@ def A2_addh_h16_sat_ll : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = add($Rt32.l,$Rs32.l):sat:<<16", -tc_779080bf, TypeALU64>, Enc_bd6011 { +tc_8a825db2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101010; @@ -160,7 +160,7 @@ def A2_addh_l16_hl : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = add($Rt32.l,$Rs32.h)", -tc_4414d8b1, TypeALU64>, Enc_bd6011 { +tc_f34c1c21, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101000; @@ -172,7 +172,7 @@ def A2_addh_l16_ll : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = add($Rt32.l,$Rs32.l)", -tc_4414d8b1, TypeALU64>, Enc_bd6011 { +tc_f34c1c21, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101000; @@ -184,7 +184,7 @@ def A2_addh_l16_sat_hl : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = add($Rt32.l,$Rs32.h):sat", -tc_779080bf, TypeALU64>, Enc_bd6011 { +tc_8a825db2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101000; @@ -197,7 +197,7 @@ def A2_addh_l16_sat_ll : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = add($Rt32.l,$Rs32.l):sat", -tc_779080bf, TypeALU64>, Enc_bd6011 { +tc_8a825db2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101000; @@ -210,13 +210,13 @@ def A2_addi : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Rd32 = add($Rs32,#$Ii)", -tc_5a2711e5, TypeALU32_ADDI>, Enc_cb9321, PredNewRel, ImmRegRel { +tc_713b66bf, TypeALU32_ADDI>, Enc_cb9321, PredNewRel, ImmRegRel { let Inst{31-28} = 0b1011; let hasNewValue = 1; let opNewValue = 0; +let BaseOpcode = "A2_addi"; let CextOpcode = "A2_add"; let InputType = "imm"; -let BaseOpcode = "A2_addi"; let isPredicable = 1; let isAdd = 1; let isExtendable = 1; @@ -229,7 +229,7 @@ def A2_addp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = add($Rss32,$Rtt32)", -tc_946df596, TypeALU64>, Enc_a56825 { +tc_5da50c4b, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011000; @@ -240,7 +240,7 @@ def A2_addpsat : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = add($Rss32,$Rtt32):sat", -tc_779080bf, TypeALU64>, Enc_a56825 { +tc_8a825db2, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011011; @@ -252,7 +252,7 @@ def A2_addsat : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = add($Rs32,$Rt32):sat", -tc_61830035, TypeALU32_3op>, Enc_5ab2be { +tc_95a33176, TypeALU32_3op>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110110010; @@ -267,14 +267,14 @@ def A2_addsp : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, DoubleRegs:$Rtt32), "$Rdd32 = add($Rs32,$Rtt32)", -tc_679309b8, TypeALU64> { +tc_01d44cb2, TypeALU64> { let isPseudo = 1; } def A2_addsph : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = add($Rss32,$Rtt32):raw:hi", -tc_679309b8, TypeALU64>, Enc_a56825 { +tc_01d44cb2, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011011; @@ -284,7 +284,7 @@ def A2_addspl : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = add($Rss32,$Rtt32):raw:lo", -tc_679309b8, TypeALU64>, Enc_a56825 { +tc_01d44cb2, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011011; @@ -294,15 +294,15 @@ def A2_and : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = and($Rs32,$Rt32)", -tc_5a2711e5, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel { +tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110001000; let hasNewValue = 1; let opNewValue = 0; +let BaseOpcode = "A2_and"; let CextOpcode = "A2_and"; let InputType = "reg"; -let BaseOpcode = "A2_and"; let isCommutable = 1; let isPredicable = 1; } @@ -310,7 +310,7 @@ def A2_andir : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Rd32 = and($Rs32,#$Ii)", -tc_5a2711e5, TypeALU32_2op>, Enc_140c83, ImmRegRel { +tc_713b66bf, TypeALU32_2op>, Enc_140c83, ImmRegRel { let Inst{31-22} = 0b0111011000; let hasNewValue = 1; let opNewValue = 0; @@ -326,7 +326,7 @@ def A2_andp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = and($Rss32,$Rtt32)", -tc_946df596, TypeALU64>, Enc_a56825 { +tc_5da50c4b, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011111; @@ -336,7 +336,7 @@ def A2_aslh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = aslh($Rs32)", -tc_57890846, TypeALU32_2op>, Enc_5e2823, PredNewRel { +tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b01110000000; let hasNewValue = 1; @@ -348,7 +348,7 @@ def A2_asrh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = asrh($Rs32)", -tc_57890846, TypeALU32_2op>, Enc_5e2823, PredNewRel { +tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b01110000001; let hasNewValue = 1; @@ -360,7 +360,7 @@ def A2_combine_hh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = combine($Rt32.h,$Rs32.h)", -tc_5a2711e5, TypeALU32_3op>, Enc_bd6011 { +tc_713b66bf, TypeALU32_3op>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110011100; @@ -372,7 +372,7 @@ def A2_combine_hl : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = combine($Rt32.h,$Rs32.l)", -tc_5a2711e5, TypeALU32_3op>, Enc_bd6011 { +tc_713b66bf, TypeALU32_3op>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110011101; @@ -384,7 +384,7 @@ def A2_combine_lh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = combine($Rt32.l,$Rs32.h)", -tc_5a2711e5, TypeALU32_3op>, Enc_bd6011 { +tc_713b66bf, TypeALU32_3op>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110011110; @@ -396,7 +396,7 @@ def A2_combine_ll : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = combine($Rt32.l,$Rs32.l)", -tc_5a2711e5, TypeALU32_3op>, Enc_bd6011 { +tc_713b66bf, TypeALU32_3op>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110011111; @@ -408,7 +408,7 @@ def A2_combineii : HInst< (outs DoubleRegs:$Rdd32), (ins s32_0Imm:$Ii, s8_0Imm:$II), "$Rdd32 = combine(#$Ii,#$II)", -tc_5a2711e5, TypeALU32_2op>, Enc_18c338 { +tc_713b66bf, TypeALU32_2op>, Enc_18c338 { let Inst{31-23} = 0b011111000; let isReMaterializable = 1; let isAsCheapAsAMove = 1; @@ -423,19 +423,19 @@ def A2_combinew : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = combine($Rs32,$Rt32)", -tc_5a2711e5, TypeALU32_3op>, Enc_be32a5, PredNewRel { +tc_713b66bf, TypeALU32_3op>, Enc_be32a5, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110101000; -let InputType = "reg"; let BaseOpcode = "A2_combinew"; +let InputType = "reg"; let isPredicable = 1; } def A2_max : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = max($Rs32,$Rt32)", -tc_779080bf, TypeALU64>, Enc_5ab2be { +tc_8a825db2, TypeALU64>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101110; @@ -447,7 +447,7 @@ def A2_maxp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = max($Rss32,$Rtt32)", -tc_779080bf, TypeALU64>, Enc_a56825 { +tc_8a825db2, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011110; @@ -457,7 +457,7 @@ def A2_maxu : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = maxu($Rs32,$Rt32)", -tc_779080bf, TypeALU64>, Enc_5ab2be { +tc_8a825db2, TypeALU64>, Enc_5ab2be { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101110; @@ -469,7 +469,7 @@ def A2_maxup : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = maxu($Rss32,$Rtt32)", -tc_779080bf, TypeALU64>, Enc_a56825 { +tc_8a825db2, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011110; @@ -479,7 +479,7 @@ def A2_min : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = min($Rt32,$Rs32)", -tc_779080bf, TypeALU64>, Enc_bd6011 { +tc_8a825db2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101101; @@ -491,7 +491,7 @@ def A2_minp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = min($Rtt32,$Rss32)", -tc_779080bf, TypeALU64>, Enc_ea23e4 { +tc_8a825db2, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011101; @@ -501,7 +501,7 @@ def A2_minu : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = minu($Rt32,$Rs32)", -tc_779080bf, TypeALU64>, Enc_bd6011 { +tc_8a825db2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101101; @@ -513,7 +513,7 @@ def A2_minup : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = minu($Rtt32,$Rss32)", -tc_779080bf, TypeALU64>, Enc_ea23e4 { +tc_8a825db2, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011101; @@ -523,7 +523,7 @@ def A2_neg : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = neg($Rs32)", -tc_57890846, TypeALU32_2op> { +tc_c57d9f39, TypeALU32_2op> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -533,7 +533,7 @@ def A2_negp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = neg($Rss32)", -tc_0ae0825c, TypeS_2op>, Enc_b9c5fb { +tc_9f6cd987, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000101; let Inst{31-21} = 0b10000000100; } @@ -541,7 +541,7 @@ def A2_negsat : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = neg($Rs32):sat", -tc_cf8126ae, TypeS_2op>, Enc_5e2823 { +tc_d61dfdc3, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10001100100; let hasNewValue = 1; @@ -553,7 +553,7 @@ def A2_nop : HInst< (outs), (ins), "nop", -tc_2eabeebe, TypeALU32_2op>, Enc_e3b0c4 { +tc_b837298f, TypeALU32_2op>, Enc_e3b0c4 { let Inst{13-0} = 0b00000000000000; let Inst{31-16} = 0b0111111100000000; } @@ -561,7 +561,7 @@ def A2_not : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = not($Rs32)", -tc_57890846, TypeALU32_2op> { +tc_c57d9f39, TypeALU32_2op> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -571,7 +571,7 @@ def A2_notp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = not($Rss32)", -tc_0ae0825c, TypeS_2op>, Enc_b9c5fb { +tc_9f6cd987, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10000000100; } @@ -579,15 +579,15 @@ def A2_or : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = or($Rs32,$Rt32)", -tc_5a2711e5, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel { +tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110001001; let hasNewValue = 1; let opNewValue = 0; +let BaseOpcode = "A2_or"; let CextOpcode = "A2_or"; let InputType = "reg"; -let BaseOpcode = "A2_or"; let isCommutable = 1; let isPredicable = 1; } @@ -595,7 +595,7 @@ def A2_orir : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Rd32 = or($Rs32,#$Ii)", -tc_5a2711e5, TypeALU32_2op>, Enc_140c83, ImmRegRel { +tc_713b66bf, TypeALU32_2op>, Enc_140c83, ImmRegRel { let Inst{31-22} = 0b0111011010; let hasNewValue = 1; let opNewValue = 0; @@ -611,7 +611,7 @@ def A2_orp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = or($Rss32,$Rtt32)", -tc_946df596, TypeALU64>, Enc_a56825 { +tc_5da50c4b, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011111; @@ -621,7 +621,7 @@ def A2_paddf : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pu4) $Rd32 = add($Rs32,$Rt32)", -tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel { +tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel { let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11111011000; @@ -629,15 +629,15 @@ let isPredicated = 1; let isPredicatedFalse = 1; let hasNewValue = 1; let opNewValue = 0; +let BaseOpcode = "A2_add"; let CextOpcode = "A2_add"; let InputType = "reg"; -let BaseOpcode = "A2_add"; } def A2_paddfnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pu4.new) $Rd32 = add($Rs32,$Rt32)", -tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel { +tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel { let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11111011000; @@ -646,24 +646,24 @@ let isPredicatedFalse = 1; let hasNewValue = 1; let opNewValue = 0; let isPredicatedNew = 1; +let BaseOpcode = "A2_add"; let CextOpcode = "A2_add"; let InputType = "reg"; -let BaseOpcode = "A2_add"; } def A2_paddif : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii), "if (!$Pu4) $Rd32 = add($Rs32,#$Ii)", -tc_4c5ba658, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel { +tc_1c2c7a4a, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel { let Inst{13-13} = 0b0; let Inst{31-23} = 0b011101001; let isPredicated = 1; let isPredicatedFalse = 1; let hasNewValue = 1; let opNewValue = 0; +let BaseOpcode = "A2_addi"; let CextOpcode = "A2_add"; let InputType = "imm"; -let BaseOpcode = "A2_addi"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 1; @@ -674,7 +674,7 @@ def A2_paddifnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii), "if (!$Pu4.new) $Rd32 = add($Rs32,#$Ii)", -tc_05c070ec, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel { +tc_442395f3, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel { let Inst{13-13} = 0b1; let Inst{31-23} = 0b011101001; let isPredicated = 1; @@ -682,9 +682,9 @@ let isPredicatedFalse = 1; let hasNewValue = 1; let opNewValue = 0; let isPredicatedNew = 1; +let BaseOpcode = "A2_addi"; let CextOpcode = "A2_add"; let InputType = "imm"; -let BaseOpcode = "A2_addi"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 1; @@ -695,15 +695,15 @@ def A2_paddit : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii), "if ($Pu4) $Rd32 = add($Rs32,#$Ii)", -tc_4c5ba658, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel { +tc_1c2c7a4a, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel { let Inst{13-13} = 0b0; let Inst{31-23} = 0b011101000; let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; +let BaseOpcode = "A2_addi"; let CextOpcode = "A2_add"; let InputType = "imm"; -let BaseOpcode = "A2_addi"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 1; @@ -714,16 +714,16 @@ def A2_padditnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii), "if ($Pu4.new) $Rd32 = add($Rs32,#$Ii)", -tc_05c070ec, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel { +tc_442395f3, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel { let Inst{13-13} = 0b1; let Inst{31-23} = 0b011101000; let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; let isPredicatedNew = 1; +let BaseOpcode = "A2_addi"; let CextOpcode = "A2_add"; let InputType = "imm"; -let BaseOpcode = "A2_addi"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 1; @@ -734,22 +734,22 @@ def A2_paddt : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pu4) $Rd32 = add($Rs32,$Rt32)", -tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel { +tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11111011000; let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; +let BaseOpcode = "A2_add"; let CextOpcode = "A2_add"; let InputType = "reg"; -let BaseOpcode = "A2_add"; } def A2_paddtnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pu4.new) $Rd32 = add($Rs32,$Rt32)", -tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel { +tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel { let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11111011000; @@ -757,15 +757,15 @@ let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; let isPredicatedNew = 1; +let BaseOpcode = "A2_add"; let CextOpcode = "A2_add"; let InputType = "reg"; -let BaseOpcode = "A2_add"; } def A2_pandf : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pu4) $Rd32 = and($Rs32,$Rt32)", -tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel { +tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel { let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11111001000; @@ -779,7 +779,7 @@ def A2_pandfnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pu4.new) $Rd32 = and($Rs32,$Rt32)", -tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel { +tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel { let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11111001000; @@ -794,7 +794,7 @@ def A2_pandt : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pu4) $Rd32 = and($Rs32,$Rt32)", -tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel { +tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11111001000; @@ -807,7 +807,7 @@ def A2_pandtnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pu4.new) $Rd32 = and($Rs32,$Rt32)", -tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel { +tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel { let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11111001000; @@ -821,7 +821,7 @@ def A2_porf : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pu4) $Rd32 = or($Rs32,$Rt32)", -tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel { +tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel { let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11111001001; @@ -835,7 +835,7 @@ def A2_porfnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pu4.new) $Rd32 = or($Rs32,$Rt32)", -tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel { +tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel { let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11111001001; @@ -850,7 +850,7 @@ def A2_port : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pu4) $Rd32 = or($Rs32,$Rt32)", -tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel { +tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11111001001; @@ -863,7 +863,7 @@ def A2_portnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pu4.new) $Rd32 = or($Rs32,$Rt32)", -tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel { +tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel { let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11111001001; @@ -877,7 +877,7 @@ def A2_psubf : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32), "if (!$Pu4) $Rd32 = sub($Rt32,$Rs32)", -tc_4c5ba658, TypeALU32_3op>, Enc_9b0bc1, PredNewRel { +tc_1c2c7a4a, TypeALU32_3op>, Enc_9b0bc1, PredNewRel { let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11111011001; @@ -891,7 +891,7 @@ def A2_psubfnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32), "if (!$Pu4.new) $Rd32 = sub($Rt32,$Rs32)", -tc_05c070ec, TypeALU32_3op>, Enc_9b0bc1, PredNewRel { +tc_442395f3, TypeALU32_3op>, Enc_9b0bc1, PredNewRel { let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11111011001; @@ -906,7 +906,7 @@ def A2_psubt : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32), "if ($Pu4) $Rd32 = sub($Rt32,$Rs32)", -tc_4c5ba658, TypeALU32_3op>, Enc_9b0bc1, PredNewRel { +tc_1c2c7a4a, TypeALU32_3op>, Enc_9b0bc1, PredNewRel { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11111011001; @@ -919,7 +919,7 @@ def A2_psubtnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32), "if ($Pu4.new) $Rd32 = sub($Rt32,$Rs32)", -tc_05c070ec, TypeALU32_3op>, Enc_9b0bc1, PredNewRel { +tc_442395f3, TypeALU32_3op>, Enc_9b0bc1, PredNewRel { let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11111011001; @@ -933,7 +933,7 @@ def A2_pxorf : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pu4) $Rd32 = xor($Rs32,$Rt32)", -tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel { +tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel { let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11111001011; @@ -947,7 +947,7 @@ def A2_pxorfnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pu4.new) $Rd32 = xor($Rs32,$Rt32)", -tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel { +tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel { let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11111001011; @@ -962,7 +962,7 @@ def A2_pxort : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pu4) $Rd32 = xor($Rs32,$Rt32)", -tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel { +tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54, PredNewRel { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11111001011; @@ -975,7 +975,7 @@ def A2_pxortnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pu4.new) $Rd32 = xor($Rs32,$Rt32)", -tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel { +tc_442395f3, TypeALU32_3op>, Enc_ea4c54, PredNewRel { let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11111001011; @@ -989,7 +989,7 @@ def A2_roundsat : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = round($Rss32):sat", -tc_cf8126ae, TypeS_2op>, Enc_90cd8b { +tc_d61dfdc3, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000110; let hasNewValue = 1; @@ -1001,7 +1001,7 @@ def A2_sat : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = sat($Rss32)", -tc_0ae0825c, TypeS_2op>, Enc_90cd8b { +tc_9f6cd987, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001000110; let hasNewValue = 1; @@ -1012,7 +1012,7 @@ def A2_satb : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = satb($Rs32)", -tc_0ae0825c, TypeS_2op>, Enc_5e2823 { +tc_9f6cd987, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000111; let Inst{31-21} = 0b10001100110; let hasNewValue = 1; @@ -1023,7 +1023,7 @@ def A2_sath : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = sath($Rs32)", -tc_0ae0825c, TypeS_2op>, Enc_5e2823 { +tc_9f6cd987, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10001100110; let hasNewValue = 1; @@ -1034,7 +1034,7 @@ def A2_satub : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = satub($Rs32)", -tc_0ae0825c, TypeS_2op>, Enc_5e2823 { +tc_9f6cd987, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10001100110; let hasNewValue = 1; @@ -1045,7 +1045,7 @@ def A2_satuh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = satuh($Rs32)", -tc_0ae0825c, TypeS_2op>, Enc_5e2823 { +tc_9f6cd987, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000101; let Inst{31-21} = 0b10001100110; let hasNewValue = 1; @@ -1056,22 +1056,22 @@ def A2_sub : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32,$Rs32)", -tc_5a2711e5, TypeALU32_3op>, Enc_bd6011, PredNewRel, ImmRegRel { +tc_713b66bf, TypeALU32_3op>, Enc_bd6011, PredNewRel, ImmRegRel { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110011001; let hasNewValue = 1; let opNewValue = 0; +let BaseOpcode = "A2_sub"; let CextOpcode = "A2_sub"; let InputType = "reg"; -let BaseOpcode = "A2_sub"; let isPredicable = 1; } def A2_subh_h16_hh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32.h,$Rs32.h):<<16", -tc_679309b8, TypeALU64>, Enc_bd6011 { +tc_01d44cb2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101011; @@ -1083,7 +1083,7 @@ def A2_subh_h16_hl : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32.h,$Rs32.l):<<16", -tc_679309b8, TypeALU64>, Enc_bd6011 { +tc_01d44cb2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101011; @@ -1095,7 +1095,7 @@ def A2_subh_h16_lh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32.l,$Rs32.h):<<16", -tc_679309b8, TypeALU64>, Enc_bd6011 { +tc_01d44cb2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101011; @@ -1107,7 +1107,7 @@ def A2_subh_h16_ll : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32.l,$Rs32.l):<<16", -tc_679309b8, TypeALU64>, Enc_bd6011 { +tc_01d44cb2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101011; @@ -1119,7 +1119,7 @@ def A2_subh_h16_sat_hh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32.h,$Rs32.h):sat:<<16", -tc_779080bf, TypeALU64>, Enc_bd6011 { +tc_8a825db2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101011; @@ -1132,7 +1132,7 @@ def A2_subh_h16_sat_hl : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32.h,$Rs32.l):sat:<<16", -tc_779080bf, TypeALU64>, Enc_bd6011 { +tc_8a825db2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101011; @@ -1145,7 +1145,7 @@ def A2_subh_h16_sat_lh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32.l,$Rs32.h):sat:<<16", -tc_779080bf, TypeALU64>, Enc_bd6011 { +tc_8a825db2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101011; @@ -1158,7 +1158,7 @@ def A2_subh_h16_sat_ll : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32.l,$Rs32.l):sat:<<16", -tc_779080bf, TypeALU64>, Enc_bd6011 { +tc_8a825db2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101011; @@ -1171,7 +1171,7 @@ def A2_subh_l16_hl : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32.l,$Rs32.h)", -tc_4414d8b1, TypeALU64>, Enc_bd6011 { +tc_f34c1c21, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101001; @@ -1183,7 +1183,7 @@ def A2_subh_l16_ll : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32.l,$Rs32.l)", -tc_4414d8b1, TypeALU64>, Enc_bd6011 { +tc_f34c1c21, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101001; @@ -1195,7 +1195,7 @@ def A2_subh_l16_sat_hl : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32.l,$Rs32.h):sat", -tc_779080bf, TypeALU64>, Enc_bd6011 { +tc_8a825db2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101001; @@ -1208,7 +1208,7 @@ def A2_subh_l16_sat_ll : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32.l,$Rs32.l):sat", -tc_779080bf, TypeALU64>, Enc_bd6011 { +tc_8a825db2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101001; @@ -1221,7 +1221,7 @@ def A2_subp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = sub($Rtt32,$Rss32)", -tc_946df596, TypeALU64>, Enc_ea23e4 { +tc_5da50c4b, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011001; @@ -1230,7 +1230,7 @@ def A2_subri : HInst< (outs IntRegs:$Rd32), (ins s32_0Imm:$Ii, IntRegs:$Rs32), "$Rd32 = sub(#$Ii,$Rs32)", -tc_5a2711e5, TypeALU32_2op>, Enc_140c83, PredNewRel, ImmRegRel { +tc_713b66bf, TypeALU32_2op>, Enc_140c83, PredNewRel, ImmRegRel { let Inst{31-22} = 0b0111011001; let hasNewValue = 1; let opNewValue = 0; @@ -1246,7 +1246,7 @@ def A2_subsat : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32,$Rs32):sat", -tc_61830035, TypeALU32_3op>, Enc_bd6011 { +tc_95a33176, TypeALU32_3op>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110110110; @@ -1260,7 +1260,7 @@ def A2_svaddh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = vaddh($Rs32,$Rt32)", -tc_5a2711e5, TypeALU32_3op>, Enc_5ab2be { +tc_713b66bf, TypeALU32_3op>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110110000; @@ -1273,7 +1273,7 @@ def A2_svaddhs : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = vaddh($Rs32,$Rt32):sat", -tc_61830035, TypeALU32_3op>, Enc_5ab2be { +tc_95a33176, TypeALU32_3op>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110110001; @@ -1288,7 +1288,7 @@ def A2_svadduhs : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = vadduh($Rs32,$Rt32):sat", -tc_61830035, TypeALU32_3op>, Enc_5ab2be { +tc_95a33176, TypeALU32_3op>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110110011; @@ -1303,7 +1303,7 @@ def A2_svavgh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = vavgh($Rs32,$Rt32)", -tc_1c80410a, TypeALU32_3op>, Enc_5ab2be { +tc_8b5bd4f5, TypeALU32_3op>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110111000; @@ -1317,7 +1317,7 @@ def A2_svavghs : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = vavgh($Rs32,$Rt32):rnd", -tc_d08ee0f4, TypeALU32_3op>, Enc_5ab2be { +tc_84a7500d, TypeALU32_3op>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110111001; @@ -1331,7 +1331,7 @@ def A2_svnavgh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = vnavgh($Rt32,$Rs32)", -tc_1c80410a, TypeALU32_3op>, Enc_bd6011 { +tc_8b5bd4f5, TypeALU32_3op>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110111011; @@ -1344,7 +1344,7 @@ def A2_svsubh : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = vsubh($Rt32,$Rs32)", -tc_5a2711e5, TypeALU32_3op>, Enc_bd6011 { +tc_713b66bf, TypeALU32_3op>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110110100; @@ -1356,7 +1356,7 @@ def A2_svsubhs : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = vsubh($Rt32,$Rs32):sat", -tc_61830035, TypeALU32_3op>, Enc_bd6011 { +tc_95a33176, TypeALU32_3op>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110110101; @@ -1370,7 +1370,7 @@ def A2_svsubuhs : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = vsubuh($Rt32,$Rs32):sat", -tc_61830035, TypeALU32_3op>, Enc_bd6011 { +tc_95a33176, TypeALU32_3op>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110110111; @@ -1384,7 +1384,7 @@ def A2_swiz : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = swiz($Rs32)", -tc_0ae0825c, TypeS_2op>, Enc_5e2823 { +tc_9f6cd987, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000111; let Inst{31-21} = 0b10001100100; let hasNewValue = 1; @@ -1394,7 +1394,7 @@ def A2_sxtb : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = sxtb($Rs32)", -tc_57890846, TypeALU32_2op>, Enc_5e2823, PredNewRel { +tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b01110000101; let hasNewValue = 1; @@ -1406,7 +1406,7 @@ def A2_sxth : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = sxth($Rs32)", -tc_57890846, TypeALU32_2op>, Enc_5e2823, PredNewRel { +tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b01110000111; let hasNewValue = 1; @@ -1418,7 +1418,7 @@ def A2_sxtw : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = sxtw($Rs32)", -tc_0ae0825c, TypeS_2op>, Enc_3a3d62 { +tc_9f6cd987, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10000100010; } @@ -1426,20 +1426,20 @@ def A2_tfr : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = $Rs32", -tc_57890846, TypeALU32_2op>, Enc_5e2823, PredNewRel { +tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b01110000011; let hasNewValue = 1; let opNewValue = 0; -let InputType = "reg"; let BaseOpcode = "A2_tfr"; +let InputType = "reg"; let isPredicable = 1; } def A2_tfrcrr : HInst< (outs IntRegs:$Rd32), (ins CtrRegs:$Cs32), "$Rd32 = $Cs32", -tc_b9272d6c, TypeCR>, Enc_0cb018 { +tc_7476d766, TypeCR>, Enc_0cb018 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b01101010000; let hasNewValue = 1; @@ -1449,14 +1449,14 @@ def A2_tfrf : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4) $Rd32 = $Rs32", -tc_4c5ba658, TypeALU32_2op>, PredNewRel, ImmRegRel { +tc_1c2c7a4a, TypeALU32_2op>, PredNewRel, ImmRegRel { let isPredicated = 1; let isPredicatedFalse = 1; let hasNewValue = 1; let opNewValue = 0; +let BaseOpcode = "A2_tfr"; let CextOpcode = "A2_tfr"; let InputType = "reg"; -let BaseOpcode = "A2_tfr"; let isPseudo = 1; let isCodeGenOnly = 1; } @@ -1464,15 +1464,15 @@ def A2_tfrfnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4.new) $Rd32 = $Rs32", -tc_05c070ec, TypeALU32_2op>, PredNewRel, ImmRegRel { +tc_442395f3, TypeALU32_2op>, PredNewRel, ImmRegRel { let isPredicated = 1; let isPredicatedFalse = 1; let hasNewValue = 1; let opNewValue = 0; let isPredicatedNew = 1; +let BaseOpcode = "A2_tfr"; let CextOpcode = "A2_tfr"; let InputType = "reg"; -let BaseOpcode = "A2_tfr"; let isPseudo = 1; let isCodeGenOnly = 1; } @@ -1480,7 +1480,7 @@ def A2_tfrih : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, u16_0Imm:$Ii), "$Rx32.h = #$Ii", -tc_5a2711e5, TypeALU32_2op>, Enc_51436c { +tc_713b66bf, TypeALU32_2op>, Enc_51436c { let Inst{21-21} = 0b1; let Inst{31-24} = 0b01110010; let hasNewValue = 1; @@ -1491,7 +1491,7 @@ def A2_tfril : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, u16_0Imm:$Ii), "$Rx32.l = #$Ii", -tc_5a2711e5, TypeALU32_2op>, Enc_51436c { +tc_713b66bf, TypeALU32_2op>, Enc_51436c { let Inst{21-21} = 0b1; let Inst{31-24} = 0b01110001; let hasNewValue = 1; @@ -1502,7 +1502,7 @@ def A2_tfrp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = $Rss32", -tc_5a2711e5, TypeALU32_2op>, PredNewRel { +tc_713b66bf, TypeALU32_2op>, PredNewRel { let BaseOpcode = "A2_tfrp"; let isPredicable = 1; let isPseudo = 1; @@ -1511,7 +1511,7 @@ def A2_tfrpf : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pu4, DoubleRegs:$Rss32), "if (!$Pu4) $Rdd32 = $Rss32", -tc_5a2711e5, TypeALU32_2op>, PredNewRel { +tc_713b66bf, TypeALU32_2op>, PredNewRel { let isPredicated = 1; let isPredicatedFalse = 1; let BaseOpcode = "A2_tfrp"; @@ -1521,7 +1521,7 @@ def A2_tfrpfnew : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pu4, DoubleRegs:$Rss32), "if (!$Pu4.new) $Rdd32 = $Rss32", -tc_1ae57e39, TypeALU32_2op>, PredNewRel { +tc_86173609, TypeALU32_2op>, PredNewRel { let isPredicated = 1; let isPredicatedFalse = 1; let isPredicatedNew = 1; @@ -1532,7 +1532,7 @@ def A2_tfrpi : HInst< (outs DoubleRegs:$Rdd32), (ins s8_0Imm:$Ii), "$Rdd32 = #$Ii", -tc_5a2711e5, TypeALU64> { +tc_713b66bf, TypeALU64> { let isReMaterializable = 1; let isAsCheapAsAMove = 1; let isMoveImm = 1; @@ -1542,7 +1542,7 @@ def A2_tfrpt : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pu4, DoubleRegs:$Rss32), "if ($Pu4) $Rdd32 = $Rss32", -tc_5a2711e5, TypeALU32_2op>, PredNewRel { +tc_713b66bf, TypeALU32_2op>, PredNewRel { let isPredicated = 1; let BaseOpcode = "A2_tfrp"; let isPseudo = 1; @@ -1551,7 +1551,7 @@ def A2_tfrptnew : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pu4, DoubleRegs:$Rss32), "if ($Pu4.new) $Rdd32 = $Rss32", -tc_1ae57e39, TypeALU32_2op>, PredNewRel { +tc_86173609, TypeALU32_2op>, PredNewRel { let isPredicated = 1; let isPredicatedNew = 1; let BaseOpcode = "A2_tfrp"; @@ -1561,7 +1561,7 @@ def A2_tfrrcr : HInst< (outs CtrRegs:$Cd32), (ins IntRegs:$Rs32), "$Cd32 = $Rs32", -tc_434c8e1e, TypeCR>, Enc_bd811a { +tc_49fdfd4b, TypeCR>, Enc_bd811a { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b01100010001; let hasNewValue = 1; @@ -1571,14 +1571,14 @@ def A2_tfrsi : HInst< (outs IntRegs:$Rd32), (ins s32_0Imm:$Ii), "$Rd32 = #$Ii", -tc_57890846, TypeALU32_2op>, Enc_5e87ce, PredNewRel, ImmRegRel { +tc_c57d9f39, TypeALU32_2op>, Enc_5e87ce, PredNewRel, ImmRegRel { let Inst{21-21} = 0b0; let Inst{31-24} = 0b01111000; let hasNewValue = 1; let opNewValue = 0; +let BaseOpcode = "A2_tfrsi"; let CextOpcode = "A2_tfr"; let InputType = "imm"; -let BaseOpcode = "A2_tfrsi"; let isPredicable = 1; let isReMaterializable = 1; let isAsCheapAsAMove = 1; @@ -1593,13 +1593,13 @@ def A2_tfrt : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4) $Rd32 = $Rs32", -tc_4c5ba658, TypeALU32_2op>, PredNewRel, ImmRegRel { +tc_1c2c7a4a, TypeALU32_2op>, PredNewRel, ImmRegRel { let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; +let BaseOpcode = "A2_tfr"; let CextOpcode = "A2_tfr"; let InputType = "reg"; -let BaseOpcode = "A2_tfr"; let isPseudo = 1; let isCodeGenOnly = 1; } @@ -1607,14 +1607,14 @@ def A2_tfrtnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4.new) $Rd32 = $Rs32", -tc_05c070ec, TypeALU32_2op>, PredNewRel, ImmRegRel { +tc_442395f3, TypeALU32_2op>, PredNewRel, ImmRegRel { let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; let isPredicatedNew = 1; +let BaseOpcode = "A2_tfr"; let CextOpcode = "A2_tfr"; let InputType = "reg"; -let BaseOpcode = "A2_tfr"; let isPseudo = 1; let isCodeGenOnly = 1; } @@ -1622,7 +1622,7 @@ def A2_vabsh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = vabsh($Rss32)", -tc_cf8126ae, TypeS_2op>, Enc_b9c5fb { +tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10000000010; let prefersSlot3 = 1; @@ -1631,7 +1631,7 @@ def A2_vabshsat : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = vabsh($Rss32):sat", -tc_cf8126ae, TypeS_2op>, Enc_b9c5fb { +tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000101; let Inst{31-21} = 0b10000000010; let prefersSlot3 = 1; @@ -1641,7 +1641,7 @@ def A2_vabsw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = vabsw($Rss32)", -tc_cf8126ae, TypeS_2op>, Enc_b9c5fb { +tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10000000010; let prefersSlot3 = 1; @@ -1650,7 +1650,7 @@ def A2_vabswsat : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = vabsw($Rss32):sat", -tc_cf8126ae, TypeS_2op>, Enc_b9c5fb { +tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000111; let Inst{31-21} = 0b10000000010; let prefersSlot3 = 1; @@ -1660,7 +1660,7 @@ def A2_vaddb_map : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vaddb($Rss32,$Rtt32)", -tc_946df596, TypeMAPPING> { +tc_5da50c4b, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -1668,7 +1668,7 @@ def A2_vaddh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vaddh($Rss32,$Rtt32)", -tc_946df596, TypeALU64>, Enc_a56825 { +tc_5da50c4b, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011000; @@ -1677,7 +1677,7 @@ def A2_vaddhs : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vaddh($Rss32,$Rtt32):sat", -tc_779080bf, TypeALU64>, Enc_a56825 { +tc_8a825db2, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011000; @@ -1688,7 +1688,7 @@ def A2_vaddub : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vaddub($Rss32,$Rtt32)", -tc_946df596, TypeALU64>, Enc_a56825 { +tc_5da50c4b, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011000; @@ -1697,7 +1697,7 @@ def A2_vaddubs : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vaddub($Rss32,$Rtt32):sat", -tc_779080bf, TypeALU64>, Enc_a56825 { +tc_8a825db2, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011000; @@ -1708,7 +1708,7 @@ def A2_vadduhs : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vadduh($Rss32,$Rtt32):sat", -tc_779080bf, TypeALU64>, Enc_a56825 { +tc_8a825db2, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011000; @@ -1719,7 +1719,7 @@ def A2_vaddw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vaddw($Rss32,$Rtt32)", -tc_946df596, TypeALU64>, Enc_a56825 { +tc_5da50c4b, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011000; @@ -1728,7 +1728,7 @@ def A2_vaddws : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vaddw($Rss32,$Rtt32):sat", -tc_779080bf, TypeALU64>, Enc_a56825 { +tc_8a825db2, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011000; @@ -1739,7 +1739,7 @@ def A2_vavgh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vavgh($Rss32,$Rtt32)", -tc_6132ba3d, TypeALU64>, Enc_a56825 { +tc_f098b237, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011010; @@ -1749,7 +1749,7 @@ def A2_vavghcr : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vavgh($Rss32,$Rtt32):crnd", -tc_002cb246, TypeALU64>, Enc_a56825 { +tc_0dfac0a7, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011010; @@ -1759,7 +1759,7 @@ def A2_vavghr : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vavgh($Rss32,$Rtt32):rnd", -tc_e4a7f9f0, TypeALU64>, Enc_a56825 { +tc_20131976, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011010; @@ -1769,7 +1769,7 @@ def A2_vavgub : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vavgub($Rss32,$Rtt32)", -tc_6132ba3d, TypeALU64>, Enc_a56825 { +tc_f098b237, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011010; @@ -1779,7 +1779,7 @@ def A2_vavgubr : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vavgub($Rss32,$Rtt32):rnd", -tc_e4a7f9f0, TypeALU64>, Enc_a56825 { +tc_20131976, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011010; @@ -1789,7 +1789,7 @@ def A2_vavguh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vavguh($Rss32,$Rtt32)", -tc_6132ba3d, TypeALU64>, Enc_a56825 { +tc_f098b237, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011010; @@ -1799,7 +1799,7 @@ def A2_vavguhr : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vavguh($Rss32,$Rtt32):rnd", -tc_e4a7f9f0, TypeALU64>, Enc_a56825 { +tc_20131976, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011010; @@ -1809,7 +1809,7 @@ def A2_vavguw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vavguw($Rss32,$Rtt32)", -tc_6132ba3d, TypeALU64>, Enc_a56825 { +tc_f098b237, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011011; @@ -1819,7 +1819,7 @@ def A2_vavguwr : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vavguw($Rss32,$Rtt32):rnd", -tc_e4a7f9f0, TypeALU64>, Enc_a56825 { +tc_20131976, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011011; @@ -1829,7 +1829,7 @@ def A2_vavgw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vavgw($Rss32,$Rtt32)", -tc_6132ba3d, TypeALU64>, Enc_a56825 { +tc_f098b237, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011011; @@ -1839,7 +1839,7 @@ def A2_vavgwcr : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vavgw($Rss32,$Rtt32):crnd", -tc_002cb246, TypeALU64>, Enc_a56825 { +tc_0dfac0a7, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011011; @@ -1849,7 +1849,7 @@ def A2_vavgwr : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vavgw($Rss32,$Rtt32):rnd", -tc_e4a7f9f0, TypeALU64>, Enc_a56825 { +tc_20131976, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011011; @@ -1859,7 +1859,7 @@ def A2_vcmpbeq : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = vcmpb.eq($Rss32,$Rtt32)", -tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { +tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b110000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010000; @@ -1868,7 +1868,7 @@ def A2_vcmpbgtu : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = vcmpb.gtu($Rss32,$Rtt32)", -tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { +tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b111000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010000; @@ -1877,7 +1877,7 @@ def A2_vcmpheq : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = vcmph.eq($Rss32,$Rtt32)", -tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { +tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b011000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010000; @@ -1886,7 +1886,7 @@ def A2_vcmphgt : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = vcmph.gt($Rss32,$Rtt32)", -tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { +tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b100000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010000; @@ -1895,7 +1895,7 @@ def A2_vcmphgtu : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = vcmph.gtu($Rss32,$Rtt32)", -tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { +tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b101000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010000; @@ -1904,7 +1904,7 @@ def A2_vcmpweq : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = vcmpw.eq($Rss32,$Rtt32)", -tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { +tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010000; @@ -1913,7 +1913,7 @@ def A2_vcmpwgt : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = vcmpw.gt($Rss32,$Rtt32)", -tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { +tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b001000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010000; @@ -1922,7 +1922,7 @@ def A2_vcmpwgtu : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = vcmpw.gtu($Rss32,$Rtt32)", -tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { +tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b010000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010000; @@ -1931,7 +1931,7 @@ def A2_vconj : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = vconj($Rss32):sat", -tc_cf8126ae, TypeS_2op>, Enc_b9c5fb { +tc_d61dfdc3, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000111; let Inst{31-21} = 0b10000000100; let prefersSlot3 = 1; @@ -1941,7 +1941,7 @@ def A2_vmaxb : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vmaxb($Rtt32,$Rss32)", -tc_779080bf, TypeALU64>, Enc_ea23e4 { +tc_8a825db2, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011110; @@ -1951,7 +1951,7 @@ def A2_vmaxh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vmaxh($Rtt32,$Rss32)", -tc_779080bf, TypeALU64>, Enc_ea23e4 { +tc_8a825db2, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011110; @@ -1961,7 +1961,7 @@ def A2_vmaxub : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vmaxub($Rtt32,$Rss32)", -tc_779080bf, TypeALU64>, Enc_ea23e4 { +tc_8a825db2, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011110; @@ -1971,7 +1971,7 @@ def A2_vmaxuh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vmaxuh($Rtt32,$Rss32)", -tc_779080bf, TypeALU64>, Enc_ea23e4 { +tc_8a825db2, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011110; @@ -1981,7 +1981,7 @@ def A2_vmaxuw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vmaxuw($Rtt32,$Rss32)", -tc_779080bf, TypeALU64>, Enc_ea23e4 { +tc_8a825db2, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011101; @@ -1991,7 +1991,7 @@ def A2_vmaxw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vmaxw($Rtt32,$Rss32)", -tc_779080bf, TypeALU64>, Enc_ea23e4 { +tc_8a825db2, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011110; @@ -2001,7 +2001,7 @@ def A2_vminb : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vminb($Rtt32,$Rss32)", -tc_779080bf, TypeALU64>, Enc_ea23e4 { +tc_8a825db2, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011110; @@ -2011,7 +2011,7 @@ def A2_vminh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vminh($Rtt32,$Rss32)", -tc_779080bf, TypeALU64>, Enc_ea23e4 { +tc_8a825db2, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011101; @@ -2021,7 +2021,7 @@ def A2_vminub : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vminub($Rtt32,$Rss32)", -tc_779080bf, TypeALU64>, Enc_ea23e4 { +tc_8a825db2, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011101; @@ -2031,7 +2031,7 @@ def A2_vminuh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vminuh($Rtt32,$Rss32)", -tc_779080bf, TypeALU64>, Enc_ea23e4 { +tc_8a825db2, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011101; @@ -2041,7 +2041,7 @@ def A2_vminuw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vminuw($Rtt32,$Rss32)", -tc_779080bf, TypeALU64>, Enc_ea23e4 { +tc_8a825db2, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011101; @@ -2051,7 +2051,7 @@ def A2_vminw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vminw($Rtt32,$Rss32)", -tc_779080bf, TypeALU64>, Enc_ea23e4 { +tc_8a825db2, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011101; @@ -2061,7 +2061,7 @@ def A2_vnavgh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vnavgh($Rtt32,$Rss32)", -tc_6132ba3d, TypeALU64>, Enc_ea23e4 { +tc_f098b237, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011100; @@ -2071,7 +2071,7 @@ def A2_vnavghcr : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vnavgh($Rtt32,$Rss32):crnd:sat", -tc_002cb246, TypeALU64>, Enc_ea23e4 { +tc_0dfac0a7, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011100; @@ -2082,7 +2082,7 @@ def A2_vnavghr : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vnavgh($Rtt32,$Rss32):rnd:sat", -tc_002cb246, TypeALU64>, Enc_ea23e4 { +tc_0dfac0a7, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011100; @@ -2093,7 +2093,7 @@ def A2_vnavgw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vnavgw($Rtt32,$Rss32)", -tc_6132ba3d, TypeALU64>, Enc_ea23e4 { +tc_f098b237, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011100; @@ -2103,7 +2103,7 @@ def A2_vnavgwcr : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vnavgw($Rtt32,$Rss32):crnd:sat", -tc_002cb246, TypeALU64>, Enc_ea23e4 { +tc_0dfac0a7, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011100; @@ -2114,7 +2114,7 @@ def A2_vnavgwr : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vnavgw($Rtt32,$Rss32):rnd:sat", -tc_002cb246, TypeALU64>, Enc_ea23e4 { +tc_0dfac0a7, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011100; @@ -2125,7 +2125,7 @@ def A2_vraddub : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vraddub($Rss32,$Rtt32)", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000010; @@ -2135,7 +2135,7 @@ def A2_vraddub_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vraddub($Rss32,$Rtt32)", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010010; @@ -2146,7 +2146,7 @@ def A2_vrsadub : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrsadub($Rss32,$Rtt32)", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000010; @@ -2156,7 +2156,7 @@ def A2_vrsadub_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrsadub($Rss32,$Rtt32)", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010010; @@ -2167,7 +2167,7 @@ def A2_vsubb_map : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vsubb($Rss32,$Rtt32)", -tc_946df596, TypeMAPPING> { +tc_5da50c4b, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -2175,7 +2175,7 @@ def A2_vsubh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vsubh($Rtt32,$Rss32)", -tc_946df596, TypeALU64>, Enc_ea23e4 { +tc_5da50c4b, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011001; @@ -2184,7 +2184,7 @@ def A2_vsubhs : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vsubh($Rtt32,$Rss32):sat", -tc_779080bf, TypeALU64>, Enc_ea23e4 { +tc_8a825db2, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011001; @@ -2195,7 +2195,7 @@ def A2_vsubub : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vsubub($Rtt32,$Rss32)", -tc_946df596, TypeALU64>, Enc_ea23e4 { +tc_5da50c4b, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011001; @@ -2204,7 +2204,7 @@ def A2_vsububs : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vsubub($Rtt32,$Rss32):sat", -tc_779080bf, TypeALU64>, Enc_ea23e4 { +tc_8a825db2, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011001; @@ -2215,7 +2215,7 @@ def A2_vsubuhs : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vsubuh($Rtt32,$Rss32):sat", -tc_779080bf, TypeALU64>, Enc_ea23e4 { +tc_8a825db2, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011001; @@ -2226,7 +2226,7 @@ def A2_vsubw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vsubw($Rtt32,$Rss32)", -tc_946df596, TypeALU64>, Enc_ea23e4 { +tc_5da50c4b, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011001; @@ -2235,7 +2235,7 @@ def A2_vsubws : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vsubw($Rtt32,$Rss32):sat", -tc_779080bf, TypeALU64>, Enc_ea23e4 { +tc_8a825db2, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011001; @@ -2246,14 +2246,14 @@ def A2_xor : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = xor($Rs32,$Rt32)", -tc_5a2711e5, TypeALU32_3op>, Enc_5ab2be, PredNewRel { +tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110001011; let hasNewValue = 1; let opNewValue = 0; -let InputType = "reg"; let BaseOpcode = "A2_xor"; +let InputType = "reg"; let isCommutable = 1; let isPredicable = 1; } @@ -2261,7 +2261,7 @@ def A2_xorp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = xor($Rss32,$Rtt32)", -tc_946df596, TypeALU64>, Enc_a56825 { +tc_5da50c4b, TypeALU64>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011111; @@ -2271,7 +2271,7 @@ def A2_zxtb : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = zxtb($Rs32)", -tc_5a2711e5, TypeALU32_2op>, PredNewRel { +tc_713b66bf, TypeALU32_2op>, PredNewRel { let hasNewValue = 1; let opNewValue = 0; let BaseOpcode = "A2_zxtb"; @@ -2283,7 +2283,7 @@ def A2_zxth : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = zxth($Rs32)", -tc_57890846, TypeALU32_2op>, Enc_5e2823, PredNewRel { +tc_c57d9f39, TypeALU32_2op>, Enc_5e2823, PredNewRel { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b01110000110; let hasNewValue = 1; @@ -2295,7 +2295,7 @@ def A4_addp_c : HInst< (outs DoubleRegs:$Rdd32, PredRegs:$Px4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Px4in), "$Rdd32 = add($Rss32,$Rtt32,$Px4):carry", -tc_9c3ecd83, TypeS_3op>, Enc_2b3f60 { +tc_1d41f8b7, TypeS_3op>, Enc_2b3f60 { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000010110; @@ -2306,7 +2306,7 @@ def A4_andn : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = and($Rt32,~$Rs32)", -tc_5a2711e5, TypeALU32_3op>, Enc_bd6011 { +tc_713b66bf, TypeALU32_3op>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110001100; @@ -2318,7 +2318,7 @@ def A4_andnp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = and($Rtt32,~$Rss32)", -tc_946df596, TypeALU64>, Enc_ea23e4 { +tc_5da50c4b, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011111; @@ -2327,7 +2327,7 @@ def A4_bitsplit : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = bitsplit($Rs32,$Rt32)", -tc_4414d8b1, TypeALU64>, Enc_be32a5 { +tc_f34c1c21, TypeALU64>, Enc_be32a5 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010100001; @@ -2337,7 +2337,7 @@ def A4_bitspliti : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rdd32 = bitsplit($Rs32,#$Ii)", -tc_4414d8b1, TypeS_2op>, Enc_311abd { +tc_f34c1c21, TypeS_2op>, Enc_311abd { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001000110; @@ -2347,14 +2347,14 @@ def A4_boundscheck : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, DoubleRegs:$Rtt32), "$Pd4 = boundscheck($Rs32,$Rtt32)", -tc_85d5d03f, TypeALU64> { +tc_4a55d03c, TypeALU64> { let isPseudo = 1; } def A4_boundscheck_hi : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = boundscheck($Rss32,$Rtt32):raw:hi", -tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { +tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b101000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11010010000; @@ -2363,7 +2363,7 @@ def A4_boundscheck_lo : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = boundscheck($Rss32,$Rtt32):raw:lo", -tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { +tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b100000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11010010000; @@ -2372,7 +2372,7 @@ def A4_cmpbeq : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = cmpb.eq($Rs32,$Rt32)", -tc_85d5d03f, TypeS_3op>, Enc_c2b48e, ImmRegRel { +tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel { let Inst{7-2} = 0b110000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111110; @@ -2385,7 +2385,7 @@ def A4_cmpbeqi : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, u8_0Imm:$Ii), "$Pd4 = cmpb.eq($Rs32,#$Ii)", -tc_643b4717, TypeALU64>, Enc_08d755, ImmRegRel { +tc_a1297125, TypeALU64>, Enc_08d755, ImmRegRel { let Inst{4-2} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11011101000; @@ -2398,7 +2398,7 @@ def A4_cmpbgt : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = cmpb.gt($Rs32,$Rt32)", -tc_85d5d03f, TypeS_3op>, Enc_c2b48e, ImmRegRel { +tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel { let Inst{7-2} = 0b010000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111110; @@ -2410,7 +2410,7 @@ def A4_cmpbgti : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, s8_0Imm:$Ii), "$Pd4 = cmpb.gt($Rs32,#$Ii)", -tc_643b4717, TypeALU64>, Enc_08d755, ImmRegRel { +tc_a1297125, TypeALU64>, Enc_08d755, ImmRegRel { let Inst{4-2} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11011101001; @@ -2422,7 +2422,7 @@ def A4_cmpbgtu : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = cmpb.gtu($Rs32,$Rt32)", -tc_85d5d03f, TypeS_3op>, Enc_c2b48e, ImmRegRel { +tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel { let Inst{7-2} = 0b111000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111110; @@ -2434,7 +2434,7 @@ def A4_cmpbgtui : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, u32_0Imm:$Ii), "$Pd4 = cmpb.gtu($Rs32,#$Ii)", -tc_643b4717, TypeALU64>, Enc_02553a, ImmRegRel { +tc_a1297125, TypeALU64>, Enc_02553a, ImmRegRel { let Inst{4-2} = 0b000; let Inst{13-12} = 0b00; let Inst{31-21} = 0b11011101010; @@ -2451,7 +2451,7 @@ def A4_cmpheq : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = cmph.eq($Rs32,$Rt32)", -tc_85d5d03f, TypeS_3op>, Enc_c2b48e, ImmRegRel { +tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel { let Inst{7-2} = 0b011000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111110; @@ -2464,7 +2464,7 @@ def A4_cmpheqi : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Pd4 = cmph.eq($Rs32,#$Ii)", -tc_643b4717, TypeALU64>, Enc_08d755, ImmRegRel { +tc_a1297125, TypeALU64>, Enc_08d755, ImmRegRel { let Inst{4-2} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11011101000; @@ -2482,7 +2482,7 @@ def A4_cmphgt : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = cmph.gt($Rs32,$Rt32)", -tc_85d5d03f, TypeS_3op>, Enc_c2b48e, ImmRegRel { +tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel { let Inst{7-2} = 0b100000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111110; @@ -2494,7 +2494,7 @@ def A4_cmphgti : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Pd4 = cmph.gt($Rs32,#$Ii)", -tc_643b4717, TypeALU64>, Enc_08d755, ImmRegRel { +tc_a1297125, TypeALU64>, Enc_08d755, ImmRegRel { let Inst{4-2} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11011101001; @@ -2511,7 +2511,7 @@ def A4_cmphgtu : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = cmph.gtu($Rs32,$Rt32)", -tc_85d5d03f, TypeS_3op>, Enc_c2b48e, ImmRegRel { +tc_4a55d03c, TypeS_3op>, Enc_c2b48e, ImmRegRel { let Inst{7-2} = 0b101000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111110; @@ -2523,7 +2523,7 @@ def A4_cmphgtui : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, u32_0Imm:$Ii), "$Pd4 = cmph.gtu($Rs32,#$Ii)", -tc_643b4717, TypeALU64>, Enc_02553a, ImmRegRel { +tc_a1297125, TypeALU64>, Enc_02553a, ImmRegRel { let Inst{4-2} = 0b010; let Inst{13-12} = 0b00; let Inst{31-21} = 0b11011101010; @@ -2540,7 +2540,7 @@ def A4_combineii : HInst< (outs DoubleRegs:$Rdd32), (ins s8_0Imm:$Ii, u32_0Imm:$II), "$Rdd32 = combine(#$Ii,#$II)", -tc_5a2711e5, TypeALU32_2op>, Enc_f0cca7 { +tc_713b66bf, TypeALU32_2op>, Enc_f0cca7 { let Inst{31-21} = 0b01111100100; let isExtendable = 1; let opExtendable = 2; @@ -2552,7 +2552,7 @@ def A4_combineir : HInst< (outs DoubleRegs:$Rdd32), (ins s32_0Imm:$Ii, IntRegs:$Rs32), "$Rdd32 = combine(#$Ii,$Rs32)", -tc_5a2711e5, TypeALU32_2op>, Enc_9cdba7 { +tc_713b66bf, TypeALU32_2op>, Enc_9cdba7 { let Inst{13-13} = 0b1; let Inst{31-21} = 0b01110011001; let isExtendable = 1; @@ -2565,7 +2565,7 @@ def A4_combineri : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Rdd32 = combine($Rs32,#$Ii)", -tc_5a2711e5, TypeALU32_2op>, Enc_9cdba7 { +tc_713b66bf, TypeALU32_2op>, Enc_9cdba7 { let Inst{13-13} = 0b1; let Inst{31-21} = 0b01110011000; let isExtendable = 1; @@ -2578,7 +2578,7 @@ def A4_cround_ri : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = cround($Rs32,#$Ii)", -tc_002cb246, TypeS_2op>, Enc_a05677 { +tc_0dfac0a7, TypeS_2op>, Enc_a05677 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001100111; @@ -2590,7 +2590,7 @@ def A4_cround_rr : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = cround($Rs32,$Rt32)", -tc_002cb246, TypeS_3op>, Enc_5ab2be { +tc_0dfac0a7, TypeS_3op>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000110110; @@ -2602,14 +2602,14 @@ def A4_ext : HInst< (outs), (ins u26_6Imm:$Ii), "immext(#$Ii)", -tc_862b3e70, TypeEXTENDER>, Enc_2b518f { +tc_112d30d6, TypeEXTENDER>, Enc_2b518f { let Inst{31-28} = 0b0000; } def A4_modwrapu : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = modwrap($Rs32,$Rt32)", -tc_779080bf, TypeALU64>, Enc_5ab2be { +tc_8a825db2, TypeALU64>, Enc_5ab2be { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011111; @@ -2621,7 +2621,7 @@ def A4_orn : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = or($Rt32,~$Rs32)", -tc_5a2711e5, TypeALU32_3op>, Enc_bd6011 { +tc_713b66bf, TypeALU32_3op>, Enc_bd6011 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110001101; @@ -2633,7 +2633,7 @@ def A4_ornp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = or($Rtt32,~$Rss32)", -tc_946df596, TypeALU64>, Enc_ea23e4 { +tc_5da50c4b, TypeALU64>, Enc_ea23e4 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010011111; @@ -2642,7 +2642,7 @@ def A4_paslhf : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4) $Rd32 = aslh($Rs32)", -tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1010; let Inst{31-21} = 0b01110000000; @@ -2656,7 +2656,7 @@ def A4_paslhfnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4.new) $Rd32 = aslh($Rs32)", -tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1011; let Inst{31-21} = 0b01110000000; @@ -2671,7 +2671,7 @@ def A4_paslht : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4) $Rd32 = aslh($Rs32)", -tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1000; let Inst{31-21} = 0b01110000000; @@ -2684,7 +2684,7 @@ def A4_paslhtnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4.new) $Rd32 = aslh($Rs32)", -tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1001; let Inst{31-21} = 0b01110000000; @@ -2698,7 +2698,7 @@ def A4_pasrhf : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4) $Rd32 = asrh($Rs32)", -tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1010; let Inst{31-21} = 0b01110000001; @@ -2712,7 +2712,7 @@ def A4_pasrhfnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4.new) $Rd32 = asrh($Rs32)", -tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1011; let Inst{31-21} = 0b01110000001; @@ -2727,7 +2727,7 @@ def A4_pasrht : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4) $Rd32 = asrh($Rs32)", -tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1000; let Inst{31-21} = 0b01110000001; @@ -2740,7 +2740,7 @@ def A4_pasrhtnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4.new) $Rd32 = asrh($Rs32)", -tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1001; let Inst{31-21} = 0b01110000001; @@ -2754,7 +2754,7 @@ def A4_psxtbf : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4) $Rd32 = sxtb($Rs32)", -tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1010; let Inst{31-21} = 0b01110000101; @@ -2768,7 +2768,7 @@ def A4_psxtbfnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4.new) $Rd32 = sxtb($Rs32)", -tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1011; let Inst{31-21} = 0b01110000101; @@ -2783,7 +2783,7 @@ def A4_psxtbt : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4) $Rd32 = sxtb($Rs32)", -tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1000; let Inst{31-21} = 0b01110000101; @@ -2796,7 +2796,7 @@ def A4_psxtbtnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4.new) $Rd32 = sxtb($Rs32)", -tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1001; let Inst{31-21} = 0b01110000101; @@ -2810,7 +2810,7 @@ def A4_psxthf : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4) $Rd32 = sxth($Rs32)", -tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1010; let Inst{31-21} = 0b01110000111; @@ -2824,7 +2824,7 @@ def A4_psxthfnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4.new) $Rd32 = sxth($Rs32)", -tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1011; let Inst{31-21} = 0b01110000111; @@ -2839,7 +2839,7 @@ def A4_psxtht : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4) $Rd32 = sxth($Rs32)", -tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1000; let Inst{31-21} = 0b01110000111; @@ -2852,7 +2852,7 @@ def A4_psxthtnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4.new) $Rd32 = sxth($Rs32)", -tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1001; let Inst{31-21} = 0b01110000111; @@ -2866,7 +2866,7 @@ def A4_pzxtbf : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4) $Rd32 = zxtb($Rs32)", -tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1010; let Inst{31-21} = 0b01110000100; @@ -2880,7 +2880,7 @@ def A4_pzxtbfnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4.new) $Rd32 = zxtb($Rs32)", -tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1011; let Inst{31-21} = 0b01110000100; @@ -2895,7 +2895,7 @@ def A4_pzxtbt : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4) $Rd32 = zxtb($Rs32)", -tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1000; let Inst{31-21} = 0b01110000100; @@ -2908,7 +2908,7 @@ def A4_pzxtbtnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4.new) $Rd32 = zxtb($Rs32)", -tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1001; let Inst{31-21} = 0b01110000100; @@ -2922,7 +2922,7 @@ def A4_pzxthf : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4) $Rd32 = zxth($Rs32)", -tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1010; let Inst{31-21} = 0b01110000110; @@ -2936,7 +2936,7 @@ def A4_pzxthfnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4.new) $Rd32 = zxth($Rs32)", -tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1011; let Inst{31-21} = 0b01110000110; @@ -2951,7 +2951,7 @@ def A4_pzxtht : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4) $Rd32 = zxth($Rs32)", -tc_5a2711e5, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_713b66bf, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1000; let Inst{31-21} = 0b01110000110; @@ -2964,7 +2964,7 @@ def A4_pzxthtnew : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4.new) $Rd32 = zxth($Rs32)", -tc_1ae57e39, TypeALU32_2op>, Enc_fb6577, PredNewRel { +tc_86173609, TypeALU32_2op>, Enc_fb6577, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1001; let Inst{31-21} = 0b01110000110; @@ -2978,7 +2978,7 @@ def A4_rcmpeq : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = cmp.eq($Rs32,$Rt32)", -tc_5a2711e5, TypeALU32_3op>, Enc_5ab2be, ImmRegRel { +tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, ImmRegRel { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110011010; @@ -2992,7 +2992,7 @@ def A4_rcmpeqi : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Rd32 = cmp.eq($Rs32,#$Ii)", -tc_5a2711e5, TypeALU32_2op>, Enc_b8c967, ImmRegRel { +tc_713b66bf, TypeALU32_2op>, Enc_b8c967, ImmRegRel { let Inst{13-13} = 0b1; let Inst{31-21} = 0b01110011010; let hasNewValue = 1; @@ -3009,7 +3009,7 @@ def A4_rcmpneq : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = !cmp.eq($Rs32,$Rt32)", -tc_5a2711e5, TypeALU32_3op>, Enc_5ab2be, ImmRegRel { +tc_713b66bf, TypeALU32_3op>, Enc_5ab2be, ImmRegRel { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110011011; @@ -3023,7 +3023,7 @@ def A4_rcmpneqi : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Rd32 = !cmp.eq($Rs32,#$Ii)", -tc_5a2711e5, TypeALU32_2op>, Enc_b8c967, ImmRegRel { +tc_713b66bf, TypeALU32_2op>, Enc_b8c967, ImmRegRel { let Inst{13-13} = 0b1; let Inst{31-21} = 0b01110011011; let hasNewValue = 1; @@ -3040,7 +3040,7 @@ def A4_round_ri : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = round($Rs32,#$Ii)", -tc_002cb246, TypeS_2op>, Enc_a05677 { +tc_0dfac0a7, TypeS_2op>, Enc_a05677 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001100111; @@ -3052,7 +3052,7 @@ def A4_round_ri_sat : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = round($Rs32,#$Ii):sat", -tc_002cb246, TypeS_2op>, Enc_a05677 { +tc_0dfac0a7, TypeS_2op>, Enc_a05677 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001100111; @@ -3065,7 +3065,7 @@ def A4_round_rr : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = round($Rs32,$Rt32)", -tc_002cb246, TypeS_3op>, Enc_5ab2be { +tc_0dfac0a7, TypeS_3op>, Enc_5ab2be { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000110110; @@ -3077,7 +3077,7 @@ def A4_round_rr_sat : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = round($Rs32,$Rt32):sat", -tc_002cb246, TypeS_3op>, Enc_5ab2be { +tc_0dfac0a7, TypeS_3op>, Enc_5ab2be { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000110110; @@ -3090,7 +3090,7 @@ def A4_subp_c : HInst< (outs DoubleRegs:$Rdd32, PredRegs:$Px4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Px4in), "$Rdd32 = sub($Rss32,$Rtt32,$Px4):carry", -tc_9c3ecd83, TypeS_3op>, Enc_2b3f60 { +tc_1d41f8b7, TypeS_3op>, Enc_2b3f60 { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000010111; @@ -3101,7 +3101,7 @@ def A4_tfrcpp : HInst< (outs DoubleRegs:$Rdd32), (ins CtrRegs64:$Css32), "$Rdd32 = $Css32", -tc_b9272d6c, TypeCR>, Enc_667b39 { +tc_7476d766, TypeCR>, Enc_667b39 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b01101000000; } @@ -3109,7 +3109,7 @@ def A4_tfrpcp : HInst< (outs CtrRegs64:$Cdd32), (ins DoubleRegs:$Rss32), "$Cdd32 = $Rss32", -tc_434c8e1e, TypeCR>, Enc_0ed752 { +tc_49fdfd4b, TypeCR>, Enc_0ed752 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b01100011001; } @@ -3117,7 +3117,7 @@ def A4_tlbmatch : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Pd4 = tlbmatch($Rss32,$Rt32)", -tc_4837eefb, TypeALU64>, Enc_03833b { +tc_d68dca5c, TypeALU64>, Enc_03833b { let Inst{7-2} = 0b011000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11010010000; @@ -3127,7 +3127,7 @@ def A4_vcmpbeq_any : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = any8(vcmpb.eq($Rss32,$Rtt32))", -tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { +tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11010010000; @@ -3136,7 +3136,7 @@ def A4_vcmpbeqi : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, u8_0Imm:$Ii), "$Pd4 = vcmpb.eq($Rss32,#$Ii)", -tc_643b4717, TypeALU64>, Enc_0d8adb { +tc_a1297125, TypeALU64>, Enc_0d8adb { let Inst{4-2} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11011100000; @@ -3145,7 +3145,7 @@ def A4_vcmpbgt : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = vcmpb.gt($Rss32,$Rtt32)", -tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { +tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b010000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11010010000; @@ -3154,7 +3154,7 @@ def A4_vcmpbgti : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, s8_0Imm:$Ii), "$Pd4 = vcmpb.gt($Rss32,#$Ii)", -tc_643b4717, TypeALU64>, Enc_0d8adb { +tc_a1297125, TypeALU64>, Enc_0d8adb { let Inst{4-2} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11011100001; @@ -3163,7 +3163,7 @@ def A4_vcmpbgtui : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, u7_0Imm:$Ii), "$Pd4 = vcmpb.gtu($Rss32,#$Ii)", -tc_643b4717, TypeALU64>, Enc_3680c2 { +tc_a1297125, TypeALU64>, Enc_3680c2 { let Inst{4-2} = 0b000; let Inst{13-12} = 0b00; let Inst{31-21} = 0b11011100010; @@ -3172,7 +3172,7 @@ def A4_vcmpheqi : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, s8_0Imm:$Ii), "$Pd4 = vcmph.eq($Rss32,#$Ii)", -tc_643b4717, TypeALU64>, Enc_0d8adb { +tc_a1297125, TypeALU64>, Enc_0d8adb { let Inst{4-2} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11011100000; @@ -3181,7 +3181,7 @@ def A4_vcmphgti : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, s8_0Imm:$Ii), "$Pd4 = vcmph.gt($Rss32,#$Ii)", -tc_643b4717, TypeALU64>, Enc_0d8adb { +tc_a1297125, TypeALU64>, Enc_0d8adb { let Inst{4-2} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11011100001; @@ -3190,7 +3190,7 @@ def A4_vcmphgtui : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, u7_0Imm:$Ii), "$Pd4 = vcmph.gtu($Rss32,#$Ii)", -tc_643b4717, TypeALU64>, Enc_3680c2 { +tc_a1297125, TypeALU64>, Enc_3680c2 { let Inst{4-2} = 0b010; let Inst{13-12} = 0b00; let Inst{31-21} = 0b11011100010; @@ -3199,7 +3199,7 @@ def A4_vcmpweqi : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, s8_0Imm:$Ii), "$Pd4 = vcmpw.eq($Rss32,#$Ii)", -tc_643b4717, TypeALU64>, Enc_0d8adb { +tc_a1297125, TypeALU64>, Enc_0d8adb { let Inst{4-2} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11011100000; @@ -3208,7 +3208,7 @@ def A4_vcmpwgti : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, s8_0Imm:$Ii), "$Pd4 = vcmpw.gt($Rss32,#$Ii)", -tc_643b4717, TypeALU64>, Enc_0d8adb { +tc_a1297125, TypeALU64>, Enc_0d8adb { let Inst{4-2} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11011100001; @@ -3217,7 +3217,7 @@ def A4_vcmpwgtui : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, u7_0Imm:$Ii), "$Pd4 = vcmpw.gtu($Rss32,#$Ii)", -tc_643b4717, TypeALU64>, Enc_3680c2 { +tc_a1297125, TypeALU64>, Enc_3680c2 { let Inst{4-2} = 0b100; let Inst{13-12} = 0b00; let Inst{31-21} = 0b11011100010; @@ -3226,7 +3226,7 @@ def A4_vrmaxh : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), "$Rxx32 = vrmaxh($Rss32,$Ru32)", -tc_5b54b33f, TypeS_3op>, Enc_412ff0 { +tc_788b1d09, TypeS_3op>, Enc_412ff0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011001; @@ -3237,7 +3237,7 @@ def A4_vrmaxuh : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), "$Rxx32 = vrmaxuh($Rss32,$Ru32)", -tc_5b54b33f, TypeS_3op>, Enc_412ff0 { +tc_788b1d09, TypeS_3op>, Enc_412ff0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11001011001; @@ -3248,7 +3248,7 @@ def A4_vrmaxuw : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), "$Rxx32 = vrmaxuw($Rss32,$Ru32)", -tc_5b54b33f, TypeS_3op>, Enc_412ff0 { +tc_788b1d09, TypeS_3op>, Enc_412ff0 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11001011001; @@ -3259,7 +3259,7 @@ def A4_vrmaxw : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), "$Rxx32 = vrmaxw($Rss32,$Ru32)", -tc_5b54b33f, TypeS_3op>, Enc_412ff0 { +tc_788b1d09, TypeS_3op>, Enc_412ff0 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011001; @@ -3270,7 +3270,7 @@ def A4_vrminh : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), "$Rxx32 = vrminh($Rss32,$Ru32)", -tc_5b54b33f, TypeS_3op>, Enc_412ff0 { +tc_788b1d09, TypeS_3op>, Enc_412ff0 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011001; @@ -3281,7 +3281,7 @@ def A4_vrminuh : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), "$Rxx32 = vrminuh($Rss32,$Ru32)", -tc_5b54b33f, TypeS_3op>, Enc_412ff0 { +tc_788b1d09, TypeS_3op>, Enc_412ff0 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11001011001; @@ -3292,7 +3292,7 @@ def A4_vrminuw : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), "$Rxx32 = vrminuw($Rss32,$Ru32)", -tc_5b54b33f, TypeS_3op>, Enc_412ff0 { +tc_788b1d09, TypeS_3op>, Enc_412ff0 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11001011001; @@ -3303,7 +3303,7 @@ def A4_vrminw : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), "$Rxx32 = vrminw($Rss32,$Ru32)", -tc_5b54b33f, TypeS_3op>, Enc_412ff0 { +tc_788b1d09, TypeS_3op>, Enc_412ff0 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011001; @@ -3314,7 +3314,7 @@ def A5_ACS : HInst< (outs DoubleRegs:$Rxx32, PredRegs:$Pe4), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32,$Pe4 = vacsh($Rss32,$Rtt32)", -tc_d1aa9eaa, TypeM>, Enc_831a7d, Requires<[HasV55]> { +tc_38e0bae9, TypeM>, Enc_831a7d, Requires<[HasV55]> { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010101; @@ -3327,7 +3327,7 @@ def A5_vaddhubs : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rd32 = vaddhub($Rss32,$Rtt32):sat", -tc_002cb246, TypeS_3op>, Enc_d2216a { +tc_0dfac0a7, TypeS_3op>, Enc_d2216a { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001010; @@ -3340,7 +3340,7 @@ def A6_vcmpbeq_notany : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = !any8(vcmpb.eq($Rss32,$Rtt32))", -tc_1fc97744, TypeALU64>, Enc_fcf7a7, Requires<[HasV65]> { +tc_407e96f9, TypeALU64>, Enc_fcf7a7, Requires<[HasV65]> { let Inst{7-2} = 0b001000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11010010000; @@ -3349,18 +3349,57 @@ def A6_vminub_RdP : HInst< (outs DoubleRegs:$Rdd32, PredRegs:$Pe4), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32,$Pe4 = vminub($Rtt32,$Rss32)", -tc_f9058dd7, TypeM>, Enc_d2c7f1, Requires<[HasV62]> { +tc_7401744f, TypeM>, Enc_d2c7f1, Requires<[HasV62]> { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010111; let isPredicateLate = 1; let prefersSlot3 = 1; } +def A7_clip : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rd32 = clip($Rs32,#$Ii)", +tc_407e96f9, TypeS_2op>, Enc_a05677, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001000110; +let hasNewValue = 1; +let opNewValue = 0; +} +def A7_croundd_ri : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rdd32 = cround($Rss32,#$Ii)", +tc_9b3c0462, TypeS_2op>, Enc_5eac98, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b010; +let Inst{31-21} = 0b10001100111; +let prefersSlot3 = 1; +} +def A7_croundd_rr : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rdd32 = cround($Rss32,$Rt32)", +tc_9b3c0462, TypeS_3op>, Enc_927852, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000110110; +let prefersSlot3 = 1; +} +def A7_vclip : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, u5_0Imm:$Ii), +"$Rdd32 = vclip($Rss32,#$Ii)", +tc_407e96f9, TypeS_2op>, Enc_7e5a82, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001000110; +} def C2_all8 : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4), "$Pd4 = all8($Ps4)", -tc_de554571, TypeCR>, Enc_65d691 { +tc_151bf368, TypeCR>, Enc_65d691 { let Inst{13-2} = 0b000000000000; let Inst{31-18} = 0b01101011101000; } @@ -3368,7 +3407,7 @@ def C2_and : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Pt4, PredRegs:$Ps4), "$Pd4 = and($Pt4,$Ps4)", -tc_640086b5, TypeCR>, Enc_454a26 { +tc_651cbe02, TypeCR>, Enc_454a26 { let Inst{7-2} = 0b000000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b01101011000000; @@ -3377,7 +3416,7 @@ def C2_andn : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Pt4, PredRegs:$Ps4), "$Pd4 = and($Pt4,!$Ps4)", -tc_640086b5, TypeCR>, Enc_454a26 { +tc_651cbe02, TypeCR>, Enc_454a26 { let Inst{7-2} = 0b000000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b01101011011000; @@ -3386,7 +3425,7 @@ def C2_any8 : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4), "$Pd4 = any8($Ps4)", -tc_de554571, TypeCR>, Enc_65d691 { +tc_151bf368, TypeCR>, Enc_65d691 { let Inst{13-2} = 0b000000000000; let Inst{31-18} = 0b01101011100000; } @@ -3394,7 +3433,7 @@ def C2_bitsclr : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = bitsclr($Rs32,$Rt32)", -tc_85d5d03f, TypeS_3op>, Enc_c2b48e { +tc_4a55d03c, TypeS_3op>, Enc_c2b48e { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111100; @@ -3403,7 +3442,7 @@ def C2_bitsclri : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, u6_0Imm:$Ii), "$Pd4 = bitsclr($Rs32,#$Ii)", -tc_643b4717, TypeS_2op>, Enc_5d6c34 { +tc_a1297125, TypeS_2op>, Enc_5d6c34 { let Inst{7-2} = 0b000000; let Inst{31-21} = 0b10000101100; } @@ -3411,7 +3450,7 @@ def C2_bitsset : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = bitsset($Rs32,$Rt32)", -tc_85d5d03f, TypeS_3op>, Enc_c2b48e { +tc_4a55d03c, TypeS_3op>, Enc_c2b48e { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111010; @@ -3420,7 +3459,7 @@ def C2_ccombinewf : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pu4) $Rdd32 = combine($Rs32,$Rt32)", -tc_4c5ba658, TypeALU32_3op>, Enc_cb4b4e, PredNewRel { +tc_1c2c7a4a, TypeALU32_3op>, Enc_cb4b4e, PredNewRel { let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11111101000; @@ -3432,7 +3471,7 @@ def C2_ccombinewnewf : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pu4.new) $Rdd32 = combine($Rs32,$Rt32)", -tc_05c070ec, TypeALU32_3op>, Enc_cb4b4e, PredNewRel { +tc_442395f3, TypeALU32_3op>, Enc_cb4b4e, PredNewRel { let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11111101000; @@ -3445,7 +3484,7 @@ def C2_ccombinewnewt : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pu4.new) $Rdd32 = combine($Rs32,$Rt32)", -tc_05c070ec, TypeALU32_3op>, Enc_cb4b4e, PredNewRel { +tc_442395f3, TypeALU32_3op>, Enc_cb4b4e, PredNewRel { let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11111101000; @@ -3457,7 +3496,7 @@ def C2_ccombinewt : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pu4) $Rdd32 = combine($Rs32,$Rt32)", -tc_4c5ba658, TypeALU32_3op>, Enc_cb4b4e, PredNewRel { +tc_1c2c7a4a, TypeALU32_3op>, Enc_cb4b4e, PredNewRel { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11111101000; @@ -3468,7 +3507,7 @@ def C2_cmoveif : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, s32_0Imm:$Ii), "if (!$Pu4) $Rd32 = #$Ii", -tc_5a2711e5, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel { +tc_713b66bf, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel { let Inst{13-13} = 0b0; let Inst{20-20} = 0b0; let Inst{31-23} = 0b011111101; @@ -3476,9 +3515,9 @@ let isPredicated = 1; let isPredicatedFalse = 1; let hasNewValue = 1; let opNewValue = 0; +let BaseOpcode = "A2_tfrsi"; let CextOpcode = "A2_tfr"; let InputType = "imm"; -let BaseOpcode = "A2_tfrsi"; let isMoveImm = 1; let isExtendable = 1; let opExtendable = 2; @@ -3490,16 +3529,16 @@ def C2_cmoveit : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, s32_0Imm:$Ii), "if ($Pu4) $Rd32 = #$Ii", -tc_5a2711e5, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel { +tc_713b66bf, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel { let Inst{13-13} = 0b0; let Inst{20-20} = 0b0; let Inst{31-23} = 0b011111100; let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; +let BaseOpcode = "A2_tfrsi"; let CextOpcode = "A2_tfr"; let InputType = "imm"; -let BaseOpcode = "A2_tfrsi"; let isMoveImm = 1; let isExtendable = 1; let opExtendable = 2; @@ -3511,7 +3550,7 @@ def C2_cmovenewif : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, s32_0Imm:$Ii), "if (!$Pu4.new) $Rd32 = #$Ii", -tc_1ae57e39, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel { +tc_86173609, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel { let Inst{13-13} = 0b1; let Inst{20-20} = 0b0; let Inst{31-23} = 0b011111101; @@ -3520,9 +3559,9 @@ let isPredicatedFalse = 1; let hasNewValue = 1; let opNewValue = 0; let isPredicatedNew = 1; +let BaseOpcode = "A2_tfrsi"; let CextOpcode = "A2_tfr"; let InputType = "imm"; -let BaseOpcode = "A2_tfrsi"; let isMoveImm = 1; let isExtendable = 1; let opExtendable = 2; @@ -3534,7 +3573,7 @@ def C2_cmovenewit : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, s32_0Imm:$Ii), "if ($Pu4.new) $Rd32 = #$Ii", -tc_1ae57e39, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel { +tc_86173609, TypeALU32_2op>, Enc_cda00a, PredNewRel, ImmRegRel { let Inst{13-13} = 0b1; let Inst{20-20} = 0b0; let Inst{31-23} = 0b011111100; @@ -3542,9 +3581,9 @@ let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; let isPredicatedNew = 1; +let BaseOpcode = "A2_tfrsi"; let CextOpcode = "A2_tfr"; let InputType = "imm"; -let BaseOpcode = "A2_tfrsi"; let isMoveImm = 1; let isExtendable = 1; let opExtendable = 2; @@ -3556,7 +3595,7 @@ def C2_cmpeq : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = cmp.eq($Rs32,$Rt32)", -tc_de4df740, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { +tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110010000; @@ -3569,7 +3608,7 @@ def C2_cmpeqi : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Pd4 = cmp.eq($Rs32,#$Ii)", -tc_56f114f4, TypeALU32_2op>, Enc_bd0b33, ImmRegRel { +tc_d33e5eee, TypeALU32_2op>, Enc_bd0b33, ImmRegRel { let Inst{4-2} = 0b000; let Inst{31-22} = 0b0111010100; let CextOpcode = "C2_cmpeq"; @@ -3585,7 +3624,7 @@ def C2_cmpeqp : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = cmp.eq($Rss32,$Rtt32)", -tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { +tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010100; @@ -3596,7 +3635,7 @@ def C2_cmpgei : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, s8_0Imm:$Ii), "$Pd4 = cmp.ge($Rs32,#$Ii)", -tc_56f114f4, TypeALU32_2op> { +tc_d33e5eee, TypeALU32_2op> { let isCompare = 1; let isPseudo = 1; } @@ -3604,7 +3643,7 @@ def C2_cmpgeui : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, u8_0Imm:$Ii), "$Pd4 = cmp.geu($Rs32,#$Ii)", -tc_56f114f4, TypeALU32_2op> { +tc_d33e5eee, TypeALU32_2op> { let isCompare = 1; let isPseudo = 1; } @@ -3612,7 +3651,7 @@ def C2_cmpgt : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = cmp.gt($Rs32,$Rt32)", -tc_de4df740, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { +tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110010010; @@ -3624,7 +3663,7 @@ def C2_cmpgti : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Pd4 = cmp.gt($Rs32,#$Ii)", -tc_56f114f4, TypeALU32_2op>, Enc_bd0b33, ImmRegRel { +tc_d33e5eee, TypeALU32_2op>, Enc_bd0b33, ImmRegRel { let Inst{4-2} = 0b000; let Inst{31-22} = 0b0111010101; let CextOpcode = "C2_cmpgt"; @@ -3640,7 +3679,7 @@ def C2_cmpgtp : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = cmp.gt($Rss32,$Rtt32)", -tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { +tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b010000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010100; @@ -3650,7 +3689,7 @@ def C2_cmpgtu : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = cmp.gtu($Rs32,$Rt32)", -tc_de4df740, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { +tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110010011; @@ -3662,7 +3701,7 @@ def C2_cmpgtui : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, u32_0Imm:$Ii), "$Pd4 = cmp.gtu($Rs32,#$Ii)", -tc_56f114f4, TypeALU32_2op>, Enc_c0cdde, ImmRegRel { +tc_d33e5eee, TypeALU32_2op>, Enc_c0cdde, ImmRegRel { let Inst{4-2} = 0b000; let Inst{31-21} = 0b01110101100; let CextOpcode = "C2_cmpgtu"; @@ -3678,7 +3717,7 @@ def C2_cmpgtup : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = cmp.gtu($Rss32,$Rtt32)", -tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { +tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b100000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010100; @@ -3688,7 +3727,7 @@ def C2_cmplt : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = cmp.lt($Rs32,$Rt32)", -tc_56f114f4, TypeALU32_3op> { +tc_d33e5eee, TypeALU32_3op> { let isCompare = 1; let isPseudo = 1; let isCodeGenOnly = 1; @@ -3697,7 +3736,7 @@ def C2_cmpltu : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = cmp.ltu($Rs32,$Rt32)", -tc_56f114f4, TypeALU32_3op> { +tc_d33e5eee, TypeALU32_3op> { let isCompare = 1; let isPseudo = 1; let isCodeGenOnly = 1; @@ -3706,7 +3745,7 @@ def C2_mask : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pt4), "$Rdd32 = mask($Pt4)", -tc_0ae0825c, TypeS_2op>, Enc_78e566 { +tc_9f6cd987, TypeS_2op>, Enc_78e566 { let Inst{7-5} = 0b000; let Inst{13-10} = 0b0000; let Inst{31-16} = 0b1000011000000000; @@ -3715,7 +3754,7 @@ def C2_mux : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mux($Pu4,$Rs32,$Rt32)", -tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54 { +tc_1c2c7a4a, TypeALU32_3op>, Enc_ea4c54 { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110100000; @@ -3727,7 +3766,7 @@ def C2_muxii : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, s32_0Imm:$Ii, s8_0Imm:$II), "$Rd32 = mux($Pu4,#$Ii,#$II)", -tc_4c5ba658, TypeALU32_2op>, Enc_830e5d { +tc_1c2c7a4a, TypeALU32_2op>, Enc_830e5d { let Inst{31-25} = 0b0111101; let hasNewValue = 1; let opNewValue = 0; @@ -3741,7 +3780,7 @@ def C2_muxir : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii), "$Rd32 = mux($Pu4,$Rs32,#$Ii)", -tc_4c5ba658, TypeALU32_2op>, Enc_e38e1f { +tc_1c2c7a4a, TypeALU32_2op>, Enc_e38e1f { let Inst{13-13} = 0b0; let Inst{31-23} = 0b011100110; let hasNewValue = 1; @@ -3757,7 +3796,7 @@ def C2_muxri : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pu4, s32_0Imm:$Ii, IntRegs:$Rs32), "$Rd32 = mux($Pu4,#$Ii,$Rs32)", -tc_4c5ba658, TypeALU32_2op>, Enc_e38e1f { +tc_1c2c7a4a, TypeALU32_2op>, Enc_e38e1f { let Inst{13-13} = 0b0; let Inst{31-23} = 0b011100111; let hasNewValue = 1; @@ -3773,7 +3812,7 @@ def C2_not : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4), "$Pd4 = not($Ps4)", -tc_de554571, TypeCR>, Enc_65d691 { +tc_151bf368, TypeCR>, Enc_65d691 { let Inst{13-2} = 0b000000000000; let Inst{31-18} = 0b01101011110000; } @@ -3781,7 +3820,7 @@ def C2_or : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Pt4, PredRegs:$Ps4), "$Pd4 = or($Pt4,$Ps4)", -tc_640086b5, TypeCR>, Enc_454a26 { +tc_651cbe02, TypeCR>, Enc_454a26 { let Inst{7-2} = 0b000000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b01101011001000; @@ -3790,7 +3829,7 @@ def C2_orn : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Pt4, PredRegs:$Ps4), "$Pd4 = or($Pt4,!$Ps4)", -tc_640086b5, TypeCR>, Enc_454a26 { +tc_651cbe02, TypeCR>, Enc_454a26 { let Inst{7-2} = 0b000000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b01101011111000; @@ -3799,7 +3838,7 @@ def C2_pxfer_map : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4), "$Pd4 = $Ps4", -tc_640086b5, TypeMAPPING> { +tc_651cbe02, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -3807,7 +3846,7 @@ def C2_tfrpr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Ps4), "$Rd32 = $Ps4", -tc_0ae0825c, TypeS_2op>, Enc_f5e933 { +tc_9f6cd987, TypeS_2op>, Enc_f5e933 { let Inst{13-5} = 0b000000000; let Inst{31-18} = 0b10001001010000; let hasNewValue = 1; @@ -3817,7 +3856,7 @@ def C2_tfrrp : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32), "$Pd4 = $Rs32", -tc_cfd8378a, TypeS_2op>, Enc_48b75f { +tc_55b33fda, TypeS_2op>, Enc_48b75f { let Inst{13-2} = 0b000000000000; let Inst{31-21} = 0b10000101010; } @@ -3825,7 +3864,7 @@ def C2_vitpack : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Ps4, PredRegs:$Pt4), "$Rd32 = vitpack($Ps4,$Pt4)", -tc_4414d8b1, TypeS_2op>, Enc_527412 { +tc_f34c1c21, TypeS_2op>, Enc_527412 { let Inst{7-5} = 0b000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b10001001000000; @@ -3837,7 +3876,7 @@ def C2_vmux : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pu4, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmux($Pu4,$Rss32,$Rtt32)", -tc_b4b5c03a, TypeALU64>, Enc_329361 { +tc_6fc5dbea, TypeALU64>, Enc_329361 { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010001000; @@ -3846,7 +3885,7 @@ def C2_xor : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4, PredRegs:$Pt4), "$Pd4 = xor($Ps4,$Pt4)", -tc_640086b5, TypeCR>, Enc_284ebb { +tc_651cbe02, TypeCR>, Enc_284ebb { let Inst{7-2} = 0b000000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b01101011010000; @@ -3855,7 +3894,7 @@ def C4_addipc : HInst< (outs IntRegs:$Rd32), (ins u32_0Imm:$Ii), "$Rd32 = add(pc,#$Ii)", -tc_a813cf9a, TypeCR>, Enc_607661 { +tc_3edca78f, TypeCR>, Enc_607661 { let Inst{6-5} = 0b00; let Inst{13-13} = 0b0; let Inst{31-16} = 0b0110101001001001; @@ -3871,7 +3910,7 @@ def C4_and_and : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), "$Pd4 = and($Ps4,and($Pt4,$Pu4))", -tc_b31c2e97, TypeCR>, Enc_9ac432 { +tc_a7a13fac, TypeCR>, Enc_9ac432 { let Inst{5-2} = 0b0000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b01101011000100; @@ -3880,7 +3919,7 @@ def C4_and_andn : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), "$Pd4 = and($Ps4,and($Pt4,!$Pu4))", -tc_b31c2e97, TypeCR>, Enc_9ac432 { +tc_a7a13fac, TypeCR>, Enc_9ac432 { let Inst{5-2} = 0b0000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b01101011100100; @@ -3889,7 +3928,7 @@ def C4_and_or : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), "$Pd4 = and($Ps4,or($Pt4,$Pu4))", -tc_b31c2e97, TypeCR>, Enc_9ac432 { +tc_a7a13fac, TypeCR>, Enc_9ac432 { let Inst{5-2} = 0b0000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b01101011001100; @@ -3898,7 +3937,7 @@ def C4_and_orn : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), "$Pd4 = and($Ps4,or($Pt4,!$Pu4))", -tc_b31c2e97, TypeCR>, Enc_9ac432 { +tc_a7a13fac, TypeCR>, Enc_9ac432 { let Inst{5-2} = 0b0000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b01101011101100; @@ -3907,7 +3946,7 @@ def C4_cmplte : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = !cmp.gt($Rs32,$Rt32)", -tc_de4df740, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { +tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { let Inst{7-2} = 0b000100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110010010; @@ -3919,7 +3958,7 @@ def C4_cmpltei : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Pd4 = !cmp.gt($Rs32,#$Ii)", -tc_56f114f4, TypeALU32_2op>, Enc_bd0b33, ImmRegRel { +tc_d33e5eee, TypeALU32_2op>, Enc_bd0b33, ImmRegRel { let Inst{4-2} = 0b100; let Inst{31-22} = 0b0111010101; let CextOpcode = "C4_cmplte"; @@ -3935,7 +3974,7 @@ def C4_cmplteu : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = !cmp.gtu($Rs32,$Rt32)", -tc_de4df740, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { +tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { let Inst{7-2} = 0b000100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110010011; @@ -3947,7 +3986,7 @@ def C4_cmplteui : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, u32_0Imm:$Ii), "$Pd4 = !cmp.gtu($Rs32,#$Ii)", -tc_56f114f4, TypeALU32_2op>, Enc_c0cdde, ImmRegRel { +tc_d33e5eee, TypeALU32_2op>, Enc_c0cdde, ImmRegRel { let Inst{4-2} = 0b100; let Inst{31-21} = 0b01110101100; let CextOpcode = "C4_cmplteu"; @@ -3963,7 +4002,7 @@ def C4_cmpneq : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = !cmp.eq($Rs32,$Rt32)", -tc_de4df740, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { +tc_9c52f549, TypeALU32_3op>, Enc_c2b48e, ImmRegRel { let Inst{7-2} = 0b000100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110010000; @@ -3976,7 +4015,7 @@ def C4_cmpneqi : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Pd4 = !cmp.eq($Rs32,#$Ii)", -tc_56f114f4, TypeALU32_2op>, Enc_bd0b33, ImmRegRel { +tc_d33e5eee, TypeALU32_2op>, Enc_bd0b33, ImmRegRel { let Inst{4-2} = 0b100; let Inst{31-22} = 0b0111010100; let CextOpcode = "C4_cmpneq"; @@ -3992,7 +4031,7 @@ def C4_fastcorner9 : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4, PredRegs:$Pt4), "$Pd4 = fastcorner9($Ps4,$Pt4)", -tc_640086b5, TypeCR>, Enc_284ebb { +tc_651cbe02, TypeCR>, Enc_284ebb { let Inst{7-2} = 0b100100; let Inst{13-10} = 0b1000; let Inst{31-18} = 0b01101011000000; @@ -4001,7 +4040,7 @@ def C4_fastcorner9_not : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4, PredRegs:$Pt4), "$Pd4 = !fastcorner9($Ps4,$Pt4)", -tc_640086b5, TypeCR>, Enc_284ebb { +tc_651cbe02, TypeCR>, Enc_284ebb { let Inst{7-2} = 0b100100; let Inst{13-10} = 0b1000; let Inst{31-18} = 0b01101011000100; @@ -4010,7 +4049,7 @@ def C4_nbitsclr : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = !bitsclr($Rs32,$Rt32)", -tc_85d5d03f, TypeS_3op>, Enc_c2b48e { +tc_4a55d03c, TypeS_3op>, Enc_c2b48e { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111101; @@ -4019,7 +4058,7 @@ def C4_nbitsclri : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, u6_0Imm:$Ii), "$Pd4 = !bitsclr($Rs32,#$Ii)", -tc_643b4717, TypeS_2op>, Enc_5d6c34 { +tc_a1297125, TypeS_2op>, Enc_5d6c34 { let Inst{7-2} = 0b000000; let Inst{31-21} = 0b10000101101; } @@ -4027,7 +4066,7 @@ def C4_nbitsset : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = !bitsset($Rs32,$Rt32)", -tc_85d5d03f, TypeS_3op>, Enc_c2b48e { +tc_4a55d03c, TypeS_3op>, Enc_c2b48e { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111011; @@ -4036,7 +4075,7 @@ def C4_or_and : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), "$Pd4 = or($Ps4,and($Pt4,$Pu4))", -tc_b31c2e97, TypeCR>, Enc_9ac432 { +tc_a7a13fac, TypeCR>, Enc_9ac432 { let Inst{5-2} = 0b0000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b01101011010100; @@ -4045,7 +4084,7 @@ def C4_or_andn : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), "$Pd4 = or($Ps4,and($Pt4,!$Pu4))", -tc_b31c2e97, TypeCR>, Enc_9ac432 { +tc_a7a13fac, TypeCR>, Enc_9ac432 { let Inst{5-2} = 0b0000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b01101011110100; @@ -4054,7 +4093,7 @@ def C4_or_or : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), "$Pd4 = or($Ps4,or($Pt4,$Pu4))", -tc_b31c2e97, TypeCR>, Enc_9ac432 { +tc_a7a13fac, TypeCR>, Enc_9ac432 { let Inst{5-2} = 0b0000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b01101011011100; @@ -4063,7 +4102,7 @@ def C4_or_orn : HInst< (outs PredRegs:$Pd4), (ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), "$Pd4 = or($Ps4,or($Pt4,!$Pu4))", -tc_b31c2e97, TypeCR>, Enc_9ac432 { +tc_a7a13fac, TypeCR>, Enc_9ac432 { let Inst{5-2} = 0b0000; let Inst{13-10} = 0b0000; let Inst{31-18} = 0b01101011111100; @@ -4072,7 +4111,7 @@ def F2_conv_d2df : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = convert_d2df($Rss32)", -tc_3a867367, TypeS_2op>, Enc_b9c5fb { +tc_9783714b, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000011; let Inst{31-21} = 0b10000000111; let isFP = 1; @@ -4082,7 +4121,7 @@ def F2_conv_d2sf : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = convert_d2sf($Rss32)", -tc_3a867367, TypeS_2op>, Enc_90cd8b { +tc_9783714b, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000010; let hasNewValue = 1; @@ -4094,7 +4133,7 @@ def F2_conv_df2d : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = convert_df2d($Rss32)", -tc_3a867367, TypeS_2op>, Enc_b9c5fb { +tc_9783714b, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10000000111; let isFP = 1; @@ -4104,7 +4143,7 @@ def F2_conv_df2d_chop : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = convert_df2d($Rss32):chop", -tc_3a867367, TypeS_2op>, Enc_b9c5fb { +tc_9783714b, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10000000111; let isFP = 1; @@ -4114,7 +4153,7 @@ def F2_conv_df2sf : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = convert_df2sf($Rss32)", -tc_3a867367, TypeS_2op>, Enc_90cd8b { +tc_9783714b, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000000; let hasNewValue = 1; @@ -4126,7 +4165,7 @@ def F2_conv_df2ud : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = convert_df2ud($Rss32)", -tc_3a867367, TypeS_2op>, Enc_b9c5fb { +tc_9783714b, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10000000111; let isFP = 1; @@ -4136,7 +4175,7 @@ def F2_conv_df2ud_chop : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = convert_df2ud($Rss32):chop", -tc_3a867367, TypeS_2op>, Enc_b9c5fb { +tc_9783714b, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000111; let Inst{31-21} = 0b10000000111; let isFP = 1; @@ -4146,7 +4185,7 @@ def F2_conv_df2uw : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = convert_df2uw($Rss32)", -tc_3a867367, TypeS_2op>, Enc_90cd8b { +tc_9783714b, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000011; let hasNewValue = 1; @@ -4158,7 +4197,7 @@ def F2_conv_df2uw_chop : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = convert_df2uw($Rss32):chop", -tc_3a867367, TypeS_2op>, Enc_90cd8b { +tc_9783714b, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000101; let hasNewValue = 1; @@ -4170,7 +4209,7 @@ def F2_conv_df2w : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = convert_df2w($Rss32)", -tc_3a867367, TypeS_2op>, Enc_90cd8b { +tc_9783714b, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000100; let hasNewValue = 1; @@ -4182,7 +4221,7 @@ def F2_conv_df2w_chop : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = convert_df2w($Rss32):chop", -tc_3a867367, TypeS_2op>, Enc_90cd8b { +tc_9783714b, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000111; let hasNewValue = 1; @@ -4194,7 +4233,7 @@ def F2_conv_sf2d : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = convert_sf2d($Rs32)", -tc_3a867367, TypeS_2op>, Enc_3a3d62 { +tc_9783714b, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10000100100; let isFP = 1; @@ -4204,7 +4243,7 @@ def F2_conv_sf2d_chop : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = convert_sf2d($Rs32):chop", -tc_3a867367, TypeS_2op>, Enc_3a3d62 { +tc_9783714b, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10000100100; let isFP = 1; @@ -4214,7 +4253,7 @@ def F2_conv_sf2df : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = convert_sf2df($Rs32)", -tc_3a867367, TypeS_2op>, Enc_3a3d62 { +tc_9783714b, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10000100100; let isFP = 1; @@ -4224,7 +4263,7 @@ def F2_conv_sf2ud : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = convert_sf2ud($Rs32)", -tc_3a867367, TypeS_2op>, Enc_3a3d62 { +tc_9783714b, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000011; let Inst{31-21} = 0b10000100100; let isFP = 1; @@ -4234,7 +4273,7 @@ def F2_conv_sf2ud_chop : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = convert_sf2ud($Rs32):chop", -tc_3a867367, TypeS_2op>, Enc_3a3d62 { +tc_9783714b, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000101; let Inst{31-21} = 0b10000100100; let isFP = 1; @@ -4244,7 +4283,7 @@ def F2_conv_sf2uw : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = convert_sf2uw($Rs32)", -tc_3a867367, TypeS_2op>, Enc_5e2823 { +tc_9783714b, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001011011; let hasNewValue = 1; @@ -4256,7 +4295,7 @@ def F2_conv_sf2uw_chop : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = convert_sf2uw($Rs32):chop", -tc_3a867367, TypeS_2op>, Enc_5e2823 { +tc_9783714b, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001011011; let hasNewValue = 1; @@ -4268,7 +4307,7 @@ def F2_conv_sf2w : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = convert_sf2w($Rs32)", -tc_3a867367, TypeS_2op>, Enc_5e2823 { +tc_9783714b, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001011100; let hasNewValue = 1; @@ -4280,7 +4319,7 @@ def F2_conv_sf2w_chop : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = convert_sf2w($Rs32):chop", -tc_3a867367, TypeS_2op>, Enc_5e2823 { +tc_9783714b, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001011100; let hasNewValue = 1; @@ -4292,7 +4331,7 @@ def F2_conv_ud2df : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = convert_ud2df($Rss32)", -tc_3a867367, TypeS_2op>, Enc_b9c5fb { +tc_9783714b, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000010; let Inst{31-21} = 0b10000000111; let isFP = 1; @@ -4302,7 +4341,7 @@ def F2_conv_ud2sf : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = convert_ud2sf($Rss32)", -tc_3a867367, TypeS_2op>, Enc_90cd8b { +tc_9783714b, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10001000001; let hasNewValue = 1; @@ -4314,7 +4353,7 @@ def F2_conv_uw2df : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = convert_uw2df($Rs32)", -tc_3a867367, TypeS_2op>, Enc_3a3d62 { +tc_9783714b, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b10000100100; let isFP = 1; @@ -4324,7 +4363,7 @@ def F2_conv_uw2sf : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = convert_uw2sf($Rs32)", -tc_3a867367, TypeS_2op>, Enc_5e2823 { +tc_9783714b, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001011001; let hasNewValue = 1; @@ -4336,7 +4375,7 @@ def F2_conv_w2df : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = convert_w2df($Rs32)", -tc_3a867367, TypeS_2op>, Enc_3a3d62 { +tc_9783714b, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000010; let Inst{31-21} = 0b10000100100; let isFP = 1; @@ -4346,7 +4385,7 @@ def F2_conv_w2sf : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = convert_w2sf($Rs32)", -tc_3a867367, TypeS_2op>, Enc_5e2823 { +tc_9783714b, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001011010; let hasNewValue = 1; @@ -4358,7 +4397,7 @@ def F2_dfadd : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = dfadd($Rss32,$Rtt32)", -tc_2f7c551d, TypeM>, Enc_a56825, Requires<[HasV66]> { +tc_f0e8e832, TypeM>, Enc_a56825, Requires<[HasV66]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000000; @@ -4369,7 +4408,7 @@ def F2_dfclass : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, u5_0Imm:$Ii), "$Pd4 = dfclass($Rss32,#$Ii)", -tc_643b4717, TypeALU64>, Enc_1f19b5 { +tc_a1297125, TypeALU64>, Enc_1f19b5 { let Inst{4-2} = 0b100; let Inst{13-10} = 0b0000; let Inst{31-21} = 0b11011100100; @@ -4380,7 +4419,7 @@ def F2_dfcmpeq : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = dfcmp.eq($Rss32,$Rtt32)", -tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { +tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010111; @@ -4392,7 +4431,7 @@ def F2_dfcmpge : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = dfcmp.ge($Rss32,$Rtt32)", -tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { +tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b010000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010111; @@ -4404,7 +4443,7 @@ def F2_dfcmpgt : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = dfcmp.gt($Rss32,$Rtt32)", -tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { +tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b001000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010111; @@ -4416,7 +4455,7 @@ def F2_dfcmpuo : HInst< (outs PredRegs:$Pd4), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Pd4 = dfcmp.uo($Rss32,$Rtt32)", -tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { +tc_4a55d03c, TypeALU64>, Enc_fcf7a7 { let Inst{7-2} = 0b011000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010010111; @@ -4428,7 +4467,7 @@ def F2_dfimm_n : HInst< (outs DoubleRegs:$Rdd32), (ins u10_0Imm:$Ii), "$Rdd32 = dfmake(#$Ii):neg", -tc_9e313203, TypeALU64>, Enc_e6c957 { +tc_65279839, TypeALU64>, Enc_e6c957 { let Inst{20-16} = 0b00000; let Inst{31-22} = 0b1101100101; let prefersSlot3 = 1; @@ -4437,16 +4476,84 @@ def F2_dfimm_p : HInst< (outs DoubleRegs:$Rdd32), (ins u10_0Imm:$Ii), "$Rdd32 = dfmake(#$Ii):pos", -tc_9e313203, TypeALU64>, Enc_e6c957 { +tc_65279839, TypeALU64>, Enc_e6c957 { let Inst{20-16} = 0b00000; let Inst{31-22} = 0b1101100100; let prefersSlot3 = 1; } +def F2_dfmax : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = dfmax($Rss32,$Rtt32)", +tc_9b3c0462, TypeM>, Enc_a56825, Requires<[HasV67]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000001; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_dfmin : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = dfmin($Rss32,$Rtt32)", +tc_9b3c0462, TypeM>, Enc_a56825, Requires<[HasV67]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000110; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_dfmpyfix : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = dfmpyfix($Rss32,$Rtt32)", +tc_f0e8e832, TypeM>, Enc_a56825, Requires<[HasV67]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000010; +let isFP = 1; +let Uses = [USR]; +} +def F2_dfmpyhh : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += dfmpyhh($Rss32,$Rtt32)", +tc_0a195f2c, TypeM>, Enc_88c16c, Requires<[HasV67]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010100; +let isFP = 1; +let Uses = [USR]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def F2_dfmpylh : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += dfmpylh($Rss32,$Rtt32)", +tc_01e1be3b, TypeM>, Enc_88c16c, Requires<[HasV67]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def F2_dfmpyll : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = dfmpyll($Rss32,$Rtt32)", +tc_556f6577, TypeM>, Enc_a56825, Requires<[HasV67]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000101; +let prefersSlot3 = 1; +} def F2_dfsub : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = dfsub($Rss32,$Rtt32)", -tc_2f7c551d, TypeM>, Enc_a56825, Requires<[HasV66]> { +tc_f0e8e832, TypeM>, Enc_a56825, Requires<[HasV66]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000100; @@ -4457,7 +4564,7 @@ def F2_sfadd : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = sfadd($Rs32,$Rt32)", -tc_3b470976, TypeM>, Enc_5ab2be { +tc_02fe1c65, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011000; @@ -4471,7 +4578,7 @@ def F2_sfclass : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Pd4 = sfclass($Rs32,#$Ii)", -tc_643b4717, TypeS_2op>, Enc_83ee64 { +tc_a1297125, TypeS_2op>, Enc_83ee64 { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10000101111; @@ -4482,7 +4589,7 @@ def F2_sfcmpeq : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = sfcmp.eq($Rs32,$Rt32)", -tc_85d5d03f, TypeS_3op>, Enc_c2b48e { +tc_4a55d03c, TypeS_3op>, Enc_c2b48e { let Inst{7-2} = 0b011000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111111; @@ -4494,7 +4601,7 @@ def F2_sfcmpge : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = sfcmp.ge($Rs32,$Rt32)", -tc_85d5d03f, TypeS_3op>, Enc_c2b48e { +tc_4a55d03c, TypeS_3op>, Enc_c2b48e { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111111; @@ -4506,7 +4613,7 @@ def F2_sfcmpgt : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = sfcmp.gt($Rs32,$Rt32)", -tc_85d5d03f, TypeS_3op>, Enc_c2b48e { +tc_4a55d03c, TypeS_3op>, Enc_c2b48e { let Inst{7-2} = 0b100000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111111; @@ -4518,7 +4625,7 @@ def F2_sfcmpuo : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = sfcmp.uo($Rs32,$Rt32)", -tc_85d5d03f, TypeS_3op>, Enc_c2b48e { +tc_4a55d03c, TypeS_3op>, Enc_c2b48e { let Inst{7-2} = 0b001000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111111; @@ -4530,7 +4637,7 @@ def F2_sffixupd : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = sffixupd($Rs32,$Rt32)", -tc_3b470976, TypeM>, Enc_5ab2be { +tc_02fe1c65, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011110; @@ -4542,7 +4649,7 @@ def F2_sffixupn : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = sffixupn($Rs32,$Rt32)", -tc_3b470976, TypeM>, Enc_5ab2be { +tc_02fe1c65, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011110; @@ -4554,7 +4661,7 @@ def F2_sffixupr : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = sffixupr($Rs32)", -tc_3a867367, TypeS_2op>, Enc_5e2823 { +tc_9783714b, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001011101; let hasNewValue = 1; @@ -4565,7 +4672,7 @@ def F2_sffma : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += sfmpy($Rs32,$Rt32)", -tc_a58fd5cc, TypeM>, Enc_2ae154 { +tc_9e72dc89, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111000; @@ -4579,7 +4686,7 @@ def F2_sffma_lib : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += sfmpy($Rs32,$Rt32):lib", -tc_a58fd5cc, TypeM>, Enc_2ae154 { +tc_9e72dc89, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111000; @@ -4593,7 +4700,7 @@ def F2_sffma_sc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32, PredRegs:$Pu4), "$Rx32 += sfmpy($Rs32,$Rt32,$Pu4):scale", -tc_4560740b, TypeM>, Enc_437f33 { +tc_9edb7c77, TypeM>, Enc_437f33 { let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111011; @@ -4607,7 +4714,7 @@ def F2_sffms : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= sfmpy($Rs32,$Rt32)", -tc_a58fd5cc, TypeM>, Enc_2ae154 { +tc_9e72dc89, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111000; @@ -4621,7 +4728,7 @@ def F2_sffms_lib : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= sfmpy($Rs32,$Rt32):lib", -tc_a58fd5cc, TypeM>, Enc_2ae154 { +tc_9e72dc89, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111000; @@ -4635,7 +4742,7 @@ def F2_sfimm_n : HInst< (outs IntRegs:$Rd32), (ins u10_0Imm:$Ii), "$Rd32 = sfmake(#$Ii):neg", -tc_9e313203, TypeALU64>, Enc_6c9440 { +tc_65279839, TypeALU64>, Enc_6c9440 { let Inst{20-16} = 0b00000; let Inst{31-22} = 0b1101011001; let hasNewValue = 1; @@ -4646,7 +4753,7 @@ def F2_sfimm_p : HInst< (outs IntRegs:$Rd32), (ins u10_0Imm:$Ii), "$Rd32 = sfmake(#$Ii):pos", -tc_9e313203, TypeALU64>, Enc_6c9440 { +tc_65279839, TypeALU64>, Enc_6c9440 { let Inst{20-16} = 0b00000; let Inst{31-22} = 0b1101011000; let hasNewValue = 1; @@ -4657,7 +4764,7 @@ def F2_sfinvsqrta : HInst< (outs IntRegs:$Rd32, PredRegs:$Pe4), (ins IntRegs:$Rs32), "$Rd32,$Pe4 = sfinvsqrta($Rs32)", -tc_b8bffe55, TypeS_2op>, Enc_890909 { +tc_7f7f45f5, TypeS_2op>, Enc_890909 { let Inst{13-7} = 0b0000000; let Inst{31-21} = 0b10001011111; let hasNewValue = 1; @@ -4669,7 +4776,7 @@ def F2_sfmax : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = sfmax($Rs32,$Rt32)", -tc_88b4f13d, TypeM>, Enc_5ab2be { +tc_c20701f0, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011100; @@ -4683,7 +4790,7 @@ def F2_sfmin : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = sfmin($Rs32,$Rt32)", -tc_88b4f13d, TypeM>, Enc_5ab2be { +tc_c20701f0, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011100; @@ -4697,7 +4804,7 @@ def F2_sfmpy : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = sfmpy($Rs32,$Rt32)", -tc_3b470976, TypeM>, Enc_5ab2be { +tc_02fe1c65, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011010; @@ -4711,7 +4818,7 @@ def F2_sfrecipa : HInst< (outs IntRegs:$Rd32, PredRegs:$Pe4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32,$Pe4 = sfrecipa($Rs32,$Rt32)", -tc_2ff964b4, TypeM>, Enc_a94f3b { +tc_f7569068, TypeM>, Enc_a94f3b { let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011111; @@ -4724,7 +4831,7 @@ def F2_sfsub : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = sfsub($Rs32,$Rt32)", -tc_3b470976, TypeM>, Enc_5ab2be { +tc_02fe1c65, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101011000; @@ -4737,7 +4844,7 @@ def G4_tfrgcpp : HInst< (outs DoubleRegs:$Rdd32), (ins GuestRegs64:$Gss32), "$Rdd32 = $Gss32", -tc_0d8f5752, TypeCR>, Enc_0aa344 { +tc_fae9dfa5, TypeCR>, Enc_0aa344 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b01101000001; } @@ -4745,7 +4852,7 @@ def G4_tfrgcrr : HInst< (outs IntRegs:$Rd32), (ins GuestRegs:$Gs32), "$Rd32 = $Gs32", -tc_0d8f5752, TypeCR>, Enc_44271f { +tc_fae9dfa5, TypeCR>, Enc_44271f { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b01101010001; let hasNewValue = 1; @@ -4755,7 +4862,7 @@ def G4_tfrgpcp : HInst< (outs GuestRegs64:$Gdd32), (ins DoubleRegs:$Rss32), "$Gdd32 = $Rss32", -tc_bcf98408, TypeCR>, Enc_ed5027 { +tc_6ae3426b, TypeCR>, Enc_ed5027 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b01100011000; let hasNewValue = 1; @@ -4765,7 +4872,7 @@ def G4_tfrgrcr : HInst< (outs GuestRegs:$Gd32), (ins IntRegs:$Rs32), "$Gd32 = $Rs32", -tc_bcf98408, TypeCR>, Enc_621fba { +tc_6ae3426b, TypeCR>, Enc_621fba { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b01100010000; let hasNewValue = 1; @@ -4775,7 +4882,7 @@ def J2_call : HInst< (outs), (ins a30_2Imm:$Ii), "call $Ii", -tc_4ae7b58b, TypeJ>, Enc_81ac1d, PredRel { +tc_44fffc58, TypeJ>, Enc_81ac1d, PredRel { let Inst{0-0} = 0b0; let Inst{31-25} = 0b0101101; let isCall = 1; @@ -4797,7 +4904,7 @@ def J2_callf : HInst< (outs), (ins PredRegs:$Pu4, a30_2Imm:$Ii), "if (!$Pu4) call $Ii", -tc_1d81e60e, TypeJ>, Enc_daea09, PredRel { +tc_69bfb303, TypeJ>, Enc_daea09, PredRel { let Inst{0-0} = 0b0; let Inst{12-10} = 0b000; let Inst{21-21} = 0b1; @@ -4824,7 +4931,7 @@ def J2_callr : HInst< (outs), (ins IntRegs:$Rs32), "callr $Rs32", -tc_3bd75825, TypeJ>, Enc_ecbcc8 { +tc_362b0be2, TypeJ>, Enc_ecbcc8 { let Inst{13-0} = 0b00000000000000; let Inst{31-21} = 0b01010000101; let isCall = 1; @@ -4838,7 +4945,7 @@ def J2_callrf : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4) callr $Rs32", -tc_1ad90acd, TypeJ>, Enc_88d4d9 { +tc_dc51281d, TypeJ>, Enc_88d4d9 { let Inst{7-0} = 0b00000000; let Inst{13-10} = 0b0000; let Inst{31-21} = 0b01010001001; @@ -4856,7 +4963,7 @@ def J2_callrt : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4) callr $Rs32", -tc_1ad90acd, TypeJ>, Enc_88d4d9 { +tc_dc51281d, TypeJ>, Enc_88d4d9 { let Inst{7-0} = 0b00000000; let Inst{13-10} = 0b0000; let Inst{31-21} = 0b01010001000; @@ -4873,7 +4980,7 @@ def J2_callt : HInst< (outs), (ins PredRegs:$Pu4, a30_2Imm:$Ii), "if ($Pu4) call $Ii", -tc_1d81e60e, TypeJ>, Enc_daea09, PredRel { +tc_69bfb303, TypeJ>, Enc_daea09, PredRel { let Inst{0-0} = 0b0; let Inst{12-10} = 0b000; let Inst{21-21} = 0b0; @@ -4899,7 +5006,7 @@ def J2_endloop0 : HInst< (outs), (ins), "endloop0", -tc_1b6f7cec, TypeJ> { +tc_23708a21, TypeJ> { let Uses = [LC0, SA0]; let Defs = [LC0, P3, PC, USR]; let isBranch = 1; @@ -4910,7 +5017,7 @@ def J2_endloop01 : HInst< (outs), (ins), "endloop01", -tc_1b6f7cec, TypeJ> { +tc_23708a21, TypeJ> { let Uses = [LC0, LC1, SA0, SA1]; let Defs = [LC0, LC1, P3, PC, USR]; let isPseudo = 1; @@ -4919,7 +5026,7 @@ def J2_endloop1 : HInst< (outs), (ins), "endloop1", -tc_1b6f7cec, TypeJ> { +tc_23708a21, TypeJ> { let Uses = [LC1, SA1]; let Defs = [LC1, PC]; let isBranch = 1; @@ -4930,7 +5037,7 @@ def J2_jump : HInst< (outs), (ins b30_2Imm:$Ii), "jump $Ii", -tc_ae53734a, TypeJ>, Enc_81ac1d, PredNewRel { +tc_decdde8a, TypeJ>, Enc_81ac1d, PredNewRel { let Inst{0-0} = 0b0; let Inst{31-25} = 0b0101100; let isTerminator = 1; @@ -4938,8 +5045,8 @@ let isBranch = 1; let cofRelax2 = 1; let cofMax1 = 1; let Defs = [PC]; -let InputType = "imm"; let BaseOpcode = "J2_jump"; +let InputType = "imm"; let isBarrier = 1; let isPredicable = 1; let isExtendable = 1; @@ -4952,7 +5059,7 @@ def J2_jumpf : HInst< (outs), (ins PredRegs:$Pu4, b30_2Imm:$Ii), "if (!$Pu4) jump:nt $Ii", -tc_db2bce9c, TypeJ>, Enc_daea09, PredNewRel { +tc_56a124a7, TypeJ>, Enc_daea09, PredNewRel { let Inst{0-0} = 0b0; let Inst{12-10} = 0b000; let Inst{21-21} = 0b1; @@ -4965,8 +5072,8 @@ let cofRelax1 = 1; let cofRelax2 = 1; let cofMax1 = 1; let Defs = [PC]; -let InputType = "imm"; let BaseOpcode = "J2_jump"; +let InputType = "imm"; let isTaken = Inst{12}; let isExtendable = 1; let opExtendable = 1; @@ -4978,7 +5085,7 @@ def J2_jumpf_nopred_map : HInst< (outs), (ins PredRegs:$Pu4, b15_2Imm:$Ii), "if (!$Pu4) jump $Ii", -tc_db2bce9c, TypeMAPPING>, Requires<[HasV60]> { +tc_56a124a7, TypeMAPPING>, Requires<[HasV60]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -4986,7 +5093,7 @@ def J2_jumpfnew : HInst< (outs), (ins PredRegs:$Pu4, b30_2Imm:$Ii), "if (!$Pu4.new) jump:nt $Ii", -tc_20cdee80, TypeJ>, Enc_daea09, PredNewRel { +tc_eeda4109, TypeJ>, Enc_daea09, PredNewRel { let Inst{0-0} = 0b0; let Inst{12-10} = 0b010; let Inst{21-21} = 0b1; @@ -5000,8 +5107,8 @@ let cofRelax1 = 1; let cofRelax2 = 1; let cofMax1 = 1; let Defs = [PC]; -let InputType = "imm"; let BaseOpcode = "J2_jump"; +let InputType = "imm"; let isTaken = Inst{12}; let isExtendable = 1; let opExtendable = 1; @@ -5013,7 +5120,7 @@ def J2_jumpfnewpt : HInst< (outs), (ins PredRegs:$Pu4, b30_2Imm:$Ii), "if (!$Pu4.new) jump:t $Ii", -tc_20cdee80, TypeJ>, Enc_daea09, PredNewRel { +tc_eeda4109, TypeJ>, Enc_daea09, PredNewRel { let Inst{0-0} = 0b0; let Inst{12-10} = 0b110; let Inst{21-21} = 0b1; @@ -5027,8 +5134,8 @@ let cofRelax1 = 1; let cofRelax2 = 1; let cofMax1 = 1; let Defs = [PC]; -let InputType = "imm"; let BaseOpcode = "J2_jump"; +let InputType = "imm"; let isTaken = Inst{12}; let isExtendable = 1; let opExtendable = 1; @@ -5040,7 +5147,7 @@ def J2_jumpfpt : HInst< (outs), (ins PredRegs:$Pu4, b30_2Imm:$Ii), "if (!$Pu4) jump:t $Ii", -tc_cd374165, TypeJ>, Enc_daea09, Requires<[HasV60]>, PredNewRel { +tc_711c805f, TypeJ>, Enc_daea09, Requires<[HasV60]>, PredNewRel { let Inst{0-0} = 0b0; let Inst{12-10} = 0b100; let Inst{21-21} = 0b1; @@ -5053,8 +5160,8 @@ let cofRelax1 = 1; let cofRelax2 = 1; let cofMax1 = 1; let Defs = [PC]; -let InputType = "imm"; let BaseOpcode = "J2_jump"; +let InputType = "imm"; let isTaken = Inst{12}; let isExtendable = 1; let opExtendable = 1; @@ -5066,7 +5173,7 @@ def J2_jumpr : HInst< (outs), (ins IntRegs:$Rs32), "jumpr $Rs32", -tc_d5b7b0c1, TypeJ>, Enc_ecbcc8, PredNewRel { +tc_60e324ff, TypeJ>, Enc_ecbcc8, PredNewRel { let Inst{13-0} = 0b00000000000000; let Inst{31-21} = 0b01010010100; let isTerminator = 1; @@ -5074,8 +5181,8 @@ let isIndirectBranch = 1; let isBranch = 1; let cofMax1 = 1; let Defs = [PC]; -let InputType = "reg"; let BaseOpcode = "J2_jumpr"; +let InputType = "reg"; let isBarrier = 1; let isPredicable = 1; } @@ -5083,7 +5190,7 @@ def J2_jumprf : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4) jumpr:nt $Rs32", -tc_85c9c08f, TypeJ>, Enc_88d4d9, PredNewRel { +tc_2f573607, TypeJ>, Enc_88d4d9, PredNewRel { let Inst{7-0} = 0b00000000; let Inst{13-10} = 0b0000; let Inst{31-21} = 0b01010011011; @@ -5094,15 +5201,15 @@ let isIndirectBranch = 1; let isBranch = 1; let cofMax1 = 1; let Defs = [PC]; -let InputType = "reg"; let BaseOpcode = "J2_jumpr"; +let InputType = "reg"; let isTaken = Inst{12}; } def J2_jumprf_nopred_map : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4) jumpr $Rs32", -tc_85c9c08f, TypeMAPPING>, Requires<[HasV60]> { +tc_2f573607, TypeMAPPING>, Requires<[HasV60]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -5110,7 +5217,7 @@ def J2_jumprfnew : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4.new) jumpr:nt $Rs32", -tc_b51dc29a, TypeJ>, Enc_88d4d9, PredNewRel { +tc_ed03645c, TypeJ>, Enc_88d4d9, PredNewRel { let Inst{7-0} = 0b00000000; let Inst{13-10} = 0b0010; let Inst{31-21} = 0b01010011011; @@ -5122,15 +5229,15 @@ let isBranch = 1; let isPredicatedNew = 1; let cofMax1 = 1; let Defs = [PC]; -let InputType = "reg"; let BaseOpcode = "J2_jumpr"; +let InputType = "reg"; let isTaken = Inst{12}; } def J2_jumprfnewpt : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4.new) jumpr:t $Rs32", -tc_b51dc29a, TypeJ>, Enc_88d4d9, PredNewRel { +tc_ed03645c, TypeJ>, Enc_88d4d9, PredNewRel { let Inst{7-0} = 0b00000000; let Inst{13-10} = 0b0110; let Inst{31-21} = 0b01010011011; @@ -5142,15 +5249,15 @@ let isBranch = 1; let isPredicatedNew = 1; let cofMax1 = 1; let Defs = [PC]; -let InputType = "reg"; let BaseOpcode = "J2_jumpr"; +let InputType = "reg"; let isTaken = Inst{12}; } def J2_jumprfpt : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if (!$Pu4) jumpr:t $Rs32", -tc_e78647bd, TypeJ>, Enc_88d4d9, Requires<[HasV60]>, PredNewRel { +tc_42ff66ba, TypeJ>, Enc_88d4d9, Requires<[HasV60]>, PredNewRel { let Inst{7-0} = 0b00000000; let Inst{13-10} = 0b0100; let Inst{31-21} = 0b01010011011; @@ -5161,15 +5268,15 @@ let isIndirectBranch = 1; let isBranch = 1; let cofMax1 = 1; let Defs = [PC]; -let InputType = "reg"; let BaseOpcode = "J2_jumpr"; +let InputType = "reg"; let isTaken = Inst{12}; } def J2_jumprgtez : HInst< (outs), (ins IntRegs:$Rs32, b13_2Imm:$Ii), "if ($Rs32>=#0) jump:nt $Ii", -tc_d9d43ecb, TypeCR>, Enc_0fa531 { +tc_57a55b54, TypeCR>, Enc_0fa531 { let Inst{0-0} = 0b0; let Inst{12-12} = 0b0; let Inst{31-22} = 0b0110000101; @@ -5187,7 +5294,7 @@ def J2_jumprgtezpt : HInst< (outs), (ins IntRegs:$Rs32, b13_2Imm:$Ii), "if ($Rs32>=#0) jump:t $Ii", -tc_d9d43ecb, TypeCR>, Enc_0fa531 { +tc_57a55b54, TypeCR>, Enc_0fa531 { let Inst{0-0} = 0b0; let Inst{12-12} = 0b1; let Inst{31-22} = 0b0110000101; @@ -5205,7 +5312,7 @@ def J2_jumprltez : HInst< (outs), (ins IntRegs:$Rs32, b13_2Imm:$Ii), "if ($Rs32<=#0) jump:nt $Ii", -tc_d9d43ecb, TypeCR>, Enc_0fa531 { +tc_57a55b54, TypeCR>, Enc_0fa531 { let Inst{0-0} = 0b0; let Inst{12-12} = 0b0; let Inst{31-22} = 0b0110000111; @@ -5223,7 +5330,7 @@ def J2_jumprltezpt : HInst< (outs), (ins IntRegs:$Rs32, b13_2Imm:$Ii), "if ($Rs32<=#0) jump:t $Ii", -tc_d9d43ecb, TypeCR>, Enc_0fa531 { +tc_57a55b54, TypeCR>, Enc_0fa531 { let Inst{0-0} = 0b0; let Inst{12-12} = 0b1; let Inst{31-22} = 0b0110000111; @@ -5241,7 +5348,7 @@ def J2_jumprnz : HInst< (outs), (ins IntRegs:$Rs32, b13_2Imm:$Ii), "if ($Rs32==#0) jump:nt $Ii", -tc_d9d43ecb, TypeCR>, Enc_0fa531 { +tc_57a55b54, TypeCR>, Enc_0fa531 { let Inst{0-0} = 0b0; let Inst{12-12} = 0b0; let Inst{31-22} = 0b0110000110; @@ -5259,7 +5366,7 @@ def J2_jumprnzpt : HInst< (outs), (ins IntRegs:$Rs32, b13_2Imm:$Ii), "if ($Rs32==#0) jump:t $Ii", -tc_d9d43ecb, TypeCR>, Enc_0fa531 { +tc_57a55b54, TypeCR>, Enc_0fa531 { let Inst{0-0} = 0b0; let Inst{12-12} = 0b1; let Inst{31-22} = 0b0110000110; @@ -5277,7 +5384,7 @@ def J2_jumprt : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4) jumpr:nt $Rs32", -tc_85c9c08f, TypeJ>, Enc_88d4d9, PredNewRel { +tc_2f573607, TypeJ>, Enc_88d4d9, PredNewRel { let Inst{7-0} = 0b00000000; let Inst{13-10} = 0b0000; let Inst{31-21} = 0b01010011010; @@ -5287,15 +5394,15 @@ let isIndirectBranch = 1; let isBranch = 1; let cofMax1 = 1; let Defs = [PC]; -let InputType = "reg"; let BaseOpcode = "J2_jumpr"; +let InputType = "reg"; let isTaken = Inst{12}; } def J2_jumprt_nopred_map : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4) jumpr $Rs32", -tc_85c9c08f, TypeMAPPING>, Requires<[HasV60]> { +tc_2f573607, TypeMAPPING>, Requires<[HasV60]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -5303,7 +5410,7 @@ def J2_jumprtnew : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4.new) jumpr:nt $Rs32", -tc_b51dc29a, TypeJ>, Enc_88d4d9, PredNewRel { +tc_ed03645c, TypeJ>, Enc_88d4d9, PredNewRel { let Inst{7-0} = 0b00000000; let Inst{13-10} = 0b0010; let Inst{31-21} = 0b01010011010; @@ -5314,15 +5421,15 @@ let isBranch = 1; let isPredicatedNew = 1; let cofMax1 = 1; let Defs = [PC]; -let InputType = "reg"; let BaseOpcode = "J2_jumpr"; +let InputType = "reg"; let isTaken = Inst{12}; } def J2_jumprtnewpt : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4.new) jumpr:t $Rs32", -tc_b51dc29a, TypeJ>, Enc_88d4d9, PredNewRel { +tc_ed03645c, TypeJ>, Enc_88d4d9, PredNewRel { let Inst{7-0} = 0b00000000; let Inst{13-10} = 0b0110; let Inst{31-21} = 0b01010011010; @@ -5333,15 +5440,15 @@ let isBranch = 1; let isPredicatedNew = 1; let cofMax1 = 1; let Defs = [PC]; -let InputType = "reg"; let BaseOpcode = "J2_jumpr"; +let InputType = "reg"; let isTaken = Inst{12}; } def J2_jumprtpt : HInst< (outs), (ins PredRegs:$Pu4, IntRegs:$Rs32), "if ($Pu4) jumpr:t $Rs32", -tc_e78647bd, TypeJ>, Enc_88d4d9, Requires<[HasV60]>, PredNewRel { +tc_42ff66ba, TypeJ>, Enc_88d4d9, Requires<[HasV60]>, PredNewRel { let Inst{7-0} = 0b00000000; let Inst{13-10} = 0b0100; let Inst{31-21} = 0b01010011010; @@ -5351,15 +5458,15 @@ let isIndirectBranch = 1; let isBranch = 1; let cofMax1 = 1; let Defs = [PC]; -let InputType = "reg"; let BaseOpcode = "J2_jumpr"; +let InputType = "reg"; let isTaken = Inst{12}; } def J2_jumprz : HInst< (outs), (ins IntRegs:$Rs32, b13_2Imm:$Ii), "if ($Rs32!=#0) jump:nt $Ii", -tc_d9d43ecb, TypeCR>, Enc_0fa531 { +tc_57a55b54, TypeCR>, Enc_0fa531 { let Inst{0-0} = 0b0; let Inst{12-12} = 0b0; let Inst{31-22} = 0b0110000100; @@ -5377,7 +5484,7 @@ def J2_jumprzpt : HInst< (outs), (ins IntRegs:$Rs32, b13_2Imm:$Ii), "if ($Rs32!=#0) jump:t $Ii", -tc_d9d43ecb, TypeCR>, Enc_0fa531 { +tc_57a55b54, TypeCR>, Enc_0fa531 { let Inst{0-0} = 0b0; let Inst{12-12} = 0b1; let Inst{31-22} = 0b0110000100; @@ -5395,7 +5502,7 @@ def J2_jumpt : HInst< (outs), (ins PredRegs:$Pu4, b30_2Imm:$Ii), "if ($Pu4) jump:nt $Ii", -tc_db2bce9c, TypeJ>, Enc_daea09, PredNewRel { +tc_56a124a7, TypeJ>, Enc_daea09, PredNewRel { let Inst{0-0} = 0b0; let Inst{12-10} = 0b000; let Inst{21-21} = 0b0; @@ -5407,8 +5514,8 @@ let cofRelax1 = 1; let cofRelax2 = 1; let cofMax1 = 1; let Defs = [PC]; -let InputType = "imm"; let BaseOpcode = "J2_jump"; +let InputType = "imm"; let isTaken = Inst{12}; let isExtendable = 1; let opExtendable = 1; @@ -5420,7 +5527,7 @@ def J2_jumpt_nopred_map : HInst< (outs), (ins PredRegs:$Pu4, b15_2Imm:$Ii), "if ($Pu4) jump $Ii", -tc_db2bce9c, TypeMAPPING>, Requires<[HasV60]> { +tc_56a124a7, TypeMAPPING>, Requires<[HasV60]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -5428,7 +5535,7 @@ def J2_jumptnew : HInst< (outs), (ins PredRegs:$Pu4, b30_2Imm:$Ii), "if ($Pu4.new) jump:nt $Ii", -tc_20cdee80, TypeJ>, Enc_daea09, PredNewRel { +tc_eeda4109, TypeJ>, Enc_daea09, PredNewRel { let Inst{0-0} = 0b0; let Inst{12-10} = 0b010; let Inst{21-21} = 0b0; @@ -5441,8 +5548,8 @@ let cofRelax1 = 1; let cofRelax2 = 1; let cofMax1 = 1; let Defs = [PC]; -let InputType = "imm"; let BaseOpcode = "J2_jump"; +let InputType = "imm"; let isTaken = Inst{12}; let isExtendable = 1; let opExtendable = 1; @@ -5454,7 +5561,7 @@ def J2_jumptnewpt : HInst< (outs), (ins PredRegs:$Pu4, b30_2Imm:$Ii), "if ($Pu4.new) jump:t $Ii", -tc_20cdee80, TypeJ>, Enc_daea09, PredNewRel { +tc_eeda4109, TypeJ>, Enc_daea09, PredNewRel { let Inst{0-0} = 0b0; let Inst{12-10} = 0b110; let Inst{21-21} = 0b0; @@ -5467,8 +5574,8 @@ let cofRelax1 = 1; let cofRelax2 = 1; let cofMax1 = 1; let Defs = [PC]; -let InputType = "imm"; let BaseOpcode = "J2_jump"; +let InputType = "imm"; let isTaken = Inst{12}; let isExtendable = 1; let opExtendable = 1; @@ -5480,7 +5587,7 @@ def J2_jumptpt : HInst< (outs), (ins PredRegs:$Pu4, b30_2Imm:$Ii), "if ($Pu4) jump:t $Ii", -tc_cd374165, TypeJ>, Enc_daea09, Requires<[HasV60]>, PredNewRel { +tc_711c805f, TypeJ>, Enc_daea09, Requires<[HasV60]>, PredNewRel { let Inst{0-0} = 0b0; let Inst{12-10} = 0b100; let Inst{21-21} = 0b0; @@ -5492,8 +5599,8 @@ let cofRelax1 = 1; let cofRelax2 = 1; let cofMax1 = 1; let Defs = [PC]; -let InputType = "imm"; let BaseOpcode = "J2_jump"; +let InputType = "imm"; let isTaken = Inst{12}; let isExtendable = 1; let opExtendable = 1; @@ -5505,7 +5612,7 @@ def J2_loop0i : HInst< (outs), (ins b30_2Imm:$Ii, u10_0Imm:$II), "loop0($Ii,#$II)", -tc_a9d88b22, TypeCR>, Enc_4dc228 { +tc_1248597c, TypeCR>, Enc_4dc228 { let Inst{2-2} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b01101001000; @@ -5522,7 +5629,7 @@ def J2_loop0r : HInst< (outs), (ins b30_2Imm:$Ii, IntRegs:$Rs32), "loop0($Ii,$Rs32)", -tc_df3319ed, TypeCR>, Enc_864a5a { +tc_9406230a, TypeCR>, Enc_864a5a { let Inst{2-0} = 0b000; let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; @@ -5540,7 +5647,7 @@ def J2_loop1i : HInst< (outs), (ins b30_2Imm:$Ii, u10_0Imm:$II), "loop1($Ii,#$II)", -tc_a9d88b22, TypeCR>, Enc_4dc228 { +tc_1248597c, TypeCR>, Enc_4dc228 { let Inst{2-2} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b01101001001; @@ -5557,7 +5664,7 @@ def J2_loop1r : HInst< (outs), (ins b30_2Imm:$Ii, IntRegs:$Rs32), "loop1($Ii,$Rs32)", -tc_df3319ed, TypeCR>, Enc_864a5a { +tc_9406230a, TypeCR>, Enc_864a5a { let Inst{2-0} = 0b000; let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; @@ -5575,7 +5682,7 @@ def J2_pause : HInst< (outs), (ins u8_0Imm:$Ii), "pause(#$Ii)", -tc_8d9d0154, TypeJ>, Enc_a51a9a { +tc_d57d649c, TypeJ>, Enc_a51a9a { let Inst{1-0} = 0b00; let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; @@ -5586,7 +5693,7 @@ def J2_ploop1si : HInst< (outs), (ins b30_2Imm:$Ii, u10_0Imm:$II), "p3 = sp1loop0($Ii,#$II)", -tc_1c4528a2, TypeCR>, Enc_4dc228 { +tc_4abdbdc6, TypeCR>, Enc_4dc228 { let Inst{2-2} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b01101001101; @@ -5604,7 +5711,7 @@ def J2_ploop1sr : HInst< (outs), (ins b30_2Imm:$Ii, IntRegs:$Rs32), "p3 = sp1loop0($Ii,$Rs32)", -tc_32779c6f, TypeCR>, Enc_864a5a { +tc_6d861a95, TypeCR>, Enc_864a5a { let Inst{2-0} = 0b000; let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; @@ -5623,7 +5730,7 @@ def J2_ploop2si : HInst< (outs), (ins b30_2Imm:$Ii, u10_0Imm:$II), "p3 = sp2loop0($Ii,#$II)", -tc_1c4528a2, TypeCR>, Enc_4dc228 { +tc_4abdbdc6, TypeCR>, Enc_4dc228 { let Inst{2-2} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b01101001110; @@ -5641,7 +5748,7 @@ def J2_ploop2sr : HInst< (outs), (ins b30_2Imm:$Ii, IntRegs:$Rs32), "p3 = sp2loop0($Ii,$Rs32)", -tc_32779c6f, TypeCR>, Enc_864a5a { +tc_6d861a95, TypeCR>, Enc_864a5a { let Inst{2-0} = 0b000; let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; @@ -5660,7 +5767,7 @@ def J2_ploop3si : HInst< (outs), (ins b30_2Imm:$Ii, u10_0Imm:$II), "p3 = sp3loop0($Ii,#$II)", -tc_1c4528a2, TypeCR>, Enc_4dc228 { +tc_4abdbdc6, TypeCR>, Enc_4dc228 { let Inst{2-2} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b01101001111; @@ -5678,7 +5785,7 @@ def J2_ploop3sr : HInst< (outs), (ins b30_2Imm:$Ii, IntRegs:$Rs32), "p3 = sp3loop0($Ii,$Rs32)", -tc_32779c6f, TypeCR>, Enc_864a5a { +tc_6d861a95, TypeCR>, Enc_864a5a { let Inst{2-0} = 0b000; let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; @@ -5697,7 +5804,7 @@ def J2_trap0 : HInst< (outs), (ins u8_0Imm:$Ii), "trap0(#$Ii)", -tc_fc3999b4, TypeJ>, Enc_a51a9a { +tc_45f9d1be, TypeJ>, Enc_a51a9a { let Inst{1-0} = 0b00; let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; @@ -5709,7 +5816,7 @@ def J2_trap1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, u8_0Imm:$Ii), "trap1($Rx32,#$Ii)", -tc_b9e09e03, TypeJ>, Enc_33f8ba { +tc_53c851ab, TypeJ>, Enc_33f8ba, Requires<[HasV65]> { let Inst{1-0} = 0b00; let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; @@ -5726,7 +5833,7 @@ def J2_trap1_noregmap : HInst< (outs), (ins u8_0Imm:$Ii), "trap1(#$Ii)", -tc_b9e09e03, TypeMAPPING> { +tc_53c851ab, TypeMAPPING>, Requires<[HasV65]> { let hasSideEffects = 1; let isPseudo = 1; let isCodeGenOnly = 1; @@ -5735,7 +5842,7 @@ def J4_cmpeq_f_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), "if (!cmp.eq($Ns8.new,$Rt32)) jump:nt $Ii", -tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel { +tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -5761,7 +5868,7 @@ def J4_cmpeq_f_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), "if (!cmp.eq($Ns8.new,$Rt32)) jump:t $Ii", -tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel { +tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -5787,7 +5894,7 @@ def J4_cmpeq_fp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p0 = cmp.eq($Rs16,$Rt16); if (!p0.new) jump:nt $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b00; let Inst{31-22} = 0b0001010001; @@ -5813,7 +5920,7 @@ def J4_cmpeq_fp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p0 = cmp.eq($Rs16,$Rt16); if (!p0.new) jump:t $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b10; let Inst{31-22} = 0b0001010001; @@ -5839,7 +5946,7 @@ def J4_cmpeq_fp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p1 = cmp.eq($Rs16,$Rt16); if (!p1.new) jump:nt $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b01; let Inst{31-22} = 0b0001010001; @@ -5865,7 +5972,7 @@ def J4_cmpeq_fp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p1 = cmp.eq($Rs16,$Rt16); if (!p1.new) jump:t $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b11; let Inst{31-22} = 0b0001010001; @@ -5891,7 +5998,7 @@ def J4_cmpeq_t_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), "if (cmp.eq($Ns8.new,$Rt32)) jump:nt $Ii", -tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel { +tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -5916,7 +6023,7 @@ def J4_cmpeq_t_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), "if (cmp.eq($Ns8.new,$Rt32)) jump:t $Ii", -tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel { +tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -5941,7 +6048,7 @@ def J4_cmpeq_tp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p0 = cmp.eq($Rs16,$Rt16); if (p0.new) jump:nt $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b00; let Inst{31-22} = 0b0001010000; @@ -5966,7 +6073,7 @@ def J4_cmpeq_tp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p0 = cmp.eq($Rs16,$Rt16); if (p0.new) jump:t $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b10; let Inst{31-22} = 0b0001010000; @@ -5991,7 +6098,7 @@ def J4_cmpeq_tp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p1 = cmp.eq($Rs16,$Rt16); if (p1.new) jump:nt $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b01; let Inst{31-22} = 0b0001010000; @@ -6016,7 +6123,7 @@ def J4_cmpeq_tp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p1 = cmp.eq($Rs16,$Rt16); if (p1.new) jump:t $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b11; let Inst{31-22} = 0b0001010000; @@ -6041,7 +6148,7 @@ def J4_cmpeqi_f_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), "if (!cmp.eq($Ns8.new,#$II)) jump:nt $Ii", -tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -6067,7 +6174,7 @@ def J4_cmpeqi_f_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), "if (!cmp.eq($Ns8.new,#$II)) jump:t $Ii", -tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -6093,7 +6200,7 @@ def J4_cmpeqi_fp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p0 = cmp.eq($Rs16,#$II); if (!p0.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{31-22} = 0b0001000001; @@ -6119,7 +6226,7 @@ def J4_cmpeqi_fp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p0 = cmp.eq($Rs16,#$II); if (!p0.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{31-22} = 0b0001000001; @@ -6145,7 +6252,7 @@ def J4_cmpeqi_fp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p1 = cmp.eq($Rs16,#$II); if (!p1.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{31-22} = 0b0001001001; @@ -6171,7 +6278,7 @@ def J4_cmpeqi_fp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p1 = cmp.eq($Rs16,#$II); if (!p1.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{31-22} = 0b0001001001; @@ -6197,7 +6304,7 @@ def J4_cmpeqi_t_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), "if (cmp.eq($Ns8.new,#$II)) jump:nt $Ii", -tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -6222,7 +6329,7 @@ def J4_cmpeqi_t_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), "if (cmp.eq($Ns8.new,#$II)) jump:t $Ii", -tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -6247,7 +6354,7 @@ def J4_cmpeqi_tp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p0 = cmp.eq($Rs16,#$II); if (p0.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{31-22} = 0b0001000000; @@ -6272,7 +6379,7 @@ def J4_cmpeqi_tp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p0 = cmp.eq($Rs16,#$II); if (p0.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{31-22} = 0b0001000000; @@ -6297,7 +6404,7 @@ def J4_cmpeqi_tp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p1 = cmp.eq($Rs16,#$II); if (p1.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{31-22} = 0b0001001000; @@ -6322,7 +6429,7 @@ def J4_cmpeqi_tp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p1 = cmp.eq($Rs16,#$II); if (p1.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{31-22} = 0b0001001000; @@ -6347,7 +6454,7 @@ def J4_cmpeqn1_f_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), "if (!cmp.eq($Ns8.new,#$n1)) jump:nt $Ii", -tc_bd8382d1, TypeNCJ>, Enc_e90a15, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_e90a15, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000000; let Inst{19-19} = 0b0; @@ -6373,7 +6480,7 @@ def J4_cmpeqn1_f_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), "if (!cmp.eq($Ns8.new,#$n1)) jump:t $Ii", -tc_bd8382d1, TypeNCJ>, Enc_5a18b3, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_5a18b3, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100000; let Inst{19-19} = 0b0; @@ -6399,7 +6506,7 @@ def J4_cmpeqn1_fp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p0 = cmp.eq($Rs16,#$n1); if (!p0.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_1de724, PredRel { +tc_24f426ab, TypeCJ>, Enc_1de724, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000000; let Inst{31-22} = 0b0001000111; @@ -6425,7 +6532,7 @@ def J4_cmpeqn1_fp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p0 = cmp.eq($Rs16,#$n1); if (!p0.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_14640c, PredRel { +tc_24f426ab, TypeCJ>, Enc_14640c, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100000; let Inst{31-22} = 0b0001000111; @@ -6451,7 +6558,7 @@ def J4_cmpeqn1_fp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p1 = cmp.eq($Rs16,#$n1); if (!p1.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_668704, PredRel { +tc_24f426ab, TypeCJ>, Enc_668704, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000000; let Inst{31-22} = 0b0001001111; @@ -6477,7 +6584,7 @@ def J4_cmpeqn1_fp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p1 = cmp.eq($Rs16,#$n1); if (!p1.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_800e04, PredRel { +tc_24f426ab, TypeCJ>, Enc_800e04, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100000; let Inst{31-22} = 0b0001001111; @@ -6503,7 +6610,7 @@ def J4_cmpeqn1_t_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), "if (cmp.eq($Ns8.new,#$n1)) jump:nt $Ii", -tc_bd8382d1, TypeNCJ>, Enc_4aca3a, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_4aca3a, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000000; let Inst{19-19} = 0b0; @@ -6528,7 +6635,7 @@ def J4_cmpeqn1_t_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), "if (cmp.eq($Ns8.new,#$n1)) jump:t $Ii", -tc_bd8382d1, TypeNCJ>, Enc_f7ea77, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_f7ea77, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100000; let Inst{19-19} = 0b0; @@ -6553,7 +6660,7 @@ def J4_cmpeqn1_tp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p0 = cmp.eq($Rs16,#$n1); if (p0.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_405228, PredRel { +tc_24f426ab, TypeCJ>, Enc_405228, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000000; let Inst{31-22} = 0b0001000110; @@ -6578,7 +6685,7 @@ def J4_cmpeqn1_tp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p0 = cmp.eq($Rs16,#$n1); if (p0.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_3a2484, PredRel { +tc_24f426ab, TypeCJ>, Enc_3a2484, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100000; let Inst{31-22} = 0b0001000110; @@ -6603,7 +6710,7 @@ def J4_cmpeqn1_tp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p1 = cmp.eq($Rs16,#$n1); if (p1.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_736575, PredRel { +tc_24f426ab, TypeCJ>, Enc_736575, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000000; let Inst{31-22} = 0b0001001110; @@ -6628,7 +6735,7 @@ def J4_cmpeqn1_tp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p1 = cmp.eq($Rs16,#$n1); if (p1.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_8e583a, PredRel { +tc_24f426ab, TypeCJ>, Enc_8e583a, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100000; let Inst{31-22} = 0b0001001110; @@ -6653,7 +6760,7 @@ def J4_cmpgt_f_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), "if (!cmp.gt($Ns8.new,$Rt32)) jump:nt $Ii", -tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel { +tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -6679,7 +6786,7 @@ def J4_cmpgt_f_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), "if (!cmp.gt($Ns8.new,$Rt32)) jump:t $Ii", -tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel { +tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -6705,7 +6812,7 @@ def J4_cmpgt_fp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p0 = cmp.gt($Rs16,$Rt16); if (!p0.new) jump:nt $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b00; let Inst{31-22} = 0b0001010011; @@ -6731,7 +6838,7 @@ def J4_cmpgt_fp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p0 = cmp.gt($Rs16,$Rt16); if (!p0.new) jump:t $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b10; let Inst{31-22} = 0b0001010011; @@ -6757,7 +6864,7 @@ def J4_cmpgt_fp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p1 = cmp.gt($Rs16,$Rt16); if (!p1.new) jump:nt $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b01; let Inst{31-22} = 0b0001010011; @@ -6783,7 +6890,7 @@ def J4_cmpgt_fp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p1 = cmp.gt($Rs16,$Rt16); if (!p1.new) jump:t $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b11; let Inst{31-22} = 0b0001010011; @@ -6809,7 +6916,7 @@ def J4_cmpgt_t_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), "if (cmp.gt($Ns8.new,$Rt32)) jump:nt $Ii", -tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel { +tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -6834,7 +6941,7 @@ def J4_cmpgt_t_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), "if (cmp.gt($Ns8.new,$Rt32)) jump:t $Ii", -tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel { +tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -6859,7 +6966,7 @@ def J4_cmpgt_tp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p0 = cmp.gt($Rs16,$Rt16); if (p0.new) jump:nt $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b00; let Inst{31-22} = 0b0001010010; @@ -6884,7 +6991,7 @@ def J4_cmpgt_tp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p0 = cmp.gt($Rs16,$Rt16); if (p0.new) jump:t $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b10; let Inst{31-22} = 0b0001010010; @@ -6909,7 +7016,7 @@ def J4_cmpgt_tp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p1 = cmp.gt($Rs16,$Rt16); if (p1.new) jump:nt $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b01; let Inst{31-22} = 0b0001010010; @@ -6934,7 +7041,7 @@ def J4_cmpgt_tp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p1 = cmp.gt($Rs16,$Rt16); if (p1.new) jump:t $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b11; let Inst{31-22} = 0b0001010010; @@ -6959,7 +7066,7 @@ def J4_cmpgti_f_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), "if (!cmp.gt($Ns8.new,#$II)) jump:nt $Ii", -tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -6985,7 +7092,7 @@ def J4_cmpgti_f_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), "if (!cmp.gt($Ns8.new,#$II)) jump:t $Ii", -tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -7011,7 +7118,7 @@ def J4_cmpgti_fp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p0 = cmp.gt($Rs16,#$II); if (!p0.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{31-22} = 0b0001000011; @@ -7037,7 +7144,7 @@ def J4_cmpgti_fp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p0 = cmp.gt($Rs16,#$II); if (!p0.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{31-22} = 0b0001000011; @@ -7063,7 +7170,7 @@ def J4_cmpgti_fp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p1 = cmp.gt($Rs16,#$II); if (!p1.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{31-22} = 0b0001001011; @@ -7089,7 +7196,7 @@ def J4_cmpgti_fp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p1 = cmp.gt($Rs16,#$II); if (!p1.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{31-22} = 0b0001001011; @@ -7115,7 +7222,7 @@ def J4_cmpgti_t_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), "if (cmp.gt($Ns8.new,#$II)) jump:nt $Ii", -tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -7140,7 +7247,7 @@ def J4_cmpgti_t_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), "if (cmp.gt($Ns8.new,#$II)) jump:t $Ii", -tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -7165,7 +7272,7 @@ def J4_cmpgti_tp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p0 = cmp.gt($Rs16,#$II); if (p0.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{31-22} = 0b0001000010; @@ -7190,7 +7297,7 @@ def J4_cmpgti_tp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p0 = cmp.gt($Rs16,#$II); if (p0.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{31-22} = 0b0001000010; @@ -7215,7 +7322,7 @@ def J4_cmpgti_tp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p1 = cmp.gt($Rs16,#$II); if (p1.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{31-22} = 0b0001001010; @@ -7240,7 +7347,7 @@ def J4_cmpgti_tp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p1 = cmp.gt($Rs16,#$II); if (p1.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{31-22} = 0b0001001010; @@ -7265,7 +7372,7 @@ def J4_cmpgtn1_f_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), "if (!cmp.gt($Ns8.new,#$n1)) jump:nt $Ii", -tc_bd8382d1, TypeNCJ>, Enc_3694bd, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_3694bd, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000000; let Inst{19-19} = 0b0; @@ -7291,7 +7398,7 @@ def J4_cmpgtn1_f_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), "if (!cmp.gt($Ns8.new,#$n1)) jump:t $Ii", -tc_bd8382d1, TypeNCJ>, Enc_a6853f, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_a6853f, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100000; let Inst{19-19} = 0b0; @@ -7317,7 +7424,7 @@ def J4_cmpgtn1_fp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p0 = cmp.gt($Rs16,#$n1); if (!p0.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_a42857, PredRel { +tc_24f426ab, TypeCJ>, Enc_a42857, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000001; let Inst{31-22} = 0b0001000111; @@ -7343,7 +7450,7 @@ def J4_cmpgtn1_fp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p0 = cmp.gt($Rs16,#$n1); if (!p0.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_f6fe0b, PredRel { +tc_24f426ab, TypeCJ>, Enc_f6fe0b, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100001; let Inst{31-22} = 0b0001000111; @@ -7369,7 +7476,7 @@ def J4_cmpgtn1_fp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p1 = cmp.gt($Rs16,#$n1); if (!p1.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_3e3989, PredRel { +tc_24f426ab, TypeCJ>, Enc_3e3989, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000001; let Inst{31-22} = 0b0001001111; @@ -7395,7 +7502,7 @@ def J4_cmpgtn1_fp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p1 = cmp.gt($Rs16,#$n1); if (!p1.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_b909d2, PredRel { +tc_24f426ab, TypeCJ>, Enc_b909d2, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100001; let Inst{31-22} = 0b0001001111; @@ -7421,7 +7528,7 @@ def J4_cmpgtn1_t_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), "if (cmp.gt($Ns8.new,#$n1)) jump:nt $Ii", -tc_bd8382d1, TypeNCJ>, Enc_f82302, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_f82302, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000000; let Inst{19-19} = 0b0; @@ -7446,7 +7553,7 @@ def J4_cmpgtn1_t_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), "if (cmp.gt($Ns8.new,#$n1)) jump:t $Ii", -tc_bd8382d1, TypeNCJ>, Enc_6413b6, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_6413b6, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100000; let Inst{19-19} = 0b0; @@ -7471,7 +7578,7 @@ def J4_cmpgtn1_tp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p0 = cmp.gt($Rs16,#$n1); if (p0.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_b78edd, PredRel { +tc_24f426ab, TypeCJ>, Enc_b78edd, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000001; let Inst{31-22} = 0b0001000110; @@ -7496,7 +7603,7 @@ def J4_cmpgtn1_tp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p0 = cmp.gt($Rs16,#$n1); if (p0.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_041d7b, PredRel { +tc_24f426ab, TypeCJ>, Enc_041d7b, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100001; let Inst{31-22} = 0b0001000110; @@ -7521,7 +7628,7 @@ def J4_cmpgtn1_tp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p1 = cmp.gt($Rs16,#$n1); if (p1.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_b1e1fb, PredRel { +tc_24f426ab, TypeCJ>, Enc_b1e1fb, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000001; let Inst{31-22} = 0b0001001110; @@ -7546,7 +7653,7 @@ def J4_cmpgtn1_tp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), "p1 = cmp.gt($Rs16,#$n1); if (p1.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_178717, PredRel { +tc_24f426ab, TypeCJ>, Enc_178717, PredRel { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100001; let Inst{31-22} = 0b0001001110; @@ -7571,7 +7678,7 @@ def J4_cmpgtu_f_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), "if (!cmp.gtu($Ns8.new,$Rt32)) jump:nt $Ii", -tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel { +tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -7597,7 +7704,7 @@ def J4_cmpgtu_f_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), "if (!cmp.gtu($Ns8.new,$Rt32)) jump:t $Ii", -tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel { +tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -7623,7 +7730,7 @@ def J4_cmpgtu_fp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p0 = cmp.gtu($Rs16,$Rt16); if (!p0.new) jump:nt $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b00; let Inst{31-22} = 0b0001010101; @@ -7649,7 +7756,7 @@ def J4_cmpgtu_fp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p0 = cmp.gtu($Rs16,$Rt16); if (!p0.new) jump:t $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b10; let Inst{31-22} = 0b0001010101; @@ -7675,7 +7782,7 @@ def J4_cmpgtu_fp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p1 = cmp.gtu($Rs16,$Rt16); if (!p1.new) jump:nt $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b01; let Inst{31-22} = 0b0001010101; @@ -7701,7 +7808,7 @@ def J4_cmpgtu_fp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p1 = cmp.gtu($Rs16,$Rt16); if (!p1.new) jump:t $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b11; let Inst{31-22} = 0b0001010101; @@ -7727,7 +7834,7 @@ def J4_cmpgtu_t_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), "if (cmp.gtu($Ns8.new,$Rt32)) jump:nt $Ii", -tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel { +tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -7752,7 +7859,7 @@ def J4_cmpgtu_t_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), "if (cmp.gtu($Ns8.new,$Rt32)) jump:t $Ii", -tc_9bfd761f, TypeNCJ>, Enc_c9a18e, PredRel { +tc_24e109c7, TypeNCJ>, Enc_c9a18e, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -7777,7 +7884,7 @@ def J4_cmpgtu_tp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p0 = cmp.gtu($Rs16,$Rt16); if (p0.new) jump:nt $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b00; let Inst{31-22} = 0b0001010100; @@ -7802,7 +7909,7 @@ def J4_cmpgtu_tp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p0 = cmp.gtu($Rs16,$Rt16); if (p0.new) jump:t $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b10; let Inst{31-22} = 0b0001010100; @@ -7827,7 +7934,7 @@ def J4_cmpgtu_tp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p1 = cmp.gtu($Rs16,$Rt16); if (p1.new) jump:nt $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b01; let Inst{31-22} = 0b0001010100; @@ -7852,7 +7959,7 @@ def J4_cmpgtu_tp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), "p1 = cmp.gtu($Rs16,$Rt16); if (p1.new) jump:t $Ii", -tc_56336eb0, TypeCJ>, Enc_6a5972, PredRel { +tc_9e27f2f9, TypeCJ>, Enc_6a5972, PredRel { let Inst{0-0} = 0b0; let Inst{13-12} = 0b11; let Inst{31-22} = 0b0001010100; @@ -7877,7 +7984,7 @@ def J4_cmpgtui_f_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), "if (!cmp.gtu($Ns8.new,#$II)) jump:nt $Ii", -tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -7903,7 +8010,7 @@ def J4_cmpgtui_f_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), "if (!cmp.gtu($Ns8.new,#$II)) jump:t $Ii", -tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -7929,7 +8036,7 @@ def J4_cmpgtui_fp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p0 = cmp.gtu($Rs16,#$II); if (!p0.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{31-22} = 0b0001000101; @@ -7955,7 +8062,7 @@ def J4_cmpgtui_fp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p0 = cmp.gtu($Rs16,#$II); if (!p0.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{31-22} = 0b0001000101; @@ -7981,7 +8088,7 @@ def J4_cmpgtui_fp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p1 = cmp.gtu($Rs16,#$II); if (!p1.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{31-22} = 0b0001001101; @@ -8007,7 +8114,7 @@ def J4_cmpgtui_fp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p1 = cmp.gtu($Rs16,#$II); if (!p1.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{31-22} = 0b0001001101; @@ -8033,7 +8140,7 @@ def J4_cmpgtui_t_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), "if (cmp.gtu($Ns8.new,#$II)) jump:nt $Ii", -tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -8058,7 +8165,7 @@ def J4_cmpgtui_t_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), "if (cmp.gtu($Ns8.new,#$II)) jump:t $Ii", -tc_bd8382d1, TypeNCJ>, Enc_eafd18, PredRel { +tc_f6e2aff9, TypeNCJ>, Enc_eafd18, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -8083,7 +8190,7 @@ def J4_cmpgtui_tp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p0 = cmp.gtu($Rs16,#$II); if (p0.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{31-22} = 0b0001000100; @@ -8108,7 +8215,7 @@ def J4_cmpgtui_tp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p0 = cmp.gtu($Rs16,#$II); if (p0.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{31-22} = 0b0001000100; @@ -8133,7 +8240,7 @@ def J4_cmpgtui_tp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p1 = cmp.gtu($Rs16,#$II); if (p1.new) jump:nt $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{31-22} = 0b0001001100; @@ -8158,7 +8265,7 @@ def J4_cmpgtui_tp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), "p1 = cmp.gtu($Rs16,#$II); if (p1.new) jump:t $Ii", -tc_3d495a39, TypeCJ>, Enc_14d27a, PredRel { +tc_24f426ab, TypeCJ>, Enc_14d27a, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{31-22} = 0b0001001100; @@ -8183,7 +8290,7 @@ def J4_cmplt_f_jumpnv_nt : HInst< (outs), (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), "if (!cmp.gt($Rt32,$Ns8.new)) jump:nt $Ii", -tc_b343892a, TypeNCJ>, Enc_5de85f, PredRel { +tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -8209,7 +8316,7 @@ def J4_cmplt_f_jumpnv_t : HInst< (outs), (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), "if (!cmp.gt($Rt32,$Ns8.new)) jump:t $Ii", -tc_b343892a, TypeNCJ>, Enc_5de85f, PredRel { +tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -8235,7 +8342,7 @@ def J4_cmplt_t_jumpnv_nt : HInst< (outs), (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), "if (cmp.gt($Rt32,$Ns8.new)) jump:nt $Ii", -tc_b343892a, TypeNCJ>, Enc_5de85f, PredRel { +tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -8260,7 +8367,7 @@ def J4_cmplt_t_jumpnv_t : HInst< (outs), (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), "if (cmp.gt($Rt32,$Ns8.new)) jump:t $Ii", -tc_b343892a, TypeNCJ>, Enc_5de85f, PredRel { +tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -8285,7 +8392,7 @@ def J4_cmpltu_f_jumpnv_nt : HInst< (outs), (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), "if (!cmp.gtu($Rt32,$Ns8.new)) jump:nt $Ii", -tc_b343892a, TypeNCJ>, Enc_5de85f, PredRel { +tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -8311,7 +8418,7 @@ def J4_cmpltu_f_jumpnv_t : HInst< (outs), (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), "if (!cmp.gtu($Rt32,$Ns8.new)) jump:t $Ii", -tc_b343892a, TypeNCJ>, Enc_5de85f, PredRel { +tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -8337,7 +8444,7 @@ def J4_cmpltu_t_jumpnv_nt : HInst< (outs), (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), "if (cmp.gtu($Rt32,$Ns8.new)) jump:nt $Ii", -tc_b343892a, TypeNCJ>, Enc_5de85f, PredRel { +tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b0; let Inst{19-19} = 0b0; @@ -8362,7 +8469,7 @@ def J4_cmpltu_t_jumpnv_t : HInst< (outs), (ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), "if (cmp.gtu($Rt32,$Ns8.new)) jump:t $Ii", -tc_b343892a, TypeNCJ>, Enc_5de85f, PredRel { +tc_975a4e54, TypeNCJ>, Enc_5de85f, PredRel { let Inst{0-0} = 0b0; let Inst{13-13} = 0b1; let Inst{19-19} = 0b0; @@ -8387,7 +8494,7 @@ def J4_hintjumpr : HInst< (outs), (ins IntRegs:$Rs32), "hintjr($Rs32)", -tc_d5b7b0c1, TypeJ>, Enc_ecbcc8 { +tc_60e324ff, TypeJ>, Enc_ecbcc8 { let Inst{13-0} = 0b00000000000000; let Inst{31-21} = 0b01010010101; let isTerminator = 1; @@ -8399,7 +8506,7 @@ def J4_jumpseti : HInst< (outs GeneralSubRegs:$Rd16), (ins u6_0Imm:$II, b30_2Imm:$Ii), "$Rd16 = #$II ; jump $Ii", -tc_0663f615, TypeCJ>, Enc_9e4c3f { +tc_5502c366, TypeCJ>, Enc_9e4c3f { let Inst{0-0} = 0b0; let Inst{31-22} = 0b0001011000; let hasNewValue = 1; @@ -8419,7 +8526,7 @@ def J4_jumpsetr : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), "$Rd16 = $Rs16 ; jump $Ii", -tc_0663f615, TypeCJ>, Enc_66bce1 { +tc_5502c366, TypeCJ>, Enc_66bce1 { let Inst{0-0} = 0b0; let Inst{13-12} = 0b00; let Inst{31-22} = 0b0001011100; @@ -8440,7 +8547,7 @@ def J4_tstbit0_f_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, b30_2Imm:$Ii), "if (!tstbit($Ns8.new,#0)) jump:nt $Ii", -tc_8c945be0, TypeNCJ>, Enc_69d63b { +tc_7b9187d3, TypeNCJ>, Enc_69d63b { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000000; let Inst{19-19} = 0b0; @@ -8465,7 +8572,7 @@ def J4_tstbit0_f_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, b30_2Imm:$Ii), "if (!tstbit($Ns8.new,#0)) jump:t $Ii", -tc_8c945be0, TypeNCJ>, Enc_69d63b { +tc_7b9187d3, TypeNCJ>, Enc_69d63b { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100000; let Inst{19-19} = 0b0; @@ -8490,7 +8597,7 @@ def J4_tstbit0_fp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), "p0 = tstbit($Rs16,#0); if (!p0.new) jump:nt $Ii", -tc_2332b92e, TypeCJ>, Enc_ad1c74 { +tc_f999c66e, TypeCJ>, Enc_ad1c74 { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000011; let Inst{31-22} = 0b0001000111; @@ -8515,7 +8622,7 @@ def J4_tstbit0_fp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), "p0 = tstbit($Rs16,#0); if (!p0.new) jump:t $Ii", -tc_2332b92e, TypeCJ>, Enc_ad1c74 { +tc_f999c66e, TypeCJ>, Enc_ad1c74 { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100011; let Inst{31-22} = 0b0001000111; @@ -8540,7 +8647,7 @@ def J4_tstbit0_fp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), "p1 = tstbit($Rs16,#0); if (!p1.new) jump:nt $Ii", -tc_2332b92e, TypeCJ>, Enc_ad1c74 { +tc_f999c66e, TypeCJ>, Enc_ad1c74 { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000011; let Inst{31-22} = 0b0001001111; @@ -8565,7 +8672,7 @@ def J4_tstbit0_fp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), "p1 = tstbit($Rs16,#0); if (!p1.new) jump:t $Ii", -tc_2332b92e, TypeCJ>, Enc_ad1c74 { +tc_f999c66e, TypeCJ>, Enc_ad1c74 { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100011; let Inst{31-22} = 0b0001001111; @@ -8590,7 +8697,7 @@ def J4_tstbit0_t_jumpnv_nt : HInst< (outs), (ins IntRegs:$Ns8, b30_2Imm:$Ii), "if (tstbit($Ns8.new,#0)) jump:nt $Ii", -tc_8c945be0, TypeNCJ>, Enc_69d63b { +tc_7b9187d3, TypeNCJ>, Enc_69d63b { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000000; let Inst{19-19} = 0b0; @@ -8614,7 +8721,7 @@ def J4_tstbit0_t_jumpnv_t : HInst< (outs), (ins IntRegs:$Ns8, b30_2Imm:$Ii), "if (tstbit($Ns8.new,#0)) jump:t $Ii", -tc_8c945be0, TypeNCJ>, Enc_69d63b { +tc_7b9187d3, TypeNCJ>, Enc_69d63b { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100000; let Inst{19-19} = 0b0; @@ -8638,7 +8745,7 @@ def J4_tstbit0_tp0_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), "p0 = tstbit($Rs16,#0); if (p0.new) jump:nt $Ii", -tc_2332b92e, TypeCJ>, Enc_ad1c74 { +tc_f999c66e, TypeCJ>, Enc_ad1c74 { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000011; let Inst{31-22} = 0b0001000110; @@ -8662,7 +8769,7 @@ def J4_tstbit0_tp0_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), "p0 = tstbit($Rs16,#0); if (p0.new) jump:t $Ii", -tc_2332b92e, TypeCJ>, Enc_ad1c74 { +tc_f999c66e, TypeCJ>, Enc_ad1c74 { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100011; let Inst{31-22} = 0b0001000110; @@ -8686,7 +8793,7 @@ def J4_tstbit0_tp1_jump_nt : HInst< (outs), (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), "p1 = tstbit($Rs16,#0); if (p1.new) jump:nt $Ii", -tc_2332b92e, TypeCJ>, Enc_ad1c74 { +tc_f999c66e, TypeCJ>, Enc_ad1c74 { let Inst{0-0} = 0b0; let Inst{13-8} = 0b000011; let Inst{31-22} = 0b0001001110; @@ -8710,7 +8817,7 @@ def J4_tstbit0_tp1_jump_t : HInst< (outs), (ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), "p1 = tstbit($Rs16,#0); if (p1.new) jump:t $Ii", -tc_2332b92e, TypeCJ>, Enc_ad1c74 { +tc_f999c66e, TypeCJ>, Enc_ad1c74 { let Inst{0-0} = 0b0; let Inst{13-8} = 0b100011; let Inst{31-22} = 0b0001001110; @@ -8734,7 +8841,7 @@ def L2_deallocframe : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = deallocframe($Rs32):raw", -tc_15aa71c5, TypeLD>, Enc_3a3d62 { +tc_e9170fb7, TypeLD>, Enc_3a3d62 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10010000000; let accessSize = DoubleWordAccess; @@ -8746,7 +8853,7 @@ def L2_loadalignb_io : HInst< (outs DoubleRegs:$Ryy32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rs32, s32_0Imm:$Ii), "$Ryy32 = memb_fifo($Rs32+#$Ii)", -tc_5ef37dc4, TypeLD>, Enc_a27588 { +tc_fedb7e19, TypeLD>, Enc_a27588 { let Inst{24-21} = 0b0100; let Inst{31-27} = 0b10010; let addrMode = BaseImmOffset; @@ -8763,7 +8870,7 @@ def L2_loadalignb_pbr : HInst< (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), "$Ryy32 = memb_fifo($Rx32++$Mu2:brev)", -tc_3c76b0ff, TypeLD>, Enc_1f5d8f { +tc_1c7522a8, TypeLD>, Enc_1f5d8f { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011110100; let addrMode = PostInc; @@ -8775,7 +8882,7 @@ def L2_loadalignb_pci : HInst< (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2), "$Ryy32 = memb_fifo($Rx32++#$Ii:circ($Mu2))", -tc_785f65a7, TypeLD>, Enc_74aef2 { +tc_76bb5435, TypeLD>, Enc_74aef2 { let Inst{12-9} = 0b0000; let Inst{31-21} = 0b10011000100; let addrMode = PostInc; @@ -8788,7 +8895,7 @@ def L2_loadalignb_pcr : HInst< (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), "$Ryy32 = memb_fifo($Rx32++I:circ($Mu2))", -tc_3c76b0ff, TypeLD>, Enc_1f5d8f { +tc_1c7522a8, TypeLD>, Enc_1f5d8f { let Inst{12-5} = 0b00010000; let Inst{31-21} = 0b10011000100; let addrMode = PostInc; @@ -8801,7 +8908,7 @@ def L2_loadalignb_pi : HInst< (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_0Imm:$Ii), "$Ryy32 = memb_fifo($Rx32++#$Ii)", -tc_3c76b0ff, TypeLD>, Enc_6b197f { +tc_1c7522a8, TypeLD>, Enc_6b197f { let Inst{13-9} = 0b00000; let Inst{31-21} = 0b10011010100; let addrMode = PostInc; @@ -8813,7 +8920,7 @@ def L2_loadalignb_pr : HInst< (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), "$Ryy32 = memb_fifo($Rx32++$Mu2)", -tc_3c76b0ff, TypeLD>, Enc_1f5d8f { +tc_1c7522a8, TypeLD>, Enc_1f5d8f { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011100100; let addrMode = PostInc; @@ -8825,7 +8932,7 @@ def L2_loadalignb_zomap : HInst< (outs DoubleRegs:$Ryy32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rs32), "$Ryy32 = memb_fifo($Rs32)", -tc_5ef37dc4, TypeMAPPING> { +tc_fedb7e19, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let Constraints = "$Ryy32 = $Ryy32in"; @@ -8834,7 +8941,7 @@ def L2_loadalignh_io : HInst< (outs DoubleRegs:$Ryy32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rs32, s31_1Imm:$Ii), "$Ryy32 = memh_fifo($Rs32+#$Ii)", -tc_5ef37dc4, TypeLD>, Enc_5cd7e9 { +tc_fedb7e19, TypeLD>, Enc_5cd7e9 { let Inst{24-21} = 0b0010; let Inst{31-27} = 0b10010; let addrMode = BaseImmOffset; @@ -8851,7 +8958,7 @@ def L2_loadalignh_pbr : HInst< (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), "$Ryy32 = memh_fifo($Rx32++$Mu2:brev)", -tc_3c76b0ff, TypeLD>, Enc_1f5d8f { +tc_1c7522a8, TypeLD>, Enc_1f5d8f { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011110010; let addrMode = PostInc; @@ -8863,7 +8970,7 @@ def L2_loadalignh_pci : HInst< (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2), "$Ryy32 = memh_fifo($Rx32++#$Ii:circ($Mu2))", -tc_785f65a7, TypeLD>, Enc_9e2e1c { +tc_76bb5435, TypeLD>, Enc_9e2e1c { let Inst{12-9} = 0b0000; let Inst{31-21} = 0b10011000010; let addrMode = PostInc; @@ -8876,7 +8983,7 @@ def L2_loadalignh_pcr : HInst< (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), "$Ryy32 = memh_fifo($Rx32++I:circ($Mu2))", -tc_3c76b0ff, TypeLD>, Enc_1f5d8f { +tc_1c7522a8, TypeLD>, Enc_1f5d8f { let Inst{12-5} = 0b00010000; let Inst{31-21} = 0b10011000010; let addrMode = PostInc; @@ -8889,7 +8996,7 @@ def L2_loadalignh_pi : HInst< (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_1Imm:$Ii), "$Ryy32 = memh_fifo($Rx32++#$Ii)", -tc_3c76b0ff, TypeLD>, Enc_bd1cbc { +tc_1c7522a8, TypeLD>, Enc_bd1cbc { let Inst{13-9} = 0b00000; let Inst{31-21} = 0b10011010010; let addrMode = PostInc; @@ -8901,7 +9008,7 @@ def L2_loadalignh_pr : HInst< (outs DoubleRegs:$Ryy32, IntRegs:$Rx32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), "$Ryy32 = memh_fifo($Rx32++$Mu2)", -tc_3c76b0ff, TypeLD>, Enc_1f5d8f { +tc_1c7522a8, TypeLD>, Enc_1f5d8f { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011100010; let addrMode = PostInc; @@ -8913,7 +9020,7 @@ def L2_loadalignh_zomap : HInst< (outs DoubleRegs:$Ryy32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rs32), "$Ryy32 = memh_fifo($Rs32)", -tc_5ef37dc4, TypeMAPPING> { +tc_fedb7e19, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let Constraints = "$Ryy32 = $Ryy32in"; @@ -8922,7 +9029,7 @@ def L2_loadbsw2_io : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s31_1Imm:$Ii), "$Rd32 = membh($Rs32+#$Ii)", -tc_17e0d2cd, TypeLD>, Enc_de0214 { +tc_4222e6bf, TypeLD>, Enc_de0214 { let Inst{24-21} = 0b0001; let Inst{31-27} = 0b10010; let hasNewValue = 1; @@ -8940,7 +9047,7 @@ def L2_loadbsw2_pbr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = membh($Rx32++$Mu2:brev)", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011110001; let hasNewValue = 1; @@ -8954,7 +9061,7 @@ def L2_loadbsw2_pci : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2), "$Rd32 = membh($Rx32++#$Ii:circ($Mu2))", -tc_e93a3d71, TypeLD>, Enc_e83554 { +tc_5ceb2f9e, TypeLD>, Enc_e83554 { let Inst{12-9} = 0b0000; let Inst{31-21} = 0b10011000001; let hasNewValue = 1; @@ -8969,7 +9076,7 @@ def L2_loadbsw2_pcr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = membh($Rx32++I:circ($Mu2))", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00010000; let Inst{31-21} = 0b10011000001; let hasNewValue = 1; @@ -8984,7 +9091,7 @@ def L2_loadbsw2_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii), "$Rd32 = membh($Rx32++#$Ii)", -tc_44d3da28, TypeLD>, Enc_152467 { +tc_075c8dd8, TypeLD>, Enc_152467 { let Inst{13-9} = 0b00000; let Inst{31-21} = 0b10011010001; let hasNewValue = 1; @@ -8998,7 +9105,7 @@ def L2_loadbsw2_pr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = membh($Rx32++$Mu2)", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011100001; let hasNewValue = 1; @@ -9012,7 +9119,7 @@ def L2_loadbsw2_zomap : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = membh($Rs32)", -tc_17e0d2cd, TypeMAPPING> { +tc_4222e6bf, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -9022,7 +9129,7 @@ def L2_loadbsw4_io : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, s30_2Imm:$Ii), "$Rdd32 = membh($Rs32+#$Ii)", -tc_17e0d2cd, TypeLD>, Enc_2d7491 { +tc_4222e6bf, TypeLD>, Enc_2d7491 { let Inst{24-21} = 0b0111; let Inst{31-27} = 0b10010; let addrMode = BaseImmOffset; @@ -9038,7 +9145,7 @@ def L2_loadbsw4_pbr : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rdd32 = membh($Rx32++$Mu2:brev)", -tc_44d3da28, TypeLD>, Enc_7eee72 { +tc_075c8dd8, TypeLD>, Enc_7eee72 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011110111; let addrMode = PostInc; @@ -9050,7 +9157,7 @@ def L2_loadbsw4_pci : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2), "$Rdd32 = membh($Rx32++#$Ii:circ($Mu2))", -tc_e93a3d71, TypeLD>, Enc_70b24b { +tc_5ceb2f9e, TypeLD>, Enc_70b24b { let Inst{12-9} = 0b0000; let Inst{31-21} = 0b10011000111; let addrMode = PostInc; @@ -9063,7 +9170,7 @@ def L2_loadbsw4_pcr : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rdd32 = membh($Rx32++I:circ($Mu2))", -tc_44d3da28, TypeLD>, Enc_7eee72 { +tc_075c8dd8, TypeLD>, Enc_7eee72 { let Inst{12-5} = 0b00010000; let Inst{31-21} = 0b10011000111; let addrMode = PostInc; @@ -9076,7 +9183,7 @@ def L2_loadbsw4_pi : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_2Imm:$Ii), "$Rdd32 = membh($Rx32++#$Ii)", -tc_44d3da28, TypeLD>, Enc_71f1b4 { +tc_075c8dd8, TypeLD>, Enc_71f1b4 { let Inst{13-9} = 0b00000; let Inst{31-21} = 0b10011010111; let addrMode = PostInc; @@ -9088,7 +9195,7 @@ def L2_loadbsw4_pr : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rdd32 = membh($Rx32++$Mu2)", -tc_44d3da28, TypeLD>, Enc_7eee72 { +tc_075c8dd8, TypeLD>, Enc_7eee72 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011100111; let addrMode = PostInc; @@ -9100,7 +9207,7 @@ def L2_loadbsw4_zomap : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = membh($Rs32)", -tc_17e0d2cd, TypeMAPPING> { +tc_4222e6bf, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -9108,7 +9215,7 @@ def L2_loadbzw2_io : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s31_1Imm:$Ii), "$Rd32 = memubh($Rs32+#$Ii)", -tc_17e0d2cd, TypeLD>, Enc_de0214 { +tc_4222e6bf, TypeLD>, Enc_de0214 { let Inst{24-21} = 0b0011; let Inst{31-27} = 0b10010; let hasNewValue = 1; @@ -9126,7 +9233,7 @@ def L2_loadbzw2_pbr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memubh($Rx32++$Mu2:brev)", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011110011; let hasNewValue = 1; @@ -9140,7 +9247,7 @@ def L2_loadbzw2_pci : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2), "$Rd32 = memubh($Rx32++#$Ii:circ($Mu2))", -tc_e93a3d71, TypeLD>, Enc_e83554 { +tc_5ceb2f9e, TypeLD>, Enc_e83554 { let Inst{12-9} = 0b0000; let Inst{31-21} = 0b10011000011; let hasNewValue = 1; @@ -9155,7 +9262,7 @@ def L2_loadbzw2_pcr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memubh($Rx32++I:circ($Mu2))", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00010000; let Inst{31-21} = 0b10011000011; let hasNewValue = 1; @@ -9170,7 +9277,7 @@ def L2_loadbzw2_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii), "$Rd32 = memubh($Rx32++#$Ii)", -tc_44d3da28, TypeLD>, Enc_152467 { +tc_075c8dd8, TypeLD>, Enc_152467 { let Inst{13-9} = 0b00000; let Inst{31-21} = 0b10011010011; let hasNewValue = 1; @@ -9184,7 +9291,7 @@ def L2_loadbzw2_pr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memubh($Rx32++$Mu2)", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011100011; let hasNewValue = 1; @@ -9198,7 +9305,7 @@ def L2_loadbzw2_zomap : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = memubh($Rs32)", -tc_17e0d2cd, TypeMAPPING> { +tc_4222e6bf, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -9208,7 +9315,7 @@ def L2_loadbzw4_io : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, s30_2Imm:$Ii), "$Rdd32 = memubh($Rs32+#$Ii)", -tc_17e0d2cd, TypeLD>, Enc_2d7491 { +tc_4222e6bf, TypeLD>, Enc_2d7491 { let Inst{24-21} = 0b0101; let Inst{31-27} = 0b10010; let addrMode = BaseImmOffset; @@ -9224,7 +9331,7 @@ def L2_loadbzw4_pbr : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rdd32 = memubh($Rx32++$Mu2:brev)", -tc_44d3da28, TypeLD>, Enc_7eee72 { +tc_075c8dd8, TypeLD>, Enc_7eee72 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011110101; let addrMode = PostInc; @@ -9236,7 +9343,7 @@ def L2_loadbzw4_pci : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2), "$Rdd32 = memubh($Rx32++#$Ii:circ($Mu2))", -tc_e93a3d71, TypeLD>, Enc_70b24b { +tc_5ceb2f9e, TypeLD>, Enc_70b24b { let Inst{12-9} = 0b0000; let Inst{31-21} = 0b10011000101; let addrMode = PostInc; @@ -9249,7 +9356,7 @@ def L2_loadbzw4_pcr : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rdd32 = memubh($Rx32++I:circ($Mu2))", -tc_44d3da28, TypeLD>, Enc_7eee72 { +tc_075c8dd8, TypeLD>, Enc_7eee72 { let Inst{12-5} = 0b00010000; let Inst{31-21} = 0b10011000101; let addrMode = PostInc; @@ -9262,7 +9369,7 @@ def L2_loadbzw4_pi : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_2Imm:$Ii), "$Rdd32 = memubh($Rx32++#$Ii)", -tc_44d3da28, TypeLD>, Enc_71f1b4 { +tc_075c8dd8, TypeLD>, Enc_71f1b4 { let Inst{13-9} = 0b00000; let Inst{31-21} = 0b10011010101; let addrMode = PostInc; @@ -9274,7 +9381,7 @@ def L2_loadbzw4_pr : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rdd32 = memubh($Rx32++$Mu2)", -tc_44d3da28, TypeLD>, Enc_7eee72 { +tc_075c8dd8, TypeLD>, Enc_7eee72 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011100101; let addrMode = PostInc; @@ -9286,7 +9393,7 @@ def L2_loadbzw4_zomap : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = memubh($Rs32)", -tc_17e0d2cd, TypeMAPPING> { +tc_4222e6bf, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -9294,7 +9401,7 @@ def L2_loadrb_io : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Rd32 = memb($Rs32+#$Ii)", -tc_17e0d2cd, TypeLD>, Enc_211aaa, AddrModeRel, PostInc_BaseImm { +tc_4222e6bf, TypeLD>, Enc_211aaa, AddrModeRel, PostInc_BaseImm { let Inst{24-21} = 0b1000; let Inst{31-27} = 0b10010; let hasNewValue = 1; @@ -9302,8 +9409,8 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = ByteAccess; let mayLoad = 1; -let CextOpcode = "L2_loadrb"; let BaseOpcode = "L2_loadrb_io"; +let CextOpcode = "L2_loadrb"; let isPredicable = 1; let isExtendable = 1; let opExtendable = 2; @@ -9315,7 +9422,7 @@ def L2_loadrb_pbr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memb($Rx32++$Mu2:brev)", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011111000; let hasNewValue = 1; @@ -9329,7 +9436,7 @@ def L2_loadrb_pci : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2), "$Rd32 = memb($Rx32++#$Ii:circ($Mu2))", -tc_e93a3d71, TypeLD>, Enc_e0a47a { +tc_5ceb2f9e, TypeLD>, Enc_e0a47a { let Inst{12-9} = 0b0000; let Inst{31-21} = 0b10011001000; let hasNewValue = 1; @@ -9344,7 +9451,7 @@ def L2_loadrb_pcr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memb($Rx32++I:circ($Mu2))", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00010000; let Inst{31-21} = 0b10011001000; let hasNewValue = 1; @@ -9359,7 +9466,7 @@ def L2_loadrb_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_0Imm:$Ii), "$Rd32 = memb($Rx32++#$Ii)", -tc_44d3da28, TypeLD>, Enc_222336, PredNewRel, PostInc_BaseImm { +tc_075c8dd8, TypeLD>, Enc_222336, PredNewRel, PostInc_BaseImm { let Inst{13-9} = 0b00000; let Inst{31-21} = 0b10011011000; let hasNewValue = 1; @@ -9367,8 +9474,8 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = ByteAccess; let mayLoad = 1; -let CextOpcode = "L2_loadrb"; let BaseOpcode = "L2_loadrb_pi"; +let CextOpcode = "L2_loadrb"; let isPredicable = 1; let Constraints = "$Rx32 = $Rx32in"; } @@ -9376,7 +9483,7 @@ def L2_loadrb_pr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memb($Rx32++$Mu2)", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011101000; let hasNewValue = 1; @@ -9390,7 +9497,7 @@ def L2_loadrb_zomap : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = memb($Rs32)", -tc_17e0d2cd, TypeMAPPING> { +tc_4222e6bf, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -9400,7 +9507,7 @@ def L2_loadrbgp : HInst< (outs IntRegs:$Rd32), (ins u32_0Imm:$Ii), "$Rd32 = memb(gp+#$Ii)", -tc_c4db48cb, TypeV2LDST>, Enc_25bef0, AddrModeRel { +tc_8a6d0d94, TypeV2LDST>, Enc_25bef0, AddrModeRel { let Inst{24-21} = 0b1000; let Inst{31-27} = 0b01001; let hasNewValue = 1; @@ -9419,14 +9526,14 @@ def L2_loadrd_io : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, s29_3Imm:$Ii), "$Rdd32 = memd($Rs32+#$Ii)", -tc_17e0d2cd, TypeLD>, Enc_fa3ba4, AddrModeRel, PostInc_BaseImm { +tc_4222e6bf, TypeLD>, Enc_fa3ba4, AddrModeRel, PostInc_BaseImm { let Inst{24-21} = 0b1110; let Inst{31-27} = 0b10010; let addrMode = BaseImmOffset; let accessSize = DoubleWordAccess; let mayLoad = 1; -let CextOpcode = "L2_loadrd"; let BaseOpcode = "L2_loadrd_io"; +let CextOpcode = "L2_loadrd"; let isPredicable = 1; let isExtendable = 1; let opExtendable = 2; @@ -9438,7 +9545,7 @@ def L2_loadrd_pbr : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rdd32 = memd($Rx32++$Mu2:brev)", -tc_44d3da28, TypeLD>, Enc_7eee72 { +tc_075c8dd8, TypeLD>, Enc_7eee72 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011111110; let addrMode = PostInc; @@ -9450,7 +9557,7 @@ def L2_loadrd_pci : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_3Imm:$Ii, ModRegs:$Mu2), "$Rdd32 = memd($Rx32++#$Ii:circ($Mu2))", -tc_e93a3d71, TypeLD>, Enc_b05839 { +tc_5ceb2f9e, TypeLD>, Enc_b05839 { let Inst{12-9} = 0b0000; let Inst{31-21} = 0b10011001110; let addrMode = PostInc; @@ -9463,7 +9570,7 @@ def L2_loadrd_pcr : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rdd32 = memd($Rx32++I:circ($Mu2))", -tc_44d3da28, TypeLD>, Enc_7eee72 { +tc_075c8dd8, TypeLD>, Enc_7eee72 { let Inst{12-5} = 0b00010000; let Inst{31-21} = 0b10011001110; let addrMode = PostInc; @@ -9476,14 +9583,14 @@ def L2_loadrd_pi : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_3Imm:$Ii), "$Rdd32 = memd($Rx32++#$Ii)", -tc_44d3da28, TypeLD>, Enc_5bdd42, PredNewRel, PostInc_BaseImm { +tc_075c8dd8, TypeLD>, Enc_5bdd42, PredNewRel, PostInc_BaseImm { let Inst{13-9} = 0b00000; let Inst{31-21} = 0b10011011110; let addrMode = PostInc; let accessSize = DoubleWordAccess; let mayLoad = 1; -let CextOpcode = "L2_loadrd"; let BaseOpcode = "L2_loadrd_pi"; +let CextOpcode = "L2_loadrd"; let isPredicable = 1; let Constraints = "$Rx32 = $Rx32in"; } @@ -9491,7 +9598,7 @@ def L2_loadrd_pr : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rdd32 = memd($Rx32++$Mu2)", -tc_44d3da28, TypeLD>, Enc_7eee72 { +tc_075c8dd8, TypeLD>, Enc_7eee72 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011101110; let addrMode = PostInc; @@ -9503,7 +9610,7 @@ def L2_loadrd_zomap : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = memd($Rs32)", -tc_17e0d2cd, TypeMAPPING> { +tc_4222e6bf, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -9511,7 +9618,7 @@ def L2_loadrdgp : HInst< (outs DoubleRegs:$Rdd32), (ins u29_3Imm:$Ii), "$Rdd32 = memd(gp+#$Ii)", -tc_c4db48cb, TypeV2LDST>, Enc_509701, AddrModeRel { +tc_8a6d0d94, TypeV2LDST>, Enc_509701, AddrModeRel { let Inst{24-21} = 0b1110; let Inst{31-27} = 0b01001; let accessSize = DoubleWordAccess; @@ -9528,7 +9635,7 @@ def L2_loadrh_io : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s31_1Imm:$Ii), "$Rd32 = memh($Rs32+#$Ii)", -tc_17e0d2cd, TypeLD>, Enc_de0214, AddrModeRel, PostInc_BaseImm { +tc_4222e6bf, TypeLD>, Enc_de0214, AddrModeRel, PostInc_BaseImm { let Inst{24-21} = 0b1010; let Inst{31-27} = 0b10010; let hasNewValue = 1; @@ -9536,8 +9643,8 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let mayLoad = 1; -let CextOpcode = "L2_loadrh"; let BaseOpcode = "L2_loadrh_io"; +let CextOpcode = "L2_loadrh"; let isPredicable = 1; let isExtendable = 1; let opExtendable = 2; @@ -9549,7 +9656,7 @@ def L2_loadrh_pbr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memh($Rx32++$Mu2:brev)", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011111010; let hasNewValue = 1; @@ -9563,7 +9670,7 @@ def L2_loadrh_pci : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2), "$Rd32 = memh($Rx32++#$Ii:circ($Mu2))", -tc_e93a3d71, TypeLD>, Enc_e83554 { +tc_5ceb2f9e, TypeLD>, Enc_e83554 { let Inst{12-9} = 0b0000; let Inst{31-21} = 0b10011001010; let hasNewValue = 1; @@ -9578,7 +9685,7 @@ def L2_loadrh_pcr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memh($Rx32++I:circ($Mu2))", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00010000; let Inst{31-21} = 0b10011001010; let hasNewValue = 1; @@ -9593,7 +9700,7 @@ def L2_loadrh_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii), "$Rd32 = memh($Rx32++#$Ii)", -tc_44d3da28, TypeLD>, Enc_152467, PredNewRel, PostInc_BaseImm { +tc_075c8dd8, TypeLD>, Enc_152467, PredNewRel, PostInc_BaseImm { let Inst{13-9} = 0b00000; let Inst{31-21} = 0b10011011010; let hasNewValue = 1; @@ -9601,8 +9708,8 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HalfWordAccess; let mayLoad = 1; -let CextOpcode = "L2_loadrh"; let BaseOpcode = "L2_loadrh_pi"; +let CextOpcode = "L2_loadrh"; let isPredicable = 1; let Constraints = "$Rx32 = $Rx32in"; } @@ -9610,7 +9717,7 @@ def L2_loadrh_pr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memh($Rx32++$Mu2)", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011101010; let hasNewValue = 1; @@ -9624,7 +9731,7 @@ def L2_loadrh_zomap : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = memh($Rs32)", -tc_17e0d2cd, TypeMAPPING> { +tc_4222e6bf, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -9634,7 +9741,7 @@ def L2_loadrhgp : HInst< (outs IntRegs:$Rd32), (ins u31_1Imm:$Ii), "$Rd32 = memh(gp+#$Ii)", -tc_c4db48cb, TypeV2LDST>, Enc_8df4be, AddrModeRel { +tc_8a6d0d94, TypeV2LDST>, Enc_8df4be, AddrModeRel { let Inst{24-21} = 0b1010; let Inst{31-27} = 0b01001; let hasNewValue = 1; @@ -9653,7 +9760,7 @@ def L2_loadri_io : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s30_2Imm:$Ii), "$Rd32 = memw($Rs32+#$Ii)", -tc_17e0d2cd, TypeLD>, Enc_2a3787, AddrModeRel, PostInc_BaseImm { +tc_4222e6bf, TypeLD>, Enc_2a3787, AddrModeRel, PostInc_BaseImm { let Inst{24-21} = 0b1100; let Inst{31-27} = 0b10010; let hasNewValue = 1; @@ -9661,8 +9768,8 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = WordAccess; let mayLoad = 1; -let CextOpcode = "L2_loadri"; let BaseOpcode = "L2_loadri_io"; +let CextOpcode = "L2_loadri"; let isPredicable = 1; let isExtendable = 1; let opExtendable = 2; @@ -9674,7 +9781,7 @@ def L2_loadri_pbr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memw($Rx32++$Mu2:brev)", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011111100; let hasNewValue = 1; @@ -9688,7 +9795,7 @@ def L2_loadri_pci : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2), "$Rd32 = memw($Rx32++#$Ii:circ($Mu2))", -tc_e93a3d71, TypeLD>, Enc_27fd0e { +tc_5ceb2f9e, TypeLD>, Enc_27fd0e { let Inst{12-9} = 0b0000; let Inst{31-21} = 0b10011001100; let hasNewValue = 1; @@ -9703,7 +9810,7 @@ def L2_loadri_pcr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memw($Rx32++I:circ($Mu2))", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00010000; let Inst{31-21} = 0b10011001100; let hasNewValue = 1; @@ -9718,7 +9825,7 @@ def L2_loadri_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_2Imm:$Ii), "$Rd32 = memw($Rx32++#$Ii)", -tc_44d3da28, TypeLD>, Enc_3d920a, PredNewRel, PostInc_BaseImm { +tc_075c8dd8, TypeLD>, Enc_3d920a, PredNewRel, PostInc_BaseImm { let Inst{13-9} = 0b00000; let Inst{31-21} = 0b10011011100; let hasNewValue = 1; @@ -9726,8 +9833,8 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = WordAccess; let mayLoad = 1; -let CextOpcode = "L2_loadri"; let BaseOpcode = "L2_loadri_pi"; +let CextOpcode = "L2_loadri"; let isPredicable = 1; let Constraints = "$Rx32 = $Rx32in"; } @@ -9735,7 +9842,7 @@ def L2_loadri_pr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memw($Rx32++$Mu2)", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011101100; let hasNewValue = 1; @@ -9749,7 +9856,7 @@ def L2_loadri_zomap : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = memw($Rs32)", -tc_17e0d2cd, TypeMAPPING> { +tc_4222e6bf, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -9759,7 +9866,7 @@ def L2_loadrigp : HInst< (outs IntRegs:$Rd32), (ins u30_2Imm:$Ii), "$Rd32 = memw(gp+#$Ii)", -tc_c4db48cb, TypeV2LDST>, Enc_4f4ed7, AddrModeRel { +tc_8a6d0d94, TypeV2LDST>, Enc_4f4ed7, AddrModeRel { let Inst{24-21} = 0b1100; let Inst{31-27} = 0b01001; let hasNewValue = 1; @@ -9778,7 +9885,7 @@ def L2_loadrub_io : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s32_0Imm:$Ii), "$Rd32 = memub($Rs32+#$Ii)", -tc_17e0d2cd, TypeLD>, Enc_211aaa, AddrModeRel, PostInc_BaseImm { +tc_4222e6bf, TypeLD>, Enc_211aaa, AddrModeRel, PostInc_BaseImm { let Inst{24-21} = 0b1001; let Inst{31-27} = 0b10010; let hasNewValue = 1; @@ -9786,8 +9893,8 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = ByteAccess; let mayLoad = 1; -let CextOpcode = "L2_loadrub"; let BaseOpcode = "L2_loadrub_io"; +let CextOpcode = "L2_loadrub"; let isPredicable = 1; let isExtendable = 1; let opExtendable = 2; @@ -9799,7 +9906,7 @@ def L2_loadrub_pbr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memub($Rx32++$Mu2:brev)", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011111001; let hasNewValue = 1; @@ -9813,7 +9920,7 @@ def L2_loadrub_pci : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2), "$Rd32 = memub($Rx32++#$Ii:circ($Mu2))", -tc_e93a3d71, TypeLD>, Enc_e0a47a { +tc_5ceb2f9e, TypeLD>, Enc_e0a47a { let Inst{12-9} = 0b0000; let Inst{31-21} = 0b10011001001; let hasNewValue = 1; @@ -9828,7 +9935,7 @@ def L2_loadrub_pcr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memub($Rx32++I:circ($Mu2))", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00010000; let Inst{31-21} = 0b10011001001; let hasNewValue = 1; @@ -9843,7 +9950,7 @@ def L2_loadrub_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_0Imm:$Ii), "$Rd32 = memub($Rx32++#$Ii)", -tc_44d3da28, TypeLD>, Enc_222336, PredNewRel, PostInc_BaseImm { +tc_075c8dd8, TypeLD>, Enc_222336, PredNewRel, PostInc_BaseImm { let Inst{13-9} = 0b00000; let Inst{31-21} = 0b10011011001; let hasNewValue = 1; @@ -9851,8 +9958,8 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = ByteAccess; let mayLoad = 1; -let CextOpcode = "L2_loadrub"; let BaseOpcode = "L2_loadrub_pi"; +let CextOpcode = "L2_loadrub"; let isPredicable = 1; let Constraints = "$Rx32 = $Rx32in"; } @@ -9860,7 +9967,7 @@ def L2_loadrub_pr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memub($Rx32++$Mu2)", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011101001; let hasNewValue = 1; @@ -9874,7 +9981,7 @@ def L2_loadrub_zomap : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = memub($Rs32)", -tc_17e0d2cd, TypeMAPPING> { +tc_4222e6bf, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -9884,7 +9991,7 @@ def L2_loadrubgp : HInst< (outs IntRegs:$Rd32), (ins u32_0Imm:$Ii), "$Rd32 = memub(gp+#$Ii)", -tc_c4db48cb, TypeV2LDST>, Enc_25bef0, AddrModeRel { +tc_8a6d0d94, TypeV2LDST>, Enc_25bef0, AddrModeRel { let Inst{24-21} = 0b1001; let Inst{31-27} = 0b01001; let hasNewValue = 1; @@ -9903,7 +10010,7 @@ def L2_loadruh_io : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s31_1Imm:$Ii), "$Rd32 = memuh($Rs32+#$Ii)", -tc_17e0d2cd, TypeLD>, Enc_de0214, AddrModeRel, PostInc_BaseImm { +tc_4222e6bf, TypeLD>, Enc_de0214, AddrModeRel, PostInc_BaseImm { let Inst{24-21} = 0b1011; let Inst{31-27} = 0b10010; let hasNewValue = 1; @@ -9911,8 +10018,8 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let mayLoad = 1; -let CextOpcode = "L2_loadruh"; let BaseOpcode = "L2_loadruh_io"; +let CextOpcode = "L2_loadruh"; let isPredicable = 1; let isExtendable = 1; let opExtendable = 2; @@ -9924,7 +10031,7 @@ def L2_loadruh_pbr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memuh($Rx32++$Mu2:brev)", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011111011; let hasNewValue = 1; @@ -9938,7 +10045,7 @@ def L2_loadruh_pci : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2), "$Rd32 = memuh($Rx32++#$Ii:circ($Mu2))", -tc_e93a3d71, TypeLD>, Enc_e83554 { +tc_5ceb2f9e, TypeLD>, Enc_e83554 { let Inst{12-9} = 0b0000; let Inst{31-21} = 0b10011001011; let hasNewValue = 1; @@ -9953,7 +10060,7 @@ def L2_loadruh_pcr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memuh($Rx32++I:circ($Mu2))", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00010000; let Inst{31-21} = 0b10011001011; let hasNewValue = 1; @@ -9968,7 +10075,7 @@ def L2_loadruh_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii), "$Rd32 = memuh($Rx32++#$Ii)", -tc_44d3da28, TypeLD>, Enc_152467, PredNewRel, PostInc_BaseImm { +tc_075c8dd8, TypeLD>, Enc_152467, PredNewRel, PostInc_BaseImm { let Inst{13-9} = 0b00000; let Inst{31-21} = 0b10011011011; let hasNewValue = 1; @@ -9976,8 +10083,8 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HalfWordAccess; let mayLoad = 1; -let CextOpcode = "L2_loadruh"; let BaseOpcode = "L2_loadruh_pi"; +let CextOpcode = "L2_loadruh"; let isPredicable = 1; let Constraints = "$Rx32 = $Rx32in"; } @@ -9985,7 +10092,7 @@ def L2_loadruh_pr : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2), "$Rd32 = memuh($Rx32++$Mu2)", -tc_44d3da28, TypeLD>, Enc_74d4e5 { +tc_075c8dd8, TypeLD>, Enc_74d4e5 { let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b10011101011; let hasNewValue = 1; @@ -9999,7 +10106,7 @@ def L2_loadruh_zomap : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = memuh($Rs32)", -tc_17e0d2cd, TypeMAPPING> { +tc_4222e6bf, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10009,7 +10116,7 @@ def L2_loadruhgp : HInst< (outs IntRegs:$Rd32), (ins u31_1Imm:$Ii), "$Rd32 = memuh(gp+#$Ii)", -tc_c4db48cb, TypeV2LDST>, Enc_8df4be, AddrModeRel { +tc_8a6d0d94, TypeV2LDST>, Enc_8df4be, AddrModeRel { let Inst{24-21} = 0b1011; let Inst{31-27} = 0b01001; let hasNewValue = 1; @@ -10028,7 +10135,7 @@ def L2_loadw_locked : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = memw_locked($Rs32)", -tc_b43e7930, TypeLD>, Enc_5e2823 { +tc_64b00d8a, TypeLD>, Enc_5e2823 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10010010000; let hasNewValue = 1; @@ -10041,7 +10148,7 @@ def L2_ploadrbf_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), "if (!$Pt4) $Rd32 = memb($Rs32+#$Ii)", -tc_5ef37dc4, TypeV2LDST>, Enc_a21d47, AddrModeRel { +tc_fedb7e19, TypeV2LDST>, Enc_a21d47, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000101000; let isPredicated = 1; @@ -10051,8 +10158,8 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = ByteAccess; let mayLoad = 1; -let CextOpcode = "L2_loadrb"; let BaseOpcode = "L2_loadrb_io"; +let CextOpcode = "L2_loadrb"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10063,7 +10170,7 @@ def L2_ploadrbf_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), "if (!$Pt4) $Rd32 = memb($Rx32++#$Ii)", -tc_3c76b0ff, TypeLD>, Enc_f4413a, PredNewRel { +tc_1c7522a8, TypeLD>, Enc_f4413a, PredNewRel { let Inst{13-11} = 0b101; let Inst{31-21} = 0b10011011000; let isPredicated = 1; @@ -10080,7 +10187,7 @@ def L2_ploadrbf_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if (!$Pt4) $Rd32 = memb($Rs32)", -tc_5ef37dc4, TypeMAPPING> { +tc_fedb7e19, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10090,7 +10197,7 @@ def L2_ploadrbfnew_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), "if (!$Pt4.new) $Rd32 = memb($Rs32+#$Ii)", -tc_44d3da28, TypeV2LDST>, Enc_a21d47, AddrModeRel { +tc_075c8dd8, TypeV2LDST>, Enc_a21d47, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000111000; let isPredicated = 1; @@ -10101,8 +10208,8 @@ let addrMode = BaseImmOffset; let accessSize = ByteAccess; let isPredicatedNew = 1; let mayLoad = 1; -let CextOpcode = "L2_loadrb"; let BaseOpcode = "L2_loadrb_io"; +let CextOpcode = "L2_loadrb"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10113,7 +10220,7 @@ def L2_ploadrbfnew_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), "if (!$Pt4.new) $Rd32 = memb($Rx32++#$Ii)", -tc_e9f3243f, TypeLD>, Enc_f4413a, PredNewRel { +tc_5f2afaf7, TypeLD>, Enc_f4413a, PredNewRel { let Inst{13-11} = 0b111; let Inst{31-21} = 0b10011011000; let isPredicated = 1; @@ -10131,7 +10238,7 @@ def L2_ploadrbfnew_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if (!$Pt4.new) $Rd32 = memb($Rs32)", -tc_44d3da28, TypeMAPPING> { +tc_075c8dd8, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10141,7 +10248,7 @@ def L2_ploadrbt_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), "if ($Pt4) $Rd32 = memb($Rs32+#$Ii)", -tc_5ef37dc4, TypeV2LDST>, Enc_a21d47, AddrModeRel { +tc_fedb7e19, TypeV2LDST>, Enc_a21d47, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000001000; let isPredicated = 1; @@ -10150,8 +10257,8 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = ByteAccess; let mayLoad = 1; -let CextOpcode = "L2_loadrb"; let BaseOpcode = "L2_loadrb_io"; +let CextOpcode = "L2_loadrb"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10162,7 +10269,7 @@ def L2_ploadrbt_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), "if ($Pt4) $Rd32 = memb($Rx32++#$Ii)", -tc_3c76b0ff, TypeLD>, Enc_f4413a, PredNewRel { +tc_1c7522a8, TypeLD>, Enc_f4413a, PredNewRel { let Inst{13-11} = 0b100; let Inst{31-21} = 0b10011011000; let isPredicated = 1; @@ -10178,7 +10285,7 @@ def L2_ploadrbt_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if ($Pt4) $Rd32 = memb($Rs32)", -tc_5ef37dc4, TypeMAPPING> { +tc_fedb7e19, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10188,7 +10295,7 @@ def L2_ploadrbtnew_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), "if ($Pt4.new) $Rd32 = memb($Rs32+#$Ii)", -tc_44d3da28, TypeV2LDST>, Enc_a21d47, AddrModeRel { +tc_075c8dd8, TypeV2LDST>, Enc_a21d47, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000011000; let isPredicated = 1; @@ -10198,8 +10305,8 @@ let addrMode = BaseImmOffset; let accessSize = ByteAccess; let isPredicatedNew = 1; let mayLoad = 1; -let CextOpcode = "L2_loadrb"; let BaseOpcode = "L2_loadrb_io"; +let CextOpcode = "L2_loadrb"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10210,7 +10317,7 @@ def L2_ploadrbtnew_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), "if ($Pt4.new) $Rd32 = memb($Rx32++#$Ii)", -tc_e9f3243f, TypeLD>, Enc_f4413a, PredNewRel { +tc_5f2afaf7, TypeLD>, Enc_f4413a, PredNewRel { let Inst{13-11} = 0b110; let Inst{31-21} = 0b10011011000; let isPredicated = 1; @@ -10227,7 +10334,7 @@ def L2_ploadrbtnew_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if ($Pt4.new) $Rd32 = memb($Rs32)", -tc_44d3da28, TypeMAPPING> { +tc_075c8dd8, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10237,7 +10344,7 @@ def L2_ploadrdf_io : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii), "if (!$Pt4) $Rdd32 = memd($Rs32+#$Ii)", -tc_5ef37dc4, TypeV2LDST>, Enc_acd6ed, AddrModeRel { +tc_fedb7e19, TypeV2LDST>, Enc_acd6ed, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000101110; let isPredicated = 1; @@ -10245,8 +10352,8 @@ let isPredicatedFalse = 1; let addrMode = BaseImmOffset; let accessSize = DoubleWordAccess; let mayLoad = 1; -let CextOpcode = "L2_loadrd"; let BaseOpcode = "L2_loadrd_io"; +let CextOpcode = "L2_loadrd"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10257,7 +10364,7 @@ def L2_ploadrdf_pi : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii), "if (!$Pt4) $Rdd32 = memd($Rx32++#$Ii)", -tc_3c76b0ff, TypeLD>, Enc_9d1247, PredNewRel { +tc_1c7522a8, TypeLD>, Enc_9d1247, PredNewRel { let Inst{13-11} = 0b101; let Inst{31-21} = 0b10011011110; let isPredicated = 1; @@ -10272,7 +10379,7 @@ def L2_ploadrdf_zomap : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if (!$Pt4) $Rdd32 = memd($Rs32)", -tc_5ef37dc4, TypeMAPPING> { +tc_fedb7e19, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -10280,7 +10387,7 @@ def L2_ploadrdfnew_io : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii), "if (!$Pt4.new) $Rdd32 = memd($Rs32+#$Ii)", -tc_44d3da28, TypeV2LDST>, Enc_acd6ed, AddrModeRel { +tc_075c8dd8, TypeV2LDST>, Enc_acd6ed, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000111110; let isPredicated = 1; @@ -10289,8 +10396,8 @@ let addrMode = BaseImmOffset; let accessSize = DoubleWordAccess; let isPredicatedNew = 1; let mayLoad = 1; -let CextOpcode = "L2_loadrd"; let BaseOpcode = "L2_loadrd_io"; +let CextOpcode = "L2_loadrd"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10301,7 +10408,7 @@ def L2_ploadrdfnew_pi : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii), "if (!$Pt4.new) $Rdd32 = memd($Rx32++#$Ii)", -tc_e9f3243f, TypeLD>, Enc_9d1247, PredNewRel { +tc_5f2afaf7, TypeLD>, Enc_9d1247, PredNewRel { let Inst{13-11} = 0b111; let Inst{31-21} = 0b10011011110; let isPredicated = 1; @@ -10317,7 +10424,7 @@ def L2_ploadrdfnew_zomap : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if (!$Pt4.new) $Rdd32 = memd($Rs32)", -tc_44d3da28, TypeMAPPING> { +tc_075c8dd8, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -10325,15 +10432,15 @@ def L2_ploadrdt_io : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii), "if ($Pt4) $Rdd32 = memd($Rs32+#$Ii)", -tc_5ef37dc4, TypeV2LDST>, Enc_acd6ed, AddrModeRel { +tc_fedb7e19, TypeV2LDST>, Enc_acd6ed, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000001110; let isPredicated = 1; let addrMode = BaseImmOffset; let accessSize = DoubleWordAccess; let mayLoad = 1; -let CextOpcode = "L2_loadrd"; let BaseOpcode = "L2_loadrd_io"; +let CextOpcode = "L2_loadrd"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10344,7 +10451,7 @@ def L2_ploadrdt_pi : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii), "if ($Pt4) $Rdd32 = memd($Rx32++#$Ii)", -tc_3c76b0ff, TypeLD>, Enc_9d1247, PredNewRel { +tc_1c7522a8, TypeLD>, Enc_9d1247, PredNewRel { let Inst{13-11} = 0b100; let Inst{31-21} = 0b10011011110; let isPredicated = 1; @@ -10358,7 +10465,7 @@ def L2_ploadrdt_zomap : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if ($Pt4) $Rdd32 = memd($Rs32)", -tc_5ef37dc4, TypeMAPPING> { +tc_fedb7e19, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -10366,7 +10473,7 @@ def L2_ploadrdtnew_io : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii), "if ($Pt4.new) $Rdd32 = memd($Rs32+#$Ii)", -tc_44d3da28, TypeV2LDST>, Enc_acd6ed, AddrModeRel { +tc_075c8dd8, TypeV2LDST>, Enc_acd6ed, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000011110; let isPredicated = 1; @@ -10374,8 +10481,8 @@ let addrMode = BaseImmOffset; let accessSize = DoubleWordAccess; let isPredicatedNew = 1; let mayLoad = 1; -let CextOpcode = "L2_loadrd"; let BaseOpcode = "L2_loadrd_io"; +let CextOpcode = "L2_loadrd"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10386,7 +10493,7 @@ def L2_ploadrdtnew_pi : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii), "if ($Pt4.new) $Rdd32 = memd($Rx32++#$Ii)", -tc_e9f3243f, TypeLD>, Enc_9d1247, PredNewRel { +tc_5f2afaf7, TypeLD>, Enc_9d1247, PredNewRel { let Inst{13-11} = 0b110; let Inst{31-21} = 0b10011011110; let isPredicated = 1; @@ -10401,7 +10508,7 @@ def L2_ploadrdtnew_zomap : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if ($Pt4.new) $Rdd32 = memd($Rs32)", -tc_44d3da28, TypeMAPPING> { +tc_075c8dd8, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -10409,7 +10516,7 @@ def L2_ploadrhf_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), "if (!$Pt4) $Rd32 = memh($Rs32+#$Ii)", -tc_5ef37dc4, TypeV2LDST>, Enc_a198f6, AddrModeRel { +tc_fedb7e19, TypeV2LDST>, Enc_a198f6, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000101010; let isPredicated = 1; @@ -10419,8 +10526,8 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let mayLoad = 1; -let CextOpcode = "L2_loadrh"; let BaseOpcode = "L2_loadrh_io"; +let CextOpcode = "L2_loadrh"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10431,7 +10538,7 @@ def L2_ploadrhf_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), "if (!$Pt4) $Rd32 = memh($Rx32++#$Ii)", -tc_3c76b0ff, TypeLD>, Enc_733b27, PredNewRel { +tc_1c7522a8, TypeLD>, Enc_733b27, PredNewRel { let Inst{13-11} = 0b101; let Inst{31-21} = 0b10011011010; let isPredicated = 1; @@ -10448,7 +10555,7 @@ def L2_ploadrhf_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if (!$Pt4) $Rd32 = memh($Rs32)", -tc_5ef37dc4, TypeMAPPING> { +tc_fedb7e19, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10458,7 +10565,7 @@ def L2_ploadrhfnew_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), "if (!$Pt4.new) $Rd32 = memh($Rs32+#$Ii)", -tc_44d3da28, TypeV2LDST>, Enc_a198f6, AddrModeRel { +tc_075c8dd8, TypeV2LDST>, Enc_a198f6, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000111010; let isPredicated = 1; @@ -10469,8 +10576,8 @@ let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayLoad = 1; -let CextOpcode = "L2_loadrh"; let BaseOpcode = "L2_loadrh_io"; +let CextOpcode = "L2_loadrh"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10481,7 +10588,7 @@ def L2_ploadrhfnew_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), "if (!$Pt4.new) $Rd32 = memh($Rx32++#$Ii)", -tc_e9f3243f, TypeLD>, Enc_733b27, PredNewRel { +tc_5f2afaf7, TypeLD>, Enc_733b27, PredNewRel { let Inst{13-11} = 0b111; let Inst{31-21} = 0b10011011010; let isPredicated = 1; @@ -10499,7 +10606,7 @@ def L2_ploadrhfnew_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if (!$Pt4.new) $Rd32 = memh($Rs32)", -tc_44d3da28, TypeMAPPING> { +tc_075c8dd8, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10509,7 +10616,7 @@ def L2_ploadrht_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), "if ($Pt4) $Rd32 = memh($Rs32+#$Ii)", -tc_5ef37dc4, TypeV2LDST>, Enc_a198f6, AddrModeRel { +tc_fedb7e19, TypeV2LDST>, Enc_a198f6, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000001010; let isPredicated = 1; @@ -10518,8 +10625,8 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let mayLoad = 1; -let CextOpcode = "L2_loadrh"; let BaseOpcode = "L2_loadrh_io"; +let CextOpcode = "L2_loadrh"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10530,7 +10637,7 @@ def L2_ploadrht_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), "if ($Pt4) $Rd32 = memh($Rx32++#$Ii)", -tc_3c76b0ff, TypeLD>, Enc_733b27, PredNewRel { +tc_1c7522a8, TypeLD>, Enc_733b27, PredNewRel { let Inst{13-11} = 0b100; let Inst{31-21} = 0b10011011010; let isPredicated = 1; @@ -10546,7 +10653,7 @@ def L2_ploadrht_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if ($Pt4) $Rd32 = memh($Rs32)", -tc_5ef37dc4, TypeMAPPING> { +tc_fedb7e19, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10556,7 +10663,7 @@ def L2_ploadrhtnew_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), "if ($Pt4.new) $Rd32 = memh($Rs32+#$Ii)", -tc_44d3da28, TypeV2LDST>, Enc_a198f6, AddrModeRel { +tc_075c8dd8, TypeV2LDST>, Enc_a198f6, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000011010; let isPredicated = 1; @@ -10566,8 +10673,8 @@ let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayLoad = 1; -let CextOpcode = "L2_loadrh"; let BaseOpcode = "L2_loadrh_io"; +let CextOpcode = "L2_loadrh"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10578,7 +10685,7 @@ def L2_ploadrhtnew_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), "if ($Pt4.new) $Rd32 = memh($Rx32++#$Ii)", -tc_e9f3243f, TypeLD>, Enc_733b27, PredNewRel { +tc_5f2afaf7, TypeLD>, Enc_733b27, PredNewRel { let Inst{13-11} = 0b110; let Inst{31-21} = 0b10011011010; let isPredicated = 1; @@ -10595,7 +10702,7 @@ def L2_ploadrhtnew_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if ($Pt4.new) $Rd32 = memh($Rs32)", -tc_44d3da28, TypeMAPPING> { +tc_075c8dd8, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10605,7 +10712,7 @@ def L2_ploadrif_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii), "if (!$Pt4) $Rd32 = memw($Rs32+#$Ii)", -tc_5ef37dc4, TypeV2LDST>, Enc_f82eaf, AddrModeRel { +tc_fedb7e19, TypeV2LDST>, Enc_f82eaf, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000101100; let isPredicated = 1; @@ -10615,8 +10722,8 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = WordAccess; let mayLoad = 1; -let CextOpcode = "L2_loadri"; let BaseOpcode = "L2_loadri_io"; +let CextOpcode = "L2_loadri"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10627,7 +10734,7 @@ def L2_ploadrif_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii), "if (!$Pt4) $Rd32 = memw($Rx32++#$Ii)", -tc_3c76b0ff, TypeLD>, Enc_b97f71, PredNewRel { +tc_1c7522a8, TypeLD>, Enc_b97f71, PredNewRel { let Inst{13-11} = 0b101; let Inst{31-21} = 0b10011011100; let isPredicated = 1; @@ -10644,7 +10751,7 @@ def L2_ploadrif_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if (!$Pt4) $Rd32 = memw($Rs32)", -tc_5ef37dc4, TypeMAPPING> { +tc_fedb7e19, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10654,7 +10761,7 @@ def L2_ploadrifnew_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii), "if (!$Pt4.new) $Rd32 = memw($Rs32+#$Ii)", -tc_44d3da28, TypeV2LDST>, Enc_f82eaf, AddrModeRel { +tc_075c8dd8, TypeV2LDST>, Enc_f82eaf, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000111100; let isPredicated = 1; @@ -10665,8 +10772,8 @@ let addrMode = BaseImmOffset; let accessSize = WordAccess; let isPredicatedNew = 1; let mayLoad = 1; -let CextOpcode = "L2_loadri"; let BaseOpcode = "L2_loadri_io"; +let CextOpcode = "L2_loadri"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10677,7 +10784,7 @@ def L2_ploadrifnew_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii), "if (!$Pt4.new) $Rd32 = memw($Rx32++#$Ii)", -tc_e9f3243f, TypeLD>, Enc_b97f71, PredNewRel { +tc_5f2afaf7, TypeLD>, Enc_b97f71, PredNewRel { let Inst{13-11} = 0b111; let Inst{31-21} = 0b10011011100; let isPredicated = 1; @@ -10695,7 +10802,7 @@ def L2_ploadrifnew_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if (!$Pt4.new) $Rd32 = memw($Rs32)", -tc_44d3da28, TypeMAPPING> { +tc_075c8dd8, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10705,7 +10812,7 @@ def L2_ploadrit_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii), "if ($Pt4) $Rd32 = memw($Rs32+#$Ii)", -tc_5ef37dc4, TypeV2LDST>, Enc_f82eaf, AddrModeRel { +tc_fedb7e19, TypeV2LDST>, Enc_f82eaf, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000001100; let isPredicated = 1; @@ -10714,8 +10821,8 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = WordAccess; let mayLoad = 1; -let CextOpcode = "L2_loadri"; let BaseOpcode = "L2_loadri_io"; +let CextOpcode = "L2_loadri"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10726,7 +10833,7 @@ def L2_ploadrit_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii), "if ($Pt4) $Rd32 = memw($Rx32++#$Ii)", -tc_3c76b0ff, TypeLD>, Enc_b97f71, PredNewRel { +tc_1c7522a8, TypeLD>, Enc_b97f71, PredNewRel { let Inst{13-11} = 0b100; let Inst{31-21} = 0b10011011100; let isPredicated = 1; @@ -10742,7 +10849,7 @@ def L2_ploadrit_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if ($Pt4) $Rd32 = memw($Rs32)", -tc_5ef37dc4, TypeMAPPING> { +tc_fedb7e19, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10752,7 +10859,7 @@ def L2_ploadritnew_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii), "if ($Pt4.new) $Rd32 = memw($Rs32+#$Ii)", -tc_44d3da28, TypeV2LDST>, Enc_f82eaf, AddrModeRel { +tc_075c8dd8, TypeV2LDST>, Enc_f82eaf, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000011100; let isPredicated = 1; @@ -10762,8 +10869,8 @@ let addrMode = BaseImmOffset; let accessSize = WordAccess; let isPredicatedNew = 1; let mayLoad = 1; -let CextOpcode = "L2_loadri"; let BaseOpcode = "L2_loadri_io"; +let CextOpcode = "L2_loadri"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10774,7 +10881,7 @@ def L2_ploadritnew_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii), "if ($Pt4.new) $Rd32 = memw($Rx32++#$Ii)", -tc_e9f3243f, TypeLD>, Enc_b97f71, PredNewRel { +tc_5f2afaf7, TypeLD>, Enc_b97f71, PredNewRel { let Inst{13-11} = 0b110; let Inst{31-21} = 0b10011011100; let isPredicated = 1; @@ -10791,7 +10898,7 @@ def L2_ploadritnew_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if ($Pt4.new) $Rd32 = memw($Rs32)", -tc_44d3da28, TypeMAPPING> { +tc_075c8dd8, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10801,7 +10908,7 @@ def L2_ploadrubf_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), "if (!$Pt4) $Rd32 = memub($Rs32+#$Ii)", -tc_5ef37dc4, TypeV2LDST>, Enc_a21d47, AddrModeRel { +tc_fedb7e19, TypeV2LDST>, Enc_a21d47, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000101001; let isPredicated = 1; @@ -10811,8 +10918,8 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = ByteAccess; let mayLoad = 1; -let CextOpcode = "L2_loadrub"; let BaseOpcode = "L2_loadrub_io"; +let CextOpcode = "L2_loadrub"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10823,7 +10930,7 @@ def L2_ploadrubf_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), "if (!$Pt4) $Rd32 = memub($Rx32++#$Ii)", -tc_3c76b0ff, TypeLD>, Enc_f4413a, PredNewRel { +tc_1c7522a8, TypeLD>, Enc_f4413a, PredNewRel { let Inst{13-11} = 0b101; let Inst{31-21} = 0b10011011001; let isPredicated = 1; @@ -10840,7 +10947,7 @@ def L2_ploadrubf_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if (!$Pt4) $Rd32 = memub($Rs32)", -tc_5ef37dc4, TypeMAPPING> { +tc_fedb7e19, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10850,7 +10957,7 @@ def L2_ploadrubfnew_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), "if (!$Pt4.new) $Rd32 = memub($Rs32+#$Ii)", -tc_44d3da28, TypeV2LDST>, Enc_a21d47, AddrModeRel { +tc_075c8dd8, TypeV2LDST>, Enc_a21d47, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000111001; let isPredicated = 1; @@ -10861,8 +10968,8 @@ let addrMode = BaseImmOffset; let accessSize = ByteAccess; let isPredicatedNew = 1; let mayLoad = 1; -let CextOpcode = "L2_loadrub"; let BaseOpcode = "L2_loadrub_io"; +let CextOpcode = "L2_loadrub"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10873,7 +10980,7 @@ def L2_ploadrubfnew_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), "if (!$Pt4.new) $Rd32 = memub($Rx32++#$Ii)", -tc_e9f3243f, TypeLD>, Enc_f4413a, PredNewRel { +tc_5f2afaf7, TypeLD>, Enc_f4413a, PredNewRel { let Inst{13-11} = 0b111; let Inst{31-21} = 0b10011011001; let isPredicated = 1; @@ -10891,7 +10998,7 @@ def L2_ploadrubfnew_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if (!$Pt4.new) $Rd32 = memub($Rs32)", -tc_44d3da28, TypeMAPPING> { +tc_075c8dd8, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10901,7 +11008,7 @@ def L2_ploadrubt_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), "if ($Pt4) $Rd32 = memub($Rs32+#$Ii)", -tc_5ef37dc4, TypeV2LDST>, Enc_a21d47, AddrModeRel { +tc_fedb7e19, TypeV2LDST>, Enc_a21d47, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000001001; let isPredicated = 1; @@ -10910,8 +11017,8 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = ByteAccess; let mayLoad = 1; -let CextOpcode = "L2_loadrub"; let BaseOpcode = "L2_loadrub_io"; +let CextOpcode = "L2_loadrub"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10922,7 +11029,7 @@ def L2_ploadrubt_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), "if ($Pt4) $Rd32 = memub($Rx32++#$Ii)", -tc_3c76b0ff, TypeLD>, Enc_f4413a, PredNewRel { +tc_1c7522a8, TypeLD>, Enc_f4413a, PredNewRel { let Inst{13-11} = 0b100; let Inst{31-21} = 0b10011011001; let isPredicated = 1; @@ -10938,7 +11045,7 @@ def L2_ploadrubt_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if ($Pt4) $Rd32 = memub($Rs32)", -tc_5ef37dc4, TypeMAPPING> { +tc_fedb7e19, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10948,7 +11055,7 @@ def L2_ploadrubtnew_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), "if ($Pt4.new) $Rd32 = memub($Rs32+#$Ii)", -tc_44d3da28, TypeV2LDST>, Enc_a21d47, AddrModeRel { +tc_075c8dd8, TypeV2LDST>, Enc_a21d47, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000011001; let isPredicated = 1; @@ -10958,8 +11065,8 @@ let addrMode = BaseImmOffset; let accessSize = ByteAccess; let isPredicatedNew = 1; let mayLoad = 1; -let CextOpcode = "L2_loadrub"; let BaseOpcode = "L2_loadrub_io"; +let CextOpcode = "L2_loadrub"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -10970,7 +11077,7 @@ def L2_ploadrubtnew_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), "if ($Pt4.new) $Rd32 = memub($Rx32++#$Ii)", -tc_e9f3243f, TypeLD>, Enc_f4413a, PredNewRel { +tc_5f2afaf7, TypeLD>, Enc_f4413a, PredNewRel { let Inst{13-11} = 0b110; let Inst{31-21} = 0b10011011001; let isPredicated = 1; @@ -10987,7 +11094,7 @@ def L2_ploadrubtnew_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if ($Pt4.new) $Rd32 = memub($Rs32)", -tc_44d3da28, TypeMAPPING> { +tc_075c8dd8, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -10997,7 +11104,7 @@ def L2_ploadruhf_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), "if (!$Pt4) $Rd32 = memuh($Rs32+#$Ii)", -tc_5ef37dc4, TypeV2LDST>, Enc_a198f6, AddrModeRel { +tc_fedb7e19, TypeV2LDST>, Enc_a198f6, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000101011; let isPredicated = 1; @@ -11007,8 +11114,8 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let mayLoad = 1; -let CextOpcode = "L2_loadruh"; let BaseOpcode = "L2_loadruh_io"; +let CextOpcode = "L2_loadruh"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -11019,7 +11126,7 @@ def L2_ploadruhf_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), "if (!$Pt4) $Rd32 = memuh($Rx32++#$Ii)", -tc_3c76b0ff, TypeLD>, Enc_733b27, PredNewRel { +tc_1c7522a8, TypeLD>, Enc_733b27, PredNewRel { let Inst{13-11} = 0b101; let Inst{31-21} = 0b10011011011; let isPredicated = 1; @@ -11036,7 +11143,7 @@ def L2_ploadruhf_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if (!$Pt4) $Rd32 = memuh($Rs32)", -tc_5ef37dc4, TypeMAPPING> { +tc_fedb7e19, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -11046,7 +11153,7 @@ def L2_ploadruhfnew_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), "if (!$Pt4.new) $Rd32 = memuh($Rs32+#$Ii)", -tc_44d3da28, TypeV2LDST>, Enc_a198f6, AddrModeRel { +tc_075c8dd8, TypeV2LDST>, Enc_a198f6, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000111011; let isPredicated = 1; @@ -11057,8 +11164,8 @@ let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayLoad = 1; -let CextOpcode = "L2_loadruh"; let BaseOpcode = "L2_loadruh_io"; +let CextOpcode = "L2_loadruh"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -11069,7 +11176,7 @@ def L2_ploadruhfnew_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), "if (!$Pt4.new) $Rd32 = memuh($Rx32++#$Ii)", -tc_e9f3243f, TypeLD>, Enc_733b27, PredNewRel { +tc_5f2afaf7, TypeLD>, Enc_733b27, PredNewRel { let Inst{13-11} = 0b111; let Inst{31-21} = 0b10011011011; let isPredicated = 1; @@ -11087,7 +11194,7 @@ def L2_ploadruhfnew_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if (!$Pt4.new) $Rd32 = memuh($Rs32)", -tc_44d3da28, TypeMAPPING> { +tc_075c8dd8, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -11097,7 +11204,7 @@ def L2_ploadruht_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), "if ($Pt4) $Rd32 = memuh($Rs32+#$Ii)", -tc_5ef37dc4, TypeV2LDST>, Enc_a198f6, AddrModeRel { +tc_fedb7e19, TypeV2LDST>, Enc_a198f6, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000001011; let isPredicated = 1; @@ -11106,8 +11213,8 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let mayLoad = 1; -let CextOpcode = "L2_loadruh"; let BaseOpcode = "L2_loadruh_io"; +let CextOpcode = "L2_loadruh"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -11118,7 +11225,7 @@ def L2_ploadruht_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), "if ($Pt4) $Rd32 = memuh($Rx32++#$Ii)", -tc_3c76b0ff, TypeLD>, Enc_733b27, PredNewRel { +tc_1c7522a8, TypeLD>, Enc_733b27, PredNewRel { let Inst{13-11} = 0b100; let Inst{31-21} = 0b10011011011; let isPredicated = 1; @@ -11134,7 +11241,7 @@ def L2_ploadruht_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if ($Pt4) $Rd32 = memuh($Rs32)", -tc_5ef37dc4, TypeMAPPING> { +tc_fedb7e19, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -11144,7 +11251,7 @@ def L2_ploadruhtnew_io : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), "if ($Pt4.new) $Rd32 = memuh($Rs32+#$Ii)", -tc_44d3da28, TypeV2LDST>, Enc_a198f6, AddrModeRel { +tc_075c8dd8, TypeV2LDST>, Enc_a198f6, AddrModeRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b01000011011; let isPredicated = 1; @@ -11154,8 +11261,8 @@ let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayLoad = 1; -let CextOpcode = "L2_loadruh"; let BaseOpcode = "L2_loadruh_io"; +let CextOpcode = "L2_loadruh"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 0; @@ -11166,7 +11273,7 @@ def L2_ploadruhtnew_pi : HInst< (outs IntRegs:$Rd32, IntRegs:$Rx32), (ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), "if ($Pt4.new) $Rd32 = memuh($Rx32++#$Ii)", -tc_e9f3243f, TypeLD>, Enc_733b27, PredNewRel { +tc_5f2afaf7, TypeLD>, Enc_733b27, PredNewRel { let Inst{13-11} = 0b110; let Inst{31-21} = 0b10011011011; let isPredicated = 1; @@ -11183,7 +11290,7 @@ def L2_ploadruhtnew_zomap : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, IntRegs:$Rs32), "if ($Pt4.new) $Rd32 = memuh($Rs32)", -tc_44d3da28, TypeMAPPING> { +tc_075c8dd8, TypeMAPPING> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -11193,7 +11300,7 @@ def L4_add_memopb_io : HInst< (outs), (ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), "memb($Rs32+#$Ii) += $Rt32", -tc_7186d325, TypeV4LDST>, Enc_d44e31 { +tc_9bcfb2ee, TypeV4LDST>, Enc_d44e31 { let Inst{6-5} = 0b00; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111110000; @@ -11212,7 +11319,7 @@ def L4_add_memopb_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memb($Rs32) += $Rt32", -tc_7186d325, TypeMAPPING> { +tc_9bcfb2ee, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11220,7 +11327,7 @@ def L4_add_memoph_io : HInst< (outs), (ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), "memh($Rs32+#$Ii) += $Rt32", -tc_7186d325, TypeV4LDST>, Enc_163a3c { +tc_9bcfb2ee, TypeV4LDST>, Enc_163a3c { let Inst{6-5} = 0b00; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111110001; @@ -11239,7 +11346,7 @@ def L4_add_memoph_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memh($Rs32) += $Rt32", -tc_7186d325, TypeMAPPING> { +tc_9bcfb2ee, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11247,7 +11354,7 @@ def L4_add_memopw_io : HInst< (outs), (ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), "memw($Rs32+#$Ii) += $Rt32", -tc_7186d325, TypeV4LDST>, Enc_226535 { +tc_9bcfb2ee, TypeV4LDST>, Enc_226535 { let Inst{6-5} = 0b00; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111110010; @@ -11266,7 +11373,7 @@ def L4_add_memopw_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memw($Rs32) += $Rt32", -tc_7186d325, TypeMAPPING> { +tc_9bcfb2ee, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11274,7 +11381,7 @@ def L4_and_memopb_io : HInst< (outs), (ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), "memb($Rs32+#$Ii) &= $Rt32", -tc_7186d325, TypeV4LDST>, Enc_d44e31 { +tc_9bcfb2ee, TypeV4LDST>, Enc_d44e31 { let Inst{6-5} = 0b10; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111110000; @@ -11293,7 +11400,7 @@ def L4_and_memopb_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memb($Rs32) &= $Rt32", -tc_7186d325, TypeMAPPING> { +tc_9bcfb2ee, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11301,7 +11408,7 @@ def L4_and_memoph_io : HInst< (outs), (ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), "memh($Rs32+#$Ii) &= $Rt32", -tc_7186d325, TypeV4LDST>, Enc_163a3c { +tc_9bcfb2ee, TypeV4LDST>, Enc_163a3c { let Inst{6-5} = 0b10; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111110001; @@ -11320,7 +11427,7 @@ def L4_and_memoph_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memh($Rs32) &= $Rt32", -tc_7186d325, TypeMAPPING> { +tc_9bcfb2ee, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11328,7 +11435,7 @@ def L4_and_memopw_io : HInst< (outs), (ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), "memw($Rs32+#$Ii) &= $Rt32", -tc_7186d325, TypeV4LDST>, Enc_226535 { +tc_9bcfb2ee, TypeV4LDST>, Enc_226535 { let Inst{6-5} = 0b10; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111110010; @@ -11347,7 +11454,7 @@ def L4_and_memopw_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memw($Rs32) &= $Rt32", -tc_7186d325, TypeMAPPING> { +tc_9bcfb2ee, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11355,7 +11462,7 @@ def L4_iadd_memopb_io : HInst< (outs), (ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II), "memb($Rs32+#$Ii) += #$II", -tc_096199d3, TypeV4LDST>, Enc_46c951 { +tc_158aa3f7, TypeV4LDST>, Enc_46c951 { let Inst{6-5} = 0b00; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111111000; @@ -11374,7 +11481,7 @@ def L4_iadd_memopb_zomap : HInst< (outs), (ins IntRegs:$Rs32, u5_0Imm:$II), "memb($Rs32) += #$II", -tc_096199d3, TypeMAPPING> { +tc_158aa3f7, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11382,7 +11489,7 @@ def L4_iadd_memoph_io : HInst< (outs), (ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II), "memh($Rs32+#$Ii) += #$II", -tc_096199d3, TypeV4LDST>, Enc_e66a97 { +tc_158aa3f7, TypeV4LDST>, Enc_e66a97 { let Inst{6-5} = 0b00; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111111001; @@ -11401,7 +11508,7 @@ def L4_iadd_memoph_zomap : HInst< (outs), (ins IntRegs:$Rs32, u5_0Imm:$II), "memh($Rs32) += #$II", -tc_096199d3, TypeMAPPING> { +tc_158aa3f7, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11409,7 +11516,7 @@ def L4_iadd_memopw_io : HInst< (outs), (ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II), "memw($Rs32+#$Ii) += #$II", -tc_096199d3, TypeV4LDST>, Enc_84b2cd { +tc_158aa3f7, TypeV4LDST>, Enc_84b2cd { let Inst{6-5} = 0b00; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111111010; @@ -11428,7 +11535,7 @@ def L4_iadd_memopw_zomap : HInst< (outs), (ins IntRegs:$Rs32, u5_0Imm:$II), "memw($Rs32) += #$II", -tc_096199d3, TypeMAPPING> { +tc_158aa3f7, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11436,7 +11543,7 @@ def L4_iand_memopb_io : HInst< (outs), (ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II), "memb($Rs32+#$Ii) = clrbit(#$II)", -tc_096199d3, TypeV4LDST>, Enc_46c951 { +tc_158aa3f7, TypeV4LDST>, Enc_46c951 { let Inst{6-5} = 0b10; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111111000; @@ -11455,7 +11562,7 @@ def L4_iand_memopb_zomap : HInst< (outs), (ins IntRegs:$Rs32, u5_0Imm:$II), "memb($Rs32) = clrbit(#$II)", -tc_096199d3, TypeMAPPING> { +tc_158aa3f7, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11463,7 +11570,7 @@ def L4_iand_memoph_io : HInst< (outs), (ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II), "memh($Rs32+#$Ii) = clrbit(#$II)", -tc_096199d3, TypeV4LDST>, Enc_e66a97 { +tc_158aa3f7, TypeV4LDST>, Enc_e66a97 { let Inst{6-5} = 0b10; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111111001; @@ -11482,7 +11589,7 @@ def L4_iand_memoph_zomap : HInst< (outs), (ins IntRegs:$Rs32, u5_0Imm:$II), "memh($Rs32) = clrbit(#$II)", -tc_096199d3, TypeMAPPING> { +tc_158aa3f7, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11490,7 +11597,7 @@ def L4_iand_memopw_io : HInst< (outs), (ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II), "memw($Rs32+#$Ii) = clrbit(#$II)", -tc_096199d3, TypeV4LDST>, Enc_84b2cd { +tc_158aa3f7, TypeV4LDST>, Enc_84b2cd { let Inst{6-5} = 0b10; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111111010; @@ -11509,7 +11616,7 @@ def L4_iand_memopw_zomap : HInst< (outs), (ins IntRegs:$Rs32, u5_0Imm:$II), "memw($Rs32) = clrbit(#$II)", -tc_096199d3, TypeMAPPING> { +tc_158aa3f7, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11517,7 +11624,7 @@ def L4_ior_memopb_io : HInst< (outs), (ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II), "memb($Rs32+#$Ii) = setbit(#$II)", -tc_096199d3, TypeV4LDST>, Enc_46c951 { +tc_158aa3f7, TypeV4LDST>, Enc_46c951 { let Inst{6-5} = 0b11; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111111000; @@ -11536,7 +11643,7 @@ def L4_ior_memopb_zomap : HInst< (outs), (ins IntRegs:$Rs32, u5_0Imm:$II), "memb($Rs32) = setbit(#$II)", -tc_096199d3, TypeMAPPING> { +tc_158aa3f7, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11544,7 +11651,7 @@ def L4_ior_memoph_io : HInst< (outs), (ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II), "memh($Rs32+#$Ii) = setbit(#$II)", -tc_096199d3, TypeV4LDST>, Enc_e66a97 { +tc_158aa3f7, TypeV4LDST>, Enc_e66a97 { let Inst{6-5} = 0b11; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111111001; @@ -11563,7 +11670,7 @@ def L4_ior_memoph_zomap : HInst< (outs), (ins IntRegs:$Rs32, u5_0Imm:$II), "memh($Rs32) = setbit(#$II)", -tc_096199d3, TypeMAPPING> { +tc_158aa3f7, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11571,7 +11678,7 @@ def L4_ior_memopw_io : HInst< (outs), (ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II), "memw($Rs32+#$Ii) = setbit(#$II)", -tc_096199d3, TypeV4LDST>, Enc_84b2cd { +tc_158aa3f7, TypeV4LDST>, Enc_84b2cd { let Inst{6-5} = 0b11; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111111010; @@ -11590,7 +11697,7 @@ def L4_ior_memopw_zomap : HInst< (outs), (ins IntRegs:$Rs32, u5_0Imm:$II), "memw($Rs32) = setbit(#$II)", -tc_096199d3, TypeMAPPING> { +tc_158aa3f7, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11598,7 +11705,7 @@ def L4_isub_memopb_io : HInst< (outs), (ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II), "memb($Rs32+#$Ii) -= #$II", -tc_096199d3, TypeV4LDST>, Enc_46c951 { +tc_158aa3f7, TypeV4LDST>, Enc_46c951 { let Inst{6-5} = 0b01; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111111000; @@ -11617,7 +11724,7 @@ def L4_isub_memopb_zomap : HInst< (outs), (ins IntRegs:$Rs32, u5_0Imm:$II), "memb($Rs32) -= #$II", -tc_096199d3, TypeMAPPING> { +tc_158aa3f7, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11625,7 +11732,7 @@ def L4_isub_memoph_io : HInst< (outs), (ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II), "memh($Rs32+#$Ii) -= #$II", -tc_096199d3, TypeV4LDST>, Enc_e66a97 { +tc_158aa3f7, TypeV4LDST>, Enc_e66a97 { let Inst{6-5} = 0b01; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111111001; @@ -11644,7 +11751,7 @@ def L4_isub_memoph_zomap : HInst< (outs), (ins IntRegs:$Rs32, u5_0Imm:$II), "memh($Rs32) -= #$II", -tc_096199d3, TypeMAPPING> { +tc_158aa3f7, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11652,7 +11759,7 @@ def L4_isub_memopw_io : HInst< (outs), (ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II), "memw($Rs32+#$Ii) -= #$II", -tc_096199d3, TypeV4LDST>, Enc_84b2cd { +tc_158aa3f7, TypeV4LDST>, Enc_84b2cd { let Inst{6-5} = 0b01; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111111010; @@ -11671,7 +11778,7 @@ def L4_isub_memopw_zomap : HInst< (outs), (ins IntRegs:$Rs32, u5_0Imm:$II), "memw($Rs32) -= #$II", -tc_096199d3, TypeMAPPING> { +tc_158aa3f7, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -11679,7 +11786,7 @@ def L4_loadalignb_ap : HInst< (outs DoubleRegs:$Ryy32, IntRegs:$Re32), (ins DoubleRegs:$Ryy32in, u32_0Imm:$II), "$Ryy32 = memb_fifo($Re32=#$II)", -tc_7a91e76a, TypeLD>, Enc_f394d3 { +tc_ac65613f, TypeLD>, Enc_f394d3 { let Inst{7-7} = 0b0; let Inst{13-12} = 0b01; let Inst{31-21} = 0b10011010100; @@ -11699,7 +11806,7 @@ def L4_loadalignb_ur : HInst< (outs DoubleRegs:$Ryy32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), "$Ryy32 = memb_fifo($Rt32<<#$Ii+#$II)", -tc_a5d4aeec, TypeLD>, Enc_04c959 { +tc_a32e03e7, TypeLD>, Enc_04c959 { let Inst{12-12} = 0b1; let Inst{31-21} = 0b10011100100; let addrMode = BaseLongOffset; @@ -11719,7 +11826,7 @@ def L4_loadalignh_ap : HInst< (outs DoubleRegs:$Ryy32, IntRegs:$Re32), (ins DoubleRegs:$Ryy32in, u32_0Imm:$II), "$Ryy32 = memh_fifo($Re32=#$II)", -tc_7a91e76a, TypeLD>, Enc_f394d3 { +tc_ac65613f, TypeLD>, Enc_f394d3 { let Inst{7-7} = 0b0; let Inst{13-12} = 0b01; let Inst{31-21} = 0b10011010010; @@ -11739,7 +11846,7 @@ def L4_loadalignh_ur : HInst< (outs DoubleRegs:$Ryy32), (ins DoubleRegs:$Ryy32in, IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), "$Ryy32 = memh_fifo($Rt32<<#$Ii+#$II)", -tc_a5d4aeec, TypeLD>, Enc_04c959 { +tc_a32e03e7, TypeLD>, Enc_04c959 { let Inst{12-12} = 0b1; let Inst{31-21} = 0b10011100010; let addrMode = BaseLongOffset; @@ -11759,7 +11866,7 @@ def L4_loadbsw2_ap : HInst< (outs IntRegs:$Rd32, IntRegs:$Re32), (ins u32_0Imm:$II), "$Rd32 = membh($Re32=#$II)", -tc_3b5b7ef9, TypeLD>, Enc_323f2d { +tc_822c3c68, TypeLD>, Enc_323f2d { let Inst{7-7} = 0b0; let Inst{13-12} = 0b01; let Inst{31-21} = 0b10011010001; @@ -11780,7 +11887,7 @@ def L4_loadbsw2_ur : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), "$Rd32 = membh($Rt32<<#$Ii+#$II)", -tc_bab0eed9, TypeLD>, Enc_4f677b { +tc_abfd9a6d, TypeLD>, Enc_4f677b { let Inst{12-12} = 0b1; let Inst{31-21} = 0b10011100001; let hasNewValue = 1; @@ -11801,7 +11908,7 @@ def L4_loadbsw4_ap : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Re32), (ins u32_0Imm:$II), "$Rdd32 = membh($Re32=#$II)", -tc_3b5b7ef9, TypeLD>, Enc_7fa7f6 { +tc_822c3c68, TypeLD>, Enc_7fa7f6 { let Inst{7-7} = 0b0; let Inst{13-12} = 0b01; let Inst{31-21} = 0b10011010111; @@ -11820,7 +11927,7 @@ def L4_loadbsw4_ur : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), "$Rdd32 = membh($Rt32<<#$Ii+#$II)", -tc_bab0eed9, TypeLD>, Enc_6185fe { +tc_abfd9a6d, TypeLD>, Enc_6185fe { let Inst{12-12} = 0b1; let Inst{31-21} = 0b10011100111; let addrMode = BaseLongOffset; @@ -11839,7 +11946,7 @@ def L4_loadbzw2_ap : HInst< (outs IntRegs:$Rd32, IntRegs:$Re32), (ins u32_0Imm:$II), "$Rd32 = memubh($Re32=#$II)", -tc_3b5b7ef9, TypeLD>, Enc_323f2d { +tc_822c3c68, TypeLD>, Enc_323f2d { let Inst{7-7} = 0b0; let Inst{13-12} = 0b01; let Inst{31-21} = 0b10011010011; @@ -11860,7 +11967,7 @@ def L4_loadbzw2_ur : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), "$Rd32 = memubh($Rt32<<#$Ii+#$II)", -tc_bab0eed9, TypeLD>, Enc_4f677b { +tc_abfd9a6d, TypeLD>, Enc_4f677b { let Inst{12-12} = 0b1; let Inst{31-21} = 0b10011100011; let hasNewValue = 1; @@ -11881,7 +11988,7 @@ def L4_loadbzw4_ap : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Re32), (ins u32_0Imm:$II), "$Rdd32 = memubh($Re32=#$II)", -tc_3b5b7ef9, TypeLD>, Enc_7fa7f6 { +tc_822c3c68, TypeLD>, Enc_7fa7f6 { let Inst{7-7} = 0b0; let Inst{13-12} = 0b01; let Inst{31-21} = 0b10011010101; @@ -11900,7 +12007,7 @@ def L4_loadbzw4_ur : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), "$Rdd32 = memubh($Rt32<<#$Ii+#$II)", -tc_bab0eed9, TypeLD>, Enc_6185fe { +tc_abfd9a6d, TypeLD>, Enc_6185fe { let Inst{12-12} = 0b1; let Inst{31-21} = 0b10011100101; let addrMode = BaseLongOffset; @@ -11919,7 +12026,7 @@ def L4_loadd_locked : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = memd_locked($Rs32)", -tc_b43e7930, TypeLD>, Enc_3a3d62 { +tc_64b00d8a, TypeLD>, Enc_3a3d62 { let Inst{13-5} = 0b010000000; let Inst{31-21} = 0b10010010000; let accessSize = DoubleWordAccess; @@ -11930,7 +12037,7 @@ def L4_loadrb_ap : HInst< (outs IntRegs:$Rd32, IntRegs:$Re32), (ins u32_0Imm:$II), "$Rd32 = memb($Re32=#$II)", -tc_3b5b7ef9, TypeLD>, Enc_323f2d { +tc_822c3c68, TypeLD>, Enc_323f2d { let Inst{7-7} = 0b0; let Inst{13-12} = 0b01; let Inst{31-21} = 0b10011011000; @@ -11951,7 +12058,7 @@ def L4_loadrb_rr : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "$Rd32 = memb($Rs32+$Rt32<<#$Ii)", -tc_bf061958, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { +tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { let Inst{6-5} = 0b00; let Inst{31-21} = 0b00111010000; let hasNewValue = 1; @@ -11959,16 +12066,16 @@ let opNewValue = 0; let addrMode = BaseRegOffset; let accessSize = ByteAccess; let mayLoad = 1; +let BaseOpcode = "L4_loadrb_rr"; let CextOpcode = "L2_loadrb"; let InputType = "reg"; -let BaseOpcode = "L4_loadrb_rr"; let isPredicable = 1; } def L4_loadrb_ur : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), "$Rd32 = memb($Rt32<<#$Ii+#$II)", -tc_bab0eed9, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { +tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { let Inst{12-12} = 0b1; let Inst{31-21} = 0b10011101000; let hasNewValue = 1; @@ -11990,7 +12097,7 @@ def L4_loadrd_ap : HInst< (outs DoubleRegs:$Rdd32, IntRegs:$Re32), (ins u32_0Imm:$II), "$Rdd32 = memd($Re32=#$II)", -tc_3b5b7ef9, TypeLD>, Enc_7fa7f6 { +tc_822c3c68, TypeLD>, Enc_7fa7f6 { let Inst{7-7} = 0b0; let Inst{13-12} = 0b01; let Inst{31-21} = 0b10011011110; @@ -12009,22 +12116,22 @@ def L4_loadrd_rr : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "$Rdd32 = memd($Rs32+$Rt32<<#$Ii)", -tc_bf061958, TypeLD>, Enc_84bff1, AddrModeRel, ImmRegShl { +tc_bf2ffc0f, TypeLD>, Enc_84bff1, AddrModeRel, ImmRegShl { let Inst{6-5} = 0b00; let Inst{31-21} = 0b00111010110; let addrMode = BaseRegOffset; let accessSize = DoubleWordAccess; let mayLoad = 1; +let BaseOpcode = "L4_loadrd_rr"; let CextOpcode = "L2_loadrd"; let InputType = "reg"; -let BaseOpcode = "L4_loadrd_rr"; let isPredicable = 1; } def L4_loadrd_ur : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), "$Rdd32 = memd($Rt32<<#$Ii+#$II)", -tc_bab0eed9, TypeLD>, Enc_6185fe, AddrModeRel, ImmRegShl { +tc_abfd9a6d, TypeLD>, Enc_6185fe, AddrModeRel, ImmRegShl { let Inst{12-12} = 0b1; let Inst{31-21} = 0b10011101110; let addrMode = BaseLongOffset; @@ -12044,7 +12151,7 @@ def L4_loadrh_ap : HInst< (outs IntRegs:$Rd32, IntRegs:$Re32), (ins u32_0Imm:$II), "$Rd32 = memh($Re32=#$II)", -tc_3b5b7ef9, TypeLD>, Enc_323f2d { +tc_822c3c68, TypeLD>, Enc_323f2d { let Inst{7-7} = 0b0; let Inst{13-12} = 0b01; let Inst{31-21} = 0b10011011010; @@ -12065,7 +12172,7 @@ def L4_loadrh_rr : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "$Rd32 = memh($Rs32+$Rt32<<#$Ii)", -tc_bf061958, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { +tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { let Inst{6-5} = 0b00; let Inst{31-21} = 0b00111010010; let hasNewValue = 1; @@ -12073,16 +12180,16 @@ let opNewValue = 0; let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let mayLoad = 1; +let BaseOpcode = "L4_loadrh_rr"; let CextOpcode = "L2_loadrh"; let InputType = "reg"; -let BaseOpcode = "L4_loadrh_rr"; let isPredicable = 1; } def L4_loadrh_ur : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), "$Rd32 = memh($Rt32<<#$Ii+#$II)", -tc_bab0eed9, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { +tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { let Inst{12-12} = 0b1; let Inst{31-21} = 0b10011101010; let hasNewValue = 1; @@ -12104,7 +12211,7 @@ def L4_loadri_ap : HInst< (outs IntRegs:$Rd32, IntRegs:$Re32), (ins u32_0Imm:$II), "$Rd32 = memw($Re32=#$II)", -tc_3b5b7ef9, TypeLD>, Enc_323f2d { +tc_822c3c68, TypeLD>, Enc_323f2d { let Inst{7-7} = 0b0; let Inst{13-12} = 0b01; let Inst{31-21} = 0b10011011100; @@ -12125,7 +12232,7 @@ def L4_loadri_rr : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "$Rd32 = memw($Rs32+$Rt32<<#$Ii)", -tc_bf061958, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { +tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { let Inst{6-5} = 0b00; let Inst{31-21} = 0b00111010100; let hasNewValue = 1; @@ -12133,16 +12240,16 @@ let opNewValue = 0; let addrMode = BaseRegOffset; let accessSize = WordAccess; let mayLoad = 1; +let BaseOpcode = "L4_loadri_rr"; let CextOpcode = "L2_loadri"; let InputType = "reg"; -let BaseOpcode = "L4_loadri_rr"; let isPredicable = 1; } def L4_loadri_ur : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), "$Rd32 = memw($Rt32<<#$Ii+#$II)", -tc_bab0eed9, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { +tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { let Inst{12-12} = 0b1; let Inst{31-21} = 0b10011101100; let hasNewValue = 1; @@ -12164,7 +12271,7 @@ def L4_loadrub_ap : HInst< (outs IntRegs:$Rd32, IntRegs:$Re32), (ins u32_0Imm:$II), "$Rd32 = memub($Re32=#$II)", -tc_3b5b7ef9, TypeLD>, Enc_323f2d { +tc_822c3c68, TypeLD>, Enc_323f2d { let Inst{7-7} = 0b0; let Inst{13-12} = 0b01; let Inst{31-21} = 0b10011011001; @@ -12185,7 +12292,7 @@ def L4_loadrub_rr : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "$Rd32 = memub($Rs32+$Rt32<<#$Ii)", -tc_bf061958, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { +tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { let Inst{6-5} = 0b00; let Inst{31-21} = 0b00111010001; let hasNewValue = 1; @@ -12193,16 +12300,16 @@ let opNewValue = 0; let addrMode = BaseRegOffset; let accessSize = ByteAccess; let mayLoad = 1; +let BaseOpcode = "L4_loadrub_rr"; let CextOpcode = "L2_loadrub"; let InputType = "reg"; -let BaseOpcode = "L4_loadrub_rr"; let isPredicable = 1; } def L4_loadrub_ur : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), "$Rd32 = memub($Rt32<<#$Ii+#$II)", -tc_bab0eed9, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { +tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { let Inst{12-12} = 0b1; let Inst{31-21} = 0b10011101001; let hasNewValue = 1; @@ -12224,7 +12331,7 @@ def L4_loadruh_ap : HInst< (outs IntRegs:$Rd32, IntRegs:$Re32), (ins u32_0Imm:$II), "$Rd32 = memuh($Re32=#$II)", -tc_3b5b7ef9, TypeLD>, Enc_323f2d { +tc_822c3c68, TypeLD>, Enc_323f2d { let Inst{7-7} = 0b0; let Inst{13-12} = 0b01; let Inst{31-21} = 0b10011011011; @@ -12245,7 +12352,7 @@ def L4_loadruh_rr : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "$Rd32 = memuh($Rs32+$Rt32<<#$Ii)", -tc_bf061958, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { +tc_bf2ffc0f, TypeLD>, Enc_da664b, AddrModeRel, ImmRegShl { let Inst{6-5} = 0b00; let Inst{31-21} = 0b00111010011; let hasNewValue = 1; @@ -12253,16 +12360,16 @@ let opNewValue = 0; let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let mayLoad = 1; +let BaseOpcode = "L4_loadruh_rr"; let CextOpcode = "L2_loadruh"; let InputType = "reg"; -let BaseOpcode = "L4_loadruh_rr"; let isPredicable = 1; } def L4_loadruh_ur : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), "$Rd32 = memuh($Rt32<<#$Ii+#$II)", -tc_bab0eed9, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { +tc_abfd9a6d, TypeLD>, Enc_4f677b, AddrModeRel, ImmRegShl { let Inst{12-12} = 0b1; let Inst{31-21} = 0b10011101011; let hasNewValue = 1; @@ -12284,7 +12391,7 @@ def L4_or_memopb_io : HInst< (outs), (ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), "memb($Rs32+#$Ii) |= $Rt32", -tc_7186d325, TypeV4LDST>, Enc_d44e31 { +tc_9bcfb2ee, TypeV4LDST>, Enc_d44e31 { let Inst{6-5} = 0b11; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111110000; @@ -12303,7 +12410,7 @@ def L4_or_memopb_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memb($Rs32) |= $Rt32", -tc_7186d325, TypeMAPPING> { +tc_9bcfb2ee, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -12311,7 +12418,7 @@ def L4_or_memoph_io : HInst< (outs), (ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), "memh($Rs32+#$Ii) |= $Rt32", -tc_7186d325, TypeV4LDST>, Enc_163a3c { +tc_9bcfb2ee, TypeV4LDST>, Enc_163a3c { let Inst{6-5} = 0b11; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111110001; @@ -12330,7 +12437,7 @@ def L4_or_memoph_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memh($Rs32) |= $Rt32", -tc_7186d325, TypeMAPPING> { +tc_9bcfb2ee, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -12338,7 +12445,7 @@ def L4_or_memopw_io : HInst< (outs), (ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), "memw($Rs32+#$Ii) |= $Rt32", -tc_7186d325, TypeV4LDST>, Enc_226535 { +tc_9bcfb2ee, TypeV4LDST>, Enc_226535 { let Inst{6-5} = 0b11; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111110010; @@ -12357,7 +12464,7 @@ def L4_or_memopw_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memw($Rs32) |= $Rt32", -tc_7186d325, TypeMAPPING> { +tc_9bcfb2ee, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -12365,7 +12472,7 @@ def L4_ploadrbf_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if (!$Pt4) $Rd32 = memb(#$Ii)", -tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel { +tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b101; let Inst{31-21} = 0b10011111000; @@ -12377,8 +12484,8 @@ let addrMode = Absolute; let accessSize = ByteAccess; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrb"; let BaseOpcode = "L4_loadrb_abs"; +let CextOpcode = "L2_loadrb"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -12390,7 +12497,7 @@ def L4_ploadrbf_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if (!$Pv4) $Rd32 = memb($Rs32+$Rt32<<#$Ii)", -tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel { +tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110001000; let isPredicated = 1; let isPredicatedFalse = 1; @@ -12399,15 +12506,15 @@ let opNewValue = 0; let addrMode = BaseRegOffset; let accessSize = ByteAccess; let mayLoad = 1; +let BaseOpcode = "L4_loadrb_rr"; let CextOpcode = "L2_loadrb"; let InputType = "reg"; -let BaseOpcode = "L4_loadrb_rr"; } def L4_ploadrbfnew_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if (!$Pt4.new) $Rd32 = memb(#$Ii)", -tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel { +tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b111; let Inst{31-21} = 0b10011111000; @@ -12420,8 +12527,8 @@ let accessSize = ByteAccess; let isPredicatedNew = 1; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrb"; let BaseOpcode = "L4_loadrb_abs"; +let CextOpcode = "L2_loadrb"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -12433,7 +12540,7 @@ def L4_ploadrbfnew_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if (!$Pv4.new) $Rd32 = memb($Rs32+$Rt32<<#$Ii)", -tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel { +tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110011000; let isPredicated = 1; let isPredicatedFalse = 1; @@ -12443,15 +12550,15 @@ let addrMode = BaseRegOffset; let accessSize = ByteAccess; let isPredicatedNew = 1; let mayLoad = 1; +let BaseOpcode = "L4_loadrb_rr"; let CextOpcode = "L2_loadrb"; let InputType = "reg"; -let BaseOpcode = "L4_loadrb_rr"; } def L4_ploadrbt_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if ($Pt4) $Rd32 = memb(#$Ii)", -tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel { +tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b100; let Inst{31-21} = 0b10011111000; @@ -12462,8 +12569,8 @@ let addrMode = Absolute; let accessSize = ByteAccess; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrb"; let BaseOpcode = "L4_loadrb_abs"; +let CextOpcode = "L2_loadrb"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -12475,7 +12582,7 @@ def L4_ploadrbt_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if ($Pv4) $Rd32 = memb($Rs32+$Rt32<<#$Ii)", -tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel { +tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110000000; let isPredicated = 1; let hasNewValue = 1; @@ -12483,15 +12590,15 @@ let opNewValue = 0; let addrMode = BaseRegOffset; let accessSize = ByteAccess; let mayLoad = 1; +let BaseOpcode = "L4_loadrb_rr"; let CextOpcode = "L2_loadrb"; let InputType = "reg"; -let BaseOpcode = "L4_loadrb_rr"; } def L4_ploadrbtnew_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if ($Pt4.new) $Rd32 = memb(#$Ii)", -tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel { +tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b110; let Inst{31-21} = 0b10011111000; @@ -12503,8 +12610,8 @@ let accessSize = ByteAccess; let isPredicatedNew = 1; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrb"; let BaseOpcode = "L4_loadrb_abs"; +let CextOpcode = "L2_loadrb"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -12516,7 +12623,7 @@ def L4_ploadrbtnew_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if ($Pv4.new) $Rd32 = memb($Rs32+$Rt32<<#$Ii)", -tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel { +tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110010000; let isPredicated = 1; let hasNewValue = 1; @@ -12525,15 +12632,15 @@ let addrMode = BaseRegOffset; let accessSize = ByteAccess; let isPredicatedNew = 1; let mayLoad = 1; +let BaseOpcode = "L4_loadrb_rr"; let CextOpcode = "L2_loadrb"; let InputType = "reg"; -let BaseOpcode = "L4_loadrb_rr"; } def L4_ploadrdf_abs : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if (!$Pt4) $Rdd32 = memd(#$Ii)", -tc_7646c131, TypeLD>, Enc_2a7b91, AddrModeRel { +tc_7c6d32e4, TypeLD>, Enc_2a7b91, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b101; let Inst{31-21} = 0b10011111110; @@ -12543,8 +12650,8 @@ let addrMode = Absolute; let accessSize = DoubleWordAccess; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrd"; let BaseOpcode = "L4_loadrd_abs"; +let CextOpcode = "L2_loadrd"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -12556,22 +12663,22 @@ def L4_ploadrdf_rr : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if (!$Pv4) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)", -tc_e4b3cb20, TypeLD>, Enc_98c0b8, AddrModeRel { +tc_45791fb8, TypeLD>, Enc_98c0b8, AddrModeRel { let Inst{31-21} = 0b00110001110; let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = BaseRegOffset; let accessSize = DoubleWordAccess; let mayLoad = 1; +let BaseOpcode = "L4_loadrd_rr"; let CextOpcode = "L2_loadrd"; let InputType = "reg"; -let BaseOpcode = "L4_loadrd_rr"; } def L4_ploadrdfnew_abs : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if (!$Pt4.new) $Rdd32 = memd(#$Ii)", -tc_3b5b7ef9, TypeLD>, Enc_2a7b91, AddrModeRel { +tc_822c3c68, TypeLD>, Enc_2a7b91, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b111; let Inst{31-21} = 0b10011111110; @@ -12582,8 +12689,8 @@ let accessSize = DoubleWordAccess; let isPredicatedNew = 1; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrd"; let BaseOpcode = "L4_loadrd_abs"; +let CextOpcode = "L2_loadrd"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -12595,7 +12702,7 @@ def L4_ploadrdfnew_rr : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if (!$Pv4.new) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)", -tc_25a78932, TypeLD>, Enc_98c0b8, AddrModeRel { +tc_b7c4062a, TypeLD>, Enc_98c0b8, AddrModeRel { let Inst{31-21} = 0b00110011110; let isPredicated = 1; let isPredicatedFalse = 1; @@ -12603,15 +12710,15 @@ let addrMode = BaseRegOffset; let accessSize = DoubleWordAccess; let isPredicatedNew = 1; let mayLoad = 1; +let BaseOpcode = "L4_loadrd_rr"; let CextOpcode = "L2_loadrd"; let InputType = "reg"; -let BaseOpcode = "L4_loadrd_rr"; } def L4_ploadrdt_abs : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if ($Pt4) $Rdd32 = memd(#$Ii)", -tc_7646c131, TypeLD>, Enc_2a7b91, AddrModeRel { +tc_7c6d32e4, TypeLD>, Enc_2a7b91, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b100; let Inst{31-21} = 0b10011111110; @@ -12620,8 +12727,8 @@ let addrMode = Absolute; let accessSize = DoubleWordAccess; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrd"; let BaseOpcode = "L4_loadrd_abs"; +let CextOpcode = "L2_loadrd"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -12633,21 +12740,21 @@ def L4_ploadrdt_rr : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if ($Pv4) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)", -tc_e4b3cb20, TypeLD>, Enc_98c0b8, AddrModeRel { +tc_45791fb8, TypeLD>, Enc_98c0b8, AddrModeRel { let Inst{31-21} = 0b00110000110; let isPredicated = 1; let addrMode = BaseRegOffset; let accessSize = DoubleWordAccess; let mayLoad = 1; +let BaseOpcode = "L4_loadrd_rr"; let CextOpcode = "L2_loadrd"; let InputType = "reg"; -let BaseOpcode = "L4_loadrd_rr"; } def L4_ploadrdtnew_abs : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if ($Pt4.new) $Rdd32 = memd(#$Ii)", -tc_3b5b7ef9, TypeLD>, Enc_2a7b91, AddrModeRel { +tc_822c3c68, TypeLD>, Enc_2a7b91, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b110; let Inst{31-21} = 0b10011111110; @@ -12657,8 +12764,8 @@ let accessSize = DoubleWordAccess; let isPredicatedNew = 1; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrd"; let BaseOpcode = "L4_loadrd_abs"; +let CextOpcode = "L2_loadrd"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -12670,22 +12777,22 @@ def L4_ploadrdtnew_rr : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if ($Pv4.new) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)", -tc_25a78932, TypeLD>, Enc_98c0b8, AddrModeRel { +tc_b7c4062a, TypeLD>, Enc_98c0b8, AddrModeRel { let Inst{31-21} = 0b00110010110; let isPredicated = 1; let addrMode = BaseRegOffset; let accessSize = DoubleWordAccess; let isPredicatedNew = 1; let mayLoad = 1; +let BaseOpcode = "L4_loadrd_rr"; let CextOpcode = "L2_loadrd"; let InputType = "reg"; -let BaseOpcode = "L4_loadrd_rr"; } def L4_ploadrhf_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if (!$Pt4) $Rd32 = memh(#$Ii)", -tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel { +tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b101; let Inst{31-21} = 0b10011111010; @@ -12697,8 +12804,8 @@ let addrMode = Absolute; let accessSize = HalfWordAccess; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrh"; let BaseOpcode = "L4_loadrh_abs"; +let CextOpcode = "L2_loadrh"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -12710,7 +12817,7 @@ def L4_ploadrhf_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if (!$Pv4) $Rd32 = memh($Rs32+$Rt32<<#$Ii)", -tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel { +tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110001010; let isPredicated = 1; let isPredicatedFalse = 1; @@ -12719,15 +12826,15 @@ let opNewValue = 0; let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let mayLoad = 1; +let BaseOpcode = "L4_loadrh_rr"; let CextOpcode = "L2_loadrh"; let InputType = "reg"; -let BaseOpcode = "L4_loadrh_rr"; } def L4_ploadrhfnew_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if (!$Pt4.new) $Rd32 = memh(#$Ii)", -tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel { +tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b111; let Inst{31-21} = 0b10011111010; @@ -12740,8 +12847,8 @@ let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrh"; let BaseOpcode = "L4_loadrh_abs"; +let CextOpcode = "L2_loadrh"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -12753,7 +12860,7 @@ def L4_ploadrhfnew_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if (!$Pv4.new) $Rd32 = memh($Rs32+$Rt32<<#$Ii)", -tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel { +tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110011010; let isPredicated = 1; let isPredicatedFalse = 1; @@ -12763,15 +12870,15 @@ let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayLoad = 1; +let BaseOpcode = "L4_loadrh_rr"; let CextOpcode = "L2_loadrh"; let InputType = "reg"; -let BaseOpcode = "L4_loadrh_rr"; } def L4_ploadrht_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if ($Pt4) $Rd32 = memh(#$Ii)", -tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel { +tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b100; let Inst{31-21} = 0b10011111010; @@ -12782,8 +12889,8 @@ let addrMode = Absolute; let accessSize = HalfWordAccess; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrh"; let BaseOpcode = "L4_loadrh_abs"; +let CextOpcode = "L2_loadrh"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -12795,7 +12902,7 @@ def L4_ploadrht_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if ($Pv4) $Rd32 = memh($Rs32+$Rt32<<#$Ii)", -tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel { +tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110000010; let isPredicated = 1; let hasNewValue = 1; @@ -12803,15 +12910,15 @@ let opNewValue = 0; let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let mayLoad = 1; +let BaseOpcode = "L4_loadrh_rr"; let CextOpcode = "L2_loadrh"; let InputType = "reg"; -let BaseOpcode = "L4_loadrh_rr"; } def L4_ploadrhtnew_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if ($Pt4.new) $Rd32 = memh(#$Ii)", -tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel { +tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b110; let Inst{31-21} = 0b10011111010; @@ -12823,8 +12930,8 @@ let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrh"; let BaseOpcode = "L4_loadrh_abs"; +let CextOpcode = "L2_loadrh"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -12836,7 +12943,7 @@ def L4_ploadrhtnew_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if ($Pv4.new) $Rd32 = memh($Rs32+$Rt32<<#$Ii)", -tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel { +tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110010010; let isPredicated = 1; let hasNewValue = 1; @@ -12845,15 +12952,15 @@ let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayLoad = 1; +let BaseOpcode = "L4_loadrh_rr"; let CextOpcode = "L2_loadrh"; let InputType = "reg"; -let BaseOpcode = "L4_loadrh_rr"; } def L4_ploadrif_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if (!$Pt4) $Rd32 = memw(#$Ii)", -tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel { +tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b101; let Inst{31-21} = 0b10011111100; @@ -12865,8 +12972,8 @@ let addrMode = Absolute; let accessSize = WordAccess; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadri"; let BaseOpcode = "L4_loadri_abs"; +let CextOpcode = "L2_loadri"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -12878,7 +12985,7 @@ def L4_ploadrif_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if (!$Pv4) $Rd32 = memw($Rs32+$Rt32<<#$Ii)", -tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel { +tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110001100; let isPredicated = 1; let isPredicatedFalse = 1; @@ -12887,15 +12994,15 @@ let opNewValue = 0; let addrMode = BaseRegOffset; let accessSize = WordAccess; let mayLoad = 1; +let BaseOpcode = "L4_loadri_rr"; let CextOpcode = "L2_loadri"; let InputType = "reg"; -let BaseOpcode = "L4_loadri_rr"; } def L4_ploadrifnew_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if (!$Pt4.new) $Rd32 = memw(#$Ii)", -tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel { +tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b111; let Inst{31-21} = 0b10011111100; @@ -12908,8 +13015,8 @@ let accessSize = WordAccess; let isPredicatedNew = 1; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadri"; let BaseOpcode = "L4_loadri_abs"; +let CextOpcode = "L2_loadri"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -12921,7 +13028,7 @@ def L4_ploadrifnew_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if (!$Pv4.new) $Rd32 = memw($Rs32+$Rt32<<#$Ii)", -tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel { +tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110011100; let isPredicated = 1; let isPredicatedFalse = 1; @@ -12931,15 +13038,15 @@ let addrMode = BaseRegOffset; let accessSize = WordAccess; let isPredicatedNew = 1; let mayLoad = 1; +let BaseOpcode = "L4_loadri_rr"; let CextOpcode = "L2_loadri"; let InputType = "reg"; -let BaseOpcode = "L4_loadri_rr"; } def L4_ploadrit_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if ($Pt4) $Rd32 = memw(#$Ii)", -tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel { +tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b100; let Inst{31-21} = 0b10011111100; @@ -12950,8 +13057,8 @@ let addrMode = Absolute; let accessSize = WordAccess; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadri"; let BaseOpcode = "L4_loadri_abs"; +let CextOpcode = "L2_loadri"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -12963,7 +13070,7 @@ def L4_ploadrit_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if ($Pv4) $Rd32 = memw($Rs32+$Rt32<<#$Ii)", -tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel { +tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110000100; let isPredicated = 1; let hasNewValue = 1; @@ -12971,15 +13078,15 @@ let opNewValue = 0; let addrMode = BaseRegOffset; let accessSize = WordAccess; let mayLoad = 1; +let BaseOpcode = "L4_loadri_rr"; let CextOpcode = "L2_loadri"; let InputType = "reg"; -let BaseOpcode = "L4_loadri_rr"; } def L4_ploadritnew_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if ($Pt4.new) $Rd32 = memw(#$Ii)", -tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel { +tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b110; let Inst{31-21} = 0b10011111100; @@ -12991,8 +13098,8 @@ let accessSize = WordAccess; let isPredicatedNew = 1; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadri"; let BaseOpcode = "L4_loadri_abs"; +let CextOpcode = "L2_loadri"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -13004,7 +13111,7 @@ def L4_ploadritnew_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if ($Pv4.new) $Rd32 = memw($Rs32+$Rt32<<#$Ii)", -tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel { +tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110010100; let isPredicated = 1; let hasNewValue = 1; @@ -13013,15 +13120,15 @@ let addrMode = BaseRegOffset; let accessSize = WordAccess; let isPredicatedNew = 1; let mayLoad = 1; +let BaseOpcode = "L4_loadri_rr"; let CextOpcode = "L2_loadri"; let InputType = "reg"; -let BaseOpcode = "L4_loadri_rr"; } def L4_ploadrubf_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if (!$Pt4) $Rd32 = memub(#$Ii)", -tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel { +tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b101; let Inst{31-21} = 0b10011111001; @@ -13033,8 +13140,8 @@ let addrMode = Absolute; let accessSize = ByteAccess; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrub"; let BaseOpcode = "L4_loadrub_abs"; +let CextOpcode = "L2_loadrub"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -13046,7 +13153,7 @@ def L4_ploadrubf_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if (!$Pv4) $Rd32 = memub($Rs32+$Rt32<<#$Ii)", -tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel { +tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110001001; let isPredicated = 1; let isPredicatedFalse = 1; @@ -13055,15 +13162,15 @@ let opNewValue = 0; let addrMode = BaseRegOffset; let accessSize = ByteAccess; let mayLoad = 1; +let BaseOpcode = "L4_loadrub_rr"; let CextOpcode = "L2_loadrub"; let InputType = "reg"; -let BaseOpcode = "L4_loadrub_rr"; } def L4_ploadrubfnew_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if (!$Pt4.new) $Rd32 = memub(#$Ii)", -tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel { +tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b111; let Inst{31-21} = 0b10011111001; @@ -13076,8 +13183,8 @@ let accessSize = ByteAccess; let isPredicatedNew = 1; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrub"; let BaseOpcode = "L4_loadrub_abs"; +let CextOpcode = "L2_loadrub"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -13089,7 +13196,7 @@ def L4_ploadrubfnew_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if (!$Pv4.new) $Rd32 = memub($Rs32+$Rt32<<#$Ii)", -tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel { +tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110011001; let isPredicated = 1; let isPredicatedFalse = 1; @@ -13099,15 +13206,15 @@ let addrMode = BaseRegOffset; let accessSize = ByteAccess; let isPredicatedNew = 1; let mayLoad = 1; +let BaseOpcode = "L4_loadrub_rr"; let CextOpcode = "L2_loadrub"; let InputType = "reg"; -let BaseOpcode = "L4_loadrub_rr"; } def L4_ploadrubt_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if ($Pt4) $Rd32 = memub(#$Ii)", -tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel { +tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b100; let Inst{31-21} = 0b10011111001; @@ -13118,8 +13225,8 @@ let addrMode = Absolute; let accessSize = ByteAccess; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrub"; let BaseOpcode = "L4_loadrub_abs"; +let CextOpcode = "L2_loadrub"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -13131,7 +13238,7 @@ def L4_ploadrubt_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if ($Pv4) $Rd32 = memub($Rs32+$Rt32<<#$Ii)", -tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel { +tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110000001; let isPredicated = 1; let hasNewValue = 1; @@ -13139,15 +13246,15 @@ let opNewValue = 0; let addrMode = BaseRegOffset; let accessSize = ByteAccess; let mayLoad = 1; +let BaseOpcode = "L4_loadrub_rr"; let CextOpcode = "L2_loadrub"; let InputType = "reg"; -let BaseOpcode = "L4_loadrub_rr"; } def L4_ploadrubtnew_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if ($Pt4.new) $Rd32 = memub(#$Ii)", -tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel { +tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b110; let Inst{31-21} = 0b10011111001; @@ -13159,8 +13266,8 @@ let accessSize = ByteAccess; let isPredicatedNew = 1; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrub"; let BaseOpcode = "L4_loadrub_abs"; +let CextOpcode = "L2_loadrub"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -13172,7 +13279,7 @@ def L4_ploadrubtnew_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if ($Pv4.new) $Rd32 = memub($Rs32+$Rt32<<#$Ii)", -tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel { +tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110010001; let isPredicated = 1; let hasNewValue = 1; @@ -13181,15 +13288,15 @@ let addrMode = BaseRegOffset; let accessSize = ByteAccess; let isPredicatedNew = 1; let mayLoad = 1; +let BaseOpcode = "L4_loadrub_rr"; let CextOpcode = "L2_loadrub"; let InputType = "reg"; -let BaseOpcode = "L4_loadrub_rr"; } def L4_ploadruhf_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if (!$Pt4) $Rd32 = memuh(#$Ii)", -tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel { +tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b101; let Inst{31-21} = 0b10011111011; @@ -13201,8 +13308,8 @@ let addrMode = Absolute; let accessSize = HalfWordAccess; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadruh"; let BaseOpcode = "L4_loadruh_abs"; +let CextOpcode = "L2_loadruh"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -13214,7 +13321,7 @@ def L4_ploadruhf_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if (!$Pv4) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)", -tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel { +tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110001011; let isPredicated = 1; let isPredicatedFalse = 1; @@ -13223,15 +13330,15 @@ let opNewValue = 0; let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let mayLoad = 1; +let BaseOpcode = "L4_loadruh_rr"; let CextOpcode = "L2_loadruh"; let InputType = "reg"; -let BaseOpcode = "L4_loadruh_rr"; } def L4_ploadruhfnew_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if (!$Pt4.new) $Rd32 = memuh(#$Ii)", -tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel { +tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b111; let Inst{31-21} = 0b10011111011; @@ -13244,8 +13351,8 @@ let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadruh"; let BaseOpcode = "L4_loadruh_abs"; +let CextOpcode = "L2_loadruh"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -13257,7 +13364,7 @@ def L4_ploadruhfnew_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if (!$Pv4.new) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)", -tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel { +tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110011011; let isPredicated = 1; let isPredicatedFalse = 1; @@ -13267,15 +13374,15 @@ let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayLoad = 1; +let BaseOpcode = "L4_loadruh_rr"; let CextOpcode = "L2_loadruh"; let InputType = "reg"; -let BaseOpcode = "L4_loadruh_rr"; } def L4_ploadruht_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if ($Pt4) $Rd32 = memuh(#$Ii)", -tc_7646c131, TypeLD>, Enc_2301d6, AddrModeRel { +tc_7c6d32e4, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b100; let Inst{31-21} = 0b10011111011; @@ -13286,8 +13393,8 @@ let addrMode = Absolute; let accessSize = HalfWordAccess; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadruh"; let BaseOpcode = "L4_loadruh_abs"; +let CextOpcode = "L2_loadruh"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -13299,7 +13406,7 @@ def L4_ploadruht_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if ($Pv4) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)", -tc_e4b3cb20, TypeLD>, Enc_2e1979, AddrModeRel { +tc_45791fb8, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110000011; let isPredicated = 1; let hasNewValue = 1; @@ -13307,15 +13414,15 @@ let opNewValue = 0; let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let mayLoad = 1; +let BaseOpcode = "L4_loadruh_rr"; let CextOpcode = "L2_loadruh"; let InputType = "reg"; -let BaseOpcode = "L4_loadruh_rr"; } def L4_ploadruhtnew_abs : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pt4, u32_0Imm:$Ii), "if ($Pt4.new) $Rd32 = memuh(#$Ii)", -tc_3b5b7ef9, TypeLD>, Enc_2301d6, AddrModeRel { +tc_822c3c68, TypeLD>, Enc_2301d6, AddrModeRel { let Inst{7-5} = 0b100; let Inst{13-11} = 0b110; let Inst{31-21} = 0b10011111011; @@ -13327,8 +13434,8 @@ let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadruh"; let BaseOpcode = "L4_loadruh_abs"; +let CextOpcode = "L2_loadruh"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -13340,7 +13447,7 @@ def L4_ploadruhtnew_rr : HInst< (outs IntRegs:$Rd32), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), "if ($Pv4.new) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)", -tc_25a78932, TypeLD>, Enc_2e1979, AddrModeRel { +tc_b7c4062a, TypeLD>, Enc_2e1979, AddrModeRel { let Inst{31-21} = 0b00110010011; let isPredicated = 1; let hasNewValue = 1; @@ -13349,15 +13456,15 @@ let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayLoad = 1; +let BaseOpcode = "L4_loadruh_rr"; let CextOpcode = "L2_loadruh"; let InputType = "reg"; -let BaseOpcode = "L4_loadruh_rr"; } def L4_return : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = dealloc_return($Rs32):raw", -tc_675e4897, TypeLD>, Enc_3a3d62, PredNewRel { +tc_40d64c94, TypeLD>, Enc_3a3d62, PredNewRel { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10010110000; let isTerminator = 1; @@ -13378,7 +13485,7 @@ def L4_return_f : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pv4, IntRegs:$Rs32), "if (!$Pv4) $Rdd32 = dealloc_return($Rs32):raw", -tc_2b8da4c2, TypeLD>, Enc_b7fad3, PredNewRel { +tc_df5d53f9, TypeLD>, Enc_b7fad3, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1100; let Inst{31-21} = 0b10010110000; @@ -13400,7 +13507,7 @@ def L4_return_fnew_pnt : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pv4, IntRegs:$Rs32), "if (!$Pv4.new) $Rdd32 = dealloc_return($Rs32):nt:raw", -tc_9da59d12, TypeLD>, Enc_b7fad3, PredNewRel { +tc_14ab4f41, TypeLD>, Enc_b7fad3, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1010; let Inst{31-21} = 0b10010110000; @@ -13423,7 +13530,7 @@ def L4_return_fnew_pt : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pv4, IntRegs:$Rs32), "if (!$Pv4.new) $Rdd32 = dealloc_return($Rs32):t:raw", -tc_9da59d12, TypeLD>, Enc_b7fad3, PredNewRel { +tc_14ab4f41, TypeLD>, Enc_b7fad3, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b1110; let Inst{31-21} = 0b10010110000; @@ -13446,7 +13553,7 @@ def L4_return_map_to_raw_f : HInst< (outs), (ins PredRegs:$Pv4), "if (!$Pv4) dealloc_return", -tc_2b8da4c2, TypeMAPPING>, Requires<[HasV65]> { +tc_df5d53f9, TypeMAPPING>, Requires<[HasV65]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -13454,7 +13561,7 @@ def L4_return_map_to_raw_fnew_pnt : HInst< (outs), (ins PredRegs:$Pv4), "if (!$Pv4.new) dealloc_return:nt", -tc_9da59d12, TypeMAPPING>, Requires<[HasV65]> { +tc_14ab4f41, TypeMAPPING>, Requires<[HasV65]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -13462,7 +13569,7 @@ def L4_return_map_to_raw_fnew_pt : HInst< (outs), (ins PredRegs:$Pv4), "if (!$Pv4.new) dealloc_return:t", -tc_9da59d12, TypeMAPPING>, Requires<[HasV65]> { +tc_14ab4f41, TypeMAPPING>, Requires<[HasV65]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -13470,7 +13577,7 @@ def L4_return_map_to_raw_t : HInst< (outs), (ins PredRegs:$Pv4), "if ($Pv4) dealloc_return", -tc_4d5fa3a1, TypeMAPPING>, Requires<[HasV65]> { +tc_f38f92e1, TypeMAPPING>, Requires<[HasV65]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -13478,7 +13585,7 @@ def L4_return_map_to_raw_tnew_pnt : HInst< (outs), (ins PredRegs:$Pv4), "if ($Pv4.new) dealloc_return:nt", -tc_e06f432a, TypeMAPPING>, Requires<[HasV65]> { +tc_1981450d, TypeMAPPING>, Requires<[HasV65]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -13486,7 +13593,7 @@ def L4_return_map_to_raw_tnew_pt : HInst< (outs), (ins PredRegs:$Pv4), "if ($Pv4.new) dealloc_return:t", -tc_e06f432a, TypeMAPPING>, Requires<[HasV65]> { +tc_1981450d, TypeMAPPING>, Requires<[HasV65]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -13494,7 +13601,7 @@ def L4_return_t : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pv4, IntRegs:$Rs32), "if ($Pv4) $Rdd32 = dealloc_return($Rs32):raw", -tc_2b8da4c2, TypeLD>, Enc_b7fad3, PredNewRel { +tc_df5d53f9, TypeLD>, Enc_b7fad3, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b0100; let Inst{31-21} = 0b10010110000; @@ -13515,7 +13622,7 @@ def L4_return_tnew_pnt : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pv4, IntRegs:$Rs32), "if ($Pv4.new) $Rdd32 = dealloc_return($Rs32):nt:raw", -tc_9da59d12, TypeLD>, Enc_b7fad3, PredNewRel { +tc_14ab4f41, TypeLD>, Enc_b7fad3, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b0010; let Inst{31-21} = 0b10010110000; @@ -13537,7 +13644,7 @@ def L4_return_tnew_pt : HInst< (outs DoubleRegs:$Rdd32), (ins PredRegs:$Pv4, IntRegs:$Rs32), "if ($Pv4.new) $Rdd32 = dealloc_return($Rs32):t:raw", -tc_9da59d12, TypeLD>, Enc_b7fad3, PredNewRel { +tc_14ab4f41, TypeLD>, Enc_b7fad3, PredNewRel { let Inst{7-5} = 0b000; let Inst{13-10} = 0b0110; let Inst{31-21} = 0b10010110000; @@ -13559,7 +13666,7 @@ def L4_sub_memopb_io : HInst< (outs), (ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), "memb($Rs32+#$Ii) -= $Rt32", -tc_7186d325, TypeV4LDST>, Enc_d44e31 { +tc_9bcfb2ee, TypeV4LDST>, Enc_d44e31 { let Inst{6-5} = 0b01; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111110000; @@ -13578,7 +13685,7 @@ def L4_sub_memopb_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memb($Rs32) -= $Rt32", -tc_7186d325, TypeMAPPING> { +tc_9bcfb2ee, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -13586,7 +13693,7 @@ def L4_sub_memoph_io : HInst< (outs), (ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), "memh($Rs32+#$Ii) -= $Rt32", -tc_7186d325, TypeV4LDST>, Enc_163a3c { +tc_9bcfb2ee, TypeV4LDST>, Enc_163a3c { let Inst{6-5} = 0b01; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111110001; @@ -13605,7 +13712,7 @@ def L4_sub_memoph_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memh($Rs32) -= $Rt32", -tc_7186d325, TypeMAPPING> { +tc_9bcfb2ee, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -13613,7 +13720,7 @@ def L4_sub_memopw_io : HInst< (outs), (ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), "memw($Rs32+#$Ii) -= $Rt32", -tc_7186d325, TypeV4LDST>, Enc_226535 { +tc_9bcfb2ee, TypeV4LDST>, Enc_226535 { let Inst{6-5} = 0b01; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00111110010; @@ -13632,7 +13739,7 @@ def L4_sub_memopw_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memw($Rs32) -= $Rt32", -tc_7186d325, TypeMAPPING> { +tc_9bcfb2ee, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -13640,7 +13747,7 @@ def L6_deallocframe_map_to_raw : HInst< (outs), (ins), "deallocframe", -tc_15aa71c5, TypeMAPPING>, Requires<[HasV65]> { +tc_e9170fb7, TypeMAPPING>, Requires<[HasV65]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -13648,7 +13755,7 @@ def L6_memcpy : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32, ModRegs:$Mu2), "memcpy($Rs32,$Rt32,$Mu2)", -tc_a6b1eca9, TypeLD>, Enc_a75aa6, Requires<[HasV66]> { +tc_5944960d, TypeLD>, Enc_a75aa6, Requires<[HasV66]> { let Inst{7-0} = 0b01000000; let Inst{31-21} = 0b10010010000; let mayLoad = 1; @@ -13659,7 +13766,7 @@ def L6_return_map_to_raw : HInst< (outs), (ins), "dealloc_return", -tc_675e4897, TypeMAPPING>, Requires<[HasV65]> { +tc_40d64c94, TypeMAPPING>, Requires<[HasV65]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -13667,7 +13774,7 @@ def M2_acci : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += add($Rs32,$Rt32)", -tc_f675fee8, TypeM>, Enc_2ae154, ImmRegRel { +tc_2c13e7f5, TypeM>, Enc_2ae154, ImmRegRel { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111000; @@ -13682,7 +13789,7 @@ def M2_accii : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii), "$Rx32 += add($Rs32,#$Ii)", -tc_f675fee8, TypeM>, Enc_c90aca, ImmRegRel { +tc_2c13e7f5, TypeM>, Enc_c90aca, ImmRegRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100010000; let hasNewValue = 1; @@ -13701,7 +13808,7 @@ def M2_cmaci_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += cmpyi($Rs32,$Rt32)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111000; @@ -13712,7 +13819,7 @@ def M2_cmacr_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += cmpyr($Rs32,$Rt32)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111000; @@ -13723,7 +13830,7 @@ def M2_cmacs_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += cmpy($Rs32,$Rt32):sat", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111000; @@ -13735,7 +13842,7 @@ def M2_cmacs_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += cmpy($Rs32,$Rt32):<<1:sat", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111100; @@ -13747,7 +13854,7 @@ def M2_cmacsc_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += cmpy($Rs32,$Rt32*):sat", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111010; @@ -13759,7 +13866,7 @@ def M2_cmacsc_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += cmpy($Rs32,$Rt32*):<<1:sat", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111110; @@ -13771,7 +13878,7 @@ def M2_cmpyi_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = cmpyi($Rs32,$Rt32)", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101000; @@ -13781,7 +13888,7 @@ def M2_cmpyr_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = cmpyr($Rs32,$Rt32)", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101000; @@ -13791,7 +13898,7 @@ def M2_cmpyrs_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = cmpy($Rs32,$Rt32):rnd:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101001; @@ -13804,7 +13911,7 @@ def M2_cmpyrs_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = cmpy($Rs32,$Rt32):<<1:rnd:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101101; @@ -13817,7 +13924,7 @@ def M2_cmpyrsc_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = cmpy($Rs32,$Rt32*):rnd:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101011; @@ -13830,7 +13937,7 @@ def M2_cmpyrsc_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = cmpy($Rs32,$Rt32*):<<1:rnd:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101111; @@ -13843,7 +13950,7 @@ def M2_cmpys_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = cmpy($Rs32,$Rt32):sat", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101000; @@ -13854,7 +13961,7 @@ def M2_cmpys_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = cmpy($Rs32,$Rt32):<<1:sat", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101100; @@ -13865,7 +13972,7 @@ def M2_cmpysc_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = cmpy($Rs32,$Rt32*):sat", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101010; @@ -13876,7 +13983,7 @@ def M2_cmpysc_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = cmpy($Rs32,$Rt32*):<<1:sat", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101110; @@ -13887,7 +13994,7 @@ def M2_cnacs_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= cmpy($Rs32,$Rt32):sat", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111000; @@ -13899,7 +14006,7 @@ def M2_cnacs_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= cmpy($Rs32,$Rt32):<<1:sat", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111100; @@ -13911,7 +14018,7 @@ def M2_cnacsc_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= cmpy($Rs32,$Rt32*):sat", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111010; @@ -13923,7 +14030,7 @@ def M2_cnacsc_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= cmpy($Rs32,$Rt32*):<<1:sat", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111110; @@ -13935,7 +14042,7 @@ def M2_dpmpyss_acc_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpy($Rs32,$Rt32)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111000; @@ -13946,7 +14053,7 @@ def M2_dpmpyss_nac_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpy($Rs32,$Rt32)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111001; @@ -13957,7 +14064,7 @@ def M2_dpmpyss_rnd_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32,$Rt32):rnd", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101001; @@ -13969,7 +14076,7 @@ def M2_dpmpyss_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32,$Rt32)", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101000; @@ -13979,7 +14086,7 @@ def M2_dpmpyuu_acc_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpyu($Rs32,$Rt32)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111010; @@ -13990,7 +14097,7 @@ def M2_dpmpyuu_nac_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpyu($Rs32,$Rt32)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111011; @@ -14001,7 +14108,7 @@ def M2_dpmpyuu_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpyu($Rs32,$Rt32)", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101010; @@ -14011,7 +14118,7 @@ def M2_hmmpyh_rs1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32,$Rt32.h):<<1:rnd:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101101; @@ -14024,7 +14131,7 @@ def M2_hmmpyh_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32,$Rt32.h):<<1:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101101; @@ -14037,7 +14144,7 @@ def M2_hmmpyl_rs1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32,$Rt32.l):<<1:rnd:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101111; @@ -14050,7 +14157,7 @@ def M2_hmmpyl_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32,$Rt32.l):<<1:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101101; @@ -14063,7 +14170,7 @@ def M2_maci : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpyi($Rs32,$Rt32)", -tc_d773585a, TypeM>, Enc_2ae154, ImmRegRel { +tc_7f8ae742, TypeM>, Enc_2ae154, ImmRegRel { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111000; @@ -14078,7 +14185,7 @@ def M2_macsin : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u32_0Imm:$Ii), "$Rx32 -= mpyi($Rs32,#$Ii)", -tc_05d3a09b, TypeM>, Enc_c90aca { +tc_a154b476, TypeM>, Enc_c90aca { let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100001100; let hasNewValue = 1; @@ -14096,7 +14203,7 @@ def M2_macsip : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u32_0Imm:$Ii), "$Rx32 += mpyi($Rs32,#$Ii)", -tc_05d3a09b, TypeM>, Enc_c90aca, ImmRegRel { +tc_a154b476, TypeM>, Enc_c90aca, ImmRegRel { let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100001000; let hasNewValue = 1; @@ -14115,7 +14222,7 @@ def M2_mmachs_rs0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpywoh($Rss32,$Rtt32):rnd:sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010001; @@ -14127,7 +14234,7 @@ def M2_mmachs_rs1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpywoh($Rss32,$Rtt32):<<1:rnd:sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010101; @@ -14139,7 +14246,7 @@ def M2_mmachs_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpywoh($Rss32,$Rtt32):sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010000; @@ -14151,7 +14258,7 @@ def M2_mmachs_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpywoh($Rss32,$Rtt32):<<1:sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010100; @@ -14163,7 +14270,7 @@ def M2_mmacls_rs0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpyweh($Rss32,$Rtt32):rnd:sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010001; @@ -14175,7 +14282,7 @@ def M2_mmacls_rs1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpyweh($Rss32,$Rtt32):<<1:rnd:sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010101; @@ -14187,7 +14294,7 @@ def M2_mmacls_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpyweh($Rss32,$Rtt32):sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010000; @@ -14199,7 +14306,7 @@ def M2_mmacls_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpyweh($Rss32,$Rtt32):<<1:sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010100; @@ -14211,7 +14318,7 @@ def M2_mmacuhs_rs0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpywouh($Rss32,$Rtt32):rnd:sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010011; @@ -14223,7 +14330,7 @@ def M2_mmacuhs_rs1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpywouh($Rss32,$Rtt32):<<1:rnd:sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010111; @@ -14235,7 +14342,7 @@ def M2_mmacuhs_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpywouh($Rss32,$Rtt32):sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010010; @@ -14247,7 +14354,7 @@ def M2_mmacuhs_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpywouh($Rss32,$Rtt32):<<1:sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010110; @@ -14259,7 +14366,7 @@ def M2_mmaculs_rs0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpyweuh($Rss32,$Rtt32):rnd:sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010011; @@ -14271,7 +14378,7 @@ def M2_mmaculs_rs1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpyweuh($Rss32,$Rtt32):<<1:rnd:sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010111; @@ -14283,7 +14390,7 @@ def M2_mmaculs_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpyweuh($Rss32,$Rtt32):sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010010; @@ -14295,7 +14402,7 @@ def M2_mmaculs_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpyweuh($Rss32,$Rtt32):<<1:sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010110; @@ -14307,7 +14414,7 @@ def M2_mmpyh_rs0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpywoh($Rss32,$Rtt32):rnd:sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000001; @@ -14318,7 +14425,7 @@ def M2_mmpyh_rs1 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpywoh($Rss32,$Rtt32):<<1:rnd:sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000101; @@ -14329,7 +14436,7 @@ def M2_mmpyh_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpywoh($Rss32,$Rtt32):sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000000; @@ -14340,7 +14447,7 @@ def M2_mmpyh_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpywoh($Rss32,$Rtt32):<<1:sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000100; @@ -14351,7 +14458,7 @@ def M2_mmpyl_rs0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpyweh($Rss32,$Rtt32):rnd:sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000001; @@ -14362,7 +14469,7 @@ def M2_mmpyl_rs1 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpyweh($Rss32,$Rtt32):<<1:rnd:sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000101; @@ -14373,7 +14480,7 @@ def M2_mmpyl_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpyweh($Rss32,$Rtt32):sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000000; @@ -14384,7 +14491,7 @@ def M2_mmpyl_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpyweh($Rss32,$Rtt32):<<1:sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000100; @@ -14395,7 +14502,7 @@ def M2_mmpyuh_rs0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpywouh($Rss32,$Rtt32):rnd:sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000011; @@ -14406,7 +14513,7 @@ def M2_mmpyuh_rs1 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpywouh($Rss32,$Rtt32):<<1:rnd:sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000111; @@ -14417,7 +14524,7 @@ def M2_mmpyuh_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpywouh($Rss32,$Rtt32):sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000010; @@ -14428,7 +14535,7 @@ def M2_mmpyuh_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpywouh($Rss32,$Rtt32):<<1:sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000110; @@ -14439,7 +14546,7 @@ def M2_mmpyul_rs0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpyweuh($Rss32,$Rtt32):rnd:sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000011; @@ -14450,7 +14557,7 @@ def M2_mmpyul_rs1 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpyweuh($Rss32,$Rtt32):<<1:rnd:sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000111; @@ -14461,7 +14568,7 @@ def M2_mmpyul_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpyweuh($Rss32,$Rtt32):sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000010; @@ -14472,7 +14579,7 @@ def M2_mmpyul_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpyweuh($Rss32,$Rtt32):<<1:sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000110; @@ -14483,7 +14590,7 @@ def M2_mnaci : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpyi($Rs32,$Rt32)", -tc_bdceeac1, TypeM>, Enc_2ae154, Requires<[HasV66]> { +tc_01e1be3b, TypeM>, Enc_2ae154, Requires<[HasV66]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111100; @@ -14496,7 +14603,7 @@ def M2_mpy_acc_hh_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.h,$Rt32.h)", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110000; @@ -14509,7 +14616,7 @@ def M2_mpy_acc_hh_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.h,$Rt32.h):<<1", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110100; @@ -14522,7 +14629,7 @@ def M2_mpy_acc_hl_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.h,$Rt32.l)", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110000; @@ -14535,7 +14642,7 @@ def M2_mpy_acc_hl_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.h,$Rt32.l):<<1", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110100; @@ -14548,7 +14655,7 @@ def M2_mpy_acc_lh_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.l,$Rt32.h)", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110000; @@ -14561,7 +14668,7 @@ def M2_mpy_acc_lh_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.l,$Rt32.h):<<1", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110100; @@ -14574,7 +14681,7 @@ def M2_mpy_acc_ll_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.l,$Rt32.l)", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110000; @@ -14587,7 +14694,7 @@ def M2_mpy_acc_ll_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.l,$Rt32.l):<<1", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110100; @@ -14600,7 +14707,7 @@ def M2_mpy_acc_sat_hh_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.h,$Rt32.h):sat", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110000; @@ -14614,7 +14721,7 @@ def M2_mpy_acc_sat_hh_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.h,$Rt32.h):<<1:sat", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110100; @@ -14628,7 +14735,7 @@ def M2_mpy_acc_sat_hl_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.h,$Rt32.l):sat", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110000; @@ -14642,7 +14749,7 @@ def M2_mpy_acc_sat_hl_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.h,$Rt32.l):<<1:sat", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110100; @@ -14656,7 +14763,7 @@ def M2_mpy_acc_sat_lh_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.l,$Rt32.h):sat", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110000; @@ -14670,7 +14777,7 @@ def M2_mpy_acc_sat_lh_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.l,$Rt32.h):<<1:sat", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110100; @@ -14684,7 +14791,7 @@ def M2_mpy_acc_sat_ll_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.l,$Rt32.l):sat", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110000; @@ -14698,7 +14805,7 @@ def M2_mpy_acc_sat_ll_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32.l,$Rt32.l):<<1:sat", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110100; @@ -14712,7 +14819,7 @@ def M2_mpy_hh_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.h)", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100000; @@ -14724,7 +14831,7 @@ def M2_mpy_hh_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.h):<<1", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100100; @@ -14736,7 +14843,7 @@ def M2_mpy_hl_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.l)", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100000; @@ -14748,7 +14855,7 @@ def M2_mpy_hl_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.l):<<1", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100100; @@ -14760,7 +14867,7 @@ def M2_mpy_lh_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.h)", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100000; @@ -14772,7 +14879,7 @@ def M2_mpy_lh_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.h):<<1", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100100; @@ -14784,7 +14891,7 @@ def M2_mpy_ll_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.l)", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100000; @@ -14796,7 +14903,7 @@ def M2_mpy_ll_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.l):<<1", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100100; @@ -14808,7 +14915,7 @@ def M2_mpy_nac_hh_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.h,$Rt32.h)", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110001; @@ -14821,7 +14928,7 @@ def M2_mpy_nac_hh_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.h,$Rt32.h):<<1", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110101; @@ -14834,7 +14941,7 @@ def M2_mpy_nac_hl_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.h,$Rt32.l)", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110001; @@ -14847,7 +14954,7 @@ def M2_mpy_nac_hl_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.h,$Rt32.l):<<1", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110101; @@ -14860,7 +14967,7 @@ def M2_mpy_nac_lh_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.l,$Rt32.h)", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110001; @@ -14873,7 +14980,7 @@ def M2_mpy_nac_lh_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.l,$Rt32.h):<<1", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110101; @@ -14886,7 +14993,7 @@ def M2_mpy_nac_ll_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.l,$Rt32.l)", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110001; @@ -14899,7 +15006,7 @@ def M2_mpy_nac_ll_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.l,$Rt32.l):<<1", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110101; @@ -14912,7 +15019,7 @@ def M2_mpy_nac_sat_hh_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.h,$Rt32.h):sat", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110001; @@ -14926,7 +15033,7 @@ def M2_mpy_nac_sat_hh_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.h,$Rt32.h):<<1:sat", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110101; @@ -14940,7 +15047,7 @@ def M2_mpy_nac_sat_hl_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.h,$Rt32.l):sat", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110001; @@ -14954,7 +15061,7 @@ def M2_mpy_nac_sat_hl_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.h,$Rt32.l):<<1:sat", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110101; @@ -14968,7 +15075,7 @@ def M2_mpy_nac_sat_lh_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.l,$Rt32.h):sat", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110001; @@ -14982,7 +15089,7 @@ def M2_mpy_nac_sat_lh_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.l,$Rt32.h):<<1:sat", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110101; @@ -14996,7 +15103,7 @@ def M2_mpy_nac_sat_ll_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.l,$Rt32.l):sat", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110001; @@ -15010,7 +15117,7 @@ def M2_mpy_nac_sat_ll_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32.l,$Rt32.l):<<1:sat", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110101; @@ -15024,7 +15131,7 @@ def M2_mpy_rnd_hh_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.h):rnd", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100001; @@ -15036,7 +15143,7 @@ def M2_mpy_rnd_hh_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100101; @@ -15048,7 +15155,7 @@ def M2_mpy_rnd_hl_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.l):rnd", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100001; @@ -15060,7 +15167,7 @@ def M2_mpy_rnd_hl_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100101; @@ -15072,7 +15179,7 @@ def M2_mpy_rnd_lh_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.h):rnd", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100001; @@ -15084,7 +15191,7 @@ def M2_mpy_rnd_lh_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100101; @@ -15096,7 +15203,7 @@ def M2_mpy_rnd_ll_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.l):rnd", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100001; @@ -15108,7 +15215,7 @@ def M2_mpy_rnd_ll_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100101; @@ -15120,7 +15227,7 @@ def M2_mpy_sat_hh_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.h):sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100000; @@ -15133,7 +15240,7 @@ def M2_mpy_sat_hh_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100100; @@ -15146,7 +15253,7 @@ def M2_mpy_sat_hl_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.l):sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100000; @@ -15159,7 +15266,7 @@ def M2_mpy_sat_hl_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100100; @@ -15172,7 +15279,7 @@ def M2_mpy_sat_lh_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.h):sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100000; @@ -15185,7 +15292,7 @@ def M2_mpy_sat_lh_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100100; @@ -15198,7 +15305,7 @@ def M2_mpy_sat_ll_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.l):sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100000; @@ -15211,7 +15318,7 @@ def M2_mpy_sat_ll_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100100; @@ -15224,7 +15331,7 @@ def M2_mpy_sat_rnd_hh_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.h):rnd:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100001; @@ -15237,7 +15344,7 @@ def M2_mpy_sat_rnd_hh_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100101; @@ -15250,7 +15357,7 @@ def M2_mpy_sat_rnd_hl_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.l):rnd:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100001; @@ -15263,7 +15370,7 @@ def M2_mpy_sat_rnd_hl_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100101; @@ -15276,7 +15383,7 @@ def M2_mpy_sat_rnd_lh_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.h):rnd:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100001; @@ -15289,7 +15396,7 @@ def M2_mpy_sat_rnd_lh_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100101; @@ -15302,7 +15409,7 @@ def M2_mpy_sat_rnd_ll_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.l):rnd:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100001; @@ -15315,7 +15422,7 @@ def M2_mpy_sat_rnd_ll_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100101; @@ -15328,7 +15435,7 @@ def M2_mpy_up : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32,$Rt32)", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101000; @@ -15340,7 +15447,7 @@ def M2_mpy_up_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32,$Rt32):<<1", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101101; @@ -15352,7 +15459,7 @@ def M2_mpy_up_s1_sat : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpy($Rs32,$Rt32):<<1:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101111; @@ -15365,7 +15472,7 @@ def M2_mpyd_acc_hh_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpy($Rs32.h,$Rt32.h)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110000; @@ -15376,7 +15483,7 @@ def M2_mpyd_acc_hh_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpy($Rs32.h,$Rt32.h):<<1", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110100; @@ -15387,7 +15494,7 @@ def M2_mpyd_acc_hl_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpy($Rs32.h,$Rt32.l)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110000; @@ -15398,7 +15505,7 @@ def M2_mpyd_acc_hl_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpy($Rs32.h,$Rt32.l):<<1", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110100; @@ -15409,7 +15516,7 @@ def M2_mpyd_acc_lh_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpy($Rs32.l,$Rt32.h)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110000; @@ -15420,7 +15527,7 @@ def M2_mpyd_acc_lh_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpy($Rs32.l,$Rt32.h):<<1", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110100; @@ -15431,7 +15538,7 @@ def M2_mpyd_acc_ll_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpy($Rs32.l,$Rt32.l)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110000; @@ -15442,7 +15549,7 @@ def M2_mpyd_acc_ll_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpy($Rs32.l,$Rt32.l):<<1", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110100; @@ -15453,7 +15560,7 @@ def M2_mpyd_hh_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.h,$Rt32.h)", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100000; @@ -15463,7 +15570,7 @@ def M2_mpyd_hh_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.h,$Rt32.h):<<1", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100100; @@ -15473,7 +15580,7 @@ def M2_mpyd_hl_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.h,$Rt32.l)", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100000; @@ -15483,7 +15590,7 @@ def M2_mpyd_hl_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.h,$Rt32.l):<<1", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100100; @@ -15493,7 +15600,7 @@ def M2_mpyd_lh_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.l,$Rt32.h)", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100000; @@ -15503,7 +15610,7 @@ def M2_mpyd_lh_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.l,$Rt32.h):<<1", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100100; @@ -15513,7 +15620,7 @@ def M2_mpyd_ll_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.l,$Rt32.l)", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100000; @@ -15523,7 +15630,7 @@ def M2_mpyd_ll_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.l,$Rt32.l):<<1", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100100; @@ -15533,7 +15640,7 @@ def M2_mpyd_nac_hh_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpy($Rs32.h,$Rt32.h)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110001; @@ -15544,7 +15651,7 @@ def M2_mpyd_nac_hh_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpy($Rs32.h,$Rt32.h):<<1", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110101; @@ -15555,7 +15662,7 @@ def M2_mpyd_nac_hl_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpy($Rs32.h,$Rt32.l)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110001; @@ -15566,7 +15673,7 @@ def M2_mpyd_nac_hl_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpy($Rs32.h,$Rt32.l):<<1", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110101; @@ -15577,7 +15684,7 @@ def M2_mpyd_nac_lh_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpy($Rs32.l,$Rt32.h)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110001; @@ -15588,7 +15695,7 @@ def M2_mpyd_nac_lh_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpy($Rs32.l,$Rt32.h):<<1", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110101; @@ -15599,7 +15706,7 @@ def M2_mpyd_nac_ll_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpy($Rs32.l,$Rt32.l)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110001; @@ -15610,7 +15717,7 @@ def M2_mpyd_nac_ll_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpy($Rs32.l,$Rt32.l):<<1", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110101; @@ -15621,7 +15728,7 @@ def M2_mpyd_rnd_hh_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.h,$Rt32.h):rnd", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100001; @@ -15631,7 +15738,7 @@ def M2_mpyd_rnd_hh_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100101; @@ -15641,7 +15748,7 @@ def M2_mpyd_rnd_hl_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.h,$Rt32.l):rnd", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100001; @@ -15651,7 +15758,7 @@ def M2_mpyd_rnd_hl_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100101; @@ -15661,7 +15768,7 @@ def M2_mpyd_rnd_lh_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.l,$Rt32.h):rnd", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100001; @@ -15671,7 +15778,7 @@ def M2_mpyd_rnd_lh_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100101; @@ -15681,7 +15788,7 @@ def M2_mpyd_rnd_ll_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.l,$Rt32.l):rnd", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100001; @@ -15691,7 +15798,7 @@ def M2_mpyd_rnd_ll_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100101; @@ -15701,7 +15808,7 @@ def M2_mpyi : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpyi($Rs32,$Rt32)", -tc_bafaade3, TypeM>, Enc_5ab2be, ImmRegRel { +tc_c21d7447, TypeM>, Enc_5ab2be, ImmRegRel { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101000; @@ -15715,7 +15822,7 @@ def M2_mpysin : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u8_0Imm:$Ii), "$Rd32 = -mpyi($Rs32,#$Ii)", -tc_c8ce0b5c, TypeM>, Enc_b8c967 { +tc_38382228, TypeM>, Enc_b8c967 { let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100000100; let hasNewValue = 1; @@ -15726,7 +15833,7 @@ def M2_mpysip : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u32_0Imm:$Ii), "$Rd32 = +mpyi($Rs32,#$Ii)", -tc_c8ce0b5c, TypeM>, Enc_b8c967 { +tc_38382228, TypeM>, Enc_b8c967 { let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100000000; let hasNewValue = 1; @@ -15742,7 +15849,7 @@ def M2_mpysmi : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, m32_0Imm:$Ii), "$Rd32 = mpyi($Rs32,#$Ii)", -tc_c8ce0b5c, TypeM>, ImmRegRel { +tc_38382228, TypeM>, ImmRegRel { let hasNewValue = 1; let opNewValue = 0; let CextOpcode = "M2_mpyi"; @@ -15758,7 +15865,7 @@ def M2_mpysu_up : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpysu($Rs32,$Rt32)", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101011; @@ -15770,7 +15877,7 @@ def M2_mpyu_acc_hh_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpyu($Rs32.h,$Rt32.h)", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110010; @@ -15783,7 +15890,7 @@ def M2_mpyu_acc_hh_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpyu($Rs32.h,$Rt32.h):<<1", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110110; @@ -15796,7 +15903,7 @@ def M2_mpyu_acc_hl_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpyu($Rs32.h,$Rt32.l)", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110010; @@ -15809,7 +15916,7 @@ def M2_mpyu_acc_hl_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpyu($Rs32.h,$Rt32.l):<<1", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110110; @@ -15822,7 +15929,7 @@ def M2_mpyu_acc_lh_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpyu($Rs32.l,$Rt32.h)", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110010; @@ -15835,7 +15942,7 @@ def M2_mpyu_acc_lh_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpyu($Rs32.l,$Rt32.h):<<1", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110110; @@ -15848,7 +15955,7 @@ def M2_mpyu_acc_ll_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpyu($Rs32.l,$Rt32.l)", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110010; @@ -15861,7 +15968,7 @@ def M2_mpyu_acc_ll_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpyu($Rs32.l,$Rt32.l):<<1", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110110; @@ -15874,7 +15981,7 @@ def M2_mpyu_hh_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpyu($Rs32.h,$Rt32.h)", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100010; @@ -15886,7 +15993,7 @@ def M2_mpyu_hh_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpyu($Rs32.h,$Rt32.h):<<1", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100110; @@ -15898,7 +16005,7 @@ def M2_mpyu_hl_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpyu($Rs32.h,$Rt32.l)", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100010; @@ -15910,7 +16017,7 @@ def M2_mpyu_hl_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpyu($Rs32.h,$Rt32.l):<<1", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100110; @@ -15922,7 +16029,7 @@ def M2_mpyu_lh_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpyu($Rs32.l,$Rt32.h)", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100010; @@ -15934,7 +16041,7 @@ def M2_mpyu_lh_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpyu($Rs32.l,$Rt32.h):<<1", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100110; @@ -15946,7 +16053,7 @@ def M2_mpyu_ll_s0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpyu($Rs32.l,$Rt32.l)", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100010; @@ -15958,7 +16065,7 @@ def M2_mpyu_ll_s1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpyu($Rs32.l,$Rt32.l):<<1", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101100110; @@ -15970,7 +16077,7 @@ def M2_mpyu_nac_hh_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpyu($Rs32.h,$Rt32.h)", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110011; @@ -15983,7 +16090,7 @@ def M2_mpyu_nac_hh_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpyu($Rs32.h,$Rt32.h):<<1", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110111; @@ -15996,7 +16103,7 @@ def M2_mpyu_nac_hl_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpyu($Rs32.h,$Rt32.l)", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110011; @@ -16009,7 +16116,7 @@ def M2_mpyu_nac_hl_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpyu($Rs32.h,$Rt32.l):<<1", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110111; @@ -16022,7 +16129,7 @@ def M2_mpyu_nac_lh_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpyu($Rs32.l,$Rt32.h)", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110011; @@ -16035,7 +16142,7 @@ def M2_mpyu_nac_lh_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpyu($Rs32.l,$Rt32.h):<<1", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110111; @@ -16048,7 +16155,7 @@ def M2_mpyu_nac_ll_s0 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpyu($Rs32.l,$Rt32.l)", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110011; @@ -16061,7 +16168,7 @@ def M2_mpyu_nac_ll_s1 : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpyu($Rs32.l,$Rt32.l):<<1", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101110111; @@ -16074,7 +16181,7 @@ def M2_mpyu_up : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpyu($Rs32,$Rt32)", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101010; @@ -16086,7 +16193,7 @@ def M2_mpyud_acc_hh_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpyu($Rs32.h,$Rt32.h)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110010; @@ -16097,7 +16204,7 @@ def M2_mpyud_acc_hh_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpyu($Rs32.h,$Rt32.h):<<1", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110110; @@ -16108,7 +16215,7 @@ def M2_mpyud_acc_hl_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpyu($Rs32.h,$Rt32.l)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110010; @@ -16119,7 +16226,7 @@ def M2_mpyud_acc_hl_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpyu($Rs32.h,$Rt32.l):<<1", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110110; @@ -16130,7 +16237,7 @@ def M2_mpyud_acc_lh_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpyu($Rs32.l,$Rt32.h)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110010; @@ -16141,7 +16248,7 @@ def M2_mpyud_acc_lh_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpyu($Rs32.l,$Rt32.h):<<1", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110110; @@ -16152,7 +16259,7 @@ def M2_mpyud_acc_ll_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpyu($Rs32.l,$Rt32.l)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110010; @@ -16163,7 +16270,7 @@ def M2_mpyud_acc_ll_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += mpyu($Rs32.l,$Rt32.l):<<1", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110110; @@ -16174,7 +16281,7 @@ def M2_mpyud_hh_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpyu($Rs32.h,$Rt32.h)", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100010; @@ -16184,7 +16291,7 @@ def M2_mpyud_hh_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpyu($Rs32.h,$Rt32.h):<<1", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100110; @@ -16194,7 +16301,7 @@ def M2_mpyud_hl_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpyu($Rs32.h,$Rt32.l)", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100010; @@ -16204,7 +16311,7 @@ def M2_mpyud_hl_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpyu($Rs32.h,$Rt32.l):<<1", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100110; @@ -16214,7 +16321,7 @@ def M2_mpyud_lh_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpyu($Rs32.l,$Rt32.h)", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100010; @@ -16224,7 +16331,7 @@ def M2_mpyud_lh_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpyu($Rs32.l,$Rt32.h):<<1", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100110; @@ -16234,7 +16341,7 @@ def M2_mpyud_ll_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpyu($Rs32.l,$Rt32.l)", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100010; @@ -16244,7 +16351,7 @@ def M2_mpyud_ll_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = mpyu($Rs32.l,$Rt32.l):<<1", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100100110; @@ -16254,7 +16361,7 @@ def M2_mpyud_nac_hh_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpyu($Rs32.h,$Rt32.h)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110011; @@ -16265,7 +16372,7 @@ def M2_mpyud_nac_hh_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpyu($Rs32.h,$Rt32.h):<<1", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110111; @@ -16276,7 +16383,7 @@ def M2_mpyud_nac_hl_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpyu($Rs32.h,$Rt32.l)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110011; @@ -16287,7 +16394,7 @@ def M2_mpyud_nac_hl_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpyu($Rs32.h,$Rt32.l):<<1", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110111; @@ -16298,7 +16405,7 @@ def M2_mpyud_nac_lh_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpyu($Rs32.l,$Rt32.h)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110011; @@ -16309,7 +16416,7 @@ def M2_mpyud_nac_lh_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpyu($Rs32.l,$Rt32.h):<<1", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110111; @@ -16320,7 +16427,7 @@ def M2_mpyud_nac_ll_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpyu($Rs32.l,$Rt32.l)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110011; @@ -16331,7 +16438,7 @@ def M2_mpyud_nac_ll_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 -= mpyu($Rs32.l,$Rt32.l):<<1", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100110111; @@ -16342,7 +16449,7 @@ def M2_mpyui : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = mpyui($Rs32,$Rt32)", -tc_bafaade3, TypeM> { +tc_c21d7447, TypeM> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -16352,7 +16459,7 @@ def M2_nacci : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= add($Rs32,$Rt32)", -tc_f675fee8, TypeM>, Enc_2ae154 { +tc_2c13e7f5, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111100; @@ -16366,7 +16473,7 @@ def M2_naccii : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii), "$Rx32 -= add($Rs32,#$Ii)", -tc_f675fee8, TypeM>, Enc_c90aca { +tc_2c13e7f5, TypeM>, Enc_c90aca { let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100010100; let hasNewValue = 1; @@ -16384,7 +16491,7 @@ def M2_subacc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rt32, IntRegs:$Rs32), "$Rx32 += sub($Rt32,$Rs32)", -tc_f675fee8, TypeM>, Enc_a568d4 { +tc_2c13e7f5, TypeM>, Enc_a568d4 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111000; @@ -16398,7 +16505,7 @@ def M2_vabsdiffh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vabsdiffh($Rtt32,$Rss32)", -tc_002cb246, TypeM>, Enc_ea23e4 { +tc_0dfac0a7, TypeM>, Enc_ea23e4 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000011; @@ -16408,7 +16515,7 @@ def M2_vabsdiffw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vabsdiffw($Rtt32,$Rss32)", -tc_002cb246, TypeM>, Enc_ea23e4 { +tc_0dfac0a7, TypeM>, Enc_ea23e4 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000001; @@ -16418,7 +16525,7 @@ def M2_vcmac_s0_sat_i : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vcmpyi($Rss32,$Rtt32):sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010010; @@ -16430,7 +16537,7 @@ def M2_vcmac_s0_sat_r : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vcmpyr($Rss32,$Rtt32):sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010001; @@ -16442,7 +16549,7 @@ def M2_vcmpy_s0_sat_i : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vcmpyi($Rss32,$Rtt32):sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000010; @@ -16453,7 +16560,7 @@ def M2_vcmpy_s0_sat_r : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vcmpyr($Rss32,$Rtt32):sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000001; @@ -16464,7 +16571,7 @@ def M2_vcmpy_s1_sat_i : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vcmpyi($Rss32,$Rtt32):<<1:sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000110; @@ -16475,7 +16582,7 @@ def M2_vcmpy_s1_sat_r : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vcmpyr($Rss32,$Rtt32):<<1:sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000101; @@ -16486,7 +16593,7 @@ def M2_vdmacs_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vdmpy($Rss32,$Rtt32):sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010000; @@ -16498,7 +16605,7 @@ def M2_vdmacs_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vdmpy($Rss32,$Rtt32):<<1:sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010100; @@ -16510,7 +16617,7 @@ def M2_vdmpyrs_s0 : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rd32 = vdmpy($Rss32,$Rtt32):rnd:sat", -tc_bafaade3, TypeM>, Enc_d2216a { +tc_c21d7447, TypeM>, Enc_d2216a { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101001000; @@ -16523,7 +16630,7 @@ def M2_vdmpyrs_s1 : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rd32 = vdmpy($Rss32,$Rtt32):<<1:rnd:sat", -tc_bafaade3, TypeM>, Enc_d2216a { +tc_c21d7447, TypeM>, Enc_d2216a { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101001100; @@ -16536,7 +16643,7 @@ def M2_vdmpys_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vdmpy($Rss32,$Rtt32):sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000000; @@ -16547,7 +16654,7 @@ def M2_vdmpys_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vdmpy($Rss32,$Rtt32):<<1:sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000100; @@ -16558,7 +16665,7 @@ def M2_vmac2 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += vmpyh($Rs32,$Rt32)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111001; @@ -16569,7 +16676,7 @@ def M2_vmac2es : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpyeh($Rss32,$Rtt32)", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010001; @@ -16580,7 +16687,7 @@ def M2_vmac2es_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpyeh($Rss32,$Rtt32):sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010000; @@ -16592,7 +16699,7 @@ def M2_vmac2es_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vmpyeh($Rss32,$Rtt32):<<1:sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010100; @@ -16604,7 +16711,7 @@ def M2_vmac2s_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += vmpyh($Rs32,$Rt32):sat", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111000; @@ -16616,7 +16723,7 @@ def M2_vmac2s_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += vmpyh($Rs32,$Rt32):<<1:sat", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111100; @@ -16628,7 +16735,7 @@ def M2_vmac2su_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += vmpyhsu($Rs32,$Rt32):sat", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111011; @@ -16640,7 +16747,7 @@ def M2_vmac2su_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += vmpyhsu($Rs32,$Rt32):<<1:sat", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111111; @@ -16652,7 +16759,7 @@ def M2_vmpy2es_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpyeh($Rss32,$Rtt32):sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000000; @@ -16663,7 +16770,7 @@ def M2_vmpy2es_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vmpyeh($Rss32,$Rtt32):<<1:sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000100; @@ -16674,7 +16781,7 @@ def M2_vmpy2s_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = vmpyh($Rs32,$Rt32):sat", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101000; @@ -16685,7 +16792,7 @@ def M2_vmpy2s_s0pack : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = vmpyh($Rs32,$Rt32):rnd:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101001; @@ -16698,7 +16805,7 @@ def M2_vmpy2s_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = vmpyh($Rs32,$Rt32):<<1:sat", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101100; @@ -16709,7 +16816,7 @@ def M2_vmpy2s_s1pack : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = vmpyh($Rs32,$Rt32):<<1:rnd:sat", -tc_bafaade3, TypeM>, Enc_5ab2be { +tc_c21d7447, TypeM>, Enc_5ab2be { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101101101; @@ -16722,7 +16829,7 @@ def M2_vmpy2su_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = vmpyhsu($Rs32,$Rt32):sat", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101000; @@ -16733,7 +16840,7 @@ def M2_vmpy2su_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = vmpyhsu($Rs32,$Rt32):<<1:sat", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101100; @@ -16744,7 +16851,7 @@ def M2_vraddh : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rd32 = vraddh($Rss32,$Rtt32)", -tc_bafaade3, TypeM>, Enc_d2216a { +tc_c21d7447, TypeM>, Enc_d2216a { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101001001; @@ -16756,7 +16863,7 @@ def M2_vradduh : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rd32 = vradduh($Rss32,$Rtt32)", -tc_bafaade3, TypeM>, Enc_d2216a { +tc_c21d7447, TypeM>, Enc_d2216a { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101001000; @@ -16768,7 +16875,7 @@ def M2_vrcmaci_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrcmpyi($Rss32,$Rtt32)", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010000; @@ -16779,7 +16886,7 @@ def M2_vrcmaci_s0c : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrcmpyi($Rss32,$Rtt32*)", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010010; @@ -16790,7 +16897,7 @@ def M2_vrcmacr_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrcmpyr($Rss32,$Rtt32)", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010000; @@ -16801,7 +16908,7 @@ def M2_vrcmacr_s0c : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrcmpyr($Rss32,$Rtt32*)", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010011; @@ -16812,7 +16919,7 @@ def M2_vrcmpyi_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrcmpyi($Rss32,$Rtt32)", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000000; @@ -16822,7 +16929,7 @@ def M2_vrcmpyi_s0c : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrcmpyi($Rss32,$Rtt32*)", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000010; @@ -16832,7 +16939,7 @@ def M2_vrcmpyr_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrcmpyr($Rss32,$Rtt32)", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000000; @@ -16842,7 +16949,7 @@ def M2_vrcmpyr_s0c : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrcmpyr($Rss32,$Rtt32*)", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000011; @@ -16852,7 +16959,7 @@ def M2_vrcmpys_acc_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 += vrcmpys($Rss32,$Rt32):<<1:sat", -tc_d773585a, TypeM> { +tc_7f8ae742, TypeM> { let isPseudo = 1; let Constraints = "$Rxx32 = $Rxx32in"; } @@ -16860,7 +16967,7 @@ def M2_vrcmpys_acc_s1_h : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrcmpys($Rss32,$Rtt32):<<1:sat:raw:hi", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010101; @@ -16872,7 +16979,7 @@ def M2_vrcmpys_acc_s1_l : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrcmpys($Rss32,$Rtt32):<<1:sat:raw:lo", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010111; @@ -16884,14 +16991,14 @@ def M2_vrcmpys_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = vrcmpys($Rss32,$Rt32):<<1:sat", -tc_bafaade3, TypeM> { +tc_c21d7447, TypeM> { let isPseudo = 1; } def M2_vrcmpys_s1_h : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrcmpys($Rss32,$Rtt32):<<1:sat:raw:hi", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000101; @@ -16902,7 +17009,7 @@ def M2_vrcmpys_s1_l : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrcmpys($Rss32,$Rtt32):<<1:sat:raw:lo", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000111; @@ -16913,7 +17020,7 @@ def M2_vrcmpys_s1rp : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rd32 = vrcmpys($Rss32,$Rt32):<<1:rnd:sat", -tc_bafaade3, TypeM> { +tc_c21d7447, TypeM> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -16922,7 +17029,7 @@ def M2_vrcmpys_s1rp_h : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rd32 = vrcmpys($Rss32,$Rtt32):<<1:rnd:sat:raw:hi", -tc_bafaade3, TypeM>, Enc_d2216a { +tc_c21d7447, TypeM>, Enc_d2216a { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101001101; @@ -16935,7 +17042,7 @@ def M2_vrcmpys_s1rp_l : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rd32 = vrcmpys($Rss32,$Rtt32):<<1:rnd:sat:raw:lo", -tc_bafaade3, TypeM>, Enc_d2216a { +tc_c21d7447, TypeM>, Enc_d2216a { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101001101; @@ -16948,7 +17055,7 @@ def M2_vrmac_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrmpyh($Rss32,$Rtt32)", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010000; @@ -16959,7 +17066,7 @@ def M2_vrmpy_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrmpyh($Rss32,$Rtt32)", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000000; @@ -16969,7 +17076,7 @@ def M2_xor_xacc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 ^= xor($Rs32,$Rt32)", -tc_f429765c, TypeM>, Enc_2ae154 { +tc_a4e22bbd, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111100; @@ -16983,7 +17090,7 @@ def M4_and_and : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 &= and($Rs32,$Rt32)", -tc_f429765c, TypeM>, Enc_2ae154 { +tc_a4e22bbd, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111010; @@ -16997,7 +17104,7 @@ def M4_and_andn : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 &= and($Rs32,~$Rt32)", -tc_f429765c, TypeM>, Enc_2ae154 { +tc_a4e22bbd, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111001; @@ -17011,7 +17118,7 @@ def M4_and_or : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 &= or($Rs32,$Rt32)", -tc_f429765c, TypeM>, Enc_2ae154 { +tc_a4e22bbd, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111010; @@ -17025,7 +17132,7 @@ def M4_and_xor : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 &= xor($Rs32,$Rt32)", -tc_f429765c, TypeM>, Enc_2ae154 { +tc_a4e22bbd, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111010; @@ -17039,7 +17146,7 @@ def M4_cmpyi_wh : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rd32 = cmpyiwh($Rss32,$Rt32):<<1:rnd:sat", -tc_bafaade3, TypeS_3op>, Enc_3d5b28 { +tc_c21d7447, TypeS_3op>, Enc_3d5b28 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000101000; @@ -17052,7 +17159,7 @@ def M4_cmpyi_whc : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rd32 = cmpyiwh($Rss32,$Rt32*):<<1:rnd:sat", -tc_bafaade3, TypeS_3op>, Enc_3d5b28 { +tc_c21d7447, TypeS_3op>, Enc_3d5b28 { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000101000; @@ -17065,7 +17172,7 @@ def M4_cmpyr_wh : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rd32 = cmpyrwh($Rss32,$Rt32):<<1:rnd:sat", -tc_bafaade3, TypeS_3op>, Enc_3d5b28 { +tc_c21d7447, TypeS_3op>, Enc_3d5b28 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000101000; @@ -17078,7 +17185,7 @@ def M4_cmpyr_whc : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rd32 = cmpyrwh($Rss32,$Rt32*):<<1:rnd:sat", -tc_bafaade3, TypeS_3op>, Enc_3d5b28 { +tc_c21d7447, TypeS_3op>, Enc_3d5b28 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000101000; @@ -17091,7 +17198,7 @@ def M4_mac_up_s1_sat : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += mpy($Rs32,$Rt32):<<1:sat", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111011; @@ -17106,7 +17213,7 @@ def M4_mpyri_addi : HInst< (outs IntRegs:$Rd32), (ins u32_0Imm:$Ii, IntRegs:$Rs32, u6_0Imm:$II), "$Rd32 = add(#$Ii,mpyi($Rs32,#$II))", -tc_05d3a09b, TypeALU64>, Enc_322e1b, ImmRegRel { +tc_a154b476, TypeALU64>, Enc_322e1b, Requires<[UseCompound]>, ImmRegRel { let Inst{31-24} = 0b11011000; let hasNewValue = 1; let opNewValue = 0; @@ -17122,7 +17229,7 @@ def M4_mpyri_addr : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Ru32, IntRegs:$Rs32, u32_0Imm:$Ii), "$Rd32 = add($Ru32,mpyi($Rs32,#$Ii))", -tc_05d3a09b, TypeALU64>, Enc_420cf3, ImmRegRel { +tc_a154b476, TypeALU64>, Enc_420cf3, Requires<[UseCompound]>, ImmRegRel { let Inst{31-23} = 0b110111111; let hasNewValue = 1; let opNewValue = 0; @@ -17139,7 +17246,7 @@ def M4_mpyri_addr_u2 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Ru32, u6_2Imm:$Ii, IntRegs:$Rs32), "$Rd32 = add($Ru32,mpyi(#$Ii,$Rs32))", -tc_1a2fd869, TypeALU64>, Enc_277737 { +tc_503ce0f3, TypeALU64>, Enc_277737, Requires<[UseCompound]> { let Inst{31-23} = 0b110111110; let hasNewValue = 1; let opNewValue = 0; @@ -17149,7 +17256,7 @@ def M4_mpyrr_addi : HInst< (outs IntRegs:$Rd32), (ins u32_0Imm:$Ii, IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = add(#$Ii,mpyi($Rs32,$Rt32))", -tc_d773585a, TypeALU64>, Enc_a7b8e8, ImmRegRel { +tc_7f8ae742, TypeALU64>, Enc_a7b8e8, Requires<[UseCompound]>, ImmRegRel { let Inst{31-23} = 0b110101110; let hasNewValue = 1; let opNewValue = 0; @@ -17166,7 +17273,7 @@ def M4_mpyrr_addr : HInst< (outs IntRegs:$Ry32), (ins IntRegs:$Ru32, IntRegs:$Ry32in, IntRegs:$Rs32), "$Ry32 = add($Ru32,mpyi($Ry32in,$Rs32))", -tc_d773585a, TypeM>, Enc_7f1a05, ImmRegRel { +tc_7f8ae742, TypeM>, Enc_7f1a05, Requires<[UseCompound]>, ImmRegRel { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100011000; @@ -17181,7 +17288,7 @@ def M4_nac_up_s1_sat : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= mpy($Rs32,$Rt32):<<1:sat", -tc_d773585a, TypeM>, Enc_2ae154 { +tc_7f8ae742, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111011; @@ -17196,7 +17303,7 @@ def M4_or_and : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 |= and($Rs32,$Rt32)", -tc_f429765c, TypeM>, Enc_2ae154 { +tc_a4e22bbd, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111010; @@ -17210,7 +17317,7 @@ def M4_or_andn : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 |= and($Rs32,~$Rt32)", -tc_f429765c, TypeM>, Enc_2ae154 { +tc_a4e22bbd, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111001; @@ -17224,7 +17331,7 @@ def M4_or_or : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 |= or($Rs32,$Rt32)", -tc_f429765c, TypeM>, Enc_2ae154 { +tc_a4e22bbd, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111110; @@ -17238,7 +17345,7 @@ def M4_or_xor : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 |= xor($Rs32,$Rt32)", -tc_f429765c, TypeM>, Enc_2ae154 { +tc_a4e22bbd, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111110; @@ -17252,7 +17359,7 @@ def M4_pmpyw : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = pmpyw($Rs32,$Rt32)", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101010; @@ -17262,7 +17369,7 @@ def M4_pmpyw_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 ^= pmpyw($Rs32,$Rt32)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111001; @@ -17273,7 +17380,7 @@ def M4_vpmpyh : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = vpmpyh($Rs32,$Rt32)", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101110; @@ -17283,7 +17390,7 @@ def M4_vpmpyh_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 ^= vpmpyh($Rs32,$Rt32)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111101; @@ -17294,7 +17401,7 @@ def M4_vrmpyeh_acc_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrmpyweh($Rss32,$Rtt32)", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010001; @@ -17305,7 +17412,7 @@ def M4_vrmpyeh_acc_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrmpyweh($Rss32,$Rtt32):<<1", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010101; @@ -17316,7 +17423,7 @@ def M4_vrmpyeh_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrmpyweh($Rss32,$Rtt32)", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000010; @@ -17326,7 +17433,7 @@ def M4_vrmpyeh_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrmpyweh($Rss32,$Rtt32):<<1", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000110; @@ -17336,7 +17443,7 @@ def M4_vrmpyoh_acc_s0 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrmpywoh($Rss32,$Rtt32)", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010011; @@ -17347,7 +17454,7 @@ def M4_vrmpyoh_acc_s1 : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrmpywoh($Rss32,$Rtt32):<<1", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010111; @@ -17358,7 +17465,7 @@ def M4_vrmpyoh_s0 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrmpywoh($Rss32,$Rtt32)", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000001; @@ -17368,7 +17475,7 @@ def M4_vrmpyoh_s1 : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrmpywoh($Rss32,$Rtt32):<<1", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000101; @@ -17378,7 +17485,7 @@ def M4_xor_and : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 ^= and($Rs32,$Rt32)", -tc_f429765c, TypeM>, Enc_2ae154 { +tc_a4e22bbd, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111110; @@ -17392,7 +17499,7 @@ def M4_xor_andn : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 ^= and($Rs32,~$Rt32)", -tc_f429765c, TypeM>, Enc_2ae154 { +tc_a4e22bbd, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111001; @@ -17406,7 +17513,7 @@ def M4_xor_or : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 ^= or($Rs32,$Rt32)", -tc_f429765c, TypeM>, Enc_2ae154 { +tc_a4e22bbd, TypeM>, Enc_2ae154 { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101111110; @@ -17420,7 +17527,7 @@ def M4_xor_xacc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 ^= xor($Rss32,$Rtt32)", -tc_f429765c, TypeS_3op>, Enc_88c16c { +tc_a4e22bbd, TypeS_3op>, Enc_88c16c { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001010100; @@ -17431,7 +17538,7 @@ def M5_vdmacbsu : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vdmpybsu($Rss32,$Rtt32):sat", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010001; @@ -17443,7 +17550,7 @@ def M5_vdmpybsu : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vdmpybsu($Rss32,$Rtt32):sat", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000101; @@ -17454,7 +17561,7 @@ def M5_vmacbsu : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += vmpybsu($Rs32,$Rt32)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111110; @@ -17465,7 +17572,7 @@ def M5_vmacbuu : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rxx32 += vmpybu($Rs32,$Rt32)", -tc_d773585a, TypeM>, Enc_61f0b0 { +tc_7f8ae742, TypeM>, Enc_61f0b0 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100111100; @@ -17476,7 +17583,7 @@ def M5_vmpybsu : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = vmpybsu($Rs32,$Rt32)", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101010; @@ -17486,7 +17593,7 @@ def M5_vmpybuu : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = vmpybu($Rs32,$Rt32)", -tc_bafaade3, TypeM>, Enc_be32a5 { +tc_c21d7447, TypeM>, Enc_be32a5 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11100101100; @@ -17496,7 +17603,7 @@ def M5_vrmacbsu : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrmpybsu($Rss32,$Rtt32)", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010110; @@ -17507,7 +17614,7 @@ def M5_vrmacbuu : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 += vrmpybu($Rss32,$Rtt32)", -tc_d773585a, TypeM>, Enc_88c16c { +tc_7f8ae742, TypeM>, Enc_88c16c { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101010100; @@ -17518,7 +17625,7 @@ def M5_vrmpybsu : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrmpybsu($Rss32,$Rtt32)", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000110; @@ -17528,7 +17635,7 @@ def M5_vrmpybuu : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vrmpybu($Rss32,$Rtt32)", -tc_bafaade3, TypeM>, Enc_a56825 { +tc_c21d7447, TypeM>, Enc_a56825 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000100; @@ -17538,7 +17645,7 @@ def M6_vabsdiffb : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vabsdiffb($Rtt32,$Rss32)", -tc_9461ff31, TypeM>, Enc_ea23e4, Requires<[HasV62]> { +tc_9b3c0462, TypeM>, Enc_ea23e4, Requires<[HasV62]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000111; @@ -17548,17 +17655,222 @@ def M6_vabsdiffub : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = vabsdiffub($Rtt32,$Rss32)", -tc_9461ff31, TypeM>, Enc_ea23e4, Requires<[HasV62]> { +tc_9b3c0462, TypeM>, Enc_ea23e4, Requires<[HasV62]> { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11101000101; let prefersSlot3 = 1; } +def M7_dcmpyiw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = cmpyiw($Rss32,$Rtt32)", +tc_5a4b5e58, TypeM>, Enc_a56825, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000011; +let prefersSlot3 = 1; +} +def M7_dcmpyiw_acc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += cmpyiw($Rss32,$Rtt32)", +tc_197dce51, TypeM>, Enc_88c16c, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010011; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M7_dcmpyiwc : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = cmpyiw($Rss32,$Rtt32*)", +tc_5a4b5e58, TypeM>, Enc_a56825, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000111; +let prefersSlot3 = 1; +} +def M7_dcmpyiwc_acc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += cmpyiw($Rss32,$Rtt32*)", +tc_197dce51, TypeM>, Enc_88c16c, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M7_dcmpyrw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = cmpyrw($Rss32,$Rtt32)", +tc_5a4b5e58, TypeM>, Enc_a56825, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000100; +let prefersSlot3 = 1; +} +def M7_dcmpyrw_acc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += cmpyrw($Rss32,$Rtt32)", +tc_197dce51, TypeM>, Enc_88c16c, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010100; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M7_dcmpyrwc : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = cmpyrw($Rss32,$Rtt32*)", +tc_5a4b5e58, TypeM>, Enc_a56825, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000110; +let prefersSlot3 = 1; +} +def M7_dcmpyrwc_acc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += cmpyrw($Rss32,$Rtt32*)", +tc_197dce51, TypeM>, Enc_88c16c, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010110; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M7_vdmpy : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vdmpyw($Rss32,$Rtt32)", +tc_5a4b5e58, TypeM>, Requires<[HasV67]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def M7_vdmpy_acc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vdmpyw($Rss32,$Rtt32)", +tc_197dce51, TypeM>, Requires<[HasV67]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M7_wcmpyiw : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rd32 = cmpyiw($Rss32,$Rtt32):<<1:sat", +tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101001001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M7_wcmpyiw_rnd : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rd32 = cmpyiw($Rss32,$Rtt32):<<1:rnd:sat", +tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101001101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M7_wcmpyiwc : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rd32 = cmpyiw($Rss32,$Rtt32*):<<1:sat", +tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101001000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M7_wcmpyiwc_rnd : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rd32 = cmpyiw($Rss32,$Rtt32*):<<1:rnd:sat", +tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101001100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M7_wcmpyrw : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rd32 = cmpyrw($Rss32,$Rtt32):<<1:sat", +tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101001010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M7_wcmpyrw_rnd : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rd32 = cmpyrw($Rss32,$Rtt32):<<1:rnd:sat", +tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101001110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M7_wcmpyrwc : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rd32 = cmpyrw($Rss32,$Rtt32*):<<1:sat", +tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101001011; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M7_wcmpyrwc_rnd : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rd32 = cmpyrw($Rss32,$Rtt32*):<<1:rnd:sat", +tc_5a4b5e58, TypeM>, Enc_d2216a, Requires<[HasV67,UseAudio]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101001111; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} def PS_loadrbabs : HInst< (outs IntRegs:$Rd32), (ins u32_0Imm:$Ii), "$Rd32 = memb(#$Ii)", -tc_c4db48cb, TypeV2LDST>, Enc_25bef0, AddrModeRel { +tc_8a6d0d94, TypeV2LDST>, Enc_25bef0, AddrModeRel { let Inst{24-21} = 0b1000; let Inst{31-27} = 0b01001; let hasNewValue = 1; @@ -17567,8 +17879,8 @@ let addrMode = Absolute; let accessSize = ByteAccess; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrb"; let BaseOpcode = "L4_loadrb_abs"; +let CextOpcode = "L2_loadrb"; let isPredicable = 1; let DecoderNamespace = "MustExtend"; let isExtended = 1; @@ -17581,15 +17893,15 @@ def PS_loadrdabs : HInst< (outs DoubleRegs:$Rdd32), (ins u29_3Imm:$Ii), "$Rdd32 = memd(#$Ii)", -tc_c4db48cb, TypeV2LDST>, Enc_509701, AddrModeRel { +tc_8a6d0d94, TypeV2LDST>, Enc_509701, AddrModeRel { let Inst{24-21} = 0b1110; let Inst{31-27} = 0b01001; let addrMode = Absolute; let accessSize = DoubleWordAccess; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrd"; let BaseOpcode = "L4_loadrd_abs"; +let CextOpcode = "L2_loadrd"; let isPredicable = 1; let DecoderNamespace = "MustExtend"; let isExtended = 1; @@ -17602,7 +17914,7 @@ def PS_loadrhabs : HInst< (outs IntRegs:$Rd32), (ins u31_1Imm:$Ii), "$Rd32 = memh(#$Ii)", -tc_c4db48cb, TypeV2LDST>, Enc_8df4be, AddrModeRel { +tc_8a6d0d94, TypeV2LDST>, Enc_8df4be, AddrModeRel { let Inst{24-21} = 0b1010; let Inst{31-27} = 0b01001; let hasNewValue = 1; @@ -17611,8 +17923,8 @@ let addrMode = Absolute; let accessSize = HalfWordAccess; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrh"; let BaseOpcode = "L4_loadrh_abs"; +let CextOpcode = "L2_loadrh"; let isPredicable = 1; let DecoderNamespace = "MustExtend"; let isExtended = 1; @@ -17625,7 +17937,7 @@ def PS_loadriabs : HInst< (outs IntRegs:$Rd32), (ins u30_2Imm:$Ii), "$Rd32 = memw(#$Ii)", -tc_c4db48cb, TypeV2LDST>, Enc_4f4ed7, AddrModeRel { +tc_8a6d0d94, TypeV2LDST>, Enc_4f4ed7, AddrModeRel { let Inst{24-21} = 0b1100; let Inst{31-27} = 0b01001; let hasNewValue = 1; @@ -17634,8 +17946,8 @@ let addrMode = Absolute; let accessSize = WordAccess; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadri"; let BaseOpcode = "L4_loadri_abs"; +let CextOpcode = "L2_loadri"; let isPredicable = 1; let DecoderNamespace = "MustExtend"; let isExtended = 1; @@ -17648,7 +17960,7 @@ def PS_loadrubabs : HInst< (outs IntRegs:$Rd32), (ins u32_0Imm:$Ii), "$Rd32 = memub(#$Ii)", -tc_c4db48cb, TypeV2LDST>, Enc_25bef0, AddrModeRel { +tc_8a6d0d94, TypeV2LDST>, Enc_25bef0, AddrModeRel { let Inst{24-21} = 0b1001; let Inst{31-27} = 0b01001; let hasNewValue = 1; @@ -17657,8 +17969,8 @@ let addrMode = Absolute; let accessSize = ByteAccess; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadrub"; let BaseOpcode = "L4_loadrub_abs"; +let CextOpcode = "L2_loadrub"; let isPredicable = 1; let DecoderNamespace = "MustExtend"; let isExtended = 1; @@ -17671,7 +17983,7 @@ def PS_loadruhabs : HInst< (outs IntRegs:$Rd32), (ins u31_1Imm:$Ii), "$Rd32 = memuh(#$Ii)", -tc_c4db48cb, TypeV2LDST>, Enc_8df4be, AddrModeRel { +tc_8a6d0d94, TypeV2LDST>, Enc_8df4be, AddrModeRel { let Inst{24-21} = 0b1011; let Inst{31-27} = 0b01001; let hasNewValue = 1; @@ -17680,8 +17992,8 @@ let addrMode = Absolute; let accessSize = HalfWordAccess; let mayLoad = 1; let isExtended = 1; -let CextOpcode = "L2_loadruh"; let BaseOpcode = "L4_loadruh_abs"; +let CextOpcode = "L2_loadruh"; let isPredicable = 1; let DecoderNamespace = "MustExtend"; let isExtended = 1; @@ -17694,15 +18006,15 @@ def PS_storerbabs : HInst< (outs), (ins u32_0Imm:$Ii, IntRegs:$Rt32), "memb(#$Ii) = $Rt32", -tc_0371abea, TypeV2LDST>, Enc_1b64fb, AddrModeRel { +tc_0655b949, TypeV2LDST>, Enc_1b64fb, AddrModeRel { let Inst{24-21} = 0b0000; let Inst{31-27} = 0b01001; let addrMode = Absolute; let accessSize = ByteAccess; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerbabs"; +let CextOpcode = "S2_storerb"; let isPredicable = 1; let isNVStorable = 1; let DecoderNamespace = "MustExtend"; @@ -17716,7 +18028,7 @@ def PS_storerbnewabs : HInst< (outs), (ins u32_0Imm:$Ii, IntRegs:$Nt8), "memb(#$Ii) = $Nt8.new", -tc_5bf126a6, TypeV2LDST>, Enc_ad1831, AddrModeRel { +tc_6e20402a, TypeV2LDST>, Enc_ad1831, AddrModeRel { let Inst{12-11} = 0b00; let Inst{24-21} = 0b0101; let Inst{31-27} = 0b01001; @@ -17727,8 +18039,8 @@ let isNewValue = 1; let isExtended = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerbabs"; +let CextOpcode = "S2_storerb"; let isPredicable = 1; let DecoderNamespace = "MustExtend"; let isExtended = 1; @@ -17742,15 +18054,15 @@ def PS_storerdabs : HInst< (outs), (ins u29_3Imm:$Ii, DoubleRegs:$Rtt32), "memd(#$Ii) = $Rtt32", -tc_0371abea, TypeV2LDST>, Enc_5c124a, AddrModeRel { +tc_0655b949, TypeV2LDST>, Enc_5c124a, AddrModeRel { let Inst{24-21} = 0b0110; let Inst{31-27} = 0b01001; let addrMode = Absolute; let accessSize = DoubleWordAccess; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerd"; let BaseOpcode = "S2_storerdabs"; +let CextOpcode = "S2_storerd"; let isPredicable = 1; let DecoderNamespace = "MustExtend"; let isExtended = 1; @@ -17763,15 +18075,15 @@ def PS_storerfabs : HInst< (outs), (ins u31_1Imm:$Ii, IntRegs:$Rt32), "memh(#$Ii) = $Rt32.h", -tc_0371abea, TypeV2LDST>, Enc_fda92c, AddrModeRel { +tc_0655b949, TypeV2LDST>, Enc_fda92c, AddrModeRel { let Inst{24-21} = 0b0011; let Inst{31-27} = 0b01001; let addrMode = Absolute; let accessSize = HalfWordAccess; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerf"; let BaseOpcode = "S2_storerfabs"; +let CextOpcode = "S2_storerf"; let isPredicable = 1; let DecoderNamespace = "MustExtend"; let isExtended = 1; @@ -17784,15 +18096,15 @@ def PS_storerhabs : HInst< (outs), (ins u31_1Imm:$Ii, IntRegs:$Rt32), "memh(#$Ii) = $Rt32", -tc_0371abea, TypeV2LDST>, Enc_fda92c, AddrModeRel { +tc_0655b949, TypeV2LDST>, Enc_fda92c, AddrModeRel { let Inst{24-21} = 0b0010; let Inst{31-27} = 0b01001; let addrMode = Absolute; let accessSize = HalfWordAccess; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerhabs"; +let CextOpcode = "S2_storerh"; let isPredicable = 1; let isNVStorable = 1; let DecoderNamespace = "MustExtend"; @@ -17806,7 +18118,7 @@ def PS_storerhnewabs : HInst< (outs), (ins u31_1Imm:$Ii, IntRegs:$Nt8), "memh(#$Ii) = $Nt8.new", -tc_5bf126a6, TypeV2LDST>, Enc_bc03e5, AddrModeRel { +tc_6e20402a, TypeV2LDST>, Enc_bc03e5, AddrModeRel { let Inst{12-11} = 0b01; let Inst{24-21} = 0b0101; let Inst{31-27} = 0b01001; @@ -17817,8 +18129,8 @@ let isNewValue = 1; let isExtended = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerhabs"; +let CextOpcode = "S2_storerh"; let isPredicable = 1; let DecoderNamespace = "MustExtend"; let isExtended = 1; @@ -17832,15 +18144,15 @@ def PS_storeriabs : HInst< (outs), (ins u30_2Imm:$Ii, IntRegs:$Rt32), "memw(#$Ii) = $Rt32", -tc_0371abea, TypeV2LDST>, Enc_541f26, AddrModeRel { +tc_0655b949, TypeV2LDST>, Enc_541f26, AddrModeRel { let Inst{24-21} = 0b0100; let Inst{31-27} = 0b01001; let addrMode = Absolute; let accessSize = WordAccess; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeriabs"; +let CextOpcode = "S2_storeri"; let isPredicable = 1; let isNVStorable = 1; let DecoderNamespace = "MustExtend"; @@ -17854,7 +18166,7 @@ def PS_storerinewabs : HInst< (outs), (ins u30_2Imm:$Ii, IntRegs:$Nt8), "memw(#$Ii) = $Nt8.new", -tc_5bf126a6, TypeV2LDST>, Enc_78cbf0, AddrModeRel { +tc_6e20402a, TypeV2LDST>, Enc_78cbf0, AddrModeRel { let Inst{12-11} = 0b10; let Inst{24-21} = 0b0101; let Inst{31-27} = 0b01001; @@ -17865,8 +18177,8 @@ let isNewValue = 1; let isExtended = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeriabs"; +let CextOpcode = "S2_storeri"; let isPredicable = 1; let DecoderNamespace = "MustExtend"; let isExtended = 1; @@ -17876,11 +18188,22 @@ let opExtentBits = 18; let opExtentAlign = 2; let opNewValue = 1; } +def PS_trap1 : HInst< +(outs), +(ins u8_0Imm:$Ii), +"trap1(#$Ii)", +tc_53c851ab, TypeJ>, Enc_a51a9a, Requires<[HasPreV65]> { +let Inst{1-0} = 0b00; +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0101010010000000; +let isSolo = 1; +} def S2_addasl_rrri : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32, u3_0Imm:$Ii), "$Rd32 = addasl($Rt32,$Rs32,#$Ii)", -tc_f675fee8, TypeS_3op>, Enc_47ef61 { +tc_2c13e7f5, TypeS_3op>, Enc_47ef61 { let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000100000; let hasNewValue = 1; @@ -17891,7 +18214,7 @@ def S2_allocframe : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, u11_3Imm:$Ii), "allocframe($Rx32,#$Ii):raw", -tc_b44ecf75, TypeST>, Enc_22c845 { +tc_934753bb, TypeST>, Enc_22c845 { let Inst{13-11} = 0b000; let Inst{31-21} = 0b10100000100; let hasNewValue = 1; @@ -17907,7 +18230,7 @@ def S2_asl_i_p : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rdd32 = asl($Rss32,#$Ii)", -tc_946df596, TypeS_2op>, Enc_5eac98 { +tc_5da50c4b, TypeS_2op>, Enc_5eac98 { let Inst{7-5} = 0b010; let Inst{31-21} = 0b10000000000; } @@ -17915,7 +18238,7 @@ def S2_asl_i_p_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 += asl($Rss32,#$Ii)", -tc_f675fee8, TypeS_2op>, Enc_70fb07 { +tc_2c13e7f5, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b110; let Inst{31-21} = 0b10000010000; let prefersSlot3 = 1; @@ -17925,7 +18248,7 @@ def S2_asl_i_p_and : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 &= asl($Rss32,#$Ii)", -tc_f429765c, TypeS_2op>, Enc_70fb07 { +tc_a4e22bbd, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b010; let Inst{31-21} = 0b10000010010; let prefersSlot3 = 1; @@ -17935,7 +18258,7 @@ def S2_asl_i_p_nac : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 -= asl($Rss32,#$Ii)", -tc_f675fee8, TypeS_2op>, Enc_70fb07 { +tc_2c13e7f5, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b010; let Inst{31-21} = 0b10000010000; let prefersSlot3 = 1; @@ -17945,7 +18268,7 @@ def S2_asl_i_p_or : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 |= asl($Rss32,#$Ii)", -tc_f429765c, TypeS_2op>, Enc_70fb07 { +tc_a4e22bbd, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b110; let Inst{31-21} = 0b10000010010; let prefersSlot3 = 1; @@ -17955,7 +18278,7 @@ def S2_asl_i_p_xacc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 ^= asl($Rss32,#$Ii)", -tc_f429765c, TypeS_2op>, Enc_70fb07 { +tc_a4e22bbd, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b010; let Inst{31-21} = 0b10000010100; let prefersSlot3 = 1; @@ -17965,7 +18288,7 @@ def S2_asl_i_r : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = asl($Rs32,#$Ii)", -tc_946df596, TypeS_2op>, Enc_a05677 { +tc_5da50c4b, TypeS_2op>, Enc_a05677 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001100000; @@ -17976,7 +18299,7 @@ def S2_asl_i_r_acc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 += asl($Rs32,#$Ii)", -tc_f675fee8, TypeS_2op>, Enc_28a2dc { +tc_2c13e7f5, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110000; @@ -17989,7 +18312,7 @@ def S2_asl_i_r_and : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 &= asl($Rs32,#$Ii)", -tc_f429765c, TypeS_2op>, Enc_28a2dc { +tc_a4e22bbd, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110010; @@ -18002,7 +18325,7 @@ def S2_asl_i_r_nac : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 -= asl($Rs32,#$Ii)", -tc_f675fee8, TypeS_2op>, Enc_28a2dc { +tc_2c13e7f5, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110000; @@ -18015,7 +18338,7 @@ def S2_asl_i_r_or : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 |= asl($Rs32,#$Ii)", -tc_f429765c, TypeS_2op>, Enc_28a2dc { +tc_a4e22bbd, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110010; @@ -18028,7 +18351,7 @@ def S2_asl_i_r_sat : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = asl($Rs32,#$Ii):sat", -tc_779080bf, TypeS_2op>, Enc_a05677 { +tc_8a825db2, TypeS_2op>, Enc_a05677 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001100010; @@ -18041,7 +18364,7 @@ def S2_asl_i_r_xacc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 ^= asl($Rs32,#$Ii)", -tc_f429765c, TypeS_2op>, Enc_28a2dc { +tc_a4e22bbd, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110100; @@ -18054,7 +18377,7 @@ def S2_asl_i_vh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u4_0Imm:$Ii), "$Rdd32 = vaslh($Rss32,#$Ii)", -tc_946df596, TypeS_2op>, Enc_12b6e9 { +tc_5da50c4b, TypeS_2op>, Enc_12b6e9 { let Inst{7-5} = 0b010; let Inst{13-12} = 0b00; let Inst{31-21} = 0b10000000100; @@ -18063,7 +18386,7 @@ def S2_asl_i_vw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u5_0Imm:$Ii), "$Rdd32 = vaslw($Rss32,#$Ii)", -tc_946df596, TypeS_2op>, Enc_7e5a82 { +tc_5da50c4b, TypeS_2op>, Enc_7e5a82 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10000000010; @@ -18072,7 +18395,7 @@ def S2_asl_r_p : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = asl($Rss32,$Rt32)", -tc_946df596, TypeS_3op>, Enc_927852 { +tc_5da50c4b, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011100; @@ -18081,7 +18404,7 @@ def S2_asl_r_p_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 += asl($Rss32,$Rt32)", -tc_f675fee8, TypeS_3op>, Enc_1aa186 { +tc_2c13e7f5, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011110; @@ -18092,7 +18415,7 @@ def S2_asl_r_p_and : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 &= asl($Rss32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_1aa186 { +tc_a4e22bbd, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011010; @@ -18103,7 +18426,7 @@ def S2_asl_r_p_nac : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 -= asl($Rss32,$Rt32)", -tc_f675fee8, TypeS_3op>, Enc_1aa186 { +tc_2c13e7f5, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011100; @@ -18114,7 +18437,7 @@ def S2_asl_r_p_or : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 |= asl($Rss32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_1aa186 { +tc_a4e22bbd, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011000; @@ -18125,7 +18448,7 @@ def S2_asl_r_p_xor : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 ^= asl($Rss32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_1aa186 { +tc_a4e22bbd, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011011; @@ -18136,7 +18459,7 @@ def S2_asl_r_r : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = asl($Rs32,$Rt32)", -tc_946df596, TypeS_3op>, Enc_5ab2be { +tc_5da50c4b, TypeS_3op>, Enc_5ab2be { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000110010; @@ -18147,7 +18470,7 @@ def S2_asl_r_r_acc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += asl($Rs32,$Rt32)", -tc_f675fee8, TypeS_3op>, Enc_2ae154 { +tc_2c13e7f5, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100110; @@ -18160,7 +18483,7 @@ def S2_asl_r_r_and : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 &= asl($Rs32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_2ae154 { +tc_a4e22bbd, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100010; @@ -18173,7 +18496,7 @@ def S2_asl_r_r_nac : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= asl($Rs32,$Rt32)", -tc_f675fee8, TypeS_3op>, Enc_2ae154 { +tc_2c13e7f5, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100100; @@ -18186,7 +18509,7 @@ def S2_asl_r_r_or : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 |= asl($Rs32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_2ae154 { +tc_a4e22bbd, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100000; @@ -18199,7 +18522,7 @@ def S2_asl_r_r_sat : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = asl($Rs32,$Rt32):sat", -tc_779080bf, TypeS_3op>, Enc_5ab2be { +tc_8a825db2, TypeS_3op>, Enc_5ab2be { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000110000; @@ -18212,7 +18535,7 @@ def S2_asl_r_vh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = vaslh($Rss32,$Rt32)", -tc_946df596, TypeS_3op>, Enc_927852 { +tc_5da50c4b, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011010; @@ -18221,7 +18544,7 @@ def S2_asl_r_vw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = vaslw($Rss32,$Rt32)", -tc_946df596, TypeS_3op>, Enc_927852 { +tc_5da50c4b, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011000; @@ -18230,7 +18553,7 @@ def S2_asr_i_p : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rdd32 = asr($Rss32,#$Ii)", -tc_946df596, TypeS_2op>, Enc_5eac98 { +tc_5da50c4b, TypeS_2op>, Enc_5eac98 { let Inst{7-5} = 0b000; let Inst{31-21} = 0b10000000000; } @@ -18238,7 +18561,7 @@ def S2_asr_i_p_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 += asr($Rss32,#$Ii)", -tc_f675fee8, TypeS_2op>, Enc_70fb07 { +tc_2c13e7f5, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b100; let Inst{31-21} = 0b10000010000; let prefersSlot3 = 1; @@ -18248,7 +18571,7 @@ def S2_asr_i_p_and : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 &= asr($Rss32,#$Ii)", -tc_f429765c, TypeS_2op>, Enc_70fb07 { +tc_a4e22bbd, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b000; let Inst{31-21} = 0b10000010010; let prefersSlot3 = 1; @@ -18258,7 +18581,7 @@ def S2_asr_i_p_nac : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 -= asr($Rss32,#$Ii)", -tc_f675fee8, TypeS_2op>, Enc_70fb07 { +tc_2c13e7f5, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b000; let Inst{31-21} = 0b10000010000; let prefersSlot3 = 1; @@ -18268,7 +18591,7 @@ def S2_asr_i_p_or : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 |= asr($Rss32,#$Ii)", -tc_f429765c, TypeS_2op>, Enc_70fb07 { +tc_a4e22bbd, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b100; let Inst{31-21} = 0b10000010010; let prefersSlot3 = 1; @@ -18278,7 +18601,7 @@ def S2_asr_i_p_rnd : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rdd32 = asr($Rss32,#$Ii):rnd", -tc_002cb246, TypeS_2op>, Enc_5eac98 { +tc_0dfac0a7, TypeS_2op>, Enc_5eac98 { let Inst{7-5} = 0b111; let Inst{31-21} = 0b10000000110; let prefersSlot3 = 1; @@ -18287,14 +18610,14 @@ def S2_asr_i_p_rnd_goodsyntax : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rdd32 = asrrnd($Rss32,#$Ii)", -tc_002cb246, TypeS_2op> { +tc_0dfac0a7, TypeS_2op> { let isPseudo = 1; } def S2_asr_i_r : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = asr($Rs32,#$Ii)", -tc_946df596, TypeS_2op>, Enc_a05677 { +tc_5da50c4b, TypeS_2op>, Enc_a05677 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001100000; @@ -18305,7 +18628,7 @@ def S2_asr_i_r_acc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 += asr($Rs32,#$Ii)", -tc_f675fee8, TypeS_2op>, Enc_28a2dc { +tc_2c13e7f5, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110000; @@ -18318,7 +18641,7 @@ def S2_asr_i_r_and : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 &= asr($Rs32,#$Ii)", -tc_f429765c, TypeS_2op>, Enc_28a2dc { +tc_a4e22bbd, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110010; @@ -18331,7 +18654,7 @@ def S2_asr_i_r_nac : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 -= asr($Rs32,#$Ii)", -tc_f675fee8, TypeS_2op>, Enc_28a2dc { +tc_2c13e7f5, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110000; @@ -18344,7 +18667,7 @@ def S2_asr_i_r_or : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 |= asr($Rs32,#$Ii)", -tc_f429765c, TypeS_2op>, Enc_28a2dc { +tc_a4e22bbd, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110010; @@ -18357,7 +18680,7 @@ def S2_asr_i_r_rnd : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = asr($Rs32,#$Ii):rnd", -tc_002cb246, TypeS_2op>, Enc_a05677 { +tc_0dfac0a7, TypeS_2op>, Enc_a05677 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001100010; @@ -18369,7 +18692,7 @@ def S2_asr_i_r_rnd_goodsyntax : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = asrrnd($Rs32,#$Ii)", -tc_002cb246, TypeS_2op> { +tc_0dfac0a7, TypeS_2op> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -18378,7 +18701,7 @@ def S2_asr_i_svw_trun : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, u5_0Imm:$Ii), "$Rd32 = vasrw($Rss32,#$Ii)", -tc_4414d8b1, TypeS_2op>, Enc_8dec2e { +tc_f34c1c21, TypeS_2op>, Enc_8dec2e { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001000110; @@ -18390,7 +18713,7 @@ def S2_asr_i_vh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u4_0Imm:$Ii), "$Rdd32 = vasrh($Rss32,#$Ii)", -tc_946df596, TypeS_2op>, Enc_12b6e9 { +tc_5da50c4b, TypeS_2op>, Enc_12b6e9 { let Inst{7-5} = 0b000; let Inst{13-12} = 0b00; let Inst{31-21} = 0b10000000100; @@ -18399,7 +18722,7 @@ def S2_asr_i_vw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u5_0Imm:$Ii), "$Rdd32 = vasrw($Rss32,#$Ii)", -tc_946df596, TypeS_2op>, Enc_7e5a82 { +tc_5da50c4b, TypeS_2op>, Enc_7e5a82 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10000000010; @@ -18408,7 +18731,7 @@ def S2_asr_r_p : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = asr($Rss32,$Rt32)", -tc_946df596, TypeS_3op>, Enc_927852 { +tc_5da50c4b, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011100; @@ -18417,7 +18740,7 @@ def S2_asr_r_p_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 += asr($Rss32,$Rt32)", -tc_f675fee8, TypeS_3op>, Enc_1aa186 { +tc_2c13e7f5, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011110; @@ -18428,7 +18751,7 @@ def S2_asr_r_p_and : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 &= asr($Rss32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_1aa186 { +tc_a4e22bbd, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011010; @@ -18439,7 +18762,7 @@ def S2_asr_r_p_nac : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 -= asr($Rss32,$Rt32)", -tc_f675fee8, TypeS_3op>, Enc_1aa186 { +tc_2c13e7f5, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011100; @@ -18450,7 +18773,7 @@ def S2_asr_r_p_or : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 |= asr($Rss32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_1aa186 { +tc_a4e22bbd, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011000; @@ -18461,7 +18784,7 @@ def S2_asr_r_p_xor : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 ^= asr($Rss32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_1aa186 { +tc_a4e22bbd, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011011; @@ -18472,7 +18795,7 @@ def S2_asr_r_r : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = asr($Rs32,$Rt32)", -tc_946df596, TypeS_3op>, Enc_5ab2be { +tc_5da50c4b, TypeS_3op>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000110010; @@ -18483,7 +18806,7 @@ def S2_asr_r_r_acc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += asr($Rs32,$Rt32)", -tc_f675fee8, TypeS_3op>, Enc_2ae154 { +tc_2c13e7f5, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100110; @@ -18496,7 +18819,7 @@ def S2_asr_r_r_and : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 &= asr($Rs32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_2ae154 { +tc_a4e22bbd, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100010; @@ -18509,7 +18832,7 @@ def S2_asr_r_r_nac : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= asr($Rs32,$Rt32)", -tc_f675fee8, TypeS_3op>, Enc_2ae154 { +tc_2c13e7f5, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100100; @@ -18522,7 +18845,7 @@ def S2_asr_r_r_or : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 |= asr($Rs32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_2ae154 { +tc_a4e22bbd, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100000; @@ -18535,7 +18858,7 @@ def S2_asr_r_r_sat : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = asr($Rs32,$Rt32):sat", -tc_779080bf, TypeS_3op>, Enc_5ab2be { +tc_8a825db2, TypeS_3op>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000110000; @@ -18548,7 +18871,7 @@ def S2_asr_r_svw_trun : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rd32 = vasrw($Rss32,$Rt32)", -tc_4414d8b1, TypeS_3op>, Enc_3d5b28 { +tc_f34c1c21, TypeS_3op>, Enc_3d5b28 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000101000; @@ -18560,7 +18883,7 @@ def S2_asr_r_vh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = vasrh($Rss32,$Rt32)", -tc_946df596, TypeS_3op>, Enc_927852 { +tc_5da50c4b, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011010; @@ -18569,7 +18892,7 @@ def S2_asr_r_vw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = vasrw($Rss32,$Rt32)", -tc_946df596, TypeS_3op>, Enc_927852 { +tc_5da50c4b, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011000; @@ -18578,7 +18901,7 @@ def S2_brev : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = brev($Rs32)", -tc_14b5c689, TypeS_2op>, Enc_5e2823 { +tc_a7bdb22c, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10001100010; let hasNewValue = 1; @@ -18589,7 +18912,7 @@ def S2_brevp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = brev($Rss32)", -tc_14b5c689, TypeS_2op>, Enc_b9c5fb { +tc_a7bdb22c, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10000000110; let prefersSlot3 = 1; @@ -18598,7 +18921,7 @@ def S2_cabacdecbin : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = decbin($Rss32,$Rtt32)", -tc_76851da1, TypeS_3op>, Enc_a56825 { +tc_db596beb, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001110; @@ -18610,7 +18933,7 @@ def S2_cl0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = cl0($Rs32)", -tc_14b5c689, TypeS_2op>, Enc_5e2823 { +tc_a7bdb22c, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000101; let Inst{31-21} = 0b10001100000; let hasNewValue = 1; @@ -18621,7 +18944,7 @@ def S2_cl0p : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = cl0($Rss32)", -tc_14b5c689, TypeS_2op>, Enc_90cd8b { +tc_a7bdb22c, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000010; let Inst{31-21} = 0b10001000010; let hasNewValue = 1; @@ -18632,7 +18955,7 @@ def S2_cl1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = cl1($Rs32)", -tc_14b5c689, TypeS_2op>, Enc_5e2823 { +tc_a7bdb22c, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10001100000; let hasNewValue = 1; @@ -18643,7 +18966,7 @@ def S2_cl1p : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = cl1($Rss32)", -tc_14b5c689, TypeS_2op>, Enc_90cd8b { +tc_a7bdb22c, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10001000010; let hasNewValue = 1; @@ -18654,7 +18977,7 @@ def S2_clb : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = clb($Rs32)", -tc_14b5c689, TypeS_2op>, Enc_5e2823 { +tc_a7bdb22c, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10001100000; let hasNewValue = 1; @@ -18665,7 +18988,7 @@ def S2_clbnorm : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = normamt($Rs32)", -tc_14b5c689, TypeS_2op>, Enc_5e2823 { +tc_a7bdb22c, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000111; let Inst{31-21} = 0b10001100000; let hasNewValue = 1; @@ -18676,7 +18999,7 @@ def S2_clbp : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = clb($Rss32)", -tc_14b5c689, TypeS_2op>, Enc_90cd8b { +tc_a7bdb22c, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001000010; let hasNewValue = 1; @@ -18687,7 +19010,7 @@ def S2_clrbit_i : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = clrbit($Rs32,#$Ii)", -tc_946df596, TypeS_2op>, Enc_a05677 { +tc_5da50c4b, TypeS_2op>, Enc_a05677 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001100110; @@ -18698,7 +19021,7 @@ def S2_clrbit_r : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = clrbit($Rs32,$Rt32)", -tc_946df596, TypeS_3op>, Enc_5ab2be { +tc_5da50c4b, TypeS_3op>, Enc_5ab2be { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000110100; @@ -18709,7 +19032,7 @@ def S2_ct0 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = ct0($Rs32)", -tc_14b5c689, TypeS_2op>, Enc_5e2823 { +tc_a7bdb22c, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10001100010; let hasNewValue = 1; @@ -18720,7 +19043,7 @@ def S2_ct0p : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = ct0($Rss32)", -tc_14b5c689, TypeS_2op>, Enc_90cd8b { +tc_a7bdb22c, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000010; let Inst{31-21} = 0b10001000111; let hasNewValue = 1; @@ -18731,7 +19054,7 @@ def S2_ct1 : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = ct1($Rs32)", -tc_14b5c689, TypeS_2op>, Enc_5e2823 { +tc_a7bdb22c, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000101; let Inst{31-21} = 0b10001100010; let hasNewValue = 1; @@ -18742,7 +19065,7 @@ def S2_ct1p : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = ct1($Rss32)", -tc_14b5c689, TypeS_2op>, Enc_90cd8b { +tc_a7bdb22c, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10001000111; let hasNewValue = 1; @@ -18753,7 +19076,7 @@ def S2_deinterleave : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = deinterleave($Rss32)", -tc_14b5c689, TypeS_2op>, Enc_b9c5fb { +tc_a7bdb22c, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10000000110; let prefersSlot3 = 1; @@ -18762,7 +19085,7 @@ def S2_extractu : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II), "$Rd32 = extractu($Rs32,#$Ii,#$II)", -tc_f675fee8, TypeS_2op>, Enc_b388cf { +tc_2c13e7f5, TypeS_2op>, Enc_b388cf { let Inst{13-13} = 0b0; let Inst{31-23} = 0b100011010; let hasNewValue = 1; @@ -18773,7 +19096,7 @@ def S2_extractu_rp : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, DoubleRegs:$Rtt32), "$Rd32 = extractu($Rs32,$Rtt32)", -tc_002cb246, TypeS_3op>, Enc_e07374 { +tc_a08b630b, TypeS_3op>, Enc_e07374 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001001000; @@ -18785,7 +19108,7 @@ def S2_extractup : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II), "$Rdd32 = extractu($Rss32,#$Ii,#$II)", -tc_f675fee8, TypeS_2op>, Enc_b84c4c { +tc_2c13e7f5, TypeS_2op>, Enc_b84c4c { let Inst{31-24} = 0b10000001; let prefersSlot3 = 1; } @@ -18793,7 +19116,7 @@ def S2_extractup_rp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = extractu($Rss32,$Rtt32)", -tc_002cb246, TypeS_3op>, Enc_a56825 { +tc_a08b630b, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001000; @@ -18803,7 +19126,7 @@ def S2_insert : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II), "$Rx32 = insert($Rs32,#$Ii,#$II)", -tc_bfec0f01, TypeS_2op>, Enc_a1e29d { +tc_bb831a7c, TypeS_2op>, Enc_a1e29d { let Inst{13-13} = 0b0; let Inst{31-23} = 0b100011110; let hasNewValue = 1; @@ -18815,7 +19138,7 @@ def S2_insert_rp : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, DoubleRegs:$Rtt32), "$Rx32 = insert($Rs32,$Rtt32)", -tc_f429765c, TypeS_3op>, Enc_179b35 { +tc_a4e22bbd, TypeS_3op>, Enc_179b35 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001000000; @@ -18828,7 +19151,7 @@ def S2_insertp : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II), "$Rxx32 = insert($Rss32,#$Ii,#$II)", -tc_bfec0f01, TypeS_2op>, Enc_143a3c { +tc_bb831a7c, TypeS_2op>, Enc_143a3c { let Inst{31-24} = 0b10000011; let prefersSlot3 = 1; let Constraints = "$Rxx32 = $Rxx32in"; @@ -18837,7 +19160,7 @@ def S2_insertp_rp : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rxx32 = insert($Rss32,$Rtt32)", -tc_f429765c, TypeS_3op>, Enc_88c16c { +tc_a4e22bbd, TypeS_3op>, Enc_88c16c { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001010000; @@ -18848,7 +19171,7 @@ def S2_interleave : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = interleave($Rss32)", -tc_14b5c689, TypeS_2op>, Enc_b9c5fb { +tc_a7bdb22c, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000101; let Inst{31-21} = 0b10000000110; let prefersSlot3 = 1; @@ -18857,7 +19180,7 @@ def S2_lfsp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = lfs($Rss32,$Rtt32)", -tc_002cb246, TypeS_3op>, Enc_a56825 { +tc_a08b630b, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001100; @@ -18867,7 +19190,7 @@ def S2_lsl_r_p : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = lsl($Rss32,$Rt32)", -tc_946df596, TypeS_3op>, Enc_927852 { +tc_5da50c4b, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011100; @@ -18876,7 +19199,7 @@ def S2_lsl_r_p_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 += lsl($Rss32,$Rt32)", -tc_f675fee8, TypeS_3op>, Enc_1aa186 { +tc_2c13e7f5, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011110; @@ -18887,7 +19210,7 @@ def S2_lsl_r_p_and : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 &= lsl($Rss32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_1aa186 { +tc_a4e22bbd, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011010; @@ -18898,7 +19221,7 @@ def S2_lsl_r_p_nac : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 -= lsl($Rss32,$Rt32)", -tc_f675fee8, TypeS_3op>, Enc_1aa186 { +tc_2c13e7f5, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011100; @@ -18909,7 +19232,7 @@ def S2_lsl_r_p_or : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 |= lsl($Rss32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_1aa186 { +tc_a4e22bbd, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011000; @@ -18920,7 +19243,7 @@ def S2_lsl_r_p_xor : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 ^= lsl($Rss32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_1aa186 { +tc_a4e22bbd, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011011; @@ -18931,7 +19254,7 @@ def S2_lsl_r_r : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = lsl($Rs32,$Rt32)", -tc_946df596, TypeS_3op>, Enc_5ab2be { +tc_5da50c4b, TypeS_3op>, Enc_5ab2be { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000110010; @@ -18942,7 +19265,7 @@ def S2_lsl_r_r_acc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += lsl($Rs32,$Rt32)", -tc_f675fee8, TypeS_3op>, Enc_2ae154 { +tc_2c13e7f5, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100110; @@ -18955,7 +19278,7 @@ def S2_lsl_r_r_and : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 &= lsl($Rs32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_2ae154 { +tc_a4e22bbd, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100010; @@ -18968,7 +19291,7 @@ def S2_lsl_r_r_nac : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= lsl($Rs32,$Rt32)", -tc_f675fee8, TypeS_3op>, Enc_2ae154 { +tc_2c13e7f5, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100100; @@ -18981,7 +19304,7 @@ def S2_lsl_r_r_or : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 |= lsl($Rs32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_2ae154 { +tc_a4e22bbd, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100000; @@ -18994,7 +19317,7 @@ def S2_lsl_r_vh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = vlslh($Rss32,$Rt32)", -tc_946df596, TypeS_3op>, Enc_927852 { +tc_5da50c4b, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011010; @@ -19003,7 +19326,7 @@ def S2_lsl_r_vw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = vlslw($Rss32,$Rt32)", -tc_946df596, TypeS_3op>, Enc_927852 { +tc_5da50c4b, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011000; @@ -19012,7 +19335,7 @@ def S2_lsr_i_p : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rdd32 = lsr($Rss32,#$Ii)", -tc_946df596, TypeS_2op>, Enc_5eac98 { +tc_5da50c4b, TypeS_2op>, Enc_5eac98 { let Inst{7-5} = 0b001; let Inst{31-21} = 0b10000000000; } @@ -19020,7 +19343,7 @@ def S2_lsr_i_p_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 += lsr($Rss32,#$Ii)", -tc_f675fee8, TypeS_2op>, Enc_70fb07 { +tc_2c13e7f5, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b101; let Inst{31-21} = 0b10000010000; let prefersSlot3 = 1; @@ -19030,7 +19353,7 @@ def S2_lsr_i_p_and : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 &= lsr($Rss32,#$Ii)", -tc_f429765c, TypeS_2op>, Enc_70fb07 { +tc_a4e22bbd, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b001; let Inst{31-21} = 0b10000010010; let prefersSlot3 = 1; @@ -19040,7 +19363,7 @@ def S2_lsr_i_p_nac : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 -= lsr($Rss32,#$Ii)", -tc_f675fee8, TypeS_2op>, Enc_70fb07 { +tc_2c13e7f5, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b001; let Inst{31-21} = 0b10000010000; let prefersSlot3 = 1; @@ -19050,7 +19373,7 @@ def S2_lsr_i_p_or : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 |= lsr($Rss32,#$Ii)", -tc_f429765c, TypeS_2op>, Enc_70fb07 { +tc_a4e22bbd, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b101; let Inst{31-21} = 0b10000010010; let prefersSlot3 = 1; @@ -19060,7 +19383,7 @@ def S2_lsr_i_p_xacc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 ^= lsr($Rss32,#$Ii)", -tc_f429765c, TypeS_2op>, Enc_70fb07 { +tc_a4e22bbd, TypeS_2op>, Enc_70fb07 { let Inst{7-5} = 0b001; let Inst{31-21} = 0b10000010100; let prefersSlot3 = 1; @@ -19070,7 +19393,7 @@ def S2_lsr_i_r : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = lsr($Rs32,#$Ii)", -tc_946df596, TypeS_2op>, Enc_a05677 { +tc_5da50c4b, TypeS_2op>, Enc_a05677 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001100000; @@ -19081,7 +19404,7 @@ def S2_lsr_i_r_acc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 += lsr($Rs32,#$Ii)", -tc_f675fee8, TypeS_2op>, Enc_28a2dc { +tc_2c13e7f5, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110000; @@ -19094,7 +19417,7 @@ def S2_lsr_i_r_and : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 &= lsr($Rs32,#$Ii)", -tc_f429765c, TypeS_2op>, Enc_28a2dc { +tc_a4e22bbd, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110010; @@ -19107,7 +19430,7 @@ def S2_lsr_i_r_nac : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 -= lsr($Rs32,#$Ii)", -tc_f675fee8, TypeS_2op>, Enc_28a2dc { +tc_2c13e7f5, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110000; @@ -19120,7 +19443,7 @@ def S2_lsr_i_r_or : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 |= lsr($Rs32,#$Ii)", -tc_f429765c, TypeS_2op>, Enc_28a2dc { +tc_a4e22bbd, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110010; @@ -19133,7 +19456,7 @@ def S2_lsr_i_r_xacc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 ^= lsr($Rs32,#$Ii)", -tc_f429765c, TypeS_2op>, Enc_28a2dc { +tc_a4e22bbd, TypeS_2op>, Enc_28a2dc { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110100; @@ -19146,7 +19469,7 @@ def S2_lsr_i_vh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u4_0Imm:$Ii), "$Rdd32 = vlsrh($Rss32,#$Ii)", -tc_946df596, TypeS_2op>, Enc_12b6e9 { +tc_5da50c4b, TypeS_2op>, Enc_12b6e9 { let Inst{7-5} = 0b001; let Inst{13-12} = 0b00; let Inst{31-21} = 0b10000000100; @@ -19155,7 +19478,7 @@ def S2_lsr_i_vw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u5_0Imm:$Ii), "$Rdd32 = vlsrw($Rss32,#$Ii)", -tc_946df596, TypeS_2op>, Enc_7e5a82 { +tc_5da50c4b, TypeS_2op>, Enc_7e5a82 { let Inst{7-5} = 0b001; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10000000010; @@ -19164,7 +19487,7 @@ def S2_lsr_r_p : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = lsr($Rss32,$Rt32)", -tc_946df596, TypeS_3op>, Enc_927852 { +tc_5da50c4b, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011100; @@ -19173,7 +19496,7 @@ def S2_lsr_r_p_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 += lsr($Rss32,$Rt32)", -tc_f675fee8, TypeS_3op>, Enc_1aa186 { +tc_2c13e7f5, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011110; @@ -19184,7 +19507,7 @@ def S2_lsr_r_p_and : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 &= lsr($Rss32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_1aa186 { +tc_a4e22bbd, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011010; @@ -19195,7 +19518,7 @@ def S2_lsr_r_p_nac : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 -= lsr($Rss32,$Rt32)", -tc_f675fee8, TypeS_3op>, Enc_1aa186 { +tc_2c13e7f5, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011100; @@ -19206,7 +19529,7 @@ def S2_lsr_r_p_or : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 |= lsr($Rss32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_1aa186 { +tc_a4e22bbd, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011000; @@ -19217,7 +19540,7 @@ def S2_lsr_r_p_xor : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 ^= lsr($Rss32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_1aa186 { +tc_a4e22bbd, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001011011; @@ -19228,7 +19551,7 @@ def S2_lsr_r_r : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = lsr($Rs32,$Rt32)", -tc_946df596, TypeS_3op>, Enc_5ab2be { +tc_5da50c4b, TypeS_3op>, Enc_5ab2be { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000110010; @@ -19239,7 +19562,7 @@ def S2_lsr_r_r_acc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 += lsr($Rs32,$Rt32)", -tc_f675fee8, TypeS_3op>, Enc_2ae154 { +tc_2c13e7f5, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100110; @@ -19252,7 +19575,7 @@ def S2_lsr_r_r_and : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 &= lsr($Rs32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_2ae154 { +tc_a4e22bbd, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100010; @@ -19265,7 +19588,7 @@ def S2_lsr_r_r_nac : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 -= lsr($Rs32,$Rt32)", -tc_f675fee8, TypeS_3op>, Enc_2ae154 { +tc_2c13e7f5, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100100; @@ -19278,7 +19601,7 @@ def S2_lsr_r_r_or : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), "$Rx32 |= lsr($Rs32,$Rt32)", -tc_f429765c, TypeS_3op>, Enc_2ae154 { +tc_a4e22bbd, TypeS_3op>, Enc_2ae154 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001100000; @@ -19291,7 +19614,7 @@ def S2_lsr_r_vh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = vlsrh($Rss32,$Rt32)", -tc_946df596, TypeS_3op>, Enc_927852 { +tc_5da50c4b, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011010; @@ -19300,7 +19623,7 @@ def S2_lsr_r_vw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = vlsrw($Rss32,$Rt32)", -tc_946df596, TypeS_3op>, Enc_927852 { +tc_5da50c4b, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011000; @@ -19309,7 +19632,7 @@ def S2_mask : HInst< (outs IntRegs:$Rd32), (ins u5_0Imm:$Ii, u5_0Imm:$II), "$Rd32 = mask(#$Ii,#$II)", -tc_9461ff31, TypeS_2op>, Enc_c85e2a, Requires<[HasV66]> { +tc_1fcb8495, TypeS_2op>, Enc_c85e2a, Requires<[HasV66]> { let Inst{13-13} = 0b1; let Inst{20-16} = 0b00000; let Inst{31-23} = 0b100011010; @@ -19321,7 +19644,7 @@ def S2_packhl : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = packhl($Rs32,$Rt32)", -tc_5a2711e5, TypeALU32_3op>, Enc_be32a5 { +tc_713b66bf, TypeALU32_3op>, Enc_be32a5 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11110101100; @@ -19331,7 +19654,7 @@ def S2_parityp : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rd32 = parity($Rss32,$Rtt32)", -tc_002cb246, TypeALU64>, Enc_d2216a { +tc_a08b630b, TypeALU64>, Enc_d2216a { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010000000; @@ -19343,7 +19666,7 @@ def S2_pstorerbf_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memb($Rs32+#$Ii) = $Rt32", -tc_f8e23f0b, TypeV2LDST>, Enc_da8d43, AddrModeRel { +tc_8035e91f, TypeV2LDST>, Enc_da8d43, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000100000; let isPredicated = 1; @@ -19351,9 +19674,9 @@ let isPredicatedFalse = 1; let addrMode = BaseImmOffset; let accessSize = ByteAccess; let mayStore = 1; +let BaseOpcode = "S2_storerb_io"; let CextOpcode = "S2_storerb"; let InputType = "imm"; -let BaseOpcode = "S2_storerb_io"; let isNVStorable = 1; let isExtendable = 1; let opExtendable = 2; @@ -19365,7 +19688,7 @@ def S2_pstorerbf_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memb($Rx32++#$Ii) = $Rt32", -tc_24b66c99, TypeST>, Enc_cc449f, AddrModeRel { +tc_9edefe01, TypeST>, Enc_cc449f, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; @@ -19383,7 +19706,7 @@ def S2_pstorerbf_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pv4) memb($Rs32) = $Rt32", -tc_f8e23f0b, TypeMAPPING> { +tc_8035e91f, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -19391,7 +19714,7 @@ def S2_pstorerbfnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memb($Rx32++#$Ii) = $Rt32", -tc_53559e35, TypeST>, Enc_cc449f, AddrModeRel { +tc_449acf79, TypeST>, Enc_cc449f, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -19410,7 +19733,7 @@ def S2_pstorerbnewf_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4) memb($Rs32+#$Ii) = $Nt8.new", -tc_8fb7ab1b, TypeV2LDST>, Enc_585242, AddrModeRel { +tc_011e0e9d, TypeV2LDST>, Enc_585242, AddrModeRel { let Inst{2-2} = 0b0; let Inst{12-11} = 0b00; let Inst{31-21} = 0b01000100101; @@ -19422,9 +19745,9 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storerb_io"; let CextOpcode = "S2_storerb"; let InputType = "imm"; -let BaseOpcode = "S2_storerb_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -19436,7 +19759,7 @@ def S2_pstorerbnewf_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4) memb($Rx32++#$Ii) = $Nt8.new", -tc_838b34ea, TypeST>, Enc_52a5dd, AddrModeRel { +tc_ce59038e, TypeST>, Enc_52a5dd, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b0; let Inst{13-11} = 0b100; @@ -19449,8 +19772,8 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerb_pi"; +let CextOpcode = "S2_storerb"; let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } @@ -19458,7 +19781,7 @@ def S2_pstorerbnewf_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), "if (!$Pv4) memb($Rs32) = $Nt8.new", -tc_8fb7ab1b, TypeMAPPING> { +tc_011e0e9d, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 2; @@ -19467,7 +19790,7 @@ def S2_pstorerbnewfnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4.new) memb($Rx32++#$Ii) = $Nt8.new", -tc_d65dbf51, TypeST>, Enc_52a5dd, AddrModeRel { +tc_f529831b, TypeST>, Enc_52a5dd, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-11} = 0b100; @@ -19481,8 +19804,8 @@ let isPredicatedNew = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerb_pi"; +let CextOpcode = "S2_storerb"; let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } @@ -19490,7 +19813,7 @@ def S2_pstorerbnewt_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4) memb($Rs32+#$Ii) = $Nt8.new", -tc_8fb7ab1b, TypeV2LDST>, Enc_585242, AddrModeRel { +tc_011e0e9d, TypeV2LDST>, Enc_585242, AddrModeRel { let Inst{2-2} = 0b0; let Inst{12-11} = 0b00; let Inst{31-21} = 0b01000000101; @@ -19501,9 +19824,9 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storerb_io"; let CextOpcode = "S2_storerb"; let InputType = "imm"; -let BaseOpcode = "S2_storerb_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -19515,7 +19838,7 @@ def S2_pstorerbnewt_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4) memb($Rx32++#$Ii) = $Nt8.new", -tc_838b34ea, TypeST>, Enc_52a5dd, AddrModeRel { +tc_ce59038e, TypeST>, Enc_52a5dd, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b0; let Inst{13-11} = 0b100; @@ -19527,8 +19850,8 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerb_pi"; +let CextOpcode = "S2_storerb"; let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } @@ -19536,7 +19859,7 @@ def S2_pstorerbnewt_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), "if ($Pv4) memb($Rs32) = $Nt8.new", -tc_8fb7ab1b, TypeMAPPING> { +tc_011e0e9d, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 2; @@ -19545,7 +19868,7 @@ def S2_pstorerbnewtnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4.new) memb($Rx32++#$Ii) = $Nt8.new", -tc_d65dbf51, TypeST>, Enc_52a5dd, AddrModeRel { +tc_f529831b, TypeST>, Enc_52a5dd, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-11} = 0b100; @@ -19558,8 +19881,8 @@ let isPredicatedNew = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerb_pi"; +let CextOpcode = "S2_storerb"; let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } @@ -19567,16 +19890,16 @@ def S2_pstorerbt_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memb($Rs32+#$Ii) = $Rt32", -tc_f8e23f0b, TypeV2LDST>, Enc_da8d43, AddrModeRel { +tc_8035e91f, TypeV2LDST>, Enc_da8d43, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000000000; let isPredicated = 1; let addrMode = BaseImmOffset; let accessSize = ByteAccess; let mayStore = 1; +let BaseOpcode = "S2_storerb_io"; let CextOpcode = "S2_storerb"; let InputType = "imm"; -let BaseOpcode = "S2_storerb_io"; let isNVStorable = 1; let isExtendable = 1; let opExtendable = 2; @@ -19588,7 +19911,7 @@ def S2_pstorerbt_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memb($Rx32++#$Ii) = $Rt32", -tc_24b66c99, TypeST>, Enc_cc449f, AddrModeRel { +tc_9edefe01, TypeST>, Enc_cc449f, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; @@ -19605,7 +19928,7 @@ def S2_pstorerbt_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pv4) memb($Rs32) = $Rt32", -tc_f8e23f0b, TypeMAPPING> { +tc_8035e91f, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -19613,7 +19936,7 @@ def S2_pstorerbtnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memb($Rx32++#$Ii) = $Rt32", -tc_53559e35, TypeST>, Enc_cc449f, AddrModeRel { +tc_449acf79, TypeST>, Enc_cc449f, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -19631,7 +19954,7 @@ def S2_pstorerdf_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32), "if (!$Pv4) memd($Rs32+#$Ii) = $Rtt32", -tc_f8e23f0b, TypeV2LDST>, Enc_57a33e, AddrModeRel { +tc_8035e91f, TypeV2LDST>, Enc_57a33e, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000100110; let isPredicated = 1; @@ -19639,9 +19962,9 @@ let isPredicatedFalse = 1; let addrMode = BaseImmOffset; let accessSize = DoubleWordAccess; let mayStore = 1; +let BaseOpcode = "S2_storerd_io"; let CextOpcode = "S2_storerd"; let InputType = "imm"; -let BaseOpcode = "S2_storerd_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -19652,7 +19975,7 @@ def S2_pstorerdf_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32), "if (!$Pv4) memd($Rx32++#$Ii) = $Rtt32", -tc_24b66c99, TypeST>, Enc_9a33d5, AddrModeRel { +tc_9edefe01, TypeST>, Enc_9a33d5, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; @@ -19662,15 +19985,15 @@ let isPredicatedFalse = 1; let addrMode = PostInc; let accessSize = DoubleWordAccess; let mayStore = 1; -let CextOpcode = "S2_storerd"; let BaseOpcode = "S2_storerd_pi"; +let CextOpcode = "S2_storerd"; let Constraints = "$Rx32 = $Rx32in"; } def S2_pstorerdf_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32), "if (!$Pv4) memd($Rs32) = $Rtt32", -tc_f8e23f0b, TypeMAPPING> { +tc_8035e91f, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -19678,7 +20001,7 @@ def S2_pstorerdfnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32), "if (!$Pv4.new) memd($Rx32++#$Ii) = $Rtt32", -tc_53559e35, TypeST>, Enc_9a33d5, AddrModeRel { +tc_449acf79, TypeST>, Enc_9a33d5, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -19689,24 +20012,24 @@ let addrMode = PostInc; let accessSize = DoubleWordAccess; let isPredicatedNew = 1; let mayStore = 1; -let CextOpcode = "S2_storerd"; let BaseOpcode = "S2_storerd_pi"; +let CextOpcode = "S2_storerd"; let Constraints = "$Rx32 = $Rx32in"; } def S2_pstorerdt_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32), "if ($Pv4) memd($Rs32+#$Ii) = $Rtt32", -tc_f8e23f0b, TypeV2LDST>, Enc_57a33e, AddrModeRel { +tc_8035e91f, TypeV2LDST>, Enc_57a33e, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000000110; let isPredicated = 1; let addrMode = BaseImmOffset; let accessSize = DoubleWordAccess; let mayStore = 1; +let BaseOpcode = "S2_storerd_io"; let CextOpcode = "S2_storerd"; let InputType = "imm"; -let BaseOpcode = "S2_storerd_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -19717,7 +20040,7 @@ def S2_pstorerdt_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32), "if ($Pv4) memd($Rx32++#$Ii) = $Rtt32", -tc_24b66c99, TypeST>, Enc_9a33d5, AddrModeRel { +tc_9edefe01, TypeST>, Enc_9a33d5, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; @@ -19726,15 +20049,15 @@ let isPredicated = 1; let addrMode = PostInc; let accessSize = DoubleWordAccess; let mayStore = 1; -let CextOpcode = "S2_storerd"; let BaseOpcode = "S2_storerd_pi"; +let CextOpcode = "S2_storerd"; let Constraints = "$Rx32 = $Rx32in"; } def S2_pstorerdt_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32), "if ($Pv4) memd($Rs32) = $Rtt32", -tc_f8e23f0b, TypeMAPPING> { +tc_8035e91f, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -19742,7 +20065,7 @@ def S2_pstorerdtnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32), "if ($Pv4.new) memd($Rx32++#$Ii) = $Rtt32", -tc_53559e35, TypeST>, Enc_9a33d5, AddrModeRel { +tc_449acf79, TypeST>, Enc_9a33d5, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -19752,15 +20075,15 @@ let addrMode = PostInc; let accessSize = DoubleWordAccess; let isPredicatedNew = 1; let mayStore = 1; -let CextOpcode = "S2_storerd"; let BaseOpcode = "S2_storerd_pi"; +let CextOpcode = "S2_storerd"; let Constraints = "$Rx32 = $Rx32in"; } def S2_pstorerff_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memh($Rs32+#$Ii) = $Rt32.h", -tc_f8e23f0b, TypeV2LDST>, Enc_e8c45e, AddrModeRel { +tc_8035e91f, TypeV2LDST>, Enc_e8c45e, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000100011; let isPredicated = 1; @@ -19768,9 +20091,9 @@ let isPredicatedFalse = 1; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let mayStore = 1; +let BaseOpcode = "S2_storerf_io"; let CextOpcode = "S2_storerf"; let InputType = "imm"; -let BaseOpcode = "S2_storerf_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -19781,7 +20104,7 @@ def S2_pstorerff_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memh($Rx32++#$Ii) = $Rt32.h", -tc_24b66c99, TypeST>, Enc_b886fd, AddrModeRel { +tc_9edefe01, TypeST>, Enc_b886fd, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; @@ -19791,15 +20114,15 @@ let isPredicatedFalse = 1; let addrMode = PostInc; let accessSize = HalfWordAccess; let mayStore = 1; -let CextOpcode = "S2_storerf"; let BaseOpcode = "S2_storerf_pi"; +let CextOpcode = "S2_storerf"; let Constraints = "$Rx32 = $Rx32in"; } def S2_pstorerff_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pv4) memh($Rs32) = $Rt32.h", -tc_f8e23f0b, TypeMAPPING> { +tc_8035e91f, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -19807,7 +20130,7 @@ def S2_pstorerffnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memh($Rx32++#$Ii) = $Rt32.h", -tc_53559e35, TypeST>, Enc_b886fd, AddrModeRel { +tc_449acf79, TypeST>, Enc_b886fd, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -19818,24 +20141,24 @@ let addrMode = PostInc; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayStore = 1; -let CextOpcode = "S2_storerf"; let BaseOpcode = "S2_storerf_pi"; +let CextOpcode = "S2_storerf"; let Constraints = "$Rx32 = $Rx32in"; } def S2_pstorerft_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memh($Rs32+#$Ii) = $Rt32.h", -tc_f8e23f0b, TypeV2LDST>, Enc_e8c45e, AddrModeRel { +tc_8035e91f, TypeV2LDST>, Enc_e8c45e, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000000011; let isPredicated = 1; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let mayStore = 1; +let BaseOpcode = "S2_storerf_io"; let CextOpcode = "S2_storerf"; let InputType = "imm"; -let BaseOpcode = "S2_storerf_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -19846,7 +20169,7 @@ def S2_pstorerft_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memh($Rx32++#$Ii) = $Rt32.h", -tc_24b66c99, TypeST>, Enc_b886fd, AddrModeRel { +tc_9edefe01, TypeST>, Enc_b886fd, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; @@ -19855,15 +20178,15 @@ let isPredicated = 1; let addrMode = PostInc; let accessSize = HalfWordAccess; let mayStore = 1; -let CextOpcode = "S2_storerf"; let BaseOpcode = "S2_storerf_pi"; +let CextOpcode = "S2_storerf"; let Constraints = "$Rx32 = $Rx32in"; } def S2_pstorerft_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pv4) memh($Rs32) = $Rt32.h", -tc_f8e23f0b, TypeMAPPING> { +tc_8035e91f, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -19871,7 +20194,7 @@ def S2_pstorerftnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memh($Rx32++#$Ii) = $Rt32.h", -tc_53559e35, TypeST>, Enc_b886fd, AddrModeRel { +tc_449acf79, TypeST>, Enc_b886fd, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -19881,15 +20204,15 @@ let addrMode = PostInc; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayStore = 1; -let CextOpcode = "S2_storerf"; let BaseOpcode = "S2_storerf_pi"; +let CextOpcode = "S2_storerf"; let Constraints = "$Rx32 = $Rx32in"; } def S2_pstorerhf_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memh($Rs32+#$Ii) = $Rt32", -tc_f8e23f0b, TypeV2LDST>, Enc_e8c45e, AddrModeRel { +tc_8035e91f, TypeV2LDST>, Enc_e8c45e, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000100010; let isPredicated = 1; @@ -19897,9 +20220,9 @@ let isPredicatedFalse = 1; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let mayStore = 1; +let BaseOpcode = "S2_storerh_io"; let CextOpcode = "S2_storerh"; let InputType = "imm"; -let BaseOpcode = "S2_storerh_io"; let isNVStorable = 1; let isExtendable = 1; let opExtendable = 2; @@ -19911,7 +20234,7 @@ def S2_pstorerhf_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memh($Rx32++#$Ii) = $Rt32", -tc_24b66c99, TypeST>, Enc_b886fd, AddrModeRel { +tc_9edefe01, TypeST>, Enc_b886fd, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; @@ -19929,7 +20252,7 @@ def S2_pstorerhf_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pv4) memh($Rs32) = $Rt32", -tc_f8e23f0b, TypeMAPPING> { +tc_8035e91f, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -19937,7 +20260,7 @@ def S2_pstorerhfnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memh($Rx32++#$Ii) = $Rt32", -tc_53559e35, TypeST>, Enc_b886fd, AddrModeRel { +tc_449acf79, TypeST>, Enc_b886fd, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -19956,7 +20279,7 @@ def S2_pstorerhnewf_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4) memh($Rs32+#$Ii) = $Nt8.new", -tc_8fb7ab1b, TypeV2LDST>, Enc_f44229, AddrModeRel { +tc_011e0e9d, TypeV2LDST>, Enc_f44229, AddrModeRel { let Inst{2-2} = 0b0; let Inst{12-11} = 0b01; let Inst{31-21} = 0b01000100101; @@ -19968,9 +20291,9 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storerh_io"; let CextOpcode = "S2_storerh"; let InputType = "imm"; -let BaseOpcode = "S2_storerh_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -19982,7 +20305,7 @@ def S2_pstorerhnewf_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4) memh($Rx32++#$Ii) = $Nt8.new", -tc_838b34ea, TypeST>, Enc_31aa6a, AddrModeRel { +tc_ce59038e, TypeST>, Enc_31aa6a, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b0; let Inst{13-11} = 0b101; @@ -19995,8 +20318,8 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerh_pi"; +let CextOpcode = "S2_storerh"; let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } @@ -20004,7 +20327,7 @@ def S2_pstorerhnewf_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), "if (!$Pv4) memh($Rs32) = $Nt8.new", -tc_8fb7ab1b, TypeMAPPING> { +tc_011e0e9d, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 2; @@ -20013,7 +20336,7 @@ def S2_pstorerhnewfnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4.new) memh($Rx32++#$Ii) = $Nt8.new", -tc_d65dbf51, TypeST>, Enc_31aa6a, AddrModeRel { +tc_f529831b, TypeST>, Enc_31aa6a, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-11} = 0b101; @@ -20027,8 +20350,8 @@ let isPredicatedNew = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerh_pi"; +let CextOpcode = "S2_storerh"; let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } @@ -20036,7 +20359,7 @@ def S2_pstorerhnewt_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8), "if ($Pv4) memh($Rs32+#$Ii) = $Nt8.new", -tc_8fb7ab1b, TypeV2LDST>, Enc_f44229, AddrModeRel { +tc_011e0e9d, TypeV2LDST>, Enc_f44229, AddrModeRel { let Inst{2-2} = 0b0; let Inst{12-11} = 0b01; let Inst{31-21} = 0b01000000101; @@ -20047,9 +20370,9 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storerh_io"; let CextOpcode = "S2_storerh"; let InputType = "imm"; -let BaseOpcode = "S2_storerh_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -20061,7 +20384,7 @@ def S2_pstorerhnewt_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8), "if ($Pv4) memh($Rx32++#$Ii) = $Nt8.new", -tc_838b34ea, TypeST>, Enc_31aa6a, AddrModeRel { +tc_ce59038e, TypeST>, Enc_31aa6a, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b0; let Inst{13-11} = 0b101; @@ -20073,8 +20396,8 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerh_pi"; +let CextOpcode = "S2_storerh"; let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } @@ -20082,7 +20405,7 @@ def S2_pstorerhnewt_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), "if ($Pv4) memh($Rs32) = $Nt8.new", -tc_8fb7ab1b, TypeMAPPING> { +tc_011e0e9d, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 2; @@ -20091,7 +20414,7 @@ def S2_pstorerhnewtnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8), "if ($Pv4.new) memh($Rx32++#$Ii) = $Nt8.new", -tc_d65dbf51, TypeST>, Enc_31aa6a, AddrModeRel { +tc_f529831b, TypeST>, Enc_31aa6a, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-11} = 0b101; @@ -20104,8 +20427,8 @@ let isPredicatedNew = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerh_pi"; +let CextOpcode = "S2_storerh"; let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } @@ -20113,16 +20436,16 @@ def S2_pstorerht_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memh($Rs32+#$Ii) = $Rt32", -tc_f8e23f0b, TypeV2LDST>, Enc_e8c45e, AddrModeRel { +tc_8035e91f, TypeV2LDST>, Enc_e8c45e, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000000010; let isPredicated = 1; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let mayStore = 1; +let BaseOpcode = "S2_storerh_io"; let CextOpcode = "S2_storerh"; let InputType = "imm"; -let BaseOpcode = "S2_storerh_io"; let isNVStorable = 1; let isExtendable = 1; let opExtendable = 2; @@ -20134,7 +20457,7 @@ def S2_pstorerht_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memh($Rx32++#$Ii) = $Rt32", -tc_24b66c99, TypeST>, Enc_b886fd, AddrModeRel { +tc_9edefe01, TypeST>, Enc_b886fd, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; @@ -20151,7 +20474,7 @@ def S2_pstorerht_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pv4) memh($Rs32) = $Rt32", -tc_f8e23f0b, TypeMAPPING> { +tc_8035e91f, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -20159,7 +20482,7 @@ def S2_pstorerhtnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memh($Rx32++#$Ii) = $Rt32", -tc_53559e35, TypeST>, Enc_b886fd, AddrModeRel { +tc_449acf79, TypeST>, Enc_b886fd, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -20177,7 +20500,7 @@ def S2_pstorerif_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memw($Rs32+#$Ii) = $Rt32", -tc_f8e23f0b, TypeV2LDST>, Enc_397f23, AddrModeRel { +tc_8035e91f, TypeV2LDST>, Enc_397f23, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000100100; let isPredicated = 1; @@ -20185,9 +20508,9 @@ let isPredicatedFalse = 1; let addrMode = BaseImmOffset; let accessSize = WordAccess; let mayStore = 1; +let BaseOpcode = "S2_storeri_io"; let CextOpcode = "S2_storeri"; let InputType = "imm"; -let BaseOpcode = "S2_storeri_io"; let isNVStorable = 1; let isExtendable = 1; let opExtendable = 2; @@ -20199,7 +20522,7 @@ def S2_pstorerif_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memw($Rx32++#$Ii) = $Rt32", -tc_24b66c99, TypeST>, Enc_7eaeb6, AddrModeRel { +tc_9edefe01, TypeST>, Enc_7eaeb6, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; @@ -20217,7 +20540,7 @@ def S2_pstorerif_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pv4) memw($Rs32) = $Rt32", -tc_f8e23f0b, TypeMAPPING> { +tc_8035e91f, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -20225,7 +20548,7 @@ def S2_pstorerifnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memw($Rx32++#$Ii) = $Rt32", -tc_53559e35, TypeST>, Enc_7eaeb6, AddrModeRel { +tc_449acf79, TypeST>, Enc_7eaeb6, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -20236,8 +20559,8 @@ let addrMode = PostInc; let accessSize = WordAccess; let isPredicatedNew = 1; let mayStore = 1; -let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeri_pi"; +let CextOpcode = "S2_storeri"; let isNVStorable = 1; let Constraints = "$Rx32 = $Rx32in"; } @@ -20245,7 +20568,7 @@ def S2_pstorerinewf_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4) memw($Rs32+#$Ii) = $Nt8.new", -tc_8fb7ab1b, TypeV2LDST>, Enc_8dbdfe, AddrModeRel { +tc_011e0e9d, TypeV2LDST>, Enc_8dbdfe, AddrModeRel { let Inst{2-2} = 0b0; let Inst{12-11} = 0b10; let Inst{31-21} = 0b01000100101; @@ -20257,9 +20580,9 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storeri_io"; let CextOpcode = "S2_storeri"; let InputType = "imm"; -let BaseOpcode = "S2_storeri_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -20271,7 +20594,7 @@ def S2_pstorerinewf_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4) memw($Rx32++#$Ii) = $Nt8.new", -tc_838b34ea, TypeST>, Enc_65f095, AddrModeRel { +tc_ce59038e, TypeST>, Enc_65f095, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b0; let Inst{13-11} = 0b110; @@ -20284,8 +20607,8 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeri_pi"; +let CextOpcode = "S2_storeri"; let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } @@ -20293,7 +20616,7 @@ def S2_pstorerinewf_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), "if (!$Pv4) memw($Rs32) = $Nt8.new", -tc_8fb7ab1b, TypeMAPPING> { +tc_011e0e9d, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 2; @@ -20302,7 +20625,7 @@ def S2_pstorerinewfnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4.new) memw($Rx32++#$Ii) = $Nt8.new", -tc_d65dbf51, TypeST>, Enc_65f095, AddrModeRel { +tc_f529831b, TypeST>, Enc_65f095, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-11} = 0b110; @@ -20316,8 +20639,8 @@ let isPredicatedNew = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeri_pi"; +let CextOpcode = "S2_storeri"; let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } @@ -20325,7 +20648,7 @@ def S2_pstorerinewt_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8), "if ($Pv4) memw($Rs32+#$Ii) = $Nt8.new", -tc_8fb7ab1b, TypeV2LDST>, Enc_8dbdfe, AddrModeRel { +tc_011e0e9d, TypeV2LDST>, Enc_8dbdfe, AddrModeRel { let Inst{2-2} = 0b0; let Inst{12-11} = 0b10; let Inst{31-21} = 0b01000000101; @@ -20336,9 +20659,9 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storeri_io"; let CextOpcode = "S2_storeri"; let InputType = "imm"; -let BaseOpcode = "S2_storeri_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -20350,7 +20673,7 @@ def S2_pstorerinewt_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8), "if ($Pv4) memw($Rx32++#$Ii) = $Nt8.new", -tc_838b34ea, TypeST>, Enc_65f095, AddrModeRel { +tc_ce59038e, TypeST>, Enc_65f095, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b0; let Inst{13-11} = 0b110; @@ -20362,8 +20685,8 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeri_pi"; +let CextOpcode = "S2_storeri"; let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } @@ -20371,7 +20694,7 @@ def S2_pstorerinewt_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), "if ($Pv4) memw($Rs32) = $Nt8.new", -tc_8fb7ab1b, TypeMAPPING> { +tc_011e0e9d, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 2; @@ -20380,7 +20703,7 @@ def S2_pstorerinewtnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8), "if ($Pv4.new) memw($Rx32++#$Ii) = $Nt8.new", -tc_d65dbf51, TypeST>, Enc_65f095, AddrModeRel { +tc_f529831b, TypeST>, Enc_65f095, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-11} = 0b110; @@ -20393,8 +20716,8 @@ let isPredicatedNew = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeri_pi"; +let CextOpcode = "S2_storeri"; let opNewValue = 4; let Constraints = "$Rx32 = $Rx32in"; } @@ -20402,16 +20725,16 @@ def S2_pstorerit_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memw($Rs32+#$Ii) = $Rt32", -tc_f8e23f0b, TypeV2LDST>, Enc_397f23, AddrModeRel { +tc_8035e91f, TypeV2LDST>, Enc_397f23, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000000100; let isPredicated = 1; let addrMode = BaseImmOffset; let accessSize = WordAccess; let mayStore = 1; +let BaseOpcode = "S2_storeri_io"; let CextOpcode = "S2_storeri"; let InputType = "imm"; -let BaseOpcode = "S2_storeri_io"; let isNVStorable = 1; let isExtendable = 1; let opExtendable = 2; @@ -20423,7 +20746,7 @@ def S2_pstorerit_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memw($Rx32++#$Ii) = $Rt32", -tc_24b66c99, TypeST>, Enc_7eaeb6, AddrModeRel { +tc_9edefe01, TypeST>, Enc_7eaeb6, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; @@ -20440,7 +20763,7 @@ def S2_pstorerit_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pv4) memw($Rs32) = $Rt32", -tc_f8e23f0b, TypeMAPPING> { +tc_8035e91f, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -20448,7 +20771,7 @@ def S2_pstoreritnew_pi : HInst< (outs IntRegs:$Rx32), (ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memw($Rx32++#$Ii) = $Rt32", -tc_53559e35, TypeST>, Enc_7eaeb6, AddrModeRel { +tc_449acf79, TypeST>, Enc_7eaeb6, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -20466,7 +20789,7 @@ def S2_setbit_i : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = setbit($Rs32,#$Ii)", -tc_946df596, TypeS_2op>, Enc_a05677 { +tc_5da50c4b, TypeS_2op>, Enc_a05677 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001100110; @@ -20477,7 +20800,7 @@ def S2_setbit_r : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = setbit($Rs32,$Rt32)", -tc_946df596, TypeS_3op>, Enc_5ab2be { +tc_5da50c4b, TypeS_3op>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000110100; @@ -20488,7 +20811,7 @@ def S2_shuffeb : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = shuffeb($Rss32,$Rtt32)", -tc_946df596, TypeS_3op>, Enc_a56825 { +tc_5da50c4b, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001000; @@ -20497,7 +20820,7 @@ def S2_shuffeh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = shuffeh($Rss32,$Rtt32)", -tc_946df596, TypeS_3op>, Enc_a56825 { +tc_5da50c4b, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001000; @@ -20506,7 +20829,7 @@ def S2_shuffob : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = shuffob($Rtt32,$Rss32)", -tc_946df596, TypeS_3op>, Enc_ea23e4 { +tc_5da50c4b, TypeS_3op>, Enc_ea23e4 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001000; @@ -20515,7 +20838,7 @@ def S2_shuffoh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), "$Rdd32 = shuffoh($Rtt32,$Rss32)", -tc_946df596, TypeS_3op>, Enc_ea23e4 { +tc_5da50c4b, TypeS_3op>, Enc_ea23e4 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001100; @@ -20524,15 +20847,15 @@ def S2_storerb_io : HInst< (outs), (ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Rt32), "memb($Rs32+#$Ii) = $Rt32", -tc_30b9bb4a, TypeST>, Enc_448f7f, AddrModeRel, PostInc_BaseImm { +tc_ae5babd7, TypeST>, Enc_448f7f, AddrModeRel, PostInc_BaseImm { let Inst{24-21} = 0b1000; let Inst{31-27} = 0b10100; let addrMode = BaseImmOffset; let accessSize = ByteAccess; let mayStore = 1; +let BaseOpcode = "S2_storerb_io"; let CextOpcode = "S2_storerb"; let InputType = "imm"; -let BaseOpcode = "S2_storerb_io"; let isPredicable = 1; let isNVStorable = 1; let isExtendable = 1; @@ -20545,7 +20868,7 @@ def S2_storerb_pbr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), "memb($Rx32++$Mu2:brev) = $Rt32", -tc_da97ee82, TypeST>, Enc_d5c73f, AddrModeRel { +tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel { let Inst{7-0} = 0b00000000; let Inst{31-21} = 0b10101111000; let addrMode = PostInc; @@ -20559,7 +20882,7 @@ def S2_storerb_pci : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32), "memb($Rx32++#$Ii:circ($Mu2)) = $Rt32", -tc_e86aa961, TypeST>, Enc_b15941, AddrModeRel { +tc_b4dc7630, TypeST>, Enc_b15941, AddrModeRel { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{31-21} = 0b10101001000; @@ -20575,7 +20898,7 @@ def S2_storerb_pcr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), "memb($Rx32++I:circ($Mu2)) = $Rt32", -tc_da97ee82, TypeST>, Enc_d5c73f, AddrModeRel { +tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel { let Inst{7-0} = 0b00000010; let Inst{31-21} = 0b10101001000; let addrMode = PostInc; @@ -20590,7 +20913,7 @@ def S2_storerb_pi : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32), "memb($Rx32++#$Ii) = $Rt32", -tc_da97ee82, TypeST>, Enc_10bc21, AddrModeRel, PostInc_BaseImm { +tc_a2b365d2, TypeST>, Enc_10bc21, AddrModeRel, PostInc_BaseImm { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; @@ -20598,8 +20921,8 @@ let Inst{31-21} = 0b10101011000; let addrMode = PostInc; let accessSize = ByteAccess; let mayStore = 1; -let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerb_pi"; +let CextOpcode = "S2_storerb"; let isPredicable = 1; let isNVStorable = 1; let Constraints = "$Rx32 = $Rx32in"; @@ -20608,12 +20931,13 @@ def S2_storerb_pr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), "memb($Rx32++$Mu2) = $Rt32", -tc_da97ee82, TypeST>, Enc_d5c73f { +tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel { let Inst{7-0} = 0b00000000; let Inst{31-21} = 0b10101101000; let addrMode = PostInc; let accessSize = ByteAccess; let mayStore = 1; +let BaseOpcode = "S2_storerb_pr"; let isNVStorable = 1; let Constraints = "$Rx32 = $Rx32in"; } @@ -20621,7 +20945,7 @@ def S2_storerb_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memb($Rs32) = $Rt32", -tc_30b9bb4a, TypeMAPPING> { +tc_ae5babd7, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -20629,7 +20953,7 @@ def S2_storerbgp : HInst< (outs), (ins u32_0Imm:$Ii, IntRegs:$Rt32), "memb(gp+#$Ii) = $Rt32", -tc_0371abea, TypeV2LDST>, Enc_1b64fb, AddrModeRel { +tc_0655b949, TypeV2LDST>, Enc_1b64fb, AddrModeRel { let Inst{24-21} = 0b0000; let Inst{31-27} = 0b01001; let accessSize = ByteAccess; @@ -20647,7 +20971,7 @@ def S2_storerbnew_io : HInst< (outs), (ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Nt8), "memb($Rs32+#$Ii) = $Nt8.new", -tc_be9602ff, TypeST>, Enc_4df4e9, AddrModeRel { +tc_5deb5e47, TypeST>, Enc_4df4e9, AddrModeRel { let Inst{12-11} = 0b00; let Inst{24-21} = 0b1101; let Inst{31-27} = 0b10100; @@ -20657,9 +20981,9 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storerb_io"; let CextOpcode = "S2_storerb"; let InputType = "imm"; -let BaseOpcode = "S2_storerb_io"; let isPredicable = 1; let isExtendable = 1; let opExtendable = 1; @@ -20672,7 +20996,7 @@ def S2_storerbnew_pbr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), "memb($Rx32++$Mu2:brev) = $Nt8.new", -tc_c79a189f, TypeST>, Enc_8dbe85, AddrModeRel { +tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel { let Inst{7-0} = 0b00000000; let Inst{12-11} = 0b00; let Inst{31-21} = 0b10101111101; @@ -20690,7 +21014,7 @@ def S2_storerbnew_pci : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8), "memb($Rx32++#$Ii:circ($Mu2)) = $Nt8.new", -tc_d5c0729a, TypeST>, Enc_96ce4f, AddrModeRel { +tc_addc37a8, TypeST>, Enc_96ce4f, AddrModeRel { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{12-11} = 0b00; @@ -20710,7 +21034,7 @@ def S2_storerbnew_pcr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), "memb($Rx32++I:circ($Mu2)) = $Nt8.new", -tc_c79a189f, TypeST>, Enc_8dbe85, AddrModeRel { +tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel { let Inst{7-0} = 0b00000010; let Inst{12-11} = 0b00; let Inst{31-21} = 0b10101001101; @@ -20729,7 +21053,7 @@ def S2_storerbnew_pi : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8), "memb($Rx32++#$Ii) = $Nt8.new", -tc_c79a189f, TypeST>, Enc_c7cd90, AddrModeRel { +tc_92240447, TypeST>, Enc_c7cd90, AddrModeRel { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{13-11} = 0b000; @@ -20750,7 +21074,7 @@ def S2_storerbnew_pr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), "memb($Rx32++$Mu2) = $Nt8.new", -tc_c79a189f, TypeST>, Enc_8dbe85 { +tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel { let Inst{7-0} = 0b00000000; let Inst{12-11} = 0b00; let Inst{31-21} = 0b10101101101; @@ -20760,6 +21084,7 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storerb_pr"; let opNewValue = 3; let Constraints = "$Rx32 = $Rx32in"; } @@ -20767,7 +21092,7 @@ def S2_storerbnew_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Nt8), "memb($Rs32) = $Nt8.new", -tc_be9602ff, TypeMAPPING> { +tc_5deb5e47, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 1; @@ -20776,7 +21101,7 @@ def S2_storerbnewgp : HInst< (outs), (ins u32_0Imm:$Ii, IntRegs:$Nt8), "memb(gp+#$Ii) = $Nt8.new", -tc_5bf126a6, TypeV2LDST>, Enc_ad1831, AddrModeRel { +tc_6e20402a, TypeV2LDST>, Enc_ad1831, AddrModeRel { let Inst{12-11} = 0b00; let Inst{24-21} = 0b0101; let Inst{31-27} = 0b01001; @@ -20798,15 +21123,15 @@ def S2_storerd_io : HInst< (outs), (ins IntRegs:$Rs32, s29_3Imm:$Ii, DoubleRegs:$Rtt32), "memd($Rs32+#$Ii) = $Rtt32", -tc_30b9bb4a, TypeST>, Enc_ce6828, AddrModeRel, PostInc_BaseImm { +tc_ae5babd7, TypeST>, Enc_ce6828, AddrModeRel, PostInc_BaseImm { let Inst{24-21} = 0b1110; let Inst{31-27} = 0b10100; let addrMode = BaseImmOffset; let accessSize = DoubleWordAccess; let mayStore = 1; +let BaseOpcode = "S2_storerd_io"; let CextOpcode = "S2_storerd"; let InputType = "imm"; -let BaseOpcode = "S2_storerd_io"; let isPredicable = 1; let isExtendable = 1; let opExtendable = 1; @@ -20818,7 +21143,7 @@ def S2_storerd_pbr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32), "memd($Rx32++$Mu2:brev) = $Rtt32", -tc_da97ee82, TypeST>, Enc_928ca1 { +tc_a2b365d2, TypeST>, Enc_928ca1 { let Inst{7-0} = 0b00000000; let Inst{31-21} = 0b10101111110; let addrMode = PostInc; @@ -20830,7 +21155,7 @@ def S2_storerd_pci : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_3Imm:$Ii, ModRegs:$Mu2, DoubleRegs:$Rtt32), "memd($Rx32++#$Ii:circ($Mu2)) = $Rtt32", -tc_e86aa961, TypeST>, Enc_395cc4 { +tc_b4dc7630, TypeST>, Enc_395cc4 { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{31-21} = 0b10101001110; @@ -20844,7 +21169,7 @@ def S2_storerd_pcr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32), "memd($Rx32++I:circ($Mu2)) = $Rtt32", -tc_da97ee82, TypeST>, Enc_928ca1 { +tc_a2b365d2, TypeST>, Enc_928ca1 { let Inst{7-0} = 0b00000010; let Inst{31-21} = 0b10101001110; let addrMode = PostInc; @@ -20857,7 +21182,7 @@ def S2_storerd_pi : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32), "memd($Rx32++#$Ii) = $Rtt32", -tc_da97ee82, TypeST>, Enc_85bf58, AddrModeRel, PostInc_BaseImm { +tc_a2b365d2, TypeST>, Enc_85bf58, AddrModeRel, PostInc_BaseImm { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; @@ -20865,8 +21190,8 @@ let Inst{31-21} = 0b10101011110; let addrMode = PostInc; let accessSize = DoubleWordAccess; let mayStore = 1; -let CextOpcode = "S2_storerd"; let BaseOpcode = "S2_storerd_pi"; +let CextOpcode = "S2_storerd"; let isPredicable = 1; let Constraints = "$Rx32 = $Rx32in"; } @@ -20874,7 +21199,7 @@ def S2_storerd_pr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32), "memd($Rx32++$Mu2) = $Rtt32", -tc_da97ee82, TypeST>, Enc_928ca1 { +tc_a2b365d2, TypeST>, Enc_928ca1 { let Inst{7-0} = 0b00000000; let Inst{31-21} = 0b10101101110; let addrMode = PostInc; @@ -20886,7 +21211,7 @@ def S2_storerd_zomap : HInst< (outs), (ins IntRegs:$Rs32, DoubleRegs:$Rtt32), "memd($Rs32) = $Rtt32", -tc_30b9bb4a, TypeMAPPING> { +tc_ae5babd7, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -20894,7 +21219,7 @@ def S2_storerdgp : HInst< (outs), (ins u29_3Imm:$Ii, DoubleRegs:$Rtt32), "memd(gp+#$Ii) = $Rtt32", -tc_0371abea, TypeV2LDST>, Enc_5c124a, AddrModeRel { +tc_0655b949, TypeV2LDST>, Enc_5c124a, AddrModeRel { let Inst{24-21} = 0b0110; let Inst{31-27} = 0b01001; let accessSize = DoubleWordAccess; @@ -20911,15 +21236,15 @@ def S2_storerf_io : HInst< (outs), (ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Rt32), "memh($Rs32+#$Ii) = $Rt32.h", -tc_30b9bb4a, TypeST>, Enc_e957fb, AddrModeRel, PostInc_BaseImm { +tc_ae5babd7, TypeST>, Enc_e957fb, AddrModeRel, PostInc_BaseImm { let Inst{24-21} = 0b1011; let Inst{31-27} = 0b10100; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let mayStore = 1; +let BaseOpcode = "S2_storerf_io"; let CextOpcode = "S2_storerf"; let InputType = "imm"; -let BaseOpcode = "S2_storerf_io"; let isPredicable = 1; let isExtendable = 1; let opExtendable = 1; @@ -20931,7 +21256,7 @@ def S2_storerf_pbr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), "memh($Rx32++$Mu2:brev) = $Rt32.h", -tc_da97ee82, TypeST>, Enc_d5c73f { +tc_a2b365d2, TypeST>, Enc_d5c73f { let Inst{7-0} = 0b00000000; let Inst{31-21} = 0b10101111011; let addrMode = PostInc; @@ -20943,7 +21268,7 @@ def S2_storerf_pci : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32), "memh($Rx32++#$Ii:circ($Mu2)) = $Rt32.h", -tc_e86aa961, TypeST>, Enc_935d9b { +tc_b4dc7630, TypeST>, Enc_935d9b { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{31-21} = 0b10101001011; @@ -20957,7 +21282,7 @@ def S2_storerf_pcr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), "memh($Rx32++I:circ($Mu2)) = $Rt32.h", -tc_da97ee82, TypeST>, Enc_d5c73f { +tc_a2b365d2, TypeST>, Enc_d5c73f { let Inst{7-0} = 0b00000010; let Inst{31-21} = 0b10101001011; let addrMode = PostInc; @@ -20970,7 +21295,7 @@ def S2_storerf_pi : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), "memh($Rx32++#$Ii) = $Rt32.h", -tc_da97ee82, TypeST>, Enc_052c7d, AddrModeRel, PostInc_BaseImm { +tc_a2b365d2, TypeST>, Enc_052c7d, AddrModeRel, PostInc_BaseImm { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; @@ -20978,8 +21303,8 @@ let Inst{31-21} = 0b10101011011; let addrMode = PostInc; let accessSize = HalfWordAccess; let mayStore = 1; -let CextOpcode = "S2_storerf"; let BaseOpcode = "S2_storerf_pi"; +let CextOpcode = "S2_storerf"; let isPredicable = 1; let Constraints = "$Rx32 = $Rx32in"; } @@ -20987,7 +21312,7 @@ def S2_storerf_pr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), "memh($Rx32++$Mu2) = $Rt32.h", -tc_da97ee82, TypeST>, Enc_d5c73f { +tc_a2b365d2, TypeST>, Enc_d5c73f { let Inst{7-0} = 0b00000000; let Inst{31-21} = 0b10101101011; let addrMode = PostInc; @@ -20999,7 +21324,7 @@ def S2_storerf_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memh($Rs32) = $Rt32.h", -tc_30b9bb4a, TypeMAPPING> { +tc_ae5babd7, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -21007,7 +21332,7 @@ def S2_storerfgp : HInst< (outs), (ins u31_1Imm:$Ii, IntRegs:$Rt32), "memh(gp+#$Ii) = $Rt32.h", -tc_0371abea, TypeV2LDST>, Enc_fda92c, AddrModeRel { +tc_0655b949, TypeV2LDST>, Enc_fda92c, AddrModeRel { let Inst{24-21} = 0b0011; let Inst{31-27} = 0b01001; let accessSize = HalfWordAccess; @@ -21024,15 +21349,15 @@ def S2_storerh_io : HInst< (outs), (ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Rt32), "memh($Rs32+#$Ii) = $Rt32", -tc_30b9bb4a, TypeST>, Enc_e957fb, AddrModeRel, PostInc_BaseImm { +tc_ae5babd7, TypeST>, Enc_e957fb, AddrModeRel, PostInc_BaseImm { let Inst{24-21} = 0b1010; let Inst{31-27} = 0b10100; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let mayStore = 1; +let BaseOpcode = "S2_storerh_io"; let CextOpcode = "S2_storerh"; let InputType = "imm"; -let BaseOpcode = "S2_storerh_io"; let isPredicable = 1; let isNVStorable = 1; let isExtendable = 1; @@ -21045,7 +21370,7 @@ def S2_storerh_pbr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), "memh($Rx32++$Mu2:brev) = $Rt32", -tc_da97ee82, TypeST>, Enc_d5c73f, AddrModeRel { +tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel { let Inst{7-0} = 0b00000000; let Inst{31-21} = 0b10101111010; let addrMode = PostInc; @@ -21059,7 +21384,7 @@ def S2_storerh_pci : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32), "memh($Rx32++#$Ii:circ($Mu2)) = $Rt32", -tc_e86aa961, TypeST>, Enc_935d9b, AddrModeRel { +tc_b4dc7630, TypeST>, Enc_935d9b, AddrModeRel { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{31-21} = 0b10101001010; @@ -21075,7 +21400,7 @@ def S2_storerh_pcr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), "memh($Rx32++I:circ($Mu2)) = $Rt32", -tc_da97ee82, TypeST>, Enc_d5c73f, AddrModeRel { +tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel { let Inst{7-0} = 0b00000010; let Inst{31-21} = 0b10101001010; let addrMode = PostInc; @@ -21090,7 +21415,7 @@ def S2_storerh_pi : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), "memh($Rx32++#$Ii) = $Rt32", -tc_da97ee82, TypeST>, Enc_052c7d, AddrModeRel, PostInc_BaseImm { +tc_a2b365d2, TypeST>, Enc_052c7d, AddrModeRel, PostInc_BaseImm { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; @@ -21098,8 +21423,8 @@ let Inst{31-21} = 0b10101011010; let addrMode = PostInc; let accessSize = HalfWordAccess; let mayStore = 1; -let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerh_pi"; +let CextOpcode = "S2_storerh"; let isPredicable = 1; let isNVStorable = 1; let Constraints = "$Rx32 = $Rx32in"; @@ -21108,12 +21433,13 @@ def S2_storerh_pr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), "memh($Rx32++$Mu2) = $Rt32", -tc_da97ee82, TypeST>, Enc_d5c73f { +tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel { let Inst{7-0} = 0b00000000; let Inst{31-21} = 0b10101101010; let addrMode = PostInc; let accessSize = HalfWordAccess; let mayStore = 1; +let BaseOpcode = "S2_storerh_pr"; let isNVStorable = 1; let Constraints = "$Rx32 = $Rx32in"; } @@ -21121,7 +21447,7 @@ def S2_storerh_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memh($Rs32) = $Rt32", -tc_30b9bb4a, TypeMAPPING> { +tc_ae5babd7, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -21129,7 +21455,7 @@ def S2_storerhgp : HInst< (outs), (ins u31_1Imm:$Ii, IntRegs:$Rt32), "memh(gp+#$Ii) = $Rt32", -tc_0371abea, TypeV2LDST>, Enc_fda92c, AddrModeRel { +tc_0655b949, TypeV2LDST>, Enc_fda92c, AddrModeRel { let Inst{24-21} = 0b0010; let Inst{31-27} = 0b01001; let accessSize = HalfWordAccess; @@ -21147,7 +21473,7 @@ def S2_storerhnew_io : HInst< (outs), (ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Nt8), "memh($Rs32+#$Ii) = $Nt8.new", -tc_be9602ff, TypeST>, Enc_0d8870, AddrModeRel { +tc_5deb5e47, TypeST>, Enc_0d8870, AddrModeRel { let Inst{12-11} = 0b01; let Inst{24-21} = 0b1101; let Inst{31-27} = 0b10100; @@ -21157,9 +21483,9 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storerh_io"; let CextOpcode = "S2_storerh"; let InputType = "imm"; -let BaseOpcode = "S2_storerh_io"; let isPredicable = 1; let isExtendable = 1; let opExtendable = 1; @@ -21172,7 +21498,7 @@ def S2_storerhnew_pbr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), "memh($Rx32++$Mu2:brev) = $Nt8.new", -tc_c79a189f, TypeST>, Enc_8dbe85, AddrModeRel { +tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel { let Inst{7-0} = 0b00000000; let Inst{12-11} = 0b01; let Inst{31-21} = 0b10101111101; @@ -21190,7 +21516,7 @@ def S2_storerhnew_pci : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8), "memh($Rx32++#$Ii:circ($Mu2)) = $Nt8.new", -tc_d5c0729a, TypeST>, Enc_91b9fe, AddrModeRel { +tc_addc37a8, TypeST>, Enc_91b9fe, AddrModeRel { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{12-11} = 0b01; @@ -21210,7 +21536,7 @@ def S2_storerhnew_pcr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), "memh($Rx32++I:circ($Mu2)) = $Nt8.new", -tc_c79a189f, TypeST>, Enc_8dbe85, AddrModeRel { +tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel { let Inst{7-0} = 0b00000010; let Inst{12-11} = 0b01; let Inst{31-21} = 0b10101001101; @@ -21229,7 +21555,7 @@ def S2_storerhnew_pi : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8), "memh($Rx32++#$Ii) = $Nt8.new", -tc_c79a189f, TypeST>, Enc_e26546, AddrModeRel { +tc_92240447, TypeST>, Enc_e26546, AddrModeRel { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{13-11} = 0b001; @@ -21250,7 +21576,7 @@ def S2_storerhnew_pr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), "memh($Rx32++$Mu2) = $Nt8.new", -tc_c79a189f, TypeST>, Enc_8dbe85 { +tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel { let Inst{7-0} = 0b00000000; let Inst{12-11} = 0b01; let Inst{31-21} = 0b10101101101; @@ -21260,6 +21586,7 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storerh_pr"; let opNewValue = 3; let Constraints = "$Rx32 = $Rx32in"; } @@ -21267,7 +21594,7 @@ def S2_storerhnew_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Nt8), "memh($Rs32) = $Nt8.new", -tc_be9602ff, TypeMAPPING> { +tc_5deb5e47, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 1; @@ -21276,7 +21603,7 @@ def S2_storerhnewgp : HInst< (outs), (ins u31_1Imm:$Ii, IntRegs:$Nt8), "memh(gp+#$Ii) = $Nt8.new", -tc_5bf126a6, TypeV2LDST>, Enc_bc03e5, AddrModeRel { +tc_6e20402a, TypeV2LDST>, Enc_bc03e5, AddrModeRel { let Inst{12-11} = 0b01; let Inst{24-21} = 0b0101; let Inst{31-27} = 0b01001; @@ -21298,15 +21625,15 @@ def S2_storeri_io : HInst< (outs), (ins IntRegs:$Rs32, s30_2Imm:$Ii, IntRegs:$Rt32), "memw($Rs32+#$Ii) = $Rt32", -tc_30b9bb4a, TypeST>, Enc_143445, AddrModeRel, PostInc_BaseImm { +tc_ae5babd7, TypeST>, Enc_143445, AddrModeRel, PostInc_BaseImm { let Inst{24-21} = 0b1100; let Inst{31-27} = 0b10100; let addrMode = BaseImmOffset; let accessSize = WordAccess; let mayStore = 1; +let BaseOpcode = "S2_storeri_io"; let CextOpcode = "S2_storeri"; let InputType = "imm"; -let BaseOpcode = "S2_storeri_io"; let isPredicable = 1; let isNVStorable = 1; let isExtendable = 1; @@ -21319,7 +21646,7 @@ def S2_storeri_pbr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), "memw($Rx32++$Mu2:brev) = $Rt32", -tc_da97ee82, TypeST>, Enc_d5c73f, AddrModeRel { +tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel { let Inst{7-0} = 0b00000000; let Inst{31-21} = 0b10101111100; let addrMode = PostInc; @@ -21333,7 +21660,7 @@ def S2_storeri_pci : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32), "memw($Rx32++#$Ii:circ($Mu2)) = $Rt32", -tc_e86aa961, TypeST>, Enc_79b8c8, AddrModeRel { +tc_b4dc7630, TypeST>, Enc_79b8c8, AddrModeRel { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{31-21} = 0b10101001100; @@ -21349,7 +21676,7 @@ def S2_storeri_pcr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), "memw($Rx32++I:circ($Mu2)) = $Rt32", -tc_da97ee82, TypeST>, Enc_d5c73f, AddrModeRel { +tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel { let Inst{7-0} = 0b00000010; let Inst{31-21} = 0b10101001100; let addrMode = PostInc; @@ -21364,7 +21691,7 @@ def S2_storeri_pi : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32), "memw($Rx32++#$Ii) = $Rt32", -tc_da97ee82, TypeST>, Enc_db40cd, AddrModeRel, PostInc_BaseImm { +tc_a2b365d2, TypeST>, Enc_db40cd, AddrModeRel, PostInc_BaseImm { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; @@ -21372,8 +21699,8 @@ let Inst{31-21} = 0b10101011100; let addrMode = PostInc; let accessSize = WordAccess; let mayStore = 1; -let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeri_pi"; +let CextOpcode = "S2_storeri"; let isPredicable = 1; let isNVStorable = 1; let Constraints = "$Rx32 = $Rx32in"; @@ -21382,12 +21709,13 @@ def S2_storeri_pr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), "memw($Rx32++$Mu2) = $Rt32", -tc_da97ee82, TypeST>, Enc_d5c73f { +tc_a2b365d2, TypeST>, Enc_d5c73f, AddrModeRel { let Inst{7-0} = 0b00000000; let Inst{31-21} = 0b10101101100; let addrMode = PostInc; let accessSize = WordAccess; let mayStore = 1; +let BaseOpcode = "S2_storeri_pr"; let isNVStorable = 1; let Constraints = "$Rx32 = $Rx32in"; } @@ -21395,7 +21723,7 @@ def S2_storeri_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memw($Rs32) = $Rt32", -tc_30b9bb4a, TypeMAPPING> { +tc_ae5babd7, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -21403,7 +21731,7 @@ def S2_storerigp : HInst< (outs), (ins u30_2Imm:$Ii, IntRegs:$Rt32), "memw(gp+#$Ii) = $Rt32", -tc_0371abea, TypeV2LDST>, Enc_541f26, AddrModeRel { +tc_0655b949, TypeV2LDST>, Enc_541f26, AddrModeRel { let Inst{24-21} = 0b0100; let Inst{31-27} = 0b01001; let accessSize = WordAccess; @@ -21421,7 +21749,7 @@ def S2_storerinew_io : HInst< (outs), (ins IntRegs:$Rs32, s30_2Imm:$Ii, IntRegs:$Nt8), "memw($Rs32+#$Ii) = $Nt8.new", -tc_be9602ff, TypeST>, Enc_690862, AddrModeRel { +tc_5deb5e47, TypeST>, Enc_690862, AddrModeRel { let Inst{12-11} = 0b10; let Inst{24-21} = 0b1101; let Inst{31-27} = 0b10100; @@ -21431,9 +21759,9 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storeri_io"; let CextOpcode = "S2_storeri"; let InputType = "imm"; -let BaseOpcode = "S2_storeri_io"; let isPredicable = 1; let isExtendable = 1; let opExtendable = 1; @@ -21446,7 +21774,7 @@ def S2_storerinew_pbr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), "memw($Rx32++$Mu2:brev) = $Nt8.new", -tc_c79a189f, TypeST>, Enc_8dbe85, AddrModeRel { +tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel { let Inst{7-0} = 0b00000000; let Inst{12-11} = 0b10; let Inst{31-21} = 0b10101111101; @@ -21464,7 +21792,7 @@ def S2_storerinew_pci : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8), "memw($Rx32++#$Ii:circ($Mu2)) = $Nt8.new", -tc_d5c0729a, TypeST>, Enc_3f97c8, AddrModeRel { +tc_addc37a8, TypeST>, Enc_3f97c8, AddrModeRel { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{12-11} = 0b10; @@ -21484,7 +21812,7 @@ def S2_storerinew_pcr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), "memw($Rx32++I:circ($Mu2)) = $Nt8.new", -tc_c79a189f, TypeST>, Enc_8dbe85, AddrModeRel { +tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel { let Inst{7-0} = 0b00000010; let Inst{12-11} = 0b10; let Inst{31-21} = 0b10101001101; @@ -21503,7 +21831,7 @@ def S2_storerinew_pi : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8), "memw($Rx32++#$Ii) = $Nt8.new", -tc_c79a189f, TypeST>, Enc_223005, AddrModeRel { +tc_92240447, TypeST>, Enc_223005, AddrModeRel { let Inst{2-0} = 0b000; let Inst{7-7} = 0b0; let Inst{13-11} = 0b010; @@ -21523,7 +21851,7 @@ def S2_storerinew_pr : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), "memw($Rx32++$Mu2) = $Nt8.new", -tc_c79a189f, TypeST>, Enc_8dbe85 { +tc_92240447, TypeST>, Enc_8dbe85, AddrModeRel { let Inst{7-0} = 0b00000000; let Inst{12-11} = 0b10; let Inst{31-21} = 0b10101101101; @@ -21533,6 +21861,7 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storeri_pr"; let opNewValue = 3; let Constraints = "$Rx32 = $Rx32in"; } @@ -21540,7 +21869,7 @@ def S2_storerinew_zomap : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Nt8), "memw($Rs32) = $Nt8.new", -tc_be9602ff, TypeMAPPING> { +tc_5deb5e47, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 1; @@ -21549,7 +21878,7 @@ def S2_storerinewgp : HInst< (outs), (ins u30_2Imm:$Ii, IntRegs:$Nt8), "memw(gp+#$Ii) = $Nt8.new", -tc_5bf126a6, TypeV2LDST>, Enc_78cbf0, AddrModeRel { +tc_6e20402a, TypeV2LDST>, Enc_78cbf0, AddrModeRel { let Inst{12-11} = 0b10; let Inst{24-21} = 0b0101; let Inst{31-27} = 0b01001; @@ -21571,7 +21900,7 @@ def S2_storew_locked : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "memw_locked($Rs32,$Pd4) = $Rt32", -tc_5abb5e3f, TypeST>, Enc_c2b48e { +tc_6f42bc60, TypeST>, Enc_c2b48e { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10100000101; @@ -21584,7 +21913,7 @@ def S2_svsathb : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = vsathb($Rs32)", -tc_0ae0825c, TypeS_2op>, Enc_5e2823 { +tc_9f6cd987, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001100100; let hasNewValue = 1; @@ -21595,7 +21924,7 @@ def S2_svsathub : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = vsathub($Rs32)", -tc_0ae0825c, TypeS_2op>, Enc_5e2823 { +tc_9f6cd987, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000010; let Inst{31-21} = 0b10001100100; let hasNewValue = 1; @@ -21606,7 +21935,7 @@ def S2_tableidxb : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II), "$Rx32 = tableidxb($Rs32,#$Ii,#$II):raw", -tc_bfec0f01, TypeS_2op>, Enc_cd82bc { +tc_bb831a7c, TypeS_2op>, Enc_cd82bc { let Inst{31-22} = 0b1000011100; let hasNewValue = 1; let opNewValue = 0; @@ -21617,7 +21946,7 @@ def S2_tableidxb_goodsyntax : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II), "$Rx32 = tableidxb($Rs32,#$Ii,#$II)", -tc_bfec0f01, TypeS_2op> { +tc_bb831a7c, TypeS_2op> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -21628,7 +21957,7 @@ def S2_tableidxd : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II), "$Rx32 = tableidxd($Rs32,#$Ii,#$II):raw", -tc_bfec0f01, TypeS_2op>, Enc_cd82bc { +tc_bb831a7c, TypeS_2op>, Enc_cd82bc { let Inst{31-22} = 0b1000011111; let hasNewValue = 1; let opNewValue = 0; @@ -21639,7 +21968,7 @@ def S2_tableidxd_goodsyntax : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II), "$Rx32 = tableidxd($Rs32,#$Ii,#$II)", -tc_bfec0f01, TypeS_2op> { +tc_bb831a7c, TypeS_2op> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -21649,7 +21978,7 @@ def S2_tableidxh : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II), "$Rx32 = tableidxh($Rs32,#$Ii,#$II):raw", -tc_bfec0f01, TypeS_2op>, Enc_cd82bc { +tc_bb831a7c, TypeS_2op>, Enc_cd82bc { let Inst{31-22} = 0b1000011101; let hasNewValue = 1; let opNewValue = 0; @@ -21660,7 +21989,7 @@ def S2_tableidxh_goodsyntax : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II), "$Rx32 = tableidxh($Rs32,#$Ii,#$II)", -tc_bfec0f01, TypeS_2op> { +tc_bb831a7c, TypeS_2op> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -21670,7 +21999,7 @@ def S2_tableidxw : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II), "$Rx32 = tableidxw($Rs32,#$Ii,#$II):raw", -tc_bfec0f01, TypeS_2op>, Enc_cd82bc { +tc_bb831a7c, TypeS_2op>, Enc_cd82bc { let Inst{31-22} = 0b1000011110; let hasNewValue = 1; let opNewValue = 0; @@ -21681,7 +22010,7 @@ def S2_tableidxw_goodsyntax : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II), "$Rx32 = tableidxw($Rs32,#$Ii,#$II)", -tc_bfec0f01, TypeS_2op> { +tc_bb831a7c, TypeS_2op> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -21691,7 +22020,7 @@ def S2_togglebit_i : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = togglebit($Rs32,#$Ii)", -tc_946df596, TypeS_2op>, Enc_a05677 { +tc_5da50c4b, TypeS_2op>, Enc_a05677 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001100110; @@ -21702,7 +22031,7 @@ def S2_togglebit_r : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = togglebit($Rs32,$Rt32)", -tc_946df596, TypeS_3op>, Enc_5ab2be { +tc_5da50c4b, TypeS_3op>, Enc_5ab2be { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000110100; @@ -21713,7 +22042,7 @@ def S2_tstbit_i : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Pd4 = tstbit($Rs32,#$Ii)", -tc_643b4717, TypeS_2op>, Enc_83ee64 { +tc_a1297125, TypeS_2op>, Enc_83ee64 { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10000101000; @@ -21722,7 +22051,7 @@ def S2_tstbit_r : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = tstbit($Rs32,$Rt32)", -tc_85d5d03f, TypeS_3op>, Enc_c2b48e { +tc_4a55d03c, TypeS_3op>, Enc_c2b48e { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111000; @@ -21731,7 +22060,7 @@ def S2_valignib : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32, u3_0Imm:$Ii), "$Rdd32 = valignb($Rtt32,$Rss32,#$Ii)", -tc_b4b5c03a, TypeS_3op>, Enc_729ff7 { +tc_6fc5dbea, TypeS_3op>, Enc_729ff7 { let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000000000; } @@ -21739,7 +22068,7 @@ def S2_valignrb : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32, PredRegs:$Pu4), "$Rdd32 = valignb($Rtt32,$Rss32,$Pu4)", -tc_b4b5c03a, TypeS_3op>, Enc_8c6530 { +tc_6fc5dbea, TypeS_3op>, Enc_8c6530 { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000010000; @@ -21748,7 +22077,7 @@ def S2_vcnegh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = vcnegh($Rss32,$Rt32)", -tc_779080bf, TypeS_3op>, Enc_927852 { +tc_8a825db2, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011110; @@ -21759,7 +22088,7 @@ def S2_vcrotate : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rdd32 = vcrotate($Rss32,$Rt32)", -tc_002cb246, TypeS_3op>, Enc_927852 { +tc_0dfac0a7, TypeS_3op>, Enc_927852 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000011110; @@ -21770,7 +22099,7 @@ def S2_vrcnegh : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), "$Rxx32 += vrcnegh($Rss32,$Rt32)", -tc_d773585a, TypeS_3op>, Enc_1aa186 { +tc_7f8ae742, TypeS_3op>, Enc_1aa186 { let Inst{7-5} = 0b111; let Inst{13-13} = 0b1; let Inst{31-21} = 0b11001011001; @@ -21781,7 +22110,7 @@ def S2_vrndpackwh : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = vrndwh($Rss32)", -tc_14b5c689, TypeS_2op>, Enc_90cd8b { +tc_e3d699e3, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10001000100; let hasNewValue = 1; @@ -21792,7 +22121,7 @@ def S2_vrndpackwhs : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = vrndwh($Rss32):sat", -tc_cf8126ae, TypeS_2op>, Enc_90cd8b { +tc_d61dfdc3, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10001000100; let hasNewValue = 1; @@ -21804,7 +22133,7 @@ def S2_vsathb : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = vsathb($Rss32)", -tc_0ae0825c, TypeS_2op>, Enc_90cd8b { +tc_9f6cd987, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10001000000; let hasNewValue = 1; @@ -21815,7 +22144,7 @@ def S2_vsathb_nopack : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = vsathb($Rss32)", -tc_0ae0825c, TypeS_2op>, Enc_b9c5fb { +tc_9f6cd987, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000111; let Inst{31-21} = 0b10000000000; let Defs = [USR_OVF]; @@ -21824,7 +22153,7 @@ def S2_vsathub : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = vsathub($Rss32)", -tc_0ae0825c, TypeS_2op>, Enc_90cd8b { +tc_9f6cd987, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001000000; let hasNewValue = 1; @@ -21835,7 +22164,7 @@ def S2_vsathub_nopack : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = vsathub($Rss32)", -tc_0ae0825c, TypeS_2op>, Enc_b9c5fb { +tc_9f6cd987, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10000000000; let Defs = [USR_OVF]; @@ -21844,7 +22173,7 @@ def S2_vsatwh : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = vsatwh($Rss32)", -tc_0ae0825c, TypeS_2op>, Enc_90cd8b { +tc_9f6cd987, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000010; let Inst{31-21} = 0b10001000000; let hasNewValue = 1; @@ -21855,7 +22184,7 @@ def S2_vsatwh_nopack : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = vsatwh($Rss32)", -tc_0ae0825c, TypeS_2op>, Enc_b9c5fb { +tc_9f6cd987, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10000000000; let Defs = [USR_OVF]; @@ -21864,7 +22193,7 @@ def S2_vsatwuh : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = vsatwuh($Rss32)", -tc_0ae0825c, TypeS_2op>, Enc_90cd8b { +tc_9f6cd987, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10001000000; let hasNewValue = 1; @@ -21875,7 +22204,7 @@ def S2_vsatwuh_nopack : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32), "$Rdd32 = vsatwuh($Rss32)", -tc_0ae0825c, TypeS_2op>, Enc_b9c5fb { +tc_9f6cd987, TypeS_2op>, Enc_b9c5fb { let Inst{13-5} = 0b000000101; let Inst{31-21} = 0b10000000000; let Defs = [USR_OVF]; @@ -21884,7 +22213,7 @@ def S2_vsplatrb : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32), "$Rd32 = vsplatb($Rs32)", -tc_0ae0825c, TypeS_2op>, Enc_5e2823 { +tc_9f6cd987, TypeS_2op>, Enc_5e2823 { let Inst{13-5} = 0b000000111; let Inst{31-21} = 0b10001100010; let hasNewValue = 1; @@ -21896,7 +22225,7 @@ def S2_vsplatrh : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = vsplath($Rs32)", -tc_0ae0825c, TypeS_2op>, Enc_3a3d62 { +tc_9f6cd987, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000010; let Inst{31-21} = 0b10000100010; let isReMaterializable = 1; @@ -21906,7 +22235,7 @@ def S2_vspliceib : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, u3_0Imm:$Ii), "$Rdd32 = vspliceb($Rss32,$Rtt32,#$Ii)", -tc_b4b5c03a, TypeS_3op>, Enc_d50cd3 { +tc_6fc5dbea, TypeS_3op>, Enc_d50cd3 { let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000000100; } @@ -21914,7 +22243,7 @@ def S2_vsplicerb : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Pu4), "$Rdd32 = vspliceb($Rss32,$Rtt32,$Pu4)", -tc_b4b5c03a, TypeS_3op>, Enc_dbd70c { +tc_6fc5dbea, TypeS_3op>, Enc_dbd70c { let Inst{7-7} = 0b0; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000010100; @@ -21923,7 +22252,7 @@ def S2_vsxtbh : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = vsxtbh($Rs32)", -tc_0ae0825c, TypeS_2op>, Enc_3a3d62 { +tc_9f6cd987, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10000100000; let isReMaterializable = 1; @@ -21933,7 +22262,7 @@ def S2_vsxthw : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = vsxthw($Rs32)", -tc_0ae0825c, TypeS_2op>, Enc_3a3d62 { +tc_9f6cd987, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10000100000; let isReMaterializable = 1; @@ -21943,7 +22272,7 @@ def S2_vtrunehb : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = vtrunehb($Rss32)", -tc_0ae0825c, TypeS_2op>, Enc_90cd8b { +tc_9f6cd987, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000010; let Inst{31-21} = 0b10001000100; let hasNewValue = 1; @@ -21953,7 +22282,7 @@ def S2_vtrunewh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vtrunewh($Rss32,$Rtt32)", -tc_946df596, TypeS_3op>, Enc_a56825 { +tc_5da50c4b, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001100; @@ -21962,7 +22291,7 @@ def S2_vtrunohb : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = vtrunohb($Rss32)", -tc_0ae0825c, TypeS_2op>, Enc_90cd8b { +tc_9f6cd987, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001000100; let hasNewValue = 1; @@ -21972,7 +22301,7 @@ def S2_vtrunowh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vtrunowh($Rss32,$Rtt32)", -tc_946df596, TypeS_3op>, Enc_a56825 { +tc_5da50c4b, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001100; @@ -21981,7 +22310,7 @@ def S2_vzxtbh : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = vzxtbh($Rs32)", -tc_0ae0825c, TypeS_2op>, Enc_3a3d62 { +tc_9f6cd987, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000010; let Inst{31-21} = 0b10000100000; let isReMaterializable = 1; @@ -21991,7 +22320,7 @@ def S2_vzxthw : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = vzxthw($Rs32)", -tc_0ae0825c, TypeS_2op>, Enc_3a3d62 { +tc_9f6cd987, TypeS_2op>, Enc_3a3d62 { let Inst{13-5} = 0b000000110; let Inst{31-21} = 0b10000100000; let isReMaterializable = 1; @@ -22001,7 +22330,7 @@ def S4_addaddi : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Ru32, s32_0Imm:$Ii), "$Rd32 = add($Rs32,add($Ru32,#$Ii))", -tc_f675fee8, TypeALU64>, Enc_8b8d61 { +tc_2c13e7f5, TypeALU64>, Enc_8b8d61, Requires<[UseCompound]> { let Inst{31-23} = 0b110110110; let hasNewValue = 1; let opNewValue = 0; @@ -22016,7 +22345,7 @@ def S4_addi_asl_ri : HInst< (outs IntRegs:$Rx32), (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), "$Rx32 = add(#$Ii,asl($Rx32in,#$II))", -tc_f675fee8, TypeALU64>, Enc_c31910 { +tc_2c13e7f5, TypeALU64>, Enc_c31910, Requires<[UseCompound]> { let Inst{2-0} = 0b100; let Inst{4-4} = 0b0; let Inst{31-24} = 0b11011110; @@ -22034,7 +22363,7 @@ def S4_addi_lsr_ri : HInst< (outs IntRegs:$Rx32), (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), "$Rx32 = add(#$Ii,lsr($Rx32in,#$II))", -tc_f675fee8, TypeALU64>, Enc_c31910 { +tc_2c13e7f5, TypeALU64>, Enc_c31910, Requires<[UseCompound]> { let Inst{2-0} = 0b100; let Inst{4-4} = 0b1; let Inst{31-24} = 0b11011110; @@ -22052,7 +22381,7 @@ def S4_andi_asl_ri : HInst< (outs IntRegs:$Rx32), (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), "$Rx32 = and(#$Ii,asl($Rx32in,#$II))", -tc_f429765c, TypeALU64>, Enc_c31910 { +tc_a4e22bbd, TypeALU64>, Enc_c31910, Requires<[UseCompound]> { let Inst{2-0} = 0b000; let Inst{4-4} = 0b0; let Inst{31-24} = 0b11011110; @@ -22070,7 +22399,7 @@ def S4_andi_lsr_ri : HInst< (outs IntRegs:$Rx32), (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), "$Rx32 = and(#$Ii,lsr($Rx32in,#$II))", -tc_f429765c, TypeALU64>, Enc_c31910 { +tc_a4e22bbd, TypeALU64>, Enc_c31910, Requires<[UseCompound]> { let Inst{2-0} = 0b000; let Inst{4-4} = 0b1; let Inst{31-24} = 0b11011110; @@ -22088,7 +22417,7 @@ def S4_clbaddi : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s6_0Imm:$Ii), "$Rd32 = add(clb($Rs32),#$Ii)", -tc_002cb246, TypeS_2op>, Enc_9fae8a { +tc_a08b630b, TypeS_2op>, Enc_9fae8a { let Inst{7-5} = 0b000; let Inst{31-21} = 0b10001100001; let hasNewValue = 1; @@ -22099,7 +22428,7 @@ def S4_clbpaddi : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, s6_0Imm:$Ii), "$Rd32 = add(clb($Rss32),#$Ii)", -tc_002cb246, TypeS_2op>, Enc_a1640c { +tc_a08b630b, TypeS_2op>, Enc_a1640c { let Inst{7-5} = 0b010; let Inst{31-21} = 0b10001000011; let hasNewValue = 1; @@ -22110,7 +22439,7 @@ def S4_clbpnorm : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = normamt($Rss32)", -tc_14b5c689, TypeS_2op>, Enc_90cd8b { +tc_a7bdb22c, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000000; let Inst{31-21} = 0b10001000011; let hasNewValue = 1; @@ -22121,7 +22450,7 @@ def S4_extract : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II), "$Rd32 = extract($Rs32,#$Ii,#$II)", -tc_f675fee8, TypeS_2op>, Enc_b388cf { +tc_2c13e7f5, TypeS_2op>, Enc_b388cf { let Inst{13-13} = 0b0; let Inst{31-23} = 0b100011011; let hasNewValue = 1; @@ -22132,7 +22461,7 @@ def S4_extract_rp : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, DoubleRegs:$Rtt32), "$Rd32 = extract($Rs32,$Rtt32)", -tc_002cb246, TypeS_3op>, Enc_e07374 { +tc_a08b630b, TypeS_3op>, Enc_e07374 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11001001000; @@ -22144,7 +22473,7 @@ def S4_extractp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II), "$Rdd32 = extract($Rss32,#$Ii,#$II)", -tc_f675fee8, TypeS_2op>, Enc_b84c4c { +tc_2c13e7f5, TypeS_2op>, Enc_b84c4c { let Inst{31-24} = 0b10001010; let prefersSlot3 = 1; } @@ -22152,7 +22481,7 @@ def S4_extractp_rp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = extract($Rss32,$Rtt32)", -tc_002cb246, TypeS_3op>, Enc_a56825 { +tc_a08b630b, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001110; @@ -22162,7 +22491,7 @@ def S4_lsli : HInst< (outs IntRegs:$Rd32), (ins s6_0Imm:$Ii, IntRegs:$Rt32), "$Rd32 = lsl(#$Ii,$Rt32)", -tc_946df596, TypeS_3op>, Enc_fef969 { +tc_5da50c4b, TypeS_3op>, Enc_fef969 { let Inst{7-6} = 0b11; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000110100; @@ -22173,7 +22502,7 @@ def S4_ntstbit_i : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Pd4 = !tstbit($Rs32,#$Ii)", -tc_643b4717, TypeS_2op>, Enc_83ee64 { +tc_a1297125, TypeS_2op>, Enc_83ee64 { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10000101001; @@ -22182,7 +22511,7 @@ def S4_ntstbit_r : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Pd4 = !tstbit($Rs32,$Rt32)", -tc_85d5d03f, TypeS_3op>, Enc_c2b48e { +tc_4a55d03c, TypeS_3op>, Enc_c2b48e { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000111001; @@ -22191,7 +22520,7 @@ def S4_or_andi : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii), "$Rx32 |= and($Rs32,#$Ii)", -tc_f429765c, TypeALU64>, Enc_b0e9d8 { +tc_a4e22bbd, TypeALU64>, Enc_b0e9d8 { let Inst{31-22} = 0b1101101000; let hasNewValue = 1; let opNewValue = 0; @@ -22208,7 +22537,7 @@ def S4_or_andix : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Ru32, IntRegs:$Rx32in, s32_0Imm:$Ii), "$Rx32 = or($Ru32,and($Rx32in,#$Ii))", -tc_f429765c, TypeALU64>, Enc_b4e6cf { +tc_a4e22bbd, TypeALU64>, Enc_b4e6cf, Requires<[UseCompound]> { let Inst{31-22} = 0b1101101001; let hasNewValue = 1; let opNewValue = 0; @@ -22224,7 +22553,7 @@ def S4_or_ori : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii), "$Rx32 |= or($Rs32,#$Ii)", -tc_f429765c, TypeALU64>, Enc_b0e9d8 { +tc_a4e22bbd, TypeALU64>, Enc_b0e9d8 { let Inst{31-22} = 0b1101101010; let hasNewValue = 1; let opNewValue = 0; @@ -22241,7 +22570,7 @@ def S4_ori_asl_ri : HInst< (outs IntRegs:$Rx32), (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), "$Rx32 = or(#$Ii,asl($Rx32in,#$II))", -tc_f429765c, TypeALU64>, Enc_c31910 { +tc_a4e22bbd, TypeALU64>, Enc_c31910, Requires<[UseCompound]> { let Inst{2-0} = 0b010; let Inst{4-4} = 0b0; let Inst{31-24} = 0b11011110; @@ -22259,7 +22588,7 @@ def S4_ori_lsr_ri : HInst< (outs IntRegs:$Rx32), (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), "$Rx32 = or(#$Ii,lsr($Rx32in,#$II))", -tc_f429765c, TypeALU64>, Enc_c31910 { +tc_a4e22bbd, TypeALU64>, Enc_c31910, Requires<[UseCompound]> { let Inst{2-0} = 0b010; let Inst{4-4} = 0b1; let Inst{31-24} = 0b11011110; @@ -22277,7 +22606,7 @@ def S4_parity : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = parity($Rs32,$Rt32)", -tc_002cb246, TypeALU64>, Enc_5ab2be { +tc_a08b630b, TypeALU64>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101111; @@ -22289,7 +22618,7 @@ def S4_pstorerbf_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memb(#$Ii) = $Rt32", -tc_362c6592, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; @@ -22300,8 +22629,8 @@ let addrMode = Absolute; let accessSize = ByteAccess; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerbabs"; +let CextOpcode = "S2_storerb"; let isNVStorable = 1; let DecoderNamespace = "MustExtend"; let isExtendable = 1; @@ -22314,23 +22643,23 @@ def S4_pstorerbf_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memb($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_3962fa26, TypeST>, Enc_6339d5, AddrModeRel { +tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110101000; let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = BaseRegOffset; let accessSize = ByteAccess; let mayStore = 1; +let BaseOpcode = "S4_storerb_rr"; let CextOpcode = "S2_storerb"; let InputType = "reg"; -let BaseOpcode = "S4_storerb_rr"; let isNVStorable = 1; } def S4_pstorerbfnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memb(#$Ii) = $Rt32", -tc_da4a37ed, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -22342,8 +22671,8 @@ let accessSize = ByteAccess; let isPredicatedNew = 1; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerbabs"; +let CextOpcode = "S2_storerb"; let isNVStorable = 1; let DecoderNamespace = "MustExtend"; let isExtendable = 1; @@ -22356,7 +22685,7 @@ def S4_pstorerbfnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memb($Rs32+#$Ii) = $Rt32", -tc_da97ee82, TypeV2LDST>, Enc_da8d43, AddrModeRel { +tc_a2b365d2, TypeV2LDST>, Enc_da8d43, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000110000; let isPredicated = 1; @@ -22365,9 +22694,9 @@ let addrMode = BaseImmOffset; let accessSize = ByteAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S2_storerb_io"; let CextOpcode = "S2_storerb"; let InputType = "imm"; -let BaseOpcode = "S2_storerb_io"; let isNVStorable = 1; let isExtendable = 1; let opExtendable = 2; @@ -22379,7 +22708,7 @@ def S4_pstorerbfnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_40116ca8, TypeST>, Enc_6339d5, AddrModeRel { +tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110111000; let isPredicated = 1; let isPredicatedFalse = 1; @@ -22387,16 +22716,16 @@ let addrMode = BaseRegOffset; let accessSize = ByteAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S4_storerb_rr"; let CextOpcode = "S2_storerb"; let InputType = "reg"; -let BaseOpcode = "S4_storerb_rr"; let isNVStorable = 1; } def S4_pstorerbfnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pv4.new) memb($Rs32) = $Rt32", -tc_da97ee82, TypeMAPPING> { +tc_a2b365d2, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -22404,7 +22733,7 @@ def S4_pstorerbnewf_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4) memb(#$Ii) = $Nt8.new", -tc_4b68bce4, TypeST>, Enc_44215c, AddrModeRel { +tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-11} = 0b000; @@ -22418,8 +22747,8 @@ let isNewValue = 1; let isExtended = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerbabs"; +let CextOpcode = "S2_storerb"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -22432,7 +22761,7 @@ def S4_pstorerbnewf_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_e95795ec, TypeST>, Enc_47ee5e, AddrModeRel { +tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel { let Inst{4-3} = 0b00; let Inst{31-21} = 0b00110101101; let isPredicated = 1; @@ -22443,16 +22772,16 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S4_storerb_rr"; let CextOpcode = "S2_storerb"; let InputType = "reg"; -let BaseOpcode = "S4_storerb_rr"; let opNewValue = 4; } def S4_pstorerbnewfnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4.new) memb(#$Ii) = $Nt8.new", -tc_d2e63d61, TypeST>, Enc_44215c, AddrModeRel { +tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-11} = 0b100; @@ -22467,8 +22796,8 @@ let isNewValue = 1; let isExtended = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerbabs"; +let CextOpcode = "S2_storerb"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -22481,7 +22810,7 @@ def S4_pstorerbnewfnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4.new) memb($Rs32+#$Ii) = $Nt8.new", -tc_c79a189f, TypeV2LDST>, Enc_585242, AddrModeRel { +tc_92240447, TypeV2LDST>, Enc_585242, AddrModeRel { let Inst{2-2} = 0b0; let Inst{12-11} = 0b00; let Inst{31-21} = 0b01000110101; @@ -22494,9 +22823,9 @@ let isPredicatedNew = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storerb_io"; let CextOpcode = "S2_storerb"; let InputType = "imm"; -let BaseOpcode = "S2_storerb_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -22508,7 +22837,7 @@ def S4_pstorerbnewfnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_b90a29b1, TypeST>, Enc_47ee5e, AddrModeRel { +tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel { let Inst{4-3} = 0b00; let Inst{31-21} = 0b00110111101; let isPredicated = 1; @@ -22520,16 +22849,16 @@ let isPredicatedNew = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S4_storerb_rr"; let CextOpcode = "S2_storerb"; let InputType = "reg"; -let BaseOpcode = "S4_storerb_rr"; let opNewValue = 4; } def S4_pstorerbnewfnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), "if (!$Pv4.new) memb($Rs32) = $Nt8.new", -tc_c79a189f, TypeMAPPING> { +tc_92240447, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 2; @@ -22538,7 +22867,7 @@ def S4_pstorerbnewt_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4) memb(#$Ii) = $Nt8.new", -tc_4b68bce4, TypeST>, Enc_44215c, AddrModeRel { +tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-11} = 0b000; @@ -22551,8 +22880,8 @@ let isNewValue = 1; let isExtended = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerbabs"; +let CextOpcode = "S2_storerb"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -22565,7 +22894,7 @@ def S4_pstorerbnewt_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_e95795ec, TypeST>, Enc_47ee5e, AddrModeRel { +tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel { let Inst{4-3} = 0b00; let Inst{31-21} = 0b00110100101; let isPredicated = 1; @@ -22575,16 +22904,16 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S4_storerb_rr"; let CextOpcode = "S2_storerb"; let InputType = "reg"; -let BaseOpcode = "S4_storerb_rr"; let opNewValue = 4; } def S4_pstorerbnewtnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4.new) memb(#$Ii) = $Nt8.new", -tc_d2e63d61, TypeST>, Enc_44215c, AddrModeRel { +tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-11} = 0b100; @@ -22598,8 +22927,8 @@ let isNewValue = 1; let isExtended = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerbabs"; +let CextOpcode = "S2_storerb"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -22612,7 +22941,7 @@ def S4_pstorerbnewtnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4.new) memb($Rs32+#$Ii) = $Nt8.new", -tc_c79a189f, TypeV2LDST>, Enc_585242, AddrModeRel { +tc_92240447, TypeV2LDST>, Enc_585242, AddrModeRel { let Inst{2-2} = 0b0; let Inst{12-11} = 0b00; let Inst{31-21} = 0b01000010101; @@ -22624,9 +22953,9 @@ let isPredicatedNew = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storerb_io"; let CextOpcode = "S2_storerb"; let InputType = "imm"; -let BaseOpcode = "S2_storerb_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -22638,7 +22967,7 @@ def S4_pstorerbnewtnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_b90a29b1, TypeST>, Enc_47ee5e, AddrModeRel { +tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel { let Inst{4-3} = 0b00; let Inst{31-21} = 0b00110110101; let isPredicated = 1; @@ -22649,16 +22978,16 @@ let isPredicatedNew = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S4_storerb_rr"; let CextOpcode = "S2_storerb"; let InputType = "reg"; -let BaseOpcode = "S4_storerb_rr"; let opNewValue = 4; } def S4_pstorerbnewtnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), "if ($Pv4.new) memb($Rs32) = $Nt8.new", -tc_c79a189f, TypeMAPPING> { +tc_92240447, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 2; @@ -22667,7 +22996,7 @@ def S4_pstorerbt_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memb(#$Ii) = $Rt32", -tc_362c6592, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; @@ -22677,8 +23006,8 @@ let addrMode = Absolute; let accessSize = ByteAccess; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerbabs"; +let CextOpcode = "S2_storerb"; let isNVStorable = 1; let DecoderNamespace = "MustExtend"; let isExtendable = 1; @@ -22691,22 +23020,22 @@ def S4_pstorerbt_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memb($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_3962fa26, TypeST>, Enc_6339d5, AddrModeRel { +tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110100000; let isPredicated = 1; let addrMode = BaseRegOffset; let accessSize = ByteAccess; let mayStore = 1; +let BaseOpcode = "S4_storerb_rr"; let CextOpcode = "S2_storerb"; let InputType = "reg"; -let BaseOpcode = "S4_storerb_rr"; let isNVStorable = 1; } def S4_pstorerbtnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memb(#$Ii) = $Rt32", -tc_da4a37ed, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -22717,8 +23046,8 @@ let accessSize = ByteAccess; let isPredicatedNew = 1; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerb"; let BaseOpcode = "S2_storerbabs"; +let CextOpcode = "S2_storerb"; let isNVStorable = 1; let DecoderNamespace = "MustExtend"; let isExtendable = 1; @@ -22731,7 +23060,7 @@ def S4_pstorerbtnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memb($Rs32+#$Ii) = $Rt32", -tc_da97ee82, TypeV2LDST>, Enc_da8d43, AddrModeRel { +tc_a2b365d2, TypeV2LDST>, Enc_da8d43, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000010000; let isPredicated = 1; @@ -22739,9 +23068,9 @@ let addrMode = BaseImmOffset; let accessSize = ByteAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S2_storerb_io"; let CextOpcode = "S2_storerb"; let InputType = "imm"; -let BaseOpcode = "S2_storerb_io"; let isNVStorable = 1; let isExtendable = 1; let opExtendable = 2; @@ -22753,23 +23082,23 @@ def S4_pstorerbtnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_40116ca8, TypeST>, Enc_6339d5, AddrModeRel { +tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110110000; let isPredicated = 1; let addrMode = BaseRegOffset; let accessSize = ByteAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S4_storerb_rr"; let CextOpcode = "S2_storerb"; let InputType = "reg"; -let BaseOpcode = "S4_storerb_rr"; let isNVStorable = 1; } def S4_pstorerbtnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pv4.new) memb($Rs32) = $Rt32", -tc_da97ee82, TypeMAPPING> { +tc_a2b365d2, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -22777,7 +23106,7 @@ def S4_pstorerdf_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32), "if (!$Pv4) memd(#$Ii) = $Rtt32", -tc_362c6592, TypeST>, Enc_50b5ac, AddrModeRel { +tc_ba9255a6, TypeST>, Enc_50b5ac, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; @@ -22788,8 +23117,8 @@ let addrMode = Absolute; let accessSize = DoubleWordAccess; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerd"; let BaseOpcode = "S2_storerdabs"; +let CextOpcode = "S2_storerd"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -22801,22 +23130,22 @@ def S4_pstorerdf_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32), "if (!$Pv4) memd($Rs32+$Ru32<<#$Ii) = $Rtt32", -tc_3962fa26, TypeST>, Enc_1a9974, AddrModeRel { +tc_1fe4ab69, TypeST>, Enc_1a9974, AddrModeRel { let Inst{31-21} = 0b00110101110; let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = BaseRegOffset; let accessSize = DoubleWordAccess; let mayStore = 1; +let BaseOpcode = "S2_storerd_rr"; let CextOpcode = "S2_storerd"; let InputType = "reg"; -let BaseOpcode = "S2_storerd_rr"; } def S4_pstorerdfnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32), "if (!$Pv4.new) memd(#$Ii) = $Rtt32", -tc_da4a37ed, TypeST>, Enc_50b5ac, AddrModeRel { +tc_bb07f2c5, TypeST>, Enc_50b5ac, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -22828,8 +23157,8 @@ let accessSize = DoubleWordAccess; let isPredicatedNew = 1; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerd"; let BaseOpcode = "S2_storerdabs"; +let CextOpcode = "S2_storerd"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -22841,7 +23170,7 @@ def S4_pstorerdfnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32), "if (!$Pv4.new) memd($Rs32+#$Ii) = $Rtt32", -tc_da97ee82, TypeV2LDST>, Enc_57a33e, AddrModeRel { +tc_a2b365d2, TypeV2LDST>, Enc_57a33e, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000110110; let isPredicated = 1; @@ -22850,9 +23179,9 @@ let addrMode = BaseImmOffset; let accessSize = DoubleWordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S2_storerd_io"; let CextOpcode = "S2_storerd"; let InputType = "imm"; -let BaseOpcode = "S2_storerd_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -22863,7 +23192,7 @@ def S4_pstorerdfnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32), "if (!$Pv4.new) memd($Rs32+$Ru32<<#$Ii) = $Rtt32", -tc_40116ca8, TypeST>, Enc_1a9974, AddrModeRel { +tc_8e82e8ca, TypeST>, Enc_1a9974, AddrModeRel { let Inst{31-21} = 0b00110111110; let isPredicated = 1; let isPredicatedFalse = 1; @@ -22871,15 +23200,15 @@ let addrMode = BaseRegOffset; let accessSize = DoubleWordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S2_storerd_rr"; let CextOpcode = "S2_storerd"; let InputType = "reg"; -let BaseOpcode = "S2_storerd_rr"; } def S4_pstorerdfnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32), "if (!$Pv4.new) memd($Rs32) = $Rtt32", -tc_da97ee82, TypeMAPPING> { +tc_a2b365d2, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -22887,7 +23216,7 @@ def S4_pstorerdt_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32), "if ($Pv4) memd(#$Ii) = $Rtt32", -tc_362c6592, TypeST>, Enc_50b5ac, AddrModeRel { +tc_ba9255a6, TypeST>, Enc_50b5ac, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; @@ -22897,8 +23226,8 @@ let addrMode = Absolute; let accessSize = DoubleWordAccess; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerd"; let BaseOpcode = "S2_storerdabs"; +let CextOpcode = "S2_storerd"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -22910,21 +23239,21 @@ def S4_pstorerdt_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32), "if ($Pv4) memd($Rs32+$Ru32<<#$Ii) = $Rtt32", -tc_3962fa26, TypeST>, Enc_1a9974, AddrModeRel { +tc_1fe4ab69, TypeST>, Enc_1a9974, AddrModeRel { let Inst{31-21} = 0b00110100110; let isPredicated = 1; let addrMode = BaseRegOffset; let accessSize = DoubleWordAccess; let mayStore = 1; +let BaseOpcode = "S2_storerd_rr"; let CextOpcode = "S2_storerd"; let InputType = "reg"; -let BaseOpcode = "S2_storerd_rr"; } def S4_pstorerdtnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32), "if ($Pv4.new) memd(#$Ii) = $Rtt32", -tc_da4a37ed, TypeST>, Enc_50b5ac, AddrModeRel { +tc_bb07f2c5, TypeST>, Enc_50b5ac, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -22935,8 +23264,8 @@ let accessSize = DoubleWordAccess; let isPredicatedNew = 1; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerd"; let BaseOpcode = "S2_storerdabs"; +let CextOpcode = "S2_storerd"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -22948,7 +23277,7 @@ def S4_pstorerdtnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32), "if ($Pv4.new) memd($Rs32+#$Ii) = $Rtt32", -tc_da97ee82, TypeV2LDST>, Enc_57a33e, AddrModeRel { +tc_a2b365d2, TypeV2LDST>, Enc_57a33e, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000010110; let isPredicated = 1; @@ -22956,9 +23285,9 @@ let addrMode = BaseImmOffset; let accessSize = DoubleWordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S2_storerd_io"; let CextOpcode = "S2_storerd"; let InputType = "imm"; -let BaseOpcode = "S2_storerd_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -22969,22 +23298,22 @@ def S4_pstorerdtnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32), "if ($Pv4.new) memd($Rs32+$Ru32<<#$Ii) = $Rtt32", -tc_40116ca8, TypeST>, Enc_1a9974, AddrModeRel { +tc_8e82e8ca, TypeST>, Enc_1a9974, AddrModeRel { let Inst{31-21} = 0b00110110110; let isPredicated = 1; let addrMode = BaseRegOffset; let accessSize = DoubleWordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S2_storerd_rr"; let CextOpcode = "S2_storerd"; let InputType = "reg"; -let BaseOpcode = "S2_storerd_rr"; } def S4_pstorerdtnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32), "if ($Pv4.new) memd($Rs32) = $Rtt32", -tc_da97ee82, TypeMAPPING> { +tc_a2b365d2, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -22992,7 +23321,7 @@ def S4_pstorerff_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memh(#$Ii) = $Rt32.h", -tc_362c6592, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; @@ -23003,8 +23332,8 @@ let addrMode = Absolute; let accessSize = HalfWordAccess; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerf"; let BaseOpcode = "S2_storerfabs"; +let CextOpcode = "S2_storerf"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -23016,22 +23345,22 @@ def S4_pstorerff_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h", -tc_3962fa26, TypeST>, Enc_6339d5, AddrModeRel { +tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110101011; let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let mayStore = 1; +let BaseOpcode = "S4_storerf_rr"; let CextOpcode = "S2_storerf"; let InputType = "reg"; -let BaseOpcode = "S4_storerf_rr"; } def S4_pstorerffnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memh(#$Ii) = $Rt32.h", -tc_da4a37ed, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -23043,8 +23372,8 @@ let accessSize = HalfWordAccess; let isPredicatedNew = 1; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerf"; let BaseOpcode = "S2_storerfabs"; +let CextOpcode = "S2_storerf"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -23056,7 +23385,7 @@ def S4_pstorerffnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memh($Rs32+#$Ii) = $Rt32.h", -tc_da97ee82, TypeV2LDST>, Enc_e8c45e, AddrModeRel { +tc_a2b365d2, TypeV2LDST>, Enc_e8c45e, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000110011; let isPredicated = 1; @@ -23065,9 +23394,9 @@ let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S2_storerf_io"; let CextOpcode = "S2_storerf"; let InputType = "imm"; -let BaseOpcode = "S2_storerf_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -23078,7 +23407,7 @@ def S4_pstorerffnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h", -tc_40116ca8, TypeST>, Enc_6339d5, AddrModeRel { +tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110111011; let isPredicated = 1; let isPredicatedFalse = 1; @@ -23086,15 +23415,15 @@ let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S4_storerf_rr"; let CextOpcode = "S2_storerf"; let InputType = "reg"; -let BaseOpcode = "S4_storerf_rr"; } def S4_pstorerffnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pv4.new) memh($Rs32) = $Rt32.h", -tc_da97ee82, TypeMAPPING> { +tc_a2b365d2, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -23102,7 +23431,7 @@ def S4_pstorerft_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memh(#$Ii) = $Rt32.h", -tc_362c6592, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; @@ -23112,8 +23441,8 @@ let addrMode = Absolute; let accessSize = HalfWordAccess; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerf"; let BaseOpcode = "S2_storerfabs"; +let CextOpcode = "S2_storerf"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -23125,21 +23454,21 @@ def S4_pstorerft_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h", -tc_3962fa26, TypeST>, Enc_6339d5, AddrModeRel { +tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110100011; let isPredicated = 1; let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let mayStore = 1; +let BaseOpcode = "S4_storerf_rr"; let CextOpcode = "S2_storerf"; let InputType = "reg"; -let BaseOpcode = "S4_storerf_rr"; } def S4_pstorerftnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memh(#$Ii) = $Rt32.h", -tc_da4a37ed, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -23150,8 +23479,8 @@ let accessSize = HalfWordAccess; let isPredicatedNew = 1; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerf"; let BaseOpcode = "S2_storerfabs"; +let CextOpcode = "S2_storerf"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -23163,7 +23492,7 @@ def S4_pstorerftnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memh($Rs32+#$Ii) = $Rt32.h", -tc_da97ee82, TypeV2LDST>, Enc_e8c45e, AddrModeRel { +tc_a2b365d2, TypeV2LDST>, Enc_e8c45e, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000010011; let isPredicated = 1; @@ -23171,9 +23500,9 @@ let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S2_storerf_io"; let CextOpcode = "S2_storerf"; let InputType = "imm"; -let BaseOpcode = "S2_storerf_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -23184,22 +23513,22 @@ def S4_pstorerftnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h", -tc_40116ca8, TypeST>, Enc_6339d5, AddrModeRel { +tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110110011; let isPredicated = 1; let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S4_storerf_rr"; let CextOpcode = "S2_storerf"; let InputType = "reg"; -let BaseOpcode = "S4_storerf_rr"; } def S4_pstorerftnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pv4.new) memh($Rs32) = $Rt32.h", -tc_da97ee82, TypeMAPPING> { +tc_a2b365d2, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -23207,7 +23536,7 @@ def S4_pstorerhf_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memh(#$Ii) = $Rt32", -tc_362c6592, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; @@ -23218,8 +23547,8 @@ let addrMode = Absolute; let accessSize = HalfWordAccess; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerhabs"; +let CextOpcode = "S2_storerh"; let isNVStorable = 1; let DecoderNamespace = "MustExtend"; let isExtendable = 1; @@ -23232,23 +23561,23 @@ def S4_pstorerhf_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_3962fa26, TypeST>, Enc_6339d5, AddrModeRel { +tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110101010; let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let mayStore = 1; +let BaseOpcode = "S2_storerh_rr"; let CextOpcode = "S2_storerh"; let InputType = "reg"; -let BaseOpcode = "S2_storerh_rr"; let isNVStorable = 1; } def S4_pstorerhfnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memh(#$Ii) = $Rt32", -tc_da4a37ed, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -23260,8 +23589,8 @@ let accessSize = HalfWordAccess; let isPredicatedNew = 1; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerhabs"; +let CextOpcode = "S2_storerh"; let isNVStorable = 1; let DecoderNamespace = "MustExtend"; let isExtendable = 1; @@ -23274,7 +23603,7 @@ def S4_pstorerhfnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memh($Rs32+#$Ii) = $Rt32", -tc_da97ee82, TypeV2LDST>, Enc_e8c45e, AddrModeRel { +tc_a2b365d2, TypeV2LDST>, Enc_e8c45e, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000110010; let isPredicated = 1; @@ -23283,9 +23612,9 @@ let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S2_storerh_io"; let CextOpcode = "S2_storerh"; let InputType = "imm"; -let BaseOpcode = "S2_storerh_io"; let isNVStorable = 1; let isExtendable = 1; let opExtendable = 2; @@ -23297,7 +23626,7 @@ def S4_pstorerhfnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_40116ca8, TypeST>, Enc_6339d5, AddrModeRel { +tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110111010; let isPredicated = 1; let isPredicatedFalse = 1; @@ -23305,16 +23634,16 @@ let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S2_storerh_rr"; let CextOpcode = "S2_storerh"; let InputType = "reg"; -let BaseOpcode = "S2_storerh_rr"; let isNVStorable = 1; } def S4_pstorerhfnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pv4.new) memh($Rs32) = $Rt32", -tc_da97ee82, TypeMAPPING> { +tc_a2b365d2, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -23322,7 +23651,7 @@ def S4_pstorerhnewf_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4) memh(#$Ii) = $Nt8.new", -tc_4b68bce4, TypeST>, Enc_44215c, AddrModeRel { +tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-11} = 0b001; @@ -23336,8 +23665,8 @@ let isNewValue = 1; let isExtended = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerhabs"; +let CextOpcode = "S2_storerh"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -23350,7 +23679,7 @@ def S4_pstorerhnewf_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_e95795ec, TypeST>, Enc_47ee5e, AddrModeRel { +tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel { let Inst{4-3} = 0b01; let Inst{31-21} = 0b00110101101; let isPredicated = 1; @@ -23361,16 +23690,16 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storerh_rr"; let CextOpcode = "S2_storerh"; let InputType = "reg"; -let BaseOpcode = "S2_storerh_rr"; let opNewValue = 4; } def S4_pstorerhnewfnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4.new) memh(#$Ii) = $Nt8.new", -tc_d2e63d61, TypeST>, Enc_44215c, AddrModeRel { +tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-11} = 0b101; @@ -23385,8 +23714,8 @@ let isNewValue = 1; let isExtended = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerhabs"; +let CextOpcode = "S2_storerh"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -23399,7 +23728,7 @@ def S4_pstorerhnewfnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4.new) memh($Rs32+#$Ii) = $Nt8.new", -tc_c79a189f, TypeV2LDST>, Enc_f44229, AddrModeRel { +tc_92240447, TypeV2LDST>, Enc_f44229, AddrModeRel { let Inst{2-2} = 0b0; let Inst{12-11} = 0b01; let Inst{31-21} = 0b01000110101; @@ -23412,9 +23741,9 @@ let isPredicatedNew = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storerh_io"; let CextOpcode = "S2_storerh"; let InputType = "imm"; -let BaseOpcode = "S2_storerh_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -23426,7 +23755,7 @@ def S4_pstorerhnewfnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_b90a29b1, TypeST>, Enc_47ee5e, AddrModeRel { +tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel { let Inst{4-3} = 0b01; let Inst{31-21} = 0b00110111101; let isPredicated = 1; @@ -23438,16 +23767,16 @@ let isPredicatedNew = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storerh_rr"; let CextOpcode = "S2_storerh"; let InputType = "reg"; -let BaseOpcode = "S2_storerh_rr"; let opNewValue = 4; } def S4_pstorerhnewfnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), "if (!$Pv4.new) memh($Rs32) = $Nt8.new", -tc_c79a189f, TypeMAPPING> { +tc_92240447, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 2; @@ -23456,7 +23785,7 @@ def S4_pstorerhnewt_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4) memh(#$Ii) = $Nt8.new", -tc_4b68bce4, TypeST>, Enc_44215c, AddrModeRel { +tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-11} = 0b001; @@ -23469,8 +23798,8 @@ let isNewValue = 1; let isExtended = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerhabs"; +let CextOpcode = "S2_storerh"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -23483,7 +23812,7 @@ def S4_pstorerhnewt_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_e95795ec, TypeST>, Enc_47ee5e, AddrModeRel { +tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel { let Inst{4-3} = 0b01; let Inst{31-21} = 0b00110100101; let isPredicated = 1; @@ -23493,16 +23822,16 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storerh_rr"; let CextOpcode = "S2_storerh"; let InputType = "reg"; -let BaseOpcode = "S2_storerh_rr"; let opNewValue = 4; } def S4_pstorerhnewtnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4.new) memh(#$Ii) = $Nt8.new", -tc_d2e63d61, TypeST>, Enc_44215c, AddrModeRel { +tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-11} = 0b101; @@ -23516,8 +23845,8 @@ let isNewValue = 1; let isExtended = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerhabs"; +let CextOpcode = "S2_storerh"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -23530,7 +23859,7 @@ def S4_pstorerhnewtnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8), "if ($Pv4.new) memh($Rs32+#$Ii) = $Nt8.new", -tc_c79a189f, TypeV2LDST>, Enc_f44229, AddrModeRel { +tc_92240447, TypeV2LDST>, Enc_f44229, AddrModeRel { let Inst{2-2} = 0b0; let Inst{12-11} = 0b01; let Inst{31-21} = 0b01000010101; @@ -23542,9 +23871,9 @@ let isPredicatedNew = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storerh_io"; let CextOpcode = "S2_storerh"; let InputType = "imm"; -let BaseOpcode = "S2_storerh_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -23556,7 +23885,7 @@ def S4_pstorerhnewtnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_b90a29b1, TypeST>, Enc_47ee5e, AddrModeRel { +tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel { let Inst{4-3} = 0b01; let Inst{31-21} = 0b00110110101; let isPredicated = 1; @@ -23567,16 +23896,16 @@ let isPredicatedNew = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storerh_rr"; let CextOpcode = "S2_storerh"; let InputType = "reg"; -let BaseOpcode = "S2_storerh_rr"; let opNewValue = 4; } def S4_pstorerhnewtnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), "if ($Pv4.new) memh($Rs32) = $Nt8.new", -tc_c79a189f, TypeMAPPING> { +tc_92240447, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 2; @@ -23585,7 +23914,7 @@ def S4_pstorerht_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memh(#$Ii) = $Rt32", -tc_362c6592, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; @@ -23595,8 +23924,8 @@ let addrMode = Absolute; let accessSize = HalfWordAccess; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerhabs"; +let CextOpcode = "S2_storerh"; let isNVStorable = 1; let DecoderNamespace = "MustExtend"; let isExtendable = 1; @@ -23609,22 +23938,22 @@ def S4_pstorerht_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_3962fa26, TypeST>, Enc_6339d5, AddrModeRel { +tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110100010; let isPredicated = 1; let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let mayStore = 1; +let BaseOpcode = "S2_storerh_rr"; let CextOpcode = "S2_storerh"; let InputType = "reg"; -let BaseOpcode = "S2_storerh_rr"; let isNVStorable = 1; } def S4_pstorerhtnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memh(#$Ii) = $Rt32", -tc_da4a37ed, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -23635,8 +23964,8 @@ let accessSize = HalfWordAccess; let isPredicatedNew = 1; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerhabs"; +let CextOpcode = "S2_storerh"; let isNVStorable = 1; let DecoderNamespace = "MustExtend"; let isExtendable = 1; @@ -23649,7 +23978,7 @@ def S4_pstorerhtnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memh($Rs32+#$Ii) = $Rt32", -tc_da97ee82, TypeV2LDST>, Enc_e8c45e, AddrModeRel { +tc_a2b365d2, TypeV2LDST>, Enc_e8c45e, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000010010; let isPredicated = 1; @@ -23657,9 +23986,9 @@ let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S2_storerh_io"; let CextOpcode = "S2_storerh"; let InputType = "imm"; -let BaseOpcode = "S2_storerh_io"; let isNVStorable = 1; let isExtendable = 1; let opExtendable = 2; @@ -23671,23 +24000,23 @@ def S4_pstorerhtnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_40116ca8, TypeST>, Enc_6339d5, AddrModeRel { +tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110110010; let isPredicated = 1; let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S2_storerh_rr"; let CextOpcode = "S2_storerh"; let InputType = "reg"; -let BaseOpcode = "S2_storerh_rr"; let isNVStorable = 1; } def S4_pstorerhtnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pv4.new) memh($Rs32) = $Rt32", -tc_da97ee82, TypeMAPPING> { +tc_a2b365d2, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -23695,7 +24024,7 @@ def S4_pstorerif_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memw(#$Ii) = $Rt32", -tc_362c6592, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; @@ -23706,8 +24035,8 @@ let addrMode = Absolute; let accessSize = WordAccess; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeriabs"; +let CextOpcode = "S2_storeri"; let isNVStorable = 1; let DecoderNamespace = "MustExtend"; let isExtendable = 1; @@ -23720,23 +24049,23 @@ def S4_pstorerif_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4) memw($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_3962fa26, TypeST>, Enc_6339d5, AddrModeRel { +tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110101100; let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = BaseRegOffset; let accessSize = WordAccess; let mayStore = 1; +let BaseOpcode = "S2_storeri_rr"; let CextOpcode = "S2_storeri"; let InputType = "reg"; -let BaseOpcode = "S2_storeri_rr"; let isNVStorable = 1; } def S4_pstorerifnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memw(#$Ii) = $Rt32", -tc_da4a37ed, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -23748,8 +24077,8 @@ let accessSize = WordAccess; let isPredicatedNew = 1; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeriabs"; +let CextOpcode = "S2_storeri"; let isNVStorable = 1; let DecoderNamespace = "MustExtend"; let isExtendable = 1; @@ -23762,7 +24091,7 @@ def S4_pstorerifnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memw($Rs32+#$Ii) = $Rt32", -tc_da97ee82, TypeV2LDST>, Enc_397f23, AddrModeRel { +tc_a2b365d2, TypeV2LDST>, Enc_397f23, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000110100; let isPredicated = 1; @@ -23771,9 +24100,9 @@ let addrMode = BaseImmOffset; let accessSize = WordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S2_storeri_io"; let CextOpcode = "S2_storeri"; let InputType = "imm"; -let BaseOpcode = "S2_storeri_io"; let isNVStorable = 1; let isExtendable = 1; let opExtendable = 2; @@ -23785,7 +24114,7 @@ def S4_pstorerifnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if (!$Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_40116ca8, TypeST>, Enc_6339d5, AddrModeRel { +tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110111100; let isPredicated = 1; let isPredicatedFalse = 1; @@ -23793,16 +24122,16 @@ let addrMode = BaseRegOffset; let accessSize = WordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S2_storeri_rr"; let CextOpcode = "S2_storeri"; let InputType = "reg"; -let BaseOpcode = "S2_storeri_rr"; let isNVStorable = 1; } def S4_pstorerifnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if (!$Pv4.new) memw($Rs32) = $Rt32", -tc_da97ee82, TypeMAPPING> { +tc_a2b365d2, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -23810,7 +24139,7 @@ def S4_pstorerinewf_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4) memw(#$Ii) = $Nt8.new", -tc_4b68bce4, TypeST>, Enc_44215c, AddrModeRel { +tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-11} = 0b010; @@ -23824,8 +24153,8 @@ let isNewValue = 1; let isExtended = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeriabs"; +let CextOpcode = "S2_storeri"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -23838,7 +24167,7 @@ def S4_pstorerinewf_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_e95795ec, TypeST>, Enc_47ee5e, AddrModeRel { +tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel { let Inst{4-3} = 0b10; let Inst{31-21} = 0b00110101101; let isPredicated = 1; @@ -23849,16 +24178,16 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storeri_rr"; let CextOpcode = "S2_storeri"; let InputType = "reg"; -let BaseOpcode = "S2_storeri_rr"; let opNewValue = 4; } def S4_pstorerinewfnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4.new) memw(#$Ii) = $Nt8.new", -tc_d2e63d61, TypeST>, Enc_44215c, AddrModeRel { +tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel { let Inst{2-2} = 0b1; let Inst{7-7} = 0b1; let Inst{13-11} = 0b110; @@ -23873,8 +24202,8 @@ let isNewValue = 1; let isExtended = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeriabs"; +let CextOpcode = "S2_storeri"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -23887,7 +24216,7 @@ def S4_pstorerinewfnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4.new) memw($Rs32+#$Ii) = $Nt8.new", -tc_c79a189f, TypeV2LDST>, Enc_8dbdfe, AddrModeRel { +tc_92240447, TypeV2LDST>, Enc_8dbdfe, AddrModeRel { let Inst{2-2} = 0b0; let Inst{12-11} = 0b10; let Inst{31-21} = 0b01000110101; @@ -23900,9 +24229,9 @@ let isPredicatedNew = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storeri_io"; let CextOpcode = "S2_storeri"; let InputType = "imm"; -let BaseOpcode = "S2_storeri_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -23914,7 +24243,7 @@ def S4_pstorerinewfnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "if (!$Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_b90a29b1, TypeST>, Enc_47ee5e, AddrModeRel { +tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel { let Inst{4-3} = 0b10; let Inst{31-21} = 0b00110111101; let isPredicated = 1; @@ -23926,16 +24255,16 @@ let isPredicatedNew = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storeri_rr"; let CextOpcode = "S2_storeri"; let InputType = "reg"; -let BaseOpcode = "S2_storeri_rr"; let opNewValue = 4; } def S4_pstorerinewfnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), "if (!$Pv4.new) memw($Rs32) = $Nt8.new", -tc_c79a189f, TypeMAPPING> { +tc_92240447, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 2; @@ -23944,7 +24273,7 @@ def S4_pstorerinewt_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4) memw(#$Ii) = $Nt8.new", -tc_4b68bce4, TypeST>, Enc_44215c, AddrModeRel { +tc_cfa0e29b, TypeST>, Enc_44215c, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-11} = 0b010; @@ -23957,8 +24286,8 @@ let isNewValue = 1; let isExtended = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeriabs"; +let CextOpcode = "S2_storeri"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -23971,7 +24300,7 @@ def S4_pstorerinewt_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_e95795ec, TypeST>, Enc_47ee5e, AddrModeRel { +tc_0a6c20ae, TypeST>, Enc_47ee5e, AddrModeRel { let Inst{4-3} = 0b10; let Inst{31-21} = 0b00110100101; let isPredicated = 1; @@ -23981,16 +24310,16 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storeri_rr"; let CextOpcode = "S2_storeri"; let InputType = "reg"; -let BaseOpcode = "S2_storeri_rr"; let opNewValue = 4; } def S4_pstorerinewtnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4.new) memw(#$Ii) = $Nt8.new", -tc_d2e63d61, TypeST>, Enc_44215c, AddrModeRel { +tc_0fac1eb8, TypeST>, Enc_44215c, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-11} = 0b110; @@ -24004,8 +24333,8 @@ let isNewValue = 1; let isExtended = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeriabs"; +let CextOpcode = "S2_storeri"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 1; @@ -24018,7 +24347,7 @@ def S4_pstorerinewtnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8), "if ($Pv4.new) memw($Rs32+#$Ii) = $Nt8.new", -tc_c79a189f, TypeV2LDST>, Enc_8dbdfe, AddrModeRel { +tc_92240447, TypeV2LDST>, Enc_8dbdfe, AddrModeRel { let Inst{2-2} = 0b0; let Inst{12-11} = 0b10; let Inst{31-21} = 0b01000010101; @@ -24030,9 +24359,9 @@ let isPredicatedNew = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storeri_io"; let CextOpcode = "S2_storeri"; let InputType = "imm"; -let BaseOpcode = "S2_storeri_io"; let isExtendable = 1; let opExtendable = 2; let isExtentSigned = 0; @@ -24044,7 +24373,7 @@ def S4_pstorerinewtnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "if ($Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_b90a29b1, TypeST>, Enc_47ee5e, AddrModeRel { +tc_829d8a86, TypeST>, Enc_47ee5e, AddrModeRel { let Inst{4-3} = 0b10; let Inst{31-21} = 0b00110110101; let isPredicated = 1; @@ -24055,16 +24384,16 @@ let isPredicatedNew = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storeri_rr"; let CextOpcode = "S2_storeri"; let InputType = "reg"; -let BaseOpcode = "S2_storeri_rr"; let opNewValue = 4; } def S4_pstorerinewtnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), "if ($Pv4.new) memw($Rs32) = $Nt8.new", -tc_c79a189f, TypeMAPPING> { +tc_92240447, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; let opNewValue = 2; @@ -24073,7 +24402,7 @@ def S4_pstorerit_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memw(#$Ii) = $Rt32", -tc_362c6592, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_ba9255a6, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b0; @@ -24083,8 +24412,8 @@ let addrMode = Absolute; let accessSize = WordAccess; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeriabs"; +let CextOpcode = "S2_storeri"; let isNVStorable = 1; let DecoderNamespace = "MustExtend"; let isExtendable = 1; @@ -24097,22 +24426,22 @@ def S4_pstorerit_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4) memw($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_3962fa26, TypeST>, Enc_6339d5, AddrModeRel { +tc_1fe4ab69, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110100100; let isPredicated = 1; let addrMode = BaseRegOffset; let accessSize = WordAccess; let mayStore = 1; +let BaseOpcode = "S2_storeri_rr"; let CextOpcode = "S2_storeri"; let InputType = "reg"; -let BaseOpcode = "S2_storeri_rr"; let isNVStorable = 1; } def S4_pstoreritnew_abs : HInst< (outs), (ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memw(#$Ii) = $Rt32", -tc_da4a37ed, TypeST>, Enc_1cf4ca, AddrModeRel { +tc_bb07f2c5, TypeST>, Enc_1cf4ca, AddrModeRel { let Inst{2-2} = 0b0; let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; @@ -24123,8 +24452,8 @@ let accessSize = WordAccess; let isPredicatedNew = 1; let isExtended = 1; let mayStore = 1; -let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeriabs"; +let CextOpcode = "S2_storeri"; let isNVStorable = 1; let DecoderNamespace = "MustExtend"; let isExtendable = 1; @@ -24137,7 +24466,7 @@ def S4_pstoreritnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memw($Rs32+#$Ii) = $Rt32", -tc_da97ee82, TypeV2LDST>, Enc_397f23, AddrModeRel { +tc_a2b365d2, TypeV2LDST>, Enc_397f23, AddrModeRel { let Inst{2-2} = 0b0; let Inst{31-21} = 0b01000010100; let isPredicated = 1; @@ -24145,9 +24474,9 @@ let addrMode = BaseImmOffset; let accessSize = WordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S2_storeri_io"; let CextOpcode = "S2_storeri"; let InputType = "imm"; -let BaseOpcode = "S2_storeri_io"; let isNVStorable = 1; let isExtendable = 1; let opExtendable = 2; @@ -24159,23 +24488,23 @@ def S4_pstoreritnew_rr : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "if ($Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_40116ca8, TypeST>, Enc_6339d5, AddrModeRel { +tc_8e82e8ca, TypeST>, Enc_6339d5, AddrModeRel { let Inst{31-21} = 0b00110110100; let isPredicated = 1; let addrMode = BaseRegOffset; let accessSize = WordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S2_storeri_rr"; let CextOpcode = "S2_storeri"; let InputType = "reg"; -let BaseOpcode = "S2_storeri_rr"; let isNVStorable = 1; } def S4_pstoreritnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), "if ($Pv4.new) memw($Rs32) = $Rt32", -tc_da97ee82, TypeMAPPING> { +tc_a2b365d2, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -24183,7 +24512,7 @@ def S4_stored_locked : HInst< (outs PredRegs:$Pd4), (ins IntRegs:$Rs32, DoubleRegs:$Rtt32), "memd_locked($Rs32,$Pd4) = $Rtt32", -tc_5abb5e3f, TypeST>, Enc_d7dc10 { +tc_6f42bc60, TypeST>, Enc_d7dc10 { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10100000111; @@ -24196,14 +24525,14 @@ def S4_storeirb_io : HInst< (outs), (ins IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II), "memb($Rs32+#$Ii) = #$II", -tc_b83e6d73, TypeST>, Enc_8203bb, PredNewRel { +tc_7c31e19a, TypeST>, Enc_8203bb, PredNewRel { let Inst{31-21} = 0b00111100000; let addrMode = BaseImmOffset; let accessSize = ByteAccess; let mayStore = 1; +let BaseOpcode = "S4_storeirb_io"; let CextOpcode = "S2_storerb"; let InputType = "imm"; -let BaseOpcode = "S4_storeirb_io"; let isPredicable = 1; let isExtendable = 1; let opExtendable = 2; @@ -24215,7 +24544,7 @@ def S4_storeirb_zomap : HInst< (outs), (ins IntRegs:$Rs32, s8_0Imm:$II), "memb($Rs32) = #$II", -tc_b83e6d73, TypeMAPPING> { +tc_7c31e19a, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -24223,16 +24552,16 @@ def S4_storeirbf_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II), "if (!$Pv4) memb($Rs32+#$Ii) = #$II", -tc_0b2be201, TypeST>, Enc_d7a65e, PredNewRel { +tc_d03278fd, TypeST>, Enc_d7a65e, PredNewRel { let Inst{31-21} = 0b00111000100; let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = BaseImmOffset; let accessSize = ByteAccess; let mayStore = 1; +let BaseOpcode = "S4_storeirb_io"; let CextOpcode = "S2_storerb"; let InputType = "imm"; -let BaseOpcode = "S4_storeirb_io"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 1; @@ -24243,7 +24572,7 @@ def S4_storeirbf_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), "if (!$Pv4) memb($Rs32) = #$II", -tc_0b2be201, TypeMAPPING> { +tc_d03278fd, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -24251,7 +24580,7 @@ def S4_storeirbfnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II), "if (!$Pv4.new) memb($Rs32+#$Ii) = #$II", -tc_c4f596e3, TypeST>, Enc_d7a65e, PredNewRel { +tc_65cbd974, TypeST>, Enc_d7a65e, PredNewRel { let Inst{31-21} = 0b00111001100; let isPredicated = 1; let isPredicatedFalse = 1; @@ -24259,9 +24588,9 @@ let addrMode = BaseImmOffset; let accessSize = ByteAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S4_storeirb_io"; let CextOpcode = "S2_storerb"; let InputType = "imm"; -let BaseOpcode = "S4_storeirb_io"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 1; @@ -24272,7 +24601,7 @@ def S4_storeirbfnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), "if (!$Pv4.new) memb($Rs32) = #$II", -tc_c4f596e3, TypeMAPPING> { +tc_65cbd974, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -24280,15 +24609,15 @@ def S4_storeirbt_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II), "if ($Pv4) memb($Rs32+#$Ii) = #$II", -tc_0b2be201, TypeST>, Enc_d7a65e, PredNewRel { +tc_d03278fd, TypeST>, Enc_d7a65e, PredNewRel { let Inst{31-21} = 0b00111000000; let isPredicated = 1; let addrMode = BaseImmOffset; let accessSize = ByteAccess; let mayStore = 1; +let BaseOpcode = "S4_storeirb_io"; let CextOpcode = "S2_storerb"; let InputType = "imm"; -let BaseOpcode = "S4_storeirb_io"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 1; @@ -24299,7 +24628,7 @@ def S4_storeirbt_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), "if ($Pv4) memb($Rs32) = #$II", -tc_0b2be201, TypeMAPPING> { +tc_d03278fd, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -24307,16 +24636,16 @@ def S4_storeirbtnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II), "if ($Pv4.new) memb($Rs32+#$Ii) = #$II", -tc_c4f596e3, TypeST>, Enc_d7a65e, PredNewRel { +tc_65cbd974, TypeST>, Enc_d7a65e, PredNewRel { let Inst{31-21} = 0b00111001000; let isPredicated = 1; let addrMode = BaseImmOffset; let accessSize = ByteAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S4_storeirb_io"; let CextOpcode = "S2_storerb"; let InputType = "imm"; -let BaseOpcode = "S4_storeirb_io"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 1; @@ -24327,7 +24656,7 @@ def S4_storeirbtnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), "if ($Pv4.new) memb($Rs32) = #$II", -tc_c4f596e3, TypeMAPPING> { +tc_65cbd974, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -24335,14 +24664,14 @@ def S4_storeirh_io : HInst< (outs), (ins IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II), "memh($Rs32+#$Ii) = #$II", -tc_b83e6d73, TypeST>, Enc_a803e0, PredNewRel { +tc_7c31e19a, TypeST>, Enc_a803e0, PredNewRel { let Inst{31-21} = 0b00111100001; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let mayStore = 1; +let BaseOpcode = "S4_storeirh_io"; let CextOpcode = "S2_storerh"; let InputType = "imm"; -let BaseOpcode = "S4_storeirh_io"; let isPredicable = 1; let isExtendable = 1; let opExtendable = 2; @@ -24354,7 +24683,7 @@ def S4_storeirh_zomap : HInst< (outs), (ins IntRegs:$Rs32, s8_0Imm:$II), "memh($Rs32) = #$II", -tc_b83e6d73, TypeMAPPING> { +tc_7c31e19a, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -24362,16 +24691,16 @@ def S4_storeirhf_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II), "if (!$Pv4) memh($Rs32+#$Ii) = #$II", -tc_0b2be201, TypeST>, Enc_f20719, PredNewRel { +tc_d03278fd, TypeST>, Enc_f20719, PredNewRel { let Inst{31-21} = 0b00111000101; let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let mayStore = 1; +let BaseOpcode = "S4_storeirh_io"; let CextOpcode = "S2_storerh"; let InputType = "imm"; -let BaseOpcode = "S4_storeirh_io"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 1; @@ -24382,7 +24711,7 @@ def S4_storeirhf_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), "if (!$Pv4) memh($Rs32) = #$II", -tc_0b2be201, TypeMAPPING> { +tc_d03278fd, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -24390,7 +24719,7 @@ def S4_storeirhfnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II), "if (!$Pv4.new) memh($Rs32+#$Ii) = #$II", -tc_c4f596e3, TypeST>, Enc_f20719, PredNewRel { +tc_65cbd974, TypeST>, Enc_f20719, PredNewRel { let Inst{31-21} = 0b00111001101; let isPredicated = 1; let isPredicatedFalse = 1; @@ -24398,9 +24727,9 @@ let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S4_storeirh_io"; let CextOpcode = "S2_storerh"; let InputType = "imm"; -let BaseOpcode = "S4_storeirh_io"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 1; @@ -24411,7 +24740,7 @@ def S4_storeirhfnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), "if (!$Pv4.new) memh($Rs32) = #$II", -tc_c4f596e3, TypeMAPPING> { +tc_65cbd974, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -24419,15 +24748,15 @@ def S4_storeirht_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II), "if ($Pv4) memh($Rs32+#$Ii) = #$II", -tc_0b2be201, TypeST>, Enc_f20719, PredNewRel { +tc_d03278fd, TypeST>, Enc_f20719, PredNewRel { let Inst{31-21} = 0b00111000001; let isPredicated = 1; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let mayStore = 1; +let BaseOpcode = "S4_storeirh_io"; let CextOpcode = "S2_storerh"; let InputType = "imm"; -let BaseOpcode = "S4_storeirh_io"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 1; @@ -24438,7 +24767,7 @@ def S4_storeirht_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), "if ($Pv4) memh($Rs32) = #$II", -tc_0b2be201, TypeMAPPING> { +tc_d03278fd, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -24446,16 +24775,16 @@ def S4_storeirhtnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II), "if ($Pv4.new) memh($Rs32+#$Ii) = #$II", -tc_c4f596e3, TypeST>, Enc_f20719, PredNewRel { +tc_65cbd974, TypeST>, Enc_f20719, PredNewRel { let Inst{31-21} = 0b00111001001; let isPredicated = 1; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S4_storeirh_io"; let CextOpcode = "S2_storerh"; let InputType = "imm"; -let BaseOpcode = "S4_storeirh_io"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 1; @@ -24466,7 +24795,7 @@ def S4_storeirhtnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), "if ($Pv4.new) memh($Rs32) = #$II", -tc_c4f596e3, TypeMAPPING> { +tc_65cbd974, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -24474,14 +24803,14 @@ def S4_storeiri_io : HInst< (outs), (ins IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II), "memw($Rs32+#$Ii) = #$II", -tc_b83e6d73, TypeST>, Enc_f37377, PredNewRel { +tc_7c31e19a, TypeST>, Enc_f37377, PredNewRel { let Inst{31-21} = 0b00111100010; let addrMode = BaseImmOffset; let accessSize = WordAccess; let mayStore = 1; +let BaseOpcode = "S4_storeiri_io"; let CextOpcode = "S2_storeri"; let InputType = "imm"; -let BaseOpcode = "S4_storeiri_io"; let isPredicable = 1; let isExtendable = 1; let opExtendable = 2; @@ -24493,7 +24822,7 @@ def S4_storeiri_zomap : HInst< (outs), (ins IntRegs:$Rs32, s8_0Imm:$II), "memw($Rs32) = #$II", -tc_b83e6d73, TypeMAPPING> { +tc_7c31e19a, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -24501,16 +24830,16 @@ def S4_storeirif_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II), "if (!$Pv4) memw($Rs32+#$Ii) = #$II", -tc_0b2be201, TypeST>, Enc_5ccba9, PredNewRel { +tc_d03278fd, TypeST>, Enc_5ccba9, PredNewRel { let Inst{31-21} = 0b00111000110; let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = BaseImmOffset; let accessSize = WordAccess; let mayStore = 1; +let BaseOpcode = "S4_storeiri_io"; let CextOpcode = "S2_storeri"; let InputType = "imm"; -let BaseOpcode = "S4_storeiri_io"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 1; @@ -24521,7 +24850,7 @@ def S4_storeirif_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), "if (!$Pv4) memw($Rs32) = #$II", -tc_0b2be201, TypeMAPPING> { +tc_d03278fd, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -24529,7 +24858,7 @@ def S4_storeirifnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II), "if (!$Pv4.new) memw($Rs32+#$Ii) = #$II", -tc_c4f596e3, TypeST>, Enc_5ccba9, PredNewRel { +tc_65cbd974, TypeST>, Enc_5ccba9, PredNewRel { let Inst{31-21} = 0b00111001110; let isPredicated = 1; let isPredicatedFalse = 1; @@ -24537,9 +24866,9 @@ let addrMode = BaseImmOffset; let accessSize = WordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S4_storeiri_io"; let CextOpcode = "S2_storeri"; let InputType = "imm"; -let BaseOpcode = "S4_storeiri_io"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 1; @@ -24550,7 +24879,7 @@ def S4_storeirifnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), "if (!$Pv4.new) memw($Rs32) = #$II", -tc_c4f596e3, TypeMAPPING> { +tc_65cbd974, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -24558,15 +24887,15 @@ def S4_storeirit_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II), "if ($Pv4) memw($Rs32+#$Ii) = #$II", -tc_0b2be201, TypeST>, Enc_5ccba9, PredNewRel { +tc_d03278fd, TypeST>, Enc_5ccba9, PredNewRel { let Inst{31-21} = 0b00111000010; let isPredicated = 1; let addrMode = BaseImmOffset; let accessSize = WordAccess; let mayStore = 1; +let BaseOpcode = "S4_storeiri_io"; let CextOpcode = "S2_storeri"; let InputType = "imm"; -let BaseOpcode = "S4_storeiri_io"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 1; @@ -24577,7 +24906,7 @@ def S4_storeirit_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), "if ($Pv4) memw($Rs32) = #$II", -tc_0b2be201, TypeMAPPING> { +tc_d03278fd, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -24585,16 +24914,16 @@ def S4_storeiritnew_io : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II), "if ($Pv4.new) memw($Rs32+#$Ii) = #$II", -tc_c4f596e3, TypeST>, Enc_5ccba9, PredNewRel { +tc_65cbd974, TypeST>, Enc_5ccba9, PredNewRel { let Inst{31-21} = 0b00111001010; let isPredicated = 1; let addrMode = BaseImmOffset; let accessSize = WordAccess; let isPredicatedNew = 1; let mayStore = 1; +let BaseOpcode = "S4_storeiri_io"; let CextOpcode = "S2_storeri"; let InputType = "imm"; -let BaseOpcode = "S4_storeiri_io"; let isExtendable = 1; let opExtendable = 3; let isExtentSigned = 1; @@ -24605,7 +24934,7 @@ def S4_storeiritnew_zomap : HInst< (outs), (ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), "if ($Pv4.new) memw($Rs32) = #$II", -tc_c4f596e3, TypeMAPPING> { +tc_65cbd974, TypeMAPPING> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -24613,7 +24942,7 @@ def S4_storerb_ap : HInst< (outs IntRegs:$Re32), (ins u32_0Imm:$II, IntRegs:$Rt32), "memb($Re32=#$II) = $Rt32", -tc_da4a37ed, TypeST>, Enc_8bcba4, AddrModeRel { +tc_bb07f2c5, TypeST>, Enc_8bcba4, AddrModeRel { let Inst{7-6} = 0b10; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10101011000; @@ -24634,15 +24963,15 @@ def S4_storerb_rr : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "memb($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_5aee39f7, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl { +tc_280f7fe1, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl { let Inst{6-5} = 0b00; let Inst{31-21} = 0b00111011000; let addrMode = BaseRegOffset; let accessSize = ByteAccess; let mayStore = 1; +let BaseOpcode = "S4_storerb_rr"; let CextOpcode = "S2_storerb"; let InputType = "reg"; -let BaseOpcode = "S4_storerb_rr"; let isNVStorable = 1; let isPredicable = 1; } @@ -24650,16 +24979,16 @@ def S4_storerb_ur : HInst< (outs), (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32), "memb($Ru32<<#$Ii+#$II) = $Rt32", -tc_14b272fa, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl { +tc_887d1bb7, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl { let Inst{7-7} = 0b1; let Inst{31-21} = 0b10101101000; let addrMode = BaseLongOffset; let accessSize = ByteAccess; let isExtended = 1; let mayStore = 1; +let BaseOpcode = "S4_storerb_ur"; let CextOpcode = "S2_storerb"; let InputType = "imm"; -let BaseOpcode = "S4_storerb_ur"; let isNVStorable = 1; let DecoderNamespace = "MustExtend"; let isExtendable = 1; @@ -24672,7 +25001,7 @@ def S4_storerbnew_ap : HInst< (outs IntRegs:$Re32), (ins u32_0Imm:$II, IntRegs:$Nt8), "memb($Re32=#$II) = $Nt8.new", -tc_d2e63d61, TypeST>, Enc_724154, AddrModeRel { +tc_0fac1eb8, TypeST>, Enc_724154, AddrModeRel { let Inst{7-6} = 0b10; let Inst{13-11} = 0b000; let Inst{31-21} = 0b10101011101; @@ -24696,7 +25025,7 @@ def S4_storerbnew_rr : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "memb($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_67435e81, TypeST>, Enc_c6220b, AddrModeRel { +tc_96ef76ef, TypeST>, Enc_c6220b, AddrModeRel { let Inst{6-3} = 0b0000; let Inst{31-21} = 0b00111011101; let addrMode = BaseRegOffset; @@ -24705,9 +25034,9 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S4_storerb_rr"; let CextOpcode = "S2_storerb"; let InputType = "reg"; -let BaseOpcode = "S4_storerb_rr"; let isPredicable = 1; let opNewValue = 3; } @@ -24715,7 +25044,7 @@ def S4_storerbnew_ur : HInst< (outs), (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8), "memb($Ru32<<#$Ii+#$II) = $Nt8.new", -tc_fcc3ddf9, TypeST>, Enc_7eb485, AddrModeRel { +tc_55a9a350, TypeST>, Enc_7eb485, AddrModeRel { let Inst{7-7} = 0b1; let Inst{12-11} = 0b00; let Inst{31-21} = 0b10101101101; @@ -24726,8 +25055,8 @@ let isNewValue = 1; let isExtended = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerb"; let BaseOpcode = "S4_storerb_ur"; +let CextOpcode = "S2_storerb"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -24740,7 +25069,7 @@ def S4_storerd_ap : HInst< (outs IntRegs:$Re32), (ins u32_0Imm:$II, DoubleRegs:$Rtt32), "memd($Re32=#$II) = $Rtt32", -tc_da4a37ed, TypeST>, Enc_c7a204 { +tc_bb07f2c5, TypeST>, Enc_c7a204 { let Inst{7-6} = 0b10; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10101011110; @@ -24760,31 +25089,31 @@ def S4_storerd_rr : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32), "memd($Rs32+$Ru32<<#$Ii) = $Rtt32", -tc_5aee39f7, TypeST>, Enc_55355c, AddrModeRel, ImmRegShl { +tc_280f7fe1, TypeST>, Enc_55355c, AddrModeRel, ImmRegShl { let Inst{6-5} = 0b00; let Inst{31-21} = 0b00111011110; let addrMode = BaseRegOffset; let accessSize = DoubleWordAccess; let mayStore = 1; +let BaseOpcode = "S2_storerd_rr"; let CextOpcode = "S2_storerd"; let InputType = "reg"; -let BaseOpcode = "S2_storerd_rr"; let isPredicable = 1; } def S4_storerd_ur : HInst< (outs), (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, DoubleRegs:$Rtt32), "memd($Ru32<<#$Ii+#$II) = $Rtt32", -tc_14b272fa, TypeST>, Enc_f79415, AddrModeRel, ImmRegShl { +tc_887d1bb7, TypeST>, Enc_f79415, AddrModeRel, ImmRegShl { let Inst{7-7} = 0b1; let Inst{31-21} = 0b10101101110; let addrMode = BaseLongOffset; let accessSize = DoubleWordAccess; let isExtended = 1; let mayStore = 1; +let BaseOpcode = "S2_storerd_ur"; let CextOpcode = "S2_storerd"; let InputType = "imm"; -let BaseOpcode = "S2_storerd_ur"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -24796,7 +25125,7 @@ def S4_storerf_ap : HInst< (outs IntRegs:$Re32), (ins u32_0Imm:$II, IntRegs:$Rt32), "memh($Re32=#$II) = $Rt32.h", -tc_da4a37ed, TypeST>, Enc_8bcba4 { +tc_bb07f2c5, TypeST>, Enc_8bcba4 { let Inst{7-6} = 0b10; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10101011011; @@ -24816,31 +25145,31 @@ def S4_storerf_rr : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "memh($Rs32+$Ru32<<#$Ii) = $Rt32.h", -tc_5aee39f7, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl { +tc_280f7fe1, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl { let Inst{6-5} = 0b00; let Inst{31-21} = 0b00111011011; let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let mayStore = 1; +let BaseOpcode = "S4_storerf_rr"; let CextOpcode = "S2_storerf"; let InputType = "reg"; -let BaseOpcode = "S4_storerf_rr"; let isPredicable = 1; } def S4_storerf_ur : HInst< (outs), (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32), "memh($Ru32<<#$Ii+#$II) = $Rt32.h", -tc_14b272fa, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl { +tc_887d1bb7, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl { let Inst{7-7} = 0b1; let Inst{31-21} = 0b10101101011; let addrMode = BaseLongOffset; let accessSize = HalfWordAccess; let isExtended = 1; let mayStore = 1; +let BaseOpcode = "S4_storerf_rr"; let CextOpcode = "S2_storerf"; let InputType = "imm"; -let BaseOpcode = "S4_storerf_rr"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -24852,7 +25181,7 @@ def S4_storerh_ap : HInst< (outs IntRegs:$Re32), (ins u32_0Imm:$II, IntRegs:$Rt32), "memh($Re32=#$II) = $Rt32", -tc_da4a37ed, TypeST>, Enc_8bcba4, AddrModeRel { +tc_bb07f2c5, TypeST>, Enc_8bcba4, AddrModeRel { let Inst{7-6} = 0b10; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10101011010; @@ -24873,15 +25202,15 @@ def S4_storerh_rr : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "memh($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_5aee39f7, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl { +tc_280f7fe1, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl { let Inst{6-5} = 0b00; let Inst{31-21} = 0b00111011010; let addrMode = BaseRegOffset; let accessSize = HalfWordAccess; let mayStore = 1; +let BaseOpcode = "S2_storerh_rr"; let CextOpcode = "S2_storerh"; let InputType = "reg"; -let BaseOpcode = "S2_storerh_rr"; let isNVStorable = 1; let isPredicable = 1; } @@ -24889,16 +25218,16 @@ def S4_storerh_ur : HInst< (outs), (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32), "memh($Ru32<<#$Ii+#$II) = $Rt32", -tc_14b272fa, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl { +tc_887d1bb7, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl { let Inst{7-7} = 0b1; let Inst{31-21} = 0b10101101010; let addrMode = BaseLongOffset; let accessSize = HalfWordAccess; let isExtended = 1; let mayStore = 1; +let BaseOpcode = "S2_storerh_ur"; let CextOpcode = "S2_storerh"; let InputType = "imm"; -let BaseOpcode = "S2_storerh_ur"; let isNVStorable = 1; let DecoderNamespace = "MustExtend"; let isExtendable = 1; @@ -24911,7 +25240,7 @@ def S4_storerhnew_ap : HInst< (outs IntRegs:$Re32), (ins u32_0Imm:$II, IntRegs:$Nt8), "memh($Re32=#$II) = $Nt8.new", -tc_d2e63d61, TypeST>, Enc_724154, AddrModeRel { +tc_0fac1eb8, TypeST>, Enc_724154, AddrModeRel { let Inst{7-6} = 0b10; let Inst{13-11} = 0b001; let Inst{31-21} = 0b10101011101; @@ -24935,7 +25264,7 @@ def S4_storerhnew_rr : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "memh($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_67435e81, TypeST>, Enc_c6220b, AddrModeRel { +tc_96ef76ef, TypeST>, Enc_c6220b, AddrModeRel { let Inst{6-3} = 0b0001; let Inst{31-21} = 0b00111011101; let addrMode = BaseRegOffset; @@ -24944,9 +25273,9 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storerh_rr"; let CextOpcode = "S2_storerh"; let InputType = "reg"; -let BaseOpcode = "S2_storerh_rr"; let isPredicable = 1; let opNewValue = 3; } @@ -24954,7 +25283,7 @@ def S4_storerhnew_ur : HInst< (outs), (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8), "memh($Ru32<<#$Ii+#$II) = $Nt8.new", -tc_fcc3ddf9, TypeST>, Enc_7eb485, AddrModeRel { +tc_55a9a350, TypeST>, Enc_7eb485, AddrModeRel { let Inst{7-7} = 0b1; let Inst{12-11} = 0b01; let Inst{31-21} = 0b10101101101; @@ -24965,8 +25294,8 @@ let isNewValue = 1; let isExtended = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storerh"; let BaseOpcode = "S2_storerh_ur"; +let CextOpcode = "S2_storerh"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -24979,7 +25308,7 @@ def S4_storeri_ap : HInst< (outs IntRegs:$Re32), (ins u32_0Imm:$II, IntRegs:$Rt32), "memw($Re32=#$II) = $Rt32", -tc_da4a37ed, TypeST>, Enc_8bcba4, AddrModeRel { +tc_bb07f2c5, TypeST>, Enc_8bcba4, AddrModeRel { let Inst{7-6} = 0b10; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10101011100; @@ -25000,15 +25329,15 @@ def S4_storeri_rr : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), "memw($Rs32+$Ru32<<#$Ii) = $Rt32", -tc_5aee39f7, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl { +tc_280f7fe1, TypeST>, Enc_eca7c8, AddrModeRel, ImmRegShl { let Inst{6-5} = 0b00; let Inst{31-21} = 0b00111011100; let addrMode = BaseRegOffset; let accessSize = WordAccess; let mayStore = 1; +let BaseOpcode = "S2_storeri_rr"; let CextOpcode = "S2_storeri"; let InputType = "reg"; -let BaseOpcode = "S2_storeri_rr"; let isNVStorable = 1; let isPredicable = 1; } @@ -25016,16 +25345,16 @@ def S4_storeri_ur : HInst< (outs), (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32), "memw($Ru32<<#$Ii+#$II) = $Rt32", -tc_14b272fa, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl { +tc_887d1bb7, TypeST>, Enc_9ea4cf, AddrModeRel, ImmRegShl { let Inst{7-7} = 0b1; let Inst{31-21} = 0b10101101100; let addrMode = BaseLongOffset; let accessSize = WordAccess; let isExtended = 1; let mayStore = 1; +let BaseOpcode = "S2_storeri_ur"; let CextOpcode = "S2_storeri"; let InputType = "imm"; -let BaseOpcode = "S2_storeri_ur"; let isNVStorable = 1; let DecoderNamespace = "MustExtend"; let isExtendable = 1; @@ -25038,7 +25367,7 @@ def S4_storerinew_ap : HInst< (outs IntRegs:$Re32), (ins u32_0Imm:$II, IntRegs:$Nt8), "memw($Re32=#$II) = $Nt8.new", -tc_d2e63d61, TypeST>, Enc_724154, AddrModeRel { +tc_0fac1eb8, TypeST>, Enc_724154, AddrModeRel { let Inst{7-6} = 0b10; let Inst{13-11} = 0b010; let Inst{31-21} = 0b10101011101; @@ -25062,7 +25391,7 @@ def S4_storerinew_rr : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), "memw($Rs32+$Ru32<<#$Ii) = $Nt8.new", -tc_67435e81, TypeST>, Enc_c6220b, AddrModeRel { +tc_96ef76ef, TypeST>, Enc_c6220b, AddrModeRel { let Inst{6-3} = 0b0010; let Inst{31-21} = 0b00111011101; let addrMode = BaseRegOffset; @@ -25071,9 +25400,9 @@ let isNVStore = 1; let isNewValue = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; +let BaseOpcode = "S2_storeri_rr"; let CextOpcode = "S2_storeri"; let InputType = "reg"; -let BaseOpcode = "S2_storeri_rr"; let isPredicable = 1; let opNewValue = 3; } @@ -25081,7 +25410,7 @@ def S4_storerinew_ur : HInst< (outs), (ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8), "memw($Ru32<<#$Ii+#$II) = $Nt8.new", -tc_fcc3ddf9, TypeST>, Enc_7eb485, AddrModeRel { +tc_55a9a350, TypeST>, Enc_7eb485, AddrModeRel { let Inst{7-7} = 0b1; let Inst{12-11} = 0b10; let Inst{31-21} = 0b10101101101; @@ -25092,8 +25421,8 @@ let isNewValue = 1; let isExtended = 1; let isRestrictNoSlot1Store = 1; let mayStore = 1; -let CextOpcode = "S2_storeri"; let BaseOpcode = "S2_storeri_ur"; +let CextOpcode = "S2_storeri"; let DecoderNamespace = "MustExtend"; let isExtendable = 1; let opExtendable = 2; @@ -25106,7 +25435,7 @@ def S4_subaddi : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Ru32), "$Rd32 = add($Rs32,sub(#$Ii,$Ru32))", -tc_f675fee8, TypeALU64>, Enc_8b8d61 { +tc_2c13e7f5, TypeALU64>, Enc_8b8d61, Requires<[UseCompound]> { let Inst{31-23} = 0b110110111; let hasNewValue = 1; let opNewValue = 0; @@ -25121,7 +25450,7 @@ def S4_subi_asl_ri : HInst< (outs IntRegs:$Rx32), (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), "$Rx32 = sub(#$Ii,asl($Rx32in,#$II))", -tc_f675fee8, TypeALU64>, Enc_c31910 { +tc_2c13e7f5, TypeALU64>, Enc_c31910, Requires<[UseCompound]> { let Inst{2-0} = 0b110; let Inst{4-4} = 0b0; let Inst{31-24} = 0b11011110; @@ -25139,7 +25468,7 @@ def S4_subi_lsr_ri : HInst< (outs IntRegs:$Rx32), (ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), "$Rx32 = sub(#$Ii,lsr($Rx32in,#$II))", -tc_f675fee8, TypeALU64>, Enc_c31910 { +tc_2c13e7f5, TypeALU64>, Enc_c31910, Requires<[UseCompound]> { let Inst{2-0} = 0b110; let Inst{4-4} = 0b1; let Inst{31-24} = 0b11011110; @@ -25157,7 +25486,7 @@ def S4_vrcrotate : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, IntRegs:$Rt32, u2_0Imm:$Ii), "$Rdd32 = vrcrotate($Rss32,$Rt32,#$Ii)", -tc_13bfbcf9, TypeS_3op>, Enc_645d54 { +tc_f0cdeccf, TypeS_3op>, Enc_645d54 { let Inst{7-6} = 0b11; let Inst{31-21} = 0b11000011110; let prefersSlot3 = 1; @@ -25166,7 +25495,7 @@ def S4_vrcrotate_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32, u2_0Imm:$Ii), "$Rxx32 += vrcrotate($Rss32,$Rt32,#$Ii)", -tc_9debc299, TypeS_3op>, Enc_b72622 { +tc_a38c45dc, TypeS_3op>, Enc_b72622 { let Inst{7-6} = 0b00; let Inst{31-21} = 0b11001011101; let prefersSlot3 = 1; @@ -25176,7 +25505,7 @@ def S4_vxaddsubh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vxaddsubh($Rss32,$Rtt32):sat", -tc_779080bf, TypeS_3op>, Enc_a56825 { +tc_8a825db2, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001010; @@ -25187,7 +25516,7 @@ def S4_vxaddsubhr : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vxaddsubh($Rss32,$Rtt32):rnd:>>1:sat", -tc_002cb246, TypeS_3op>, Enc_a56825 { +tc_0dfac0a7, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001110; @@ -25198,7 +25527,7 @@ def S4_vxaddsubw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vxaddsubw($Rss32,$Rtt32):sat", -tc_779080bf, TypeS_3op>, Enc_a56825 { +tc_8a825db2, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001010; @@ -25209,7 +25538,7 @@ def S4_vxsubaddh : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vxsubaddh($Rss32,$Rtt32):sat", -tc_779080bf, TypeS_3op>, Enc_a56825 { +tc_8a825db2, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b110; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001010; @@ -25220,7 +25549,7 @@ def S4_vxsubaddhr : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vxsubaddh($Rss32,$Rtt32):rnd:>>1:sat", -tc_002cb246, TypeS_3op>, Enc_a56825 { +tc_0dfac0a7, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001110; @@ -25231,7 +25560,7 @@ def S4_vxsubaddw : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vxsubaddw($Rss32,$Rtt32):sat", -tc_779080bf, TypeS_3op>, Enc_a56825 { +tc_8a825db2, TypeS_3op>, Enc_a56825 { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001010; @@ -25242,7 +25571,7 @@ def S5_asrhub_rnd_sat : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, u4_0Imm:$Ii), "$Rd32 = vasrhub($Rss32,#$Ii):raw", -tc_002cb246, TypeS_2op>, Enc_11a146 { +tc_0dfac0a7, TypeS_2op>, Enc_11a146 { let Inst{7-5} = 0b100; let Inst{13-12} = 0b00; let Inst{31-21} = 0b10001000011; @@ -25255,7 +25584,7 @@ def S5_asrhub_rnd_sat_goodsyntax : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, u4_0Imm:$Ii), "$Rd32 = vasrhub($Rss32,#$Ii):rnd:sat", -tc_002cb246, TypeS_2op> { +tc_0dfac0a7, TypeS_2op> { let hasNewValue = 1; let opNewValue = 0; let isPseudo = 1; @@ -25264,7 +25593,7 @@ def S5_asrhub_sat : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32, u4_0Imm:$Ii), "$Rd32 = vasrhub($Rss32,#$Ii):sat", -tc_002cb246, TypeS_2op>, Enc_11a146 { +tc_0dfac0a7, TypeS_2op>, Enc_11a146 { let Inst{7-5} = 0b101; let Inst{13-12} = 0b00; let Inst{31-21} = 0b10001000011; @@ -25277,7 +25606,7 @@ def S5_popcountp : HInst< (outs IntRegs:$Rd32), (ins DoubleRegs:$Rss32), "$Rd32 = popcount($Rss32)", -tc_703e822c, TypeS_2op>, Enc_90cd8b { +tc_d3632d88, TypeS_2op>, Enc_90cd8b { let Inst{13-5} = 0b000000011; let Inst{31-21} = 0b10001000011; let hasNewValue = 1; @@ -25288,7 +25617,7 @@ def S5_vasrhrnd : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u4_0Imm:$Ii), "$Rdd32 = vasrh($Rss32,#$Ii):raw", -tc_002cb246, TypeS_2op>, Enc_12b6e9 { +tc_0dfac0a7, TypeS_2op>, Enc_12b6e9 { let Inst{7-5} = 0b000; let Inst{13-12} = 0b00; let Inst{31-21} = 0b10000000001; @@ -25298,14 +25627,14 @@ def S5_vasrhrnd_goodsyntax : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u4_0Imm:$Ii), "$Rdd32 = vasrh($Rss32,#$Ii):rnd", -tc_002cb246, TypeS_2op> { +tc_0dfac0a7, TypeS_2op> { let isPseudo = 1; } def S6_allocframe_to_raw : HInst< (outs), (ins u11_3Imm:$Ii), "allocframe(#$Ii)", -tc_b44ecf75, TypeMAPPING>, Requires<[HasV65]> { +tc_934753bb, TypeMAPPING>, Requires<[HasV65]> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -25313,7 +25642,7 @@ def S6_rol_i_p : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rdd32 = rol($Rss32,#$Ii)", -tc_1fc97744, TypeS_2op>, Enc_5eac98, Requires<[HasV60]> { +tc_407e96f9, TypeS_2op>, Enc_5eac98, Requires<[HasV60]> { let Inst{7-5} = 0b011; let Inst{31-21} = 0b10000000000; } @@ -25321,7 +25650,7 @@ def S6_rol_i_p_acc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 += rol($Rss32,#$Ii)", -tc_784490da, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> { +tc_5e4cf0e8, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> { let Inst{7-5} = 0b111; let Inst{31-21} = 0b10000010000; let prefersSlot3 = 1; @@ -25331,7 +25660,7 @@ def S6_rol_i_p_and : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 &= rol($Rss32,#$Ii)", -tc_784490da, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> { +tc_5e4cf0e8, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> { let Inst{7-5} = 0b011; let Inst{31-21} = 0b10000010010; let prefersSlot3 = 1; @@ -25341,7 +25670,7 @@ def S6_rol_i_p_nac : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 -= rol($Rss32,#$Ii)", -tc_784490da, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> { +tc_5e4cf0e8, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> { let Inst{7-5} = 0b011; let Inst{31-21} = 0b10000010000; let prefersSlot3 = 1; @@ -25351,7 +25680,7 @@ def S6_rol_i_p_or : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 |= rol($Rss32,#$Ii)", -tc_784490da, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> { +tc_5e4cf0e8, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> { let Inst{7-5} = 0b111; let Inst{31-21} = 0b10000010010; let prefersSlot3 = 1; @@ -25361,7 +25690,7 @@ def S6_rol_i_p_xacc : HInst< (outs DoubleRegs:$Rxx32), (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), "$Rxx32 ^= rol($Rss32,#$Ii)", -tc_784490da, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> { +tc_5e4cf0e8, TypeS_2op>, Enc_70fb07, Requires<[HasV60]> { let Inst{7-5} = 0b011; let Inst{31-21} = 0b10000010100; let prefersSlot3 = 1; @@ -25371,7 +25700,7 @@ def S6_rol_i_r : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, u5_0Imm:$Ii), "$Rd32 = rol($Rs32,#$Ii)", -tc_1fc97744, TypeS_2op>, Enc_a05677, Requires<[HasV60]> { +tc_407e96f9, TypeS_2op>, Enc_a05677, Requires<[HasV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001100000; @@ -25382,7 +25711,7 @@ def S6_rol_i_r_acc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 += rol($Rs32,#$Ii)", -tc_784490da, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> { +tc_5e4cf0e8, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110000; @@ -25395,7 +25724,7 @@ def S6_rol_i_r_and : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 &= rol($Rs32,#$Ii)", -tc_784490da, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> { +tc_5e4cf0e8, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110010; @@ -25408,7 +25737,7 @@ def S6_rol_i_r_nac : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 -= rol($Rs32,#$Ii)", -tc_784490da, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> { +tc_5e4cf0e8, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110000; @@ -25421,7 +25750,7 @@ def S6_rol_i_r_or : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 |= rol($Rs32,#$Ii)", -tc_784490da, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> { +tc_5e4cf0e8, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> { let Inst{7-5} = 0b111; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110010; @@ -25434,7 +25763,7 @@ def S6_rol_i_r_xacc : HInst< (outs IntRegs:$Rx32), (ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), "$Rx32 ^= rol($Rs32,#$Ii)", -tc_784490da, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> { +tc_5e4cf0e8, TypeS_2op>, Enc_28a2dc, Requires<[HasV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10001110100; @@ -25447,7 +25776,7 @@ def S6_vsplatrbp : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32), "$Rdd32 = vsplatb($Rs32)", -tc_a1c00888, TypeS_2op>, Enc_3a3d62, Requires<[HasV62]> { +tc_ef921005, TypeS_2op>, Enc_3a3d62, Requires<[HasV62]> { let Inst{13-5} = 0b000000100; let Inst{31-21} = 0b10000100010; } @@ -25455,7 +25784,7 @@ def S6_vtrunehb_ppp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vtrunehb($Rss32,$Rtt32)", -tc_1fc97744, TypeS_3op>, Enc_a56825, Requires<[HasV62]> { +tc_407e96f9, TypeS_3op>, Enc_a56825, Requires<[HasV62]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001100; @@ -25464,7 +25793,7 @@ def S6_vtrunohb_ppp : HInst< (outs DoubleRegs:$Rdd32), (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), "$Rdd32 = vtrunohb($Rss32,$Rtt32)", -tc_1fc97744, TypeS_3op>, Enc_a56825, Requires<[HasV62]> { +tc_407e96f9, TypeS_3op>, Enc_a56825, Requires<[HasV62]> { let Inst{7-5} = 0b101; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11000001100; @@ -25473,7 +25802,7 @@ def SA1_addi : HInst< (outs GeneralSubRegs:$Rx16), (ins IntRegs:$Rx16in, s32_0Imm:$Ii), "$Rx16 = add($Rx16in,#$Ii)", -tc_0a705168, TypeSUBINSN>, Enc_93af4c { +tc_5b347363, TypeSUBINSN>, Enc_93af4c { let Inst{12-11} = 0b00; let hasNewValue = 1; let opNewValue = 0; @@ -25490,7 +25819,7 @@ def SA1_addrx : HInst< (outs GeneralSubRegs:$Rx16), (ins IntRegs:$Rx16in, GeneralSubRegs:$Rs16), "$Rx16 = add($Rx16in,$Rs16)", -tc_0a705168, TypeSUBINSN>, Enc_0527db { +tc_5b347363, TypeSUBINSN>, Enc_0527db { let Inst{12-8} = 0b11000; let hasNewValue = 1; let opNewValue = 0; @@ -25502,7 +25831,7 @@ def SA1_addsp : HInst< (outs GeneralSubRegs:$Rd16), (ins u6_2Imm:$Ii), "$Rd16 = add(r29,#$Ii)", -tc_9fc3dae0, TypeSUBINSN>, Enc_2df31d { +tc_3d14a17b, TypeSUBINSN>, Enc_2df31d { let Inst{12-10} = 0b011; let hasNewValue = 1; let opNewValue = 0; @@ -25514,7 +25843,7 @@ def SA1_and1 : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16), "$Rd16 = and($Rs16,#1)", -tc_9fc3dae0, TypeSUBINSN>, Enc_97d666 { +tc_3d14a17b, TypeSUBINSN>, Enc_97d666 { let Inst{12-8} = 0b10010; let hasNewValue = 1; let opNewValue = 0; @@ -25525,7 +25854,7 @@ def SA1_clrf : HInst< (outs GeneralSubRegs:$Rd16), (ins), "if (!p0) $Rd16 = #0", -tc_a1123dda, TypeSUBINSN>, Enc_1f5ba6 { +tc_3fbf1042, TypeSUBINSN>, Enc_1f5ba6 { let Inst{12-4} = 0b110100111; let isPredicated = 1; let isPredicatedFalse = 1; @@ -25539,7 +25868,7 @@ def SA1_clrfnew : HInst< (outs GeneralSubRegs:$Rd16), (ins), "if (!p0.new) $Rd16 = #0", -tc_8b3e402a, TypeSUBINSN>, Enc_1f5ba6 { +tc_63567288, TypeSUBINSN>, Enc_1f5ba6 { let Inst{12-4} = 0b110100101; let isPredicated = 1; let isPredicatedFalse = 1; @@ -25554,7 +25883,7 @@ def SA1_clrt : HInst< (outs GeneralSubRegs:$Rd16), (ins), "if (p0) $Rd16 = #0", -tc_a1123dda, TypeSUBINSN>, Enc_1f5ba6 { +tc_3fbf1042, TypeSUBINSN>, Enc_1f5ba6 { let Inst{12-4} = 0b110100110; let isPredicated = 1; let hasNewValue = 1; @@ -25567,7 +25896,7 @@ def SA1_clrtnew : HInst< (outs GeneralSubRegs:$Rd16), (ins), "if (p0.new) $Rd16 = #0", -tc_8b3e402a, TypeSUBINSN>, Enc_1f5ba6 { +tc_63567288, TypeSUBINSN>, Enc_1f5ba6 { let Inst{12-4} = 0b110100100; let isPredicated = 1; let hasNewValue = 1; @@ -25581,7 +25910,7 @@ def SA1_cmpeqi : HInst< (outs), (ins GeneralSubRegs:$Rs16, u2_0Imm:$Ii), "p0 = cmp.eq($Rs16,#$Ii)", -tc_5b7c0967, TypeSUBINSN>, Enc_63eaeb { +tc_59a7822c, TypeSUBINSN>, Enc_63eaeb { let Inst{3-2} = 0b00; let Inst{12-8} = 0b11001; let AsmVariantName = "NonParsable"; @@ -25592,7 +25921,7 @@ def SA1_combine0i : HInst< (outs GeneralDoubleLow8Regs:$Rdd8), (ins u2_0Imm:$Ii), "$Rdd8 = combine(#0,#$Ii)", -tc_9fc3dae0, TypeSUBINSN>, Enc_ed48be { +tc_3d14a17b, TypeSUBINSN>, Enc_ed48be { let Inst{4-3} = 0b00; let Inst{12-7} = 0b111000; let hasNewValue = 1; @@ -25604,7 +25933,7 @@ def SA1_combine1i : HInst< (outs GeneralDoubleLow8Regs:$Rdd8), (ins u2_0Imm:$Ii), "$Rdd8 = combine(#1,#$Ii)", -tc_9fc3dae0, TypeSUBINSN>, Enc_ed48be { +tc_3d14a17b, TypeSUBINSN>, Enc_ed48be { let Inst{4-3} = 0b01; let Inst{12-7} = 0b111000; let hasNewValue = 1; @@ -25616,7 +25945,7 @@ def SA1_combine2i : HInst< (outs GeneralDoubleLow8Regs:$Rdd8), (ins u2_0Imm:$Ii), "$Rdd8 = combine(#2,#$Ii)", -tc_9fc3dae0, TypeSUBINSN>, Enc_ed48be { +tc_3d14a17b, TypeSUBINSN>, Enc_ed48be { let Inst{4-3} = 0b10; let Inst{12-7} = 0b111000; let hasNewValue = 1; @@ -25628,7 +25957,7 @@ def SA1_combine3i : HInst< (outs GeneralDoubleLow8Regs:$Rdd8), (ins u2_0Imm:$Ii), "$Rdd8 = combine(#3,#$Ii)", -tc_9fc3dae0, TypeSUBINSN>, Enc_ed48be { +tc_3d14a17b, TypeSUBINSN>, Enc_ed48be { let Inst{4-3} = 0b11; let Inst{12-7} = 0b111000; let hasNewValue = 1; @@ -25640,7 +25969,7 @@ def SA1_combinerz : HInst< (outs GeneralDoubleLow8Regs:$Rdd8), (ins GeneralSubRegs:$Rs16), "$Rdd8 = combine($Rs16,#0)", -tc_9fc3dae0, TypeSUBINSN>, Enc_399e12 { +tc_3d14a17b, TypeSUBINSN>, Enc_399e12 { let Inst{3-3} = 0b1; let Inst{12-8} = 0b11101; let hasNewValue = 1; @@ -25652,7 +25981,7 @@ def SA1_combinezr : HInst< (outs GeneralDoubleLow8Regs:$Rdd8), (ins GeneralSubRegs:$Rs16), "$Rdd8 = combine(#0,$Rs16)", -tc_9fc3dae0, TypeSUBINSN>, Enc_399e12 { +tc_3d14a17b, TypeSUBINSN>, Enc_399e12 { let Inst{3-3} = 0b0; let Inst{12-8} = 0b11101; let hasNewValue = 1; @@ -25664,7 +25993,7 @@ def SA1_dec : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16, n1Const:$n1), "$Rd16 = add($Rs16,#$n1)", -tc_0a705168, TypeSUBINSN>, Enc_ee5ed0 { +tc_5b347363, TypeSUBINSN>, Enc_ee5ed0 { let Inst{12-8} = 0b10011; let hasNewValue = 1; let opNewValue = 0; @@ -25675,7 +26004,7 @@ def SA1_inc : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16), "$Rd16 = add($Rs16,#1)", -tc_9fc3dae0, TypeSUBINSN>, Enc_97d666 { +tc_3d14a17b, TypeSUBINSN>, Enc_97d666 { let Inst{12-8} = 0b10001; let hasNewValue = 1; let opNewValue = 0; @@ -25686,7 +26015,7 @@ def SA1_seti : HInst< (outs GeneralSubRegs:$Rd16), (ins u32_0Imm:$Ii), "$Rd16 = #$Ii", -tc_9fc3dae0, TypeSUBINSN>, Enc_e39bb2 { +tc_3d14a17b, TypeSUBINSN>, Enc_e39bb2 { let Inst{12-10} = 0b010; let hasNewValue = 1; let opNewValue = 0; @@ -25702,7 +26031,7 @@ def SA1_setin1 : HInst< (outs GeneralSubRegs:$Rd16), (ins n1Const:$n1), "$Rd16 = #$n1", -tc_9fc3dae0, TypeSUBINSN>, Enc_7a0ea6 { +tc_3d14a17b, TypeSUBINSN>, Enc_7a0ea6 { let Inst{12-4} = 0b110100000; let hasNewValue = 1; let opNewValue = 0; @@ -25713,7 +26042,7 @@ def SA1_sxtb : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16), "$Rd16 = sxtb($Rs16)", -tc_9fc3dae0, TypeSUBINSN>, Enc_97d666 { +tc_3d14a17b, TypeSUBINSN>, Enc_97d666 { let Inst{12-8} = 0b10101; let hasNewValue = 1; let opNewValue = 0; @@ -25724,7 +26053,7 @@ def SA1_sxth : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16), "$Rd16 = sxth($Rs16)", -tc_9fc3dae0, TypeSUBINSN>, Enc_97d666 { +tc_3d14a17b, TypeSUBINSN>, Enc_97d666 { let Inst{12-8} = 0b10100; let hasNewValue = 1; let opNewValue = 0; @@ -25735,7 +26064,7 @@ def SA1_tfr : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16), "$Rd16 = $Rs16", -tc_9fc3dae0, TypeSUBINSN>, Enc_97d666 { +tc_3d14a17b, TypeSUBINSN>, Enc_97d666 { let Inst{12-8} = 0b10000; let hasNewValue = 1; let opNewValue = 0; @@ -25746,7 +26075,7 @@ def SA1_zxtb : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16), "$Rd16 = and($Rs16,#255)", -tc_9fc3dae0, TypeSUBINSN>, Enc_97d666 { +tc_3d14a17b, TypeSUBINSN>, Enc_97d666 { let Inst{12-8} = 0b10111; let hasNewValue = 1; let opNewValue = 0; @@ -25757,7 +26086,7 @@ def SA1_zxth : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16), "$Rd16 = zxth($Rs16)", -tc_9fc3dae0, TypeSUBINSN>, Enc_97d666 { +tc_3d14a17b, TypeSUBINSN>, Enc_97d666 { let Inst{12-8} = 0b10110; let hasNewValue = 1; let opNewValue = 0; @@ -25768,7 +26097,7 @@ def SL1_loadri_io : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii), "$Rd16 = memw($Rs16+#$Ii)", -tc_17e0d2cd, TypeSUBINSN>, Enc_53dca9 { +tc_4222e6bf, TypeSUBINSN>, Enc_53dca9 { let Inst{12-12} = 0b0; let hasNewValue = 1; let opNewValue = 0; @@ -25782,7 +26111,7 @@ def SL1_loadrub_io : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii), "$Rd16 = memub($Rs16+#$Ii)", -tc_17e0d2cd, TypeSUBINSN>, Enc_c175d0 { +tc_4222e6bf, TypeSUBINSN>, Enc_c175d0 { let Inst{12-12} = 0b1; let hasNewValue = 1; let opNewValue = 0; @@ -25796,20 +26125,20 @@ def SL2_deallocframe : HInst< (outs), (ins), "deallocframe", -tc_39dfefe8, TypeSUBINSN>, Enc_e3b0c4 { +tc_937dd41c, TypeSUBINSN>, Enc_e3b0c4 { let Inst{12-0} = 0b1111100000000; let accessSize = DoubleWordAccess; let AsmVariantName = "NonParsable"; let mayLoad = 1; let Uses = [FRAMEKEY, R30]; -let Defs = [R30, R29, R31]; +let Defs = [R29, R30, R31]; let DecoderNamespace = "SUBINSN_L2"; } def SL2_jumpr31 : HInst< (outs), (ins), "jumpr r31", -tc_b4407292, TypeSUBINSN>, Enc_e3b0c4 { +tc_a4ee89db, TypeSUBINSN>, Enc_e3b0c4 { let Inst{12-0} = 0b1111111000000; let isTerminator = 1; let isIndirectBranch = 1; @@ -25824,7 +26153,7 @@ def SL2_jumpr31_f : HInst< (outs), (ins), "if (!p0) jumpr r31", -tc_b4407292, TypeSUBINSN>, Enc_e3b0c4 { +tc_a4ee89db, TypeSUBINSN>, Enc_e3b0c4 { let Inst{12-0} = 0b1111111000101; let isPredicated = 1; let isPredicatedFalse = 1; @@ -25842,7 +26171,7 @@ def SL2_jumpr31_fnew : HInst< (outs), (ins), "if (!p0.new) jumpr:nt r31", -tc_b4407292, TypeSUBINSN>, Enc_e3b0c4 { +tc_a4ee89db, TypeSUBINSN>, Enc_e3b0c4 { let Inst{12-0} = 0b1111111000111; let isPredicated = 1; let isPredicatedFalse = 1; @@ -25861,7 +26190,7 @@ def SL2_jumpr31_t : HInst< (outs), (ins), "if (p0) jumpr r31", -tc_b4407292, TypeSUBINSN>, Enc_e3b0c4 { +tc_a4ee89db, TypeSUBINSN>, Enc_e3b0c4 { let Inst{12-0} = 0b1111111000100; let isPredicated = 1; let isTerminator = 1; @@ -25878,7 +26207,7 @@ def SL2_jumpr31_tnew : HInst< (outs), (ins), "if (p0.new) jumpr:nt r31", -tc_b4407292, TypeSUBINSN>, Enc_e3b0c4 { +tc_a4ee89db, TypeSUBINSN>, Enc_e3b0c4 { let Inst{12-0} = 0b1111111000110; let isPredicated = 1; let isTerminator = 1; @@ -25896,7 +26225,7 @@ def SL2_loadrb_io : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16, u3_0Imm:$Ii), "$Rd16 = memb($Rs16+#$Ii)", -tc_17e0d2cd, TypeSUBINSN>, Enc_2fbf3c { +tc_4222e6bf, TypeSUBINSN>, Enc_2fbf3c { let Inst{12-11} = 0b10; let hasNewValue = 1; let opNewValue = 0; @@ -25910,7 +26239,7 @@ def SL2_loadrd_sp : HInst< (outs GeneralDoubleLow8Regs:$Rdd8), (ins u5_3Imm:$Ii), "$Rdd8 = memd(r29+#$Ii)", -tc_c4db48cb, TypeSUBINSN>, Enc_86a14b { +tc_8a6d0d94, TypeSUBINSN>, Enc_86a14b { let Inst{12-8} = 0b11110; let hasNewValue = 1; let opNewValue = 0; @@ -25925,7 +26254,7 @@ def SL2_loadrh_io : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii), "$Rd16 = memh($Rs16+#$Ii)", -tc_17e0d2cd, TypeSUBINSN>, Enc_2bae10 { +tc_4222e6bf, TypeSUBINSN>, Enc_2bae10 { let Inst{12-11} = 0b00; let hasNewValue = 1; let opNewValue = 0; @@ -25939,7 +26268,7 @@ def SL2_loadri_sp : HInst< (outs GeneralSubRegs:$Rd16), (ins u5_2Imm:$Ii), "$Rd16 = memw(r29+#$Ii)", -tc_c4db48cb, TypeSUBINSN>, Enc_51635c { +tc_8a6d0d94, TypeSUBINSN>, Enc_51635c { let Inst{12-9} = 0b1110; let hasNewValue = 1; let opNewValue = 0; @@ -25954,7 +26283,7 @@ def SL2_loadruh_io : HInst< (outs GeneralSubRegs:$Rd16), (ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii), "$Rd16 = memuh($Rs16+#$Ii)", -tc_17e0d2cd, TypeSUBINSN>, Enc_2bae10 { +tc_4222e6bf, TypeSUBINSN>, Enc_2bae10 { let Inst{12-11} = 0b01; let hasNewValue = 1; let opNewValue = 0; @@ -25968,7 +26297,7 @@ def SL2_return : HInst< (outs), (ins), "dealloc_return", -tc_36153880, TypeSUBINSN>, Enc_e3b0c4 { +tc_c818ff7f, TypeSUBINSN>, Enc_e3b0c4 { let Inst{12-0} = 0b1111101000000; let isTerminator = 1; let isIndirectBranch = 1; @@ -25979,14 +26308,14 @@ let cofMax1 = 1; let isRestrictNoSlot1Store = 1; let isReturn = 1; let Uses = [FRAMEKEY, R30]; -let Defs = [PC, R30, R29, R31]; +let Defs = [PC, R29, R30, R31]; let DecoderNamespace = "SUBINSN_L2"; } def SL2_return_f : HInst< (outs), (ins), "if (!p0) dealloc_return", -tc_36153880, TypeSUBINSN>, Enc_e3b0c4 { +tc_c818ff7f, TypeSUBINSN>, Enc_e3b0c4 { let Inst{12-0} = 0b1111101000101; let isPredicated = 1; let isPredicatedFalse = 1; @@ -25999,7 +26328,7 @@ let cofMax1 = 1; let isRestrictNoSlot1Store = 1; let isReturn = 1; let Uses = [FRAMEKEY, P0, R30]; -let Defs = [PC, R30, R29, R31]; +let Defs = [PC, R29, R30, R31]; let isTaken = Inst{4}; let DecoderNamespace = "SUBINSN_L2"; } @@ -26007,7 +26336,7 @@ def SL2_return_fnew : HInst< (outs), (ins), "if (!p0.new) dealloc_return:nt", -tc_36153880, TypeSUBINSN>, Enc_e3b0c4 { +tc_c818ff7f, TypeSUBINSN>, Enc_e3b0c4 { let Inst{12-0} = 0b1111101000111; let isPredicated = 1; let isPredicatedFalse = 1; @@ -26021,7 +26350,7 @@ let cofMax1 = 1; let isRestrictNoSlot1Store = 1; let isReturn = 1; let Uses = [FRAMEKEY, P0, R30]; -let Defs = [PC, R30, R29, R31]; +let Defs = [PC, R29, R30, R31]; let isTaken = Inst{4}; let DecoderNamespace = "SUBINSN_L2"; } @@ -26029,7 +26358,7 @@ def SL2_return_t : HInst< (outs), (ins), "if (p0) dealloc_return", -tc_36153880, TypeSUBINSN>, Enc_e3b0c4 { +tc_c818ff7f, TypeSUBINSN>, Enc_e3b0c4 { let Inst{12-0} = 0b1111101000100; let isPredicated = 1; let isTerminator = 1; @@ -26041,7 +26370,7 @@ let cofMax1 = 1; let isRestrictNoSlot1Store = 1; let isReturn = 1; let Uses = [FRAMEKEY, P0, R30]; -let Defs = [PC, R30, R29, R31]; +let Defs = [PC, R29, R30, R31]; let isTaken = Inst{4}; let DecoderNamespace = "SUBINSN_L2"; } @@ -26049,7 +26378,7 @@ def SL2_return_tnew : HInst< (outs), (ins), "if (p0.new) dealloc_return:nt", -tc_36153880, TypeSUBINSN>, Enc_e3b0c4 { +tc_c818ff7f, TypeSUBINSN>, Enc_e3b0c4 { let Inst{12-0} = 0b1111101000110; let isPredicated = 1; let isTerminator = 1; @@ -26062,7 +26391,7 @@ let cofMax1 = 1; let isRestrictNoSlot1Store = 1; let isReturn = 1; let Uses = [FRAMEKEY, P0, R30]; -let Defs = [PC, R30, R29, R31]; +let Defs = [PC, R29, R30, R31]; let isTaken = Inst{4}; let DecoderNamespace = "SUBINSN_L2"; } @@ -26070,7 +26399,7 @@ def SS1_storeb_io : HInst< (outs), (ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii, GeneralSubRegs:$Rt16), "memb($Rs16+#$Ii) = $Rt16", -tc_30b9bb4a, TypeSUBINSN>, Enc_b38ffc { +tc_ae5babd7, TypeSUBINSN>, Enc_b38ffc { let Inst{12-12} = 0b1; let addrMode = BaseImmOffset; let accessSize = ByteAccess; @@ -26082,7 +26411,7 @@ def SS1_storew_io : HInst< (outs), (ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii, GeneralSubRegs:$Rt16), "memw($Rs16+#$Ii) = $Rt16", -tc_30b9bb4a, TypeSUBINSN>, Enc_f55a0c { +tc_ae5babd7, TypeSUBINSN>, Enc_f55a0c { let Inst{12-12} = 0b0; let addrMode = BaseImmOffset; let accessSize = WordAccess; @@ -26094,22 +26423,22 @@ def SS2_allocframe : HInst< (outs), (ins u5_3Imm:$Ii), "allocframe(#$Ii)", -tc_49a8207d, TypeSUBINSN>, Enc_6f70ca { +tc_1242dc2a, TypeSUBINSN>, Enc_6f70ca { let Inst{3-0} = 0b0000; let Inst{12-9} = 0b1110; let addrMode = BaseImmOffset; let accessSize = DoubleWordAccess; let AsmVariantName = "NonParsable"; let mayStore = 1; -let Uses = [FRAMEKEY, FRAMELIMIT, R30, R29, R31]; -let Defs = [R30, R29]; +let Uses = [FRAMEKEY, FRAMELIMIT, R29, R30, R31]; +let Defs = [R29, R30]; let DecoderNamespace = "SUBINSN_S2"; } def SS2_storebi0 : HInst< (outs), (ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii), "memb($Rs16+#$Ii) = #0", -tc_89e94ad3, TypeSUBINSN>, Enc_84d359 { +tc_44d5a428, TypeSUBINSN>, Enc_84d359 { let Inst{12-8} = 0b10010; let addrMode = BaseImmOffset; let accessSize = ByteAccess; @@ -26121,7 +26450,7 @@ def SS2_storebi1 : HInst< (outs), (ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii), "memb($Rs16+#$Ii) = #1", -tc_89e94ad3, TypeSUBINSN>, Enc_84d359 { +tc_44d5a428, TypeSUBINSN>, Enc_84d359 { let Inst{12-8} = 0b10011; let addrMode = BaseImmOffset; let accessSize = ByteAccess; @@ -26133,7 +26462,7 @@ def SS2_stored_sp : HInst< (outs), (ins s6_3Imm:$Ii, GeneralDoubleLow8Regs:$Rtt8), "memd(r29+#$Ii) = $Rtt8", -tc_0371abea, TypeSUBINSN>, Enc_b8309d { +tc_0655b949, TypeSUBINSN>, Enc_b8309d { let Inst{12-9} = 0b0101; let addrMode = BaseImmOffset; let accessSize = DoubleWordAccess; @@ -26146,7 +26475,7 @@ def SS2_storeh_io : HInst< (outs), (ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii, GeneralSubRegs:$Rt16), "memh($Rs16+#$Ii) = $Rt16", -tc_30b9bb4a, TypeSUBINSN>, Enc_625deb { +tc_ae5babd7, TypeSUBINSN>, Enc_625deb { let Inst{12-11} = 0b00; let addrMode = BaseImmOffset; let accessSize = HalfWordAccess; @@ -26158,7 +26487,7 @@ def SS2_storew_sp : HInst< (outs), (ins u5_2Imm:$Ii, GeneralSubRegs:$Rt16), "memw(r29+#$Ii) = $Rt16", -tc_0371abea, TypeSUBINSN>, Enc_87c142 { +tc_0655b949, TypeSUBINSN>, Enc_87c142 { let Inst{12-9} = 0b0100; let addrMode = BaseImmOffset; let accessSize = WordAccess; @@ -26171,7 +26500,7 @@ def SS2_storewi0 : HInst< (outs), (ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii), "memw($Rs16+#$Ii) = #0", -tc_89e94ad3, TypeSUBINSN>, Enc_a6ce9c { +tc_44d5a428, TypeSUBINSN>, Enc_a6ce9c { let Inst{12-8} = 0b10000; let addrMode = BaseImmOffset; let accessSize = WordAccess; @@ -26183,7 +26512,7 @@ def SS2_storewi1 : HInst< (outs), (ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii), "memw($Rs16+#$Ii) = #1", -tc_89e94ad3, TypeSUBINSN>, Enc_a6ce9c { +tc_44d5a428, TypeSUBINSN>, Enc_a6ce9c { let Inst{12-8} = 0b10001; let addrMode = BaseImmOffset; let accessSize = WordAccess; @@ -26198,6 +26527,7 @@ def V6_MAP_equb : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26207,6 +26537,7 @@ def V6_MAP_equb_and : HInst< (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.eq($Vu32.ub,$Vv32.ub)", PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26218,6 +26549,7 @@ def V6_MAP_equb_ior : HInst< "$Qx4 |= vcmp.eq($Vu32.ub,$Vv32.ub)", PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26228,6 +26560,7 @@ def V6_MAP_equb_xor : HInst< (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.eq($Vu32.ub,$Vv32.ub)", PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26240,6 +26573,7 @@ def V6_MAP_equh : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26249,6 +26583,7 @@ def V6_MAP_equh_and : HInst< (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.eq($Vu32.uh,$Vv32.uh)", PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26260,6 +26595,7 @@ def V6_MAP_equh_ior : HInst< "$Qx4 |= vcmp.eq($Vu32.uh,$Vv32.uh)", PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26270,6 +26606,7 @@ def V6_MAP_equh_xor : HInst< (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.eq($Vu32.uh,$Vv32.uh)", PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26282,6 +26619,7 @@ def V6_MAP_equw : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26291,6 +26629,7 @@ def V6_MAP_equw_and : HInst< (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 &= vcmp.eq($Vu32.uw,$Vv32.uw)", PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26302,6 +26641,7 @@ def V6_MAP_equw_ior : HInst< "$Qx4 |= vcmp.eq($Vu32.uw,$Vv32.uw)", PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26312,6 +26652,7 @@ def V6_MAP_equw_xor : HInst< (ins HvxQR:$Qx4in, HvxVR:$Vu32, HvxVR:$Vv32), "$Qx4 ^= vcmp.eq($Vu32.uw,$Vv32.uw)", PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26327,6 +26668,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b10010010000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isSolo = 1; let mayLoad = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26338,6 +26680,7 @@ def V6_extractw_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26349,6 +26692,7 @@ def V6_hi : HInst< CVI_VA, TypeCVI_VA>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let DecoderNamespace = "EXT_mmvec"; } @@ -26359,6 +26703,7 @@ def V6_ld0 : HInst< PSEUDO, TypeCVI_VM_LD>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26370,6 +26715,7 @@ def V6_ldcnp0 : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26381,6 +26727,7 @@ def V6_ldcnpnt0 : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26392,6 +26739,7 @@ def V6_ldcp0 : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26403,6 +26751,7 @@ def V6_ldcpnt0 : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26414,6 +26763,7 @@ def V6_ldnp0 : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26425,6 +26775,7 @@ def V6_ldnpnt0 : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26436,6 +26787,7 @@ def V6_ldnt0 : HInst< PSEUDO, TypeCVI_VM_LD>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26458,6 +26810,7 @@ def V6_ldp0 : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26469,6 +26822,7 @@ def V6_ldpnt0 : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26480,6 +26834,7 @@ def V6_ldtnp0 : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26491,6 +26846,7 @@ def V6_ldtnpnt0 : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26502,6 +26858,7 @@ def V6_ldtp0 : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26513,6 +26870,7 @@ def V6_ldtpnt0 : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26524,6 +26882,7 @@ def V6_ldu0 : HInst< PSEUDO, TypeCVI_VM_LD>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26535,6 +26894,7 @@ def V6_lo : HInst< CVI_VA, TypeCVI_VA>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let DecoderNamespace = "EXT_mmvec"; } @@ -26542,22 +26902,24 @@ def V6_lvsplatb : HInst< (outs HvxVR:$Vd32), (ins IntRegs:$Rt32), "$Vd32.b = vsplat($Rt32)", -tc_c4edf264, TypeCVI_VX>, Enc_a5ed8a, Requires<[UseHVXV62]> { +tc_c4edf264, TypeCVI_VX_LATE>, Enc_a5ed8a, Requires<[UseHVXV62]> { let Inst{13-5} = 0b000000010; let Inst{31-21} = 0b00011001110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_lvsplath : HInst< (outs HvxVR:$Vd32), (ins IntRegs:$Rt32), "$Vd32.h = vsplat($Rt32)", -tc_c4edf264, TypeCVI_VX>, Enc_a5ed8a, Requires<[UseHVXV62]> { +tc_c4edf264, TypeCVI_VX_LATE>, Enc_a5ed8a, Requires<[UseHVXV62]> { let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b00011001110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_lvsplatw : HInst< @@ -26569,6 +26931,7 @@ let Inst{13-5} = 0b000000001; let Inst{31-21} = 0b00011001101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_pred_and : HInst< @@ -26582,6 +26945,7 @@ let Inst{21-16} = 0b000011; let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_pred_and_n : HInst< @@ -26595,6 +26959,7 @@ let Inst{21-16} = 0b000011; let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_pred_not : HInst< @@ -26607,6 +26972,7 @@ let Inst{13-10} = 0b0000; let Inst{31-16} = 0b0001111000000011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_pred_or : HInst< @@ -26620,6 +26986,7 @@ let Inst{21-16} = 0b000011; let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_pred_or_n : HInst< @@ -26633,6 +27000,7 @@ let Inst{21-16} = 0b000011; let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_pred_scalar2 : HInst< @@ -26644,6 +27012,7 @@ let Inst{13-2} = 0b000000010001; let Inst{31-21} = 0b00011001101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_pred_scalar2v2 : HInst< @@ -26655,6 +27024,7 @@ let Inst{13-2} = 0b000000010011; let Inst{31-21} = 0b00011001101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_pred_xor : HInst< @@ -26668,6 +27038,7 @@ let Inst{21-16} = 0b000011; let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_shuffeqh : HInst< @@ -26681,6 +27052,7 @@ let Inst{21-16} = 0b000011; let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_shuffeqw : HInst< @@ -26694,6 +27066,7 @@ let Inst{21-16} = 0b000011; let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_st0 : HInst< @@ -26701,6 +27074,7 @@ def V6_st0 : HInst< (ins IntRegs:$Rt32, HvxVR:$Vs32), "vmem($Rt32) = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26710,6 +27084,7 @@ def V6_stn0 : HInst< (ins IntRegs:$Rt32, HvxVR:$Os8), "vmem($Rt32) = $Os8.new", PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26720,6 +27095,7 @@ def V6_stnnt0 : HInst< (ins IntRegs:$Rt32, HvxVR:$Os8), "vmem($Rt32):nt = $Os8.new", PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26730,6 +27106,7 @@ def V6_stnp0 : HInst< (ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32), "if (!$Pv4) vmem($Rt32) = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26739,6 +27116,7 @@ def V6_stnpnt0 : HInst< (ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32), "if (!$Pv4) vmem($Rt32):nt = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26748,6 +27126,7 @@ def V6_stnq0 : HInst< (ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32), "if (!$Qv4) vmem($Rt32) = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26757,6 +27136,7 @@ def V6_stnqnt0 : HInst< (ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32), "if (!$Qv4) vmem($Rt32):nt = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26766,6 +27146,7 @@ def V6_stnt0 : HInst< (ins IntRegs:$Rt32, HvxVR:$Vs32), "vmem($Rt32):nt = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26775,6 +27156,7 @@ def V6_stp0 : HInst< (ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32), "if ($Pv4) vmem($Rt32) = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26784,6 +27166,7 @@ def V6_stpnt0 : HInst< (ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32), "if ($Pv4) vmem($Rt32):nt = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26793,6 +27176,7 @@ def V6_stq0 : HInst< (ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32), "if ($Qv4) vmem($Rt32) = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26802,6 +27186,7 @@ def V6_stqnt0 : HInst< (ins HvxQR:$Qv4, IntRegs:$Rt32, HvxVR:$Vs32), "if ($Qv4) vmem($Rt32):nt = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26811,6 +27196,7 @@ def V6_stu0 : HInst< (ins IntRegs:$Rt32, HvxVR:$Vs32), "vmemu($Rt32) = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26820,6 +27206,7 @@ def V6_stunp0 : HInst< (ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32), "if (!$Pv4) vmemu($Rt32) = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26829,6 +27216,7 @@ def V6_stup0 : HInst< (ins PredRegs:$Pv4, IntRegs:$Rt32, HvxVR:$Vs32), "if ($Pv4) vmemu($Rt32) = $Vs32", PSEUDO, TypeCVI_VM_ST>, Requires<[UseHVXV60]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26846,6 +27234,7 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26863,6 +27252,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_pi"; @@ -26881,6 +27271,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let DecoderNamespace = "EXT_mmvec"; @@ -26899,6 +27290,7 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_ai"; @@ -26919,6 +27311,7 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let CVINew = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; @@ -26940,6 +27333,7 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let CVINew = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; @@ -26961,6 +27355,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let CVINew = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; @@ -26982,6 +27377,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let CVINew = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; @@ -27002,6 +27398,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let CVINew = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; @@ -27022,6 +27419,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let CVINew = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; @@ -27043,6 +27441,7 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let CVINew = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; @@ -27063,6 +27462,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let CVINew = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; @@ -27083,6 +27483,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let CVINew = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; @@ -27104,6 +27505,7 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_ai"; @@ -27124,6 +27526,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_pi"; @@ -27144,6 +27547,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_ppu"; @@ -27163,6 +27567,7 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -27184,6 +27589,7 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let CVINew = 1; let mayLoad = 1; let isNonTemporal = 1; @@ -27206,6 +27612,7 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let CVINew = 1; let mayLoad = 1; let isNonTemporal = 1; @@ -27228,6 +27635,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let CVINew = 1; let mayLoad = 1; let isNonTemporal = 1; @@ -27250,6 +27658,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let CVINew = 1; let mayLoad = 1; let isNonTemporal = 1; @@ -27271,6 +27680,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let CVINew = 1; let mayLoad = 1; let isNonTemporal = 1; @@ -27292,6 +27702,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let CVINew = 1; let mayLoad = 1; let isNonTemporal = 1; @@ -27314,6 +27725,7 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let CVINew = 1; let mayLoad = 1; let isNonTemporal = 1; @@ -27335,6 +27747,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let CVINew = 1; let mayLoad = 1; let isNonTemporal = 1; @@ -27356,6 +27769,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let CVINew = 1; let mayLoad = 1; let isNonTemporal = 1; @@ -27378,6 +27792,7 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -27399,6 +27814,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -27420,6 +27836,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -27440,6 +27857,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -27461,6 +27879,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -27483,6 +27902,7 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -27503,6 +27923,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -27523,6 +27944,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -27543,6 +27965,7 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -27564,6 +27987,7 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -27585,6 +28009,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -27606,6 +28031,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -27626,6 +28052,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -27646,6 +28073,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -27667,6 +28095,7 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -27687,6 +28116,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -27707,6 +28137,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isNonTemporal = 1; let isRestrictNoSlot1Store = 1; @@ -27727,6 +28158,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_pi"; @@ -27747,6 +28179,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_ppu"; @@ -27768,6 +28201,7 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_ai"; @@ -27787,6 +28221,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_pi"; @@ -27806,6 +28241,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_ppu"; @@ -27825,6 +28261,7 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_tmp_ai"; @@ -27845,6 +28282,7 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_tmp_ai"; @@ -27865,6 +28303,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_tmp_pi"; @@ -27885,6 +28324,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_tmp_ppu"; @@ -27904,6 +28344,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_tmp_pi"; @@ -27923,6 +28364,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_tmp_ppu"; @@ -27943,6 +28385,7 @@ let opNewValue = 0; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_tmp_ai"; @@ -27962,6 +28405,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_tmp_pi"; @@ -27981,6 +28425,7 @@ let opNewValue = 0; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isCVLoad = 1; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let BaseOpcode = "V6_vL32b_tmp_ppu"; @@ -27997,6 +28442,7 @@ let Inst{12-11} = 0b00; let Inst{31-21} = 0b00101000001; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let BaseOpcode = "V6_vS32Ub_ai"; let isPredicable = 1; @@ -28013,6 +28459,7 @@ let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let BaseOpcode = "V6_vS32Ub_ai"; let DecoderNamespace = "EXT_mmvec"; @@ -28029,6 +28476,7 @@ let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let BaseOpcode = "V6_vS32Ub_pi"; let DecoderNamespace = "EXT_mmvec"; @@ -28045,6 +28493,7 @@ let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let BaseOpcode = "V6_vS32Ub_ppu"; let DecoderNamespace = "EXT_mmvec"; @@ -28060,6 +28509,7 @@ let Inst{13-11} = 0b000; let Inst{31-21} = 0b00101001001; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let BaseOpcode = "V6_vS32Ub_pi"; let isPredicable = 1; @@ -28075,6 +28525,7 @@ let Inst{12-5} = 0b00000111; let Inst{31-21} = 0b00101011001; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let BaseOpcode = "V6_vS32Ub_ppu"; let isPredicable = 1; @@ -28091,6 +28542,7 @@ let Inst{31-21} = 0b00101000101; let isPredicated = 1; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let BaseOpcode = "V6_vS32Ub_ai"; let DecoderNamespace = "EXT_mmvec"; @@ -28106,6 +28558,7 @@ let Inst{31-21} = 0b00101001101; let isPredicated = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let BaseOpcode = "V6_vS32Ub_pi"; let DecoderNamespace = "EXT_mmvec"; @@ -28121,6 +28574,7 @@ let Inst{31-21} = 0b00101011101; let isPredicated = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let BaseOpcode = "V6_vS32Ub_ppu"; let DecoderNamespace = "EXT_mmvec"; @@ -28136,6 +28590,7 @@ let Inst{12-11} = 0b00; let Inst{31-21} = 0b00101000001; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_ai"; let isNVStorable = 1; @@ -28153,6 +28608,7 @@ let Inst{31-21} = 0b00101000001; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isNVStore = 1; +let isCVI = 1; let CVINew = 1; let isNewValue = 1; let mayStore = 1; @@ -28173,6 +28629,7 @@ let isPredicatedFalse = 1; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isNVStore = 1; +let isCVI = 1; let CVINew = 1; let isNewValue = 1; let mayStore = 1; @@ -28193,6 +28650,7 @@ let isPredicatedFalse = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isNVStore = 1; +let isCVI = 1; let CVINew = 1; let isNewValue = 1; let mayStore = 1; @@ -28213,6 +28671,7 @@ let isPredicatedFalse = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isNVStore = 1; +let isCVI = 1; let CVINew = 1; let isNewValue = 1; let mayStore = 1; @@ -28232,6 +28691,7 @@ let Inst{31-21} = 0b00101001001; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isNVStore = 1; +let isCVI = 1; let CVINew = 1; let isNewValue = 1; let mayStore = 1; @@ -28251,6 +28711,7 @@ let Inst{31-21} = 0b00101011001; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isNVStore = 1; +let isCVI = 1; let CVINew = 1; let isNewValue = 1; let mayStore = 1; @@ -28271,6 +28732,7 @@ let isPredicated = 1; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isNVStore = 1; +let isCVI = 1; let CVINew = 1; let isNewValue = 1; let mayStore = 1; @@ -28290,6 +28752,7 @@ let isPredicated = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isNVStore = 1; +let isCVI = 1; let CVINew = 1; let isNewValue = 1; let mayStore = 1; @@ -28309,6 +28772,7 @@ let isPredicated = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isNVStore = 1; +let isCVI = 1; let CVINew = 1; let isNewValue = 1; let mayStore = 1; @@ -28328,6 +28792,7 @@ let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_ai"; let isNVStorable = 1; @@ -28345,6 +28810,7 @@ let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_pi"; let isNVStorable = 1; @@ -28362,6 +28828,7 @@ let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_ppu"; let isNVStorable = 1; @@ -28377,6 +28844,7 @@ let Inst{7-5} = 0b001; let Inst{31-21} = 0b00101000100; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; } @@ -28390,6 +28858,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001100; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; @@ -28403,6 +28872,7 @@ let Inst{10-5} = 0b000001; let Inst{31-21} = 0b00101011100; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; @@ -28417,6 +28887,7 @@ let Inst{12-11} = 0b00; let Inst{31-21} = 0b00101000011; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; +let isCVI = 1; let isNonTemporal = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_ai"; @@ -28435,6 +28906,7 @@ let Inst{31-21} = 0b00101000011; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isNVStore = 1; +let isCVI = 1; let CVINew = 1; let isNewValue = 1; let isNonTemporal = 1; @@ -28456,6 +28928,7 @@ let isPredicatedFalse = 1; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isNVStore = 1; +let isCVI = 1; let CVINew = 1; let isNewValue = 1; let isNonTemporal = 1; @@ -28477,6 +28950,7 @@ let isPredicatedFalse = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isNVStore = 1; +let isCVI = 1; let CVINew = 1; let isNewValue = 1; let isNonTemporal = 1; @@ -28498,6 +28972,7 @@ let isPredicatedFalse = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isNVStore = 1; +let isCVI = 1; let CVINew = 1; let isNewValue = 1; let isNonTemporal = 1; @@ -28518,6 +28993,7 @@ let Inst{31-21} = 0b00101001011; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isNVStore = 1; +let isCVI = 1; let CVINew = 1; let isNewValue = 1; let isNonTemporal = 1; @@ -28538,6 +29014,7 @@ let Inst{31-21} = 0b00101011011; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isNVStore = 1; +let isCVI = 1; let CVINew = 1; let isNewValue = 1; let isNonTemporal = 1; @@ -28559,6 +29036,7 @@ let isPredicated = 1; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; let isNVStore = 1; +let isCVI = 1; let CVINew = 1; let isNewValue = 1; let isNonTemporal = 1; @@ -28579,6 +29057,7 @@ let isPredicated = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isNVStore = 1; +let isCVI = 1; let CVINew = 1; let isNewValue = 1; let isNonTemporal = 1; @@ -28599,6 +29078,7 @@ let isPredicated = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; let isNVStore = 1; +let isCVI = 1; let CVINew = 1; let isNewValue = 1; let isNonTemporal = 1; @@ -28619,6 +29099,7 @@ let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; +let isCVI = 1; let isNonTemporal = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_ai"; @@ -28637,6 +29118,7 @@ let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let isNonTemporal = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_pi"; @@ -28655,6 +29137,7 @@ let isPredicated = 1; let isPredicatedFalse = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let isNonTemporal = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_ppu"; @@ -28671,6 +29154,7 @@ let Inst{7-5} = 0b001; let Inst{31-21} = 0b00101000110; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; +let isCVI = 1; let isNonTemporal = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; @@ -28685,6 +29169,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001110; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let isNonTemporal = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; @@ -28699,6 +29184,7 @@ let Inst{10-5} = 0b000001; let Inst{31-21} = 0b00101011110; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let isNonTemporal = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; @@ -28714,6 +29200,7 @@ let Inst{13-11} = 0b000; let Inst{31-21} = 0b00101001011; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let isNonTemporal = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_pi"; @@ -28731,6 +29218,7 @@ let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b00101011011; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let isNonTemporal = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_ppu"; @@ -28749,6 +29237,7 @@ let Inst{31-21} = 0b00101000111; let isPredicated = 1; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; +let isCVI = 1; let isNonTemporal = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_ai"; @@ -28766,6 +29255,7 @@ let Inst{31-21} = 0b00101001111; let isPredicated = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let isNonTemporal = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_pi"; @@ -28783,6 +29273,7 @@ let Inst{31-21} = 0b00101011111; let isPredicated = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let isNonTemporal = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_ppu"; @@ -28799,6 +29290,7 @@ let Inst{7-5} = 0b000; let Inst{31-21} = 0b00101000110; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; +let isCVI = 1; let isNonTemporal = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; @@ -28813,6 +29305,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001110; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let isNonTemporal = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; @@ -28827,6 +29320,7 @@ let Inst{10-5} = 0b000000; let Inst{31-21} = 0b00101011110; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let isNonTemporal = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; @@ -28842,6 +29336,7 @@ let Inst{13-11} = 0b000; let Inst{31-21} = 0b00101001001; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_pi"; let isNVStorable = 1; @@ -28858,7 +29353,9 @@ let Inst{12-5} = 0b00000000; let Inst{31-21} = 0b00101011001; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; +let BaseOpcode = "V6_vS32b_ppu"; let isNVStorable = 1; let isPredicable = 1; let DecoderNamespace = "EXT_mmvec"; @@ -28874,6 +29371,7 @@ let Inst{31-21} = 0b00101000101; let isPredicated = 1; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_ai"; let isNVStorable = 1; @@ -28890,6 +29388,7 @@ let Inst{31-21} = 0b00101001101; let isPredicated = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_pi"; let isNVStorable = 1; @@ -28906,6 +29405,7 @@ let Inst{31-21} = 0b00101011101; let isPredicated = 1; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let BaseOpcode = "V6_vS32b_ppu"; let isNVStorable = 1; @@ -28921,6 +29421,7 @@ let Inst{7-5} = 0b000; let Inst{31-21} = 0b00101000100; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; } @@ -28934,6 +29435,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101001100; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; @@ -28947,6 +29449,7 @@ let Inst{10-5} = 0b000000; let Inst{31-21} = 0b00101011100; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx32 = $Rx32in"; @@ -28961,6 +29464,7 @@ let Inst{12-11} = 0b00; let Inst{31-21} = 0b00101000001; let addrMode = BaseImmOffset; let accessSize = HVXVectorAccess; +let isCVI = 1; let CVINew = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; @@ -28975,6 +29479,7 @@ let Inst{13-11} = 0b000; let Inst{31-21} = 0b00101001001; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let CVINew = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; @@ -28989,6 +29494,7 @@ let Inst{12-0} = 0b0000000101000; let Inst{31-21} = 0b00101011001; let addrMode = PostInc; let accessSize = HVXVectorAccess; +let isCVI = 1; let CVINew = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29004,6 +29510,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vabsb_alt : HInst< @@ -29013,6 +29520,7 @@ def V6_vabsb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29027,6 +29535,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vabsb_sat_alt : HInst< @@ -29036,6 +29545,7 @@ def V6_vabsb_sat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29050,6 +29560,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vabsdiffh_alt : HInst< @@ -29059,6 +29570,7 @@ def V6_vabsdiffh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29073,6 +29585,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vabsdiffub_alt : HInst< @@ -29082,6 +29595,7 @@ def V6_vabsdiffub_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29096,6 +29610,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vabsdiffuh_alt : HInst< @@ -29105,6 +29620,7 @@ def V6_vabsdiffuh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29119,6 +29635,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vabsdiffw_alt : HInst< @@ -29128,6 +29645,7 @@ def V6_vabsdiffw_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29142,6 +29660,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vabsh_alt : HInst< @@ -29151,6 +29670,7 @@ def V6_vabsh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29165,6 +29685,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vabsh_sat_alt : HInst< @@ -29174,6 +29695,7 @@ def V6_vabsh_sat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29185,6 +29707,7 @@ def V6_vabsub_alt : HInst< tc_0ec46cf9, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29196,6 +29719,7 @@ def V6_vabsuh_alt : HInst< tc_0ec46cf9, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29207,6 +29731,7 @@ def V6_vabsuw_alt : HInst< tc_0ec46cf9, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29221,6 +29746,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vabsw_alt : HInst< @@ -29230,6 +29756,7 @@ def V6_vabsw_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29244,6 +29771,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vabsw_sat_alt : HInst< @@ -29253,6 +29781,7 @@ def V6_vabsw_sat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29267,6 +29796,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddb_alt : HInst< @@ -29276,6 +29806,7 @@ def V6_vaddb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29290,6 +29821,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddb_dv_alt : HInst< @@ -29299,6 +29831,7 @@ def V6_vaddb_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29315,6 +29848,7 @@ let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -29326,6 +29860,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29343,6 +29878,7 @@ let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -29354,6 +29890,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29369,6 +29906,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddbsat_alt : HInst< @@ -29378,6 +29916,7 @@ def V6_vaddbsat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29392,6 +29931,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011110101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddbsat_dv_alt : HInst< @@ -29401,6 +29941,7 @@ def V6_vaddbsat_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29415,6 +29956,7 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -29422,7 +29964,7 @@ def V6_vaddcarryo : HInst< (outs HvxVR:$Vd32, HvxQR:$Qe4), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w,$Qe4 = vadd($Vu32.w,$Vv32.w):carry", -tc_e35c1e93, TypeCOPROC_VX>, Enc_c1d806, Requires<[UseHVXV66]> { +tc_e35c1e93, TypeCVI_VA>, Enc_c1d806, Requires<[UseHVXV66]> { let Inst{7-7} = 0b0; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011101101; @@ -29430,6 +29972,7 @@ let hasNewValue = 1; let opNewValue = 0; let hasNewValue2 = 1; let opNewValue2 = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddcarrysat : HInst< @@ -29442,6 +29985,7 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011101100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddclbh : HInst< @@ -29454,6 +29998,7 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011111000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddclbw : HInst< @@ -29466,6 +30011,7 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011111000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddh : HInst< @@ -29478,6 +30024,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddh_alt : HInst< @@ -29487,6 +30034,7 @@ def V6_vaddh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29501,6 +30049,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddh_dv_alt : HInst< @@ -29510,6 +30059,7 @@ def V6_vaddh_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29526,6 +30076,7 @@ let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -29537,6 +30088,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29554,6 +30106,7 @@ let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -29565,6 +30118,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29580,6 +30134,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddhsat_alt : HInst< @@ -29589,6 +30144,7 @@ def V6_vaddhsat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29603,6 +30159,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddhsat_dv_alt : HInst< @@ -29612,6 +30169,7 @@ def V6_vaddhsat_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29626,6 +30184,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddhw_acc : HInst< @@ -29639,6 +30198,7 @@ let Inst{31-21} = 0b00011100001; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -29650,6 +30210,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29662,6 +30223,7 @@ def V6_vaddhw_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29676,6 +30238,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddubh_acc : HInst< @@ -29689,6 +30252,7 @@ let Inst{31-21} = 0b00011100010; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -29700,6 +30264,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29712,6 +30277,7 @@ def V6_vaddubh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29726,6 +30292,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddubsat_alt : HInst< @@ -29735,6 +30302,7 @@ def V6_vaddubsat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29749,6 +30317,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddubsat_dv_alt : HInst< @@ -29758,6 +30327,7 @@ def V6_vaddubsat_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29772,6 +30342,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011110101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vadduhsat : HInst< @@ -29784,6 +30355,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vadduhsat_alt : HInst< @@ -29793,6 +30365,7 @@ def V6_vadduhsat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29807,6 +30380,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vadduhsat_dv_alt : HInst< @@ -29816,6 +30390,7 @@ def V6_vadduhsat_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29830,6 +30405,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vadduhw_acc : HInst< @@ -29843,6 +30419,7 @@ let Inst{31-21} = 0b00011100010; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -29854,6 +30431,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29866,6 +30444,7 @@ def V6_vadduhw_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29880,6 +30459,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vadduwsat_alt : HInst< @@ -29889,6 +30469,7 @@ def V6_vadduwsat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29903,6 +30484,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011110101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vadduwsat_dv_alt : HInst< @@ -29912,6 +30494,7 @@ def V6_vadduwsat_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29926,6 +30509,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddw_alt : HInst< @@ -29935,6 +30519,7 @@ def V6_vaddw_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29949,6 +30534,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddw_dv_alt : HInst< @@ -29958,6 +30544,7 @@ def V6_vaddw_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -29974,6 +30561,7 @@ let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -29985,6 +30573,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30002,6 +30591,7 @@ let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -30013,6 +30603,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30028,6 +30619,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddwsat_alt : HInst< @@ -30037,6 +30629,7 @@ def V6_vaddwsat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30051,6 +30644,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaddwsat_dv_alt : HInst< @@ -30060,6 +30654,7 @@ def V6_vaddwsat_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30074,6 +30669,7 @@ let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_valignbi : HInst< @@ -30085,6 +30681,7 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011110001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vand : HInst< @@ -30097,31 +30694,34 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vandnqrt : HInst< (outs HvxVR:$Vd32), (ins HvxQR:$Qu4, IntRegs:$Rt32), "$Vd32 = vand(!$Qu4,$Rt32)", -tc_ac4046bc, TypeCVI_VX>, Enc_7b7ba8, Requires<[UseHVXV62]> { +tc_ac4046bc, TypeCVI_VX_LATE>, Enc_7b7ba8, Requires<[UseHVXV62]> { let Inst{7-5} = 0b101; let Inst{13-10} = 0b0001; let Inst{31-21} = 0b00011001101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vandnqrt_acc : HInst< (outs HvxVR:$Vx32), (ins HvxVR:$Vx32in, HvxQR:$Qu4, IntRegs:$Rt32), "$Vx32 |= vand(!$Qu4,$Rt32)", -tc_2e8f5f6e, TypeCVI_VX>, Enc_895bd9, Requires<[UseHVXV62]> { +tc_2e8f5f6e, TypeCVI_VX_LATE>, Enc_895bd9, Requires<[UseHVXV62]> { let Inst{7-5} = 0b011; let Inst{13-10} = 0b1001; let Inst{31-21} = 0b00011001011; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -30133,6 +30733,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30145,6 +30746,7 @@ def V6_vandnqrt_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30159,6 +30761,7 @@ let Inst{13-10} = 0b0000; let Inst{31-21} = 0b00011001101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vandqrt_acc : HInst< @@ -30172,6 +30775,7 @@ let Inst{31-21} = 0b00011001011; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -30183,6 +30787,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30195,6 +30800,7 @@ def V6_vandqrt_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30210,6 +30816,7 @@ let Inst{21-16} = 0b000011; let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vandvqv : HInst< @@ -30223,6 +30830,7 @@ let Inst{21-16} = 0b000011; let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vandvrt : HInst< @@ -30235,6 +30843,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vandvrt_acc : HInst< @@ -30246,6 +30855,7 @@ let Inst{7-2} = 0b100000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001011; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -30255,6 +30865,7 @@ def V6_vandvrt_acc_alt : HInst< "$Qx4.ub |= vand($Vu32.ub,$Rt32.ub)", PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30267,6 +30878,7 @@ def V6_vandvrt_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30281,6 +30893,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaslh_acc : HInst< @@ -30294,6 +30907,7 @@ let Inst{31-21} = 0b00011001101; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -30305,6 +30919,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30317,6 +30932,7 @@ def V6_vaslh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30331,6 +30947,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaslhv_alt : HInst< @@ -30340,6 +30957,7 @@ def V6_vaslhv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30354,6 +30972,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaslw_acc : HInst< @@ -30367,6 +30986,7 @@ let Inst{31-21} = 0b00011001011; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -30378,6 +30998,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30390,6 +31011,7 @@ def V6_vaslw_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30404,6 +31026,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vaslwv_alt : HInst< @@ -30413,6 +31036,7 @@ def V6_vaslwv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30427,6 +31051,7 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011010101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -30437,6 +31062,7 @@ def V6_vasr_into_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV66]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30452,6 +31078,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vasrh_acc : HInst< @@ -30465,6 +31092,7 @@ let Inst{31-21} = 0b00011001100; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -30476,6 +31104,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30488,6 +31117,7 @@ def V6_vasrh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30502,18 +31132,9 @@ let Inst{13-13} = 0b1; let Inst{31-24} = 0b00011011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vasrhbrndsat_alt : HInst< -(outs HvxVR:$Vd32), -(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), -"$Vd32 = vasrhb($Vu32,$Vv32,$Rt8):rnd:sat", -tc_16ff9ef8, TypeMAPPING>, Requires<[HasV60]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -} def V6_vasrhbsat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), @@ -30524,6 +31145,7 @@ let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vasrhubrndsat : HInst< @@ -30536,18 +31158,9 @@ let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vasrhubrndsat_alt : HInst< -(outs HvxVR:$Vd32), -(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), -"$Vd32 = vasrhub($Vu32,$Vv32,$Rt8):rnd:sat", -tc_16ff9ef8, TypeMAPPING>, Requires<[HasV60]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -} def V6_vasrhubsat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), @@ -30558,18 +31171,9 @@ let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vasrhubsat_alt : HInst< -(outs HvxVR:$Vd32), -(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), -"$Vd32 = vasrhub($Vu32,$Vv32,$Rt8):sat", -tc_16ff9ef8, TypeMAPPING>, Requires<[HasV60]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -} def V6_vasrhv : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), @@ -30580,6 +31184,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vasrhv_alt : HInst< @@ -30589,6 +31194,7 @@ def V6_vasrhv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30603,6 +31209,7 @@ let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vasruhubsat : HInst< @@ -30615,6 +31222,7 @@ let Inst{13-13} = 0b1; let Inst{31-24} = 0b00011000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vasruwuhrndsat : HInst< @@ -30627,6 +31235,7 @@ let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vasruwuhsat : HInst< @@ -30639,6 +31248,7 @@ let Inst{13-13} = 0b1; let Inst{31-24} = 0b00011000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vasrw : HInst< @@ -30651,6 +31261,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vasrw_acc : HInst< @@ -30664,6 +31275,7 @@ let Inst{31-21} = 0b00011001011; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -30675,6 +31287,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30687,6 +31300,7 @@ def V6_vasrw_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30701,18 +31315,9 @@ let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vasrwh_alt : HInst< -(outs HvxVR:$Vd32), -(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), -"$Vd32 = vasrwh($Vu32,$Vv32,$Rt8)", -tc_16ff9ef8, TypeMAPPING>, Requires<[HasV60]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -} def V6_vasrwhrndsat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), @@ -30723,18 +31328,9 @@ let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vasrwhrndsat_alt : HInst< -(outs HvxVR:$Vd32), -(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), -"$Vd32 = vasrwh($Vu32,$Vv32,$Rt8):rnd:sat", -tc_16ff9ef8, TypeMAPPING>, Requires<[HasV60]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -} def V6_vasrwhsat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), @@ -30745,18 +31341,9 @@ let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vasrwhsat_alt : HInst< -(outs HvxVR:$Vd32), -(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), -"$Vd32 = vasrwh($Vu32,$Vv32,$Rt8):sat", -tc_16ff9ef8, TypeMAPPING>, Requires<[HasV60]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -} def V6_vasrwuhrndsat : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), @@ -30767,6 +31354,7 @@ let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vasrwuhsat : HInst< @@ -30779,18 +31367,9 @@ let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } -def V6_vasrwuhsat_alt : HInst< -(outs HvxVR:$Vd32), -(ins HvxVR:$Vu32, HvxVR:$Vv32, IntRegsLow8:$Rt8), -"$Vd32 = vasrwuh($Vu32,$Vv32,$Rt8):sat", -tc_16ff9ef8, TypeMAPPING>, Requires<[HasV60]> { -let hasNewValue = 1; -let opNewValue = 0; -let isPseudo = 1; -let isCodeGenOnly = 1; -} def V6_vasrwv : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), @@ -30801,6 +31380,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vasrwv_alt : HInst< @@ -30810,6 +31390,7 @@ def V6_vasrwv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30824,6 +31405,7 @@ let Inst{13-13} = 0b1; let Inst{31-16} = 0b0001111000000011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vassignp : HInst< @@ -30833,6 +31415,7 @@ def V6_vassignp : HInst< CVI_VA, TypeCVI_VA_DV>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let DecoderNamespace = "EXT_mmvec"; } @@ -30846,6 +31429,7 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011111000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vavgb_alt : HInst< @@ -30855,6 +31439,7 @@ def V6_vavgb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30869,6 +31454,7 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011111000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vavgbrnd_alt : HInst< @@ -30878,6 +31464,7 @@ def V6_vavgbrnd_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30892,6 +31479,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vavgh_alt : HInst< @@ -30901,6 +31489,7 @@ def V6_vavgh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30915,6 +31504,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100111; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vavghrnd_alt : HInst< @@ -30924,6 +31514,7 @@ def V6_vavghrnd_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30938,6 +31529,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vavgub_alt : HInst< @@ -30947,6 +31539,7 @@ def V6_vavgub_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30961,6 +31554,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100111; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vavgubrnd_alt : HInst< @@ -30970,6 +31564,7 @@ def V6_vavgubrnd_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -30984,6 +31579,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vavguh_alt : HInst< @@ -30993,6 +31589,7 @@ def V6_vavguh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31007,6 +31604,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100111; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vavguhrnd_alt : HInst< @@ -31016,6 +31614,7 @@ def V6_vavguhrnd_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31030,6 +31629,7 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011111000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vavguw_alt : HInst< @@ -31039,6 +31639,7 @@ def V6_vavguw_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31053,6 +31654,7 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011111000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vavguwrnd_alt : HInst< @@ -31062,6 +31664,7 @@ def V6_vavguwrnd_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31076,6 +31679,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vavgw_alt : HInst< @@ -31085,6 +31689,7 @@ def V6_vavgw_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31099,6 +31704,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100111; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vavgwrnd_alt : HInst< @@ -31108,6 +31714,7 @@ def V6_vavgwrnd_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31123,6 +31730,7 @@ let Inst{31-21} = 0b00011010011; let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vcl0h : HInst< @@ -31135,6 +31743,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vcl0h_alt : HInst< @@ -31144,6 +31753,7 @@ def V6_vcl0h_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31158,6 +31768,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vcl0w_alt : HInst< @@ -31167,6 +31778,7 @@ def V6_vcl0w_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31182,6 +31794,7 @@ let Inst{31-16} = 0b0001101000000000; let isPredicated = 1; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vcombine : HInst< @@ -31194,6 +31807,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isRegSequence = 1; let DecoderNamespace = "EXT_mmvec"; } @@ -31204,6 +31818,7 @@ def V6_vd0 : HInst< CVI_VA, TypeCVI_VA>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31215,6 +31830,7 @@ def V6_vdd0 : HInst< tc_718b5c53, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31231,6 +31847,7 @@ let hasNewValue = 1; let opNewValue = 0; let hasNewValue2 = 1; let opNewValue2 = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in"; } @@ -31244,6 +31861,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vdealb4w : HInst< @@ -31256,6 +31874,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vdealb4w_alt : HInst< @@ -31265,6 +31884,7 @@ def V6_vdealb4w_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31276,6 +31896,7 @@ def V6_vdealb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31290,6 +31911,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vdealh_alt : HInst< @@ -31299,6 +31921,7 @@ def V6_vdealh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31313,6 +31936,7 @@ let Inst{13-13} = 0b1; let Inst{31-24} = 0b00011011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vdelta : HInst< @@ -31325,6 +31949,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vdmpybus : HInst< @@ -31337,6 +31962,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vdmpybus_acc : HInst< @@ -31350,6 +31976,7 @@ let Inst{31-21} = 0b00011001000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -31361,6 +31988,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31373,6 +32001,7 @@ def V6_vdmpybus_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31387,6 +32016,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vdmpybus_dv_acc : HInst< @@ -31400,6 +32030,7 @@ let Inst{31-21} = 0b00011001000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -31411,6 +32042,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31423,6 +32055,7 @@ def V6_vdmpybus_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31437,6 +32070,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vdmpyhb_acc : HInst< @@ -31450,6 +32084,7 @@ let Inst{31-21} = 0b00011001000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -31461,6 +32096,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31473,6 +32109,7 @@ def V6_vdmpyhb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31487,6 +32124,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vdmpyhb_dv_acc : HInst< @@ -31500,6 +32138,7 @@ let Inst{31-21} = 0b00011001001; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -31511,6 +32150,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31523,6 +32163,7 @@ def V6_vdmpyhb_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31537,6 +32178,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vdmpyhisat_acc : HInst< @@ -31550,6 +32192,7 @@ let Inst{31-21} = 0b00011001001; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -31561,6 +32204,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31573,6 +32217,7 @@ def V6_vdmpyhisat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31587,6 +32232,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vdmpyhsat_acc : HInst< @@ -31600,6 +32246,7 @@ let Inst{31-21} = 0b00011001001; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -31611,6 +32258,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31623,6 +32271,7 @@ def V6_vdmpyhsat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31637,6 +32286,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vdmpyhsuisat_acc : HInst< @@ -31650,6 +32300,7 @@ let Inst{31-21} = 0b00011001001; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -31661,6 +32312,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31673,6 +32325,7 @@ def V6_vdmpyhsuisat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31687,6 +32340,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vdmpyhsusat_acc : HInst< @@ -31700,6 +32354,7 @@ let Inst{31-21} = 0b00011001001; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -31711,6 +32366,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31723,6 +32379,7 @@ def V6_vdmpyhsusat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31737,6 +32394,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vdmpyhvsat_acc : HInst< @@ -31750,6 +32408,7 @@ let Inst{31-21} = 0b00011100000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -31761,6 +32420,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31773,6 +32433,7 @@ def V6_vdmpyhvsat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31787,6 +32448,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vdsaduh_acc : HInst< @@ -31800,6 +32462,7 @@ let Inst{31-21} = 0b00011001011; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -31811,6 +32474,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31823,6 +32487,7 @@ def V6_vdsaduh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -31837,6 +32502,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_veqb_and : HInst< @@ -31847,6 +32513,7 @@ tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b000000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -31859,6 +32526,7 @@ let Inst{7-2} = 0b010000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -31870,6 +32538,7 @@ tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b100000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -31883,6 +32552,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_veqh_and : HInst< @@ -31893,6 +32563,7 @@ tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b000001; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -31905,6 +32576,7 @@ let Inst{7-2} = 0b010001; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -31916,6 +32588,7 @@ tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b100001; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -31929,6 +32602,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_veqw_and : HInst< @@ -31939,6 +32613,7 @@ tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b000010; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -31951,6 +32626,7 @@ let Inst{7-2} = 0b010010; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -31962,6 +32638,7 @@ tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b100010; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -31976,6 +32653,7 @@ let hasNewValue = 1; let opNewValue = 0; let accessSize = HalfWordAccess; let isCVLoad = 1; +let isCVI = 1; let hasTmpDst = 1; let mayLoad = 1; let Defs = [VTMP]; @@ -31992,6 +32670,7 @@ let hasNewValue = 1; let opNewValue = 0; let accessSize = HalfWordAccess; let isCVLoad = 1; +let isCVI = 1; let hasTmpDst = 1; let mayLoad = 1; let Defs = [VTMP]; @@ -32001,13 +32680,14 @@ def V6_vgathermhw : HInst< (outs), (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32), "vtmp.h = vgather($Rt32,$Mu2,$Vvv32.w).h", -tc_05058f6f, TypeCVI_GATHER>, Enc_28dcbb, Requires<[UseHVXV65]> { +tc_05058f6f, TypeCVI_GATHER_DV>, Enc_28dcbb, Requires<[UseHVXV65]> { let Inst{12-5} = 0b00010000; let Inst{31-21} = 0b00101111000; let hasNewValue = 1; let opNewValue = 0; let accessSize = HalfWordAccess; let isCVLoad = 1; +let isCVI = 1; let hasTmpDst = 1; let mayLoad = 1; let Defs = [VTMP]; @@ -32017,13 +32697,14 @@ def V6_vgathermhwq : HInst< (outs), (ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32), "if ($Qs4) vtmp.h = vgather($Rt32,$Mu2,$Vvv32.w).h", -tc_fd7610da, TypeCVI_GATHER>, Enc_4e4a80, Requires<[UseHVXV65]> { +tc_fd7610da, TypeCVI_GATHER_DV>, Enc_4e4a80, Requires<[UseHVXV65]> { let Inst{12-7} = 0b001100; let Inst{31-21} = 0b00101111000; let hasNewValue = 1; let opNewValue = 0; let accessSize = HalfWordAccess; let isCVLoad = 1; +let isCVI = 1; let hasTmpDst = 1; let mayLoad = 1; let Defs = [VTMP]; @@ -32040,6 +32721,7 @@ let hasNewValue = 1; let opNewValue = 0; let accessSize = WordAccess; let isCVLoad = 1; +let isCVI = 1; let hasTmpDst = 1; let mayLoad = 1; let Defs = [VTMP]; @@ -32056,6 +32738,7 @@ let hasNewValue = 1; let opNewValue = 0; let accessSize = WordAccess; let isCVLoad = 1; +let isCVI = 1; let hasTmpDst = 1; let mayLoad = 1; let Defs = [VTMP]; @@ -32071,6 +32754,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vgtb_and : HInst< @@ -32081,6 +32765,7 @@ tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b000100; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -32093,6 +32778,7 @@ let Inst{7-2} = 0b010100; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -32104,6 +32790,7 @@ tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b100100; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -32117,6 +32804,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vgth_and : HInst< @@ -32127,6 +32815,7 @@ tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b000101; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -32139,6 +32828,7 @@ let Inst{7-2} = 0b010101; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -32150,6 +32840,7 @@ tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b100101; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -32163,6 +32854,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vgtub_and : HInst< @@ -32173,6 +32865,7 @@ tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b001000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -32185,6 +32878,7 @@ let Inst{7-2} = 0b011000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -32196,6 +32890,7 @@ tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b101000; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -32209,6 +32904,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vgtuh_and : HInst< @@ -32219,6 +32915,7 @@ tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b001001; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -32231,6 +32928,7 @@ let Inst{7-2} = 0b011001; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -32242,6 +32940,7 @@ tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b101001; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -32255,6 +32954,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vgtuw_and : HInst< @@ -32265,6 +32965,7 @@ tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b001010; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -32277,6 +32978,7 @@ let Inst{7-2} = 0b011010; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -32288,6 +32990,7 @@ tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b101010; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -32301,6 +33004,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vgtw_and : HInst< @@ -32311,6 +33015,7 @@ tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b000110; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -32323,6 +33028,7 @@ let Inst{7-2} = 0b010110; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -32334,6 +33040,7 @@ tc_257f6f7c, TypeCVI_VA>, Enc_eaa9f8, Requires<[UseHVXV60]> { let Inst{7-2} = 0b100110; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100100; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -32344,6 +33051,7 @@ def V6_vhist : HInst< tc_1381a97c, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV60]> { let Inst{13-0} = 0b10000010000000; let Inst{31-16} = 0b0001111000000000; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vhistq : HInst< @@ -32354,6 +33062,7 @@ tc_e3f68a46, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV60]> { let Inst{13-0} = 0b10000010000000; let Inst{21-16} = 0b000010; let Inst{31-24} = 0b00011110; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vinsertwr : HInst< @@ -32365,6 +33074,7 @@ let Inst{13-5} = 0b100000001; let Inst{31-21} = 0b00011001101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -32378,6 +33088,7 @@ let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vlalignbi : HInst< @@ -32389,6 +33100,7 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011110011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vlsrb : HInst< @@ -32401,6 +33113,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vlsrh : HInst< @@ -32413,6 +33126,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vlsrh_alt : HInst< @@ -32422,6 +33136,7 @@ def V6_vlsrh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -32436,6 +33151,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vlsrhv_alt : HInst< @@ -32445,6 +33161,7 @@ def V6_vlsrhv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -32459,6 +33176,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vlsrw_alt : HInst< @@ -32468,6 +33186,7 @@ def V6_vlsrw_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -32482,6 +33201,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vlsrwv_alt : HInst< @@ -32491,6 +33211,7 @@ def V6_vlsrwv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -32505,6 +33226,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vlutvvb : HInst< @@ -32517,6 +33239,7 @@ let Inst{13-13} = 0b1; let Inst{31-24} = 0b00011011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vlutvvb_nm : HInst< @@ -32529,6 +33252,7 @@ let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vlutvvb_oracc : HInst< @@ -32542,6 +33266,7 @@ let Inst{31-24} = 0b00011011; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -32555,6 +33280,7 @@ let Inst{31-21} = 0b00011100110; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -32567,6 +33293,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011110001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vlutvwh : HInst< @@ -32579,6 +33306,7 @@ let Inst{13-13} = 0b1; let Inst{31-24} = 0b00011011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vlutvwh_nm : HInst< @@ -32591,6 +33319,7 @@ let Inst{13-13} = 0b0; let Inst{31-24} = 0b00011000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vlutvwh_oracc : HInst< @@ -32604,6 +33333,7 @@ let Inst{31-24} = 0b00011011; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -32617,6 +33347,7 @@ let Inst{31-21} = 0b00011100111; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -32629,6 +33360,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011110011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmaxb : HInst< @@ -32641,6 +33373,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmaxb_alt : HInst< @@ -32650,6 +33383,7 @@ def V6_vmaxb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -32664,6 +33398,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmaxh_alt : HInst< @@ -32673,6 +33408,7 @@ def V6_vmaxh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -32687,6 +33423,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmaxub_alt : HInst< @@ -32696,6 +33433,7 @@ def V6_vmaxub_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -32710,6 +33448,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmaxuh_alt : HInst< @@ -32719,6 +33458,7 @@ def V6_vmaxuh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -32733,6 +33473,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmaxw_alt : HInst< @@ -32742,6 +33483,7 @@ def V6_vmaxw_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -32756,6 +33498,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vminb_alt : HInst< @@ -32765,6 +33508,7 @@ def V6_vminb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -32779,6 +33523,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vminh_alt : HInst< @@ -32788,6 +33533,7 @@ def V6_vminh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -32802,6 +33548,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vminub_alt : HInst< @@ -32811,6 +33558,7 @@ def V6_vminub_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -32825,6 +33573,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vminuh_alt : HInst< @@ -32834,6 +33583,7 @@ def V6_vminuh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -32848,6 +33598,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vminw_alt : HInst< @@ -32857,6 +33608,7 @@ def V6_vminw_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -32871,6 +33623,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpabus_acc : HInst< @@ -32884,6 +33637,7 @@ let Inst{31-21} = 0b00011001001; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -32895,6 +33649,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -32907,6 +33662,7 @@ def V6_vmpabus_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -32921,6 +33677,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpabusv_alt : HInst< @@ -32930,6 +33687,7 @@ def V6_vmpabusv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -32944,6 +33702,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpabuu_acc : HInst< @@ -32957,6 +33716,7 @@ let Inst{31-21} = 0b00011001101; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -32968,6 +33728,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -32980,6 +33741,7 @@ def V6_vmpabuu_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -32994,6 +33756,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100111; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpabuuv_alt : HInst< @@ -33003,6 +33766,7 @@ def V6_vmpabuuv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33017,6 +33781,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpahb_acc : HInst< @@ -33030,6 +33795,7 @@ let Inst{31-21} = 0b00011001001; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -33041,6 +33807,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33053,6 +33820,7 @@ def V6_vmpahb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33067,6 +33835,7 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -33080,6 +33849,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpauhb_acc : HInst< @@ -33093,6 +33863,7 @@ let Inst{31-21} = 0b00011001100; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -33104,6 +33875,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33116,6 +33888,7 @@ def V6_vmpauhb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33130,6 +33903,7 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -33143,6 +33917,7 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011001100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -33156,6 +33931,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpybus_acc : HInst< @@ -33169,6 +33945,7 @@ let Inst{31-21} = 0b00011001001; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -33180,6 +33957,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33192,6 +33970,7 @@ def V6_vmpybus_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33206,6 +33985,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpybusv_acc : HInst< @@ -33219,6 +33999,7 @@ let Inst{31-21} = 0b00011100000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -33230,6 +34011,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33242,6 +34024,7 @@ def V6_vmpybusv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33256,6 +34039,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpybv_acc : HInst< @@ -33269,6 +34053,7 @@ let Inst{31-21} = 0b00011100000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -33280,6 +34065,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33292,6 +34078,7 @@ def V6_vmpybv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33306,6 +34093,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111111; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyewuh_64 : HInst< @@ -33318,6 +34106,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011110101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyewuh_alt : HInst< @@ -33327,6 +34116,7 @@ def V6_vmpyewuh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33341,6 +34131,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyh_acc : HInst< @@ -33354,6 +34145,7 @@ let Inst{31-21} = 0b00011001101; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -33365,6 +34157,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33377,6 +34170,7 @@ def V6_vmpyh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33392,6 +34186,7 @@ let Inst{31-21} = 0b00011001010; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -33403,6 +34198,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33418,6 +34214,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyhsrs_alt : HInst< @@ -33427,6 +34224,7 @@ def V6_vmpyhsrs_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33441,6 +34239,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyhss_alt : HInst< @@ -33450,6 +34249,7 @@ def V6_vmpyhss_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33464,6 +34264,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyhus_acc : HInst< @@ -33477,6 +34278,7 @@ let Inst{31-21} = 0b00011100001; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -33488,6 +34290,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33500,6 +34303,7 @@ def V6_vmpyhus_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33514,6 +34318,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyhv_acc : HInst< @@ -33527,6 +34332,7 @@ let Inst{31-21} = 0b00011100000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -33538,6 +34344,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33550,6 +34357,7 @@ def V6_vmpyhv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33564,6 +34372,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyhvsrs_alt : HInst< @@ -33573,6 +34382,7 @@ def V6_vmpyhvsrs_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33587,6 +34397,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyiewh_acc : HInst< @@ -33600,6 +34411,7 @@ let Inst{31-21} = 0b00011100010; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -33611,6 +34423,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33626,6 +34439,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyiewuh_acc : HInst< @@ -33639,6 +34453,7 @@ let Inst{31-21} = 0b00011100001; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -33650,6 +34465,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33662,6 +34478,7 @@ def V6_vmpyiewuh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33676,6 +34493,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyih_acc : HInst< @@ -33689,6 +34507,7 @@ let Inst{31-21} = 0b00011100001; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -33700,6 +34519,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33712,6 +34532,7 @@ def V6_vmpyih_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33726,6 +34547,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyihb_acc : HInst< @@ -33739,6 +34561,7 @@ let Inst{31-21} = 0b00011001011; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -33750,6 +34573,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33762,6 +34586,7 @@ def V6_vmpyihb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33776,6 +34601,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyiowh_alt : HInst< @@ -33785,6 +34611,7 @@ def V6_vmpyiowh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33799,6 +34626,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyiwb_acc : HInst< @@ -33812,6 +34640,7 @@ let Inst{31-21} = 0b00011001010; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -33823,6 +34652,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33835,6 +34665,7 @@ def V6_vmpyiwb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33849,6 +34680,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyiwh_acc : HInst< @@ -33862,6 +34694,7 @@ let Inst{31-21} = 0b00011001010; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -33873,6 +34706,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33885,6 +34719,7 @@ def V6_vmpyiwh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33899,6 +34734,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyiwub_acc : HInst< @@ -33912,6 +34748,7 @@ let Inst{31-21} = 0b00011001100; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -33923,6 +34760,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33935,6 +34773,7 @@ def V6_vmpyiwub_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33949,6 +34788,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111111; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyowh_64_acc : HInst< @@ -33962,6 +34802,7 @@ let Inst{31-21} = 0b00011100001; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -33972,6 +34813,7 @@ def V6_vmpyowh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -33986,6 +34828,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyowh_rnd_alt : HInst< @@ -33995,6 +34838,7 @@ def V6_vmpyowh_rnd_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34010,6 +34854,7 @@ let Inst{31-21} = 0b00011100001; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -34021,6 +34866,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; @@ -34036,6 +34882,7 @@ let Inst{31-21} = 0b00011100001; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -34047,6 +34894,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; @@ -34061,6 +34909,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyub_acc : HInst< @@ -34074,6 +34923,7 @@ let Inst{31-21} = 0b00011001100; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -34085,6 +34935,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34097,6 +34948,7 @@ def V6_vmpyub_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34111,6 +34963,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyubv_acc : HInst< @@ -34124,6 +34977,7 @@ let Inst{31-21} = 0b00011100000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -34135,6 +34989,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34147,6 +35002,7 @@ def V6_vmpyubv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34161,6 +35017,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyuh_acc : HInst< @@ -34174,6 +35031,7 @@ let Inst{31-21} = 0b00011001010; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -34185,6 +35043,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34197,6 +35056,7 @@ def V6_vmpyuh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34211,6 +35071,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyuhe_acc : HInst< @@ -34224,6 +35085,7 @@ let Inst{31-21} = 0b00011001100; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -34237,6 +35099,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vmpyuhv_acc : HInst< @@ -34250,6 +35113,7 @@ let Inst{31-21} = 0b00011100001; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -34261,6 +35125,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34273,6 +35138,7 @@ def V6_vmpyuhv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34287,6 +35153,7 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011110111; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vnavgb : HInst< @@ -34299,6 +35166,7 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011111000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vnavgb_alt : HInst< @@ -34308,6 +35176,7 @@ def V6_vnavgb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34322,6 +35191,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100111; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vnavgh_alt : HInst< @@ -34331,6 +35201,7 @@ def V6_vnavgh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34345,6 +35216,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100111; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vnavgub_alt : HInst< @@ -34354,6 +35226,7 @@ def V6_vnavgub_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34368,6 +35241,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100111; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vnavgw_alt : HInst< @@ -34377,6 +35251,7 @@ def V6_vnavgw_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34393,6 +35268,7 @@ let isPredicated = 1; let isPredicatedFalse = 1; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vncmov : HInst< @@ -34407,6 +35283,7 @@ let isPredicated = 1; let isPredicatedFalse = 1; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vnormamth : HInst< @@ -34419,6 +35296,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vnormamth_alt : HInst< @@ -34428,6 +35306,7 @@ def V6_vnormamth_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34442,6 +35321,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vnormamtw_alt : HInst< @@ -34451,6 +35331,7 @@ def V6_vnormamtw_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34465,6 +35346,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vor : HInst< @@ -34477,6 +35359,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vpackeb : HInst< @@ -34489,6 +35372,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vpackeb_alt : HInst< @@ -34498,6 +35382,7 @@ def V6_vpackeb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34512,6 +35397,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vpackeh_alt : HInst< @@ -34521,6 +35407,7 @@ def V6_vpackeh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34535,6 +35422,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vpackhb_sat_alt : HInst< @@ -34544,6 +35432,7 @@ def V6_vpackhb_sat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34558,6 +35447,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vpackhub_sat_alt : HInst< @@ -34567,6 +35457,7 @@ def V6_vpackhub_sat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34581,6 +35472,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111111; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vpackob_alt : HInst< @@ -34590,6 +35482,7 @@ def V6_vpackob_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34604,6 +35497,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111111; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vpackoh_alt : HInst< @@ -34613,6 +35507,7 @@ def V6_vpackoh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34627,6 +35522,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111111; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vpackwh_sat_alt : HInst< @@ -34636,6 +35532,7 @@ def V6_vpackwh_sat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34650,6 +35547,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vpackwuh_sat_alt : HInst< @@ -34659,6 +35557,7 @@ def V6_vpackwuh_sat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34673,6 +35572,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vpopcounth_alt : HInst< @@ -34682,6 +35582,7 @@ def V6_vpopcounth_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34696,6 +35597,7 @@ let Inst{21-16} = 0b000011; let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vprefixqh : HInst< @@ -34708,6 +35610,7 @@ let Inst{21-16} = 0b000011; let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vprefixqw : HInst< @@ -34720,6 +35623,7 @@ let Inst{21-16} = 0b000011; let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrdelta : HInst< @@ -34732,6 +35636,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrmpybub_rtt : HInst< @@ -34744,6 +35649,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrmpybub_rtt_acc : HInst< @@ -34757,6 +35663,7 @@ let Inst{31-21} = 0b00011001101; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -34768,6 +35675,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34780,6 +35688,7 @@ def V6_vrmpybub_rtt_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34794,6 +35703,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrmpybus_acc : HInst< @@ -34807,6 +35717,7 @@ let Inst{31-21} = 0b00011001000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -34818,6 +35729,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34830,6 +35742,7 @@ def V6_vrmpybus_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34844,6 +35757,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrmpybusi_acc : HInst< @@ -34857,6 +35771,7 @@ let Inst{31-21} = 0b00011001010; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -34868,6 +35783,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34880,6 +35796,7 @@ def V6_vrmpybusi_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34894,6 +35811,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrmpybusv_acc : HInst< @@ -34907,6 +35825,7 @@ let Inst{31-21} = 0b00011100000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -34918,6 +35837,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34930,6 +35850,7 @@ def V6_vrmpybusv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34944,6 +35865,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrmpybv_acc : HInst< @@ -34957,6 +35879,7 @@ let Inst{31-21} = 0b00011100000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -34968,6 +35891,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34980,6 +35904,7 @@ def V6_vrmpybv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -34994,6 +35919,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrmpyub_acc : HInst< @@ -35007,6 +35933,7 @@ let Inst{31-21} = 0b00011001000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -35018,6 +35945,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35030,6 +35958,7 @@ def V6_vrmpyub_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35044,6 +35973,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrmpyub_rtt_acc : HInst< @@ -35057,6 +35987,7 @@ let Inst{31-21} = 0b00011001101; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -35068,6 +35999,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35080,6 +36012,7 @@ def V6_vrmpyub_rtt_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35094,6 +36027,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrmpyubi_acc : HInst< @@ -35107,6 +36041,7 @@ let Inst{31-21} = 0b00011001011; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -35118,6 +36053,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35130,6 +36066,7 @@ def V6_vrmpyubi_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35144,6 +36081,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrmpyubv_acc : HInst< @@ -35157,6 +36095,7 @@ let Inst{31-21} = 0b00011100000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -35168,6 +36107,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35180,6 +36120,7 @@ def V6_vrmpyubv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35194,6 +36135,7 @@ let Inst{13-13} = 0b0; let Inst{31-19} = 0b0001100111101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrmpyzbb_rt_acc : HInst< @@ -35207,6 +36149,7 @@ let Inst{31-19} = 0b0001100111000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vyyyy32 = $Vyyyy32in"; } @@ -35220,6 +36163,7 @@ let Inst{13-13} = 0b0; let Inst{31-19} = 0b0001100111100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx8 = $Rx8in"; } @@ -35234,6 +36178,7 @@ let Inst{31-19} = 0b0001100111001; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in"; } @@ -35247,6 +36192,7 @@ let Inst{13-13} = 0b0; let Inst{31-19} = 0b0001100111111; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrmpyzbub_rt_acc : HInst< @@ -35260,6 +36206,7 @@ let Inst{31-19} = 0b0001100111010; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vyyyy32 = $Vyyyy32in"; } @@ -35273,6 +36220,7 @@ let Inst{13-13} = 0b0; let Inst{31-19} = 0b0001100111110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx8 = $Rx8in"; } @@ -35287,6 +36235,7 @@ let Inst{31-19} = 0b0001100111011; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in"; } @@ -35300,6 +36249,7 @@ let Inst{13-13} = 0b0; let Inst{31-19} = 0b0001100111101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrmpyzcb_rt_acc : HInst< @@ -35313,6 +36263,7 @@ let Inst{31-19} = 0b0001100111000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vyyyy32 = $Vyyyy32in"; } @@ -35326,6 +36277,7 @@ let Inst{13-13} = 0b0; let Inst{31-19} = 0b0001100111100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx8 = $Rx8in"; } @@ -35340,6 +36292,7 @@ let Inst{31-19} = 0b0001100111001; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in"; } @@ -35353,6 +36306,7 @@ let Inst{13-13} = 0b0; let Inst{31-19} = 0b0001100111101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrmpyzcbs_rt_acc : HInst< @@ -35366,6 +36320,7 @@ let Inst{31-19} = 0b0001100111000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vyyyy32 = $Vyyyy32in"; } @@ -35379,6 +36334,7 @@ let Inst{13-13} = 0b0; let Inst{31-19} = 0b0001100111100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx8 = $Rx8in"; } @@ -35393,6 +36349,7 @@ let Inst{31-19} = 0b0001100111001; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in"; } @@ -35406,6 +36363,7 @@ let Inst{13-13} = 0b0; let Inst{31-19} = 0b0001100111111; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrmpyznb_rt_acc : HInst< @@ -35419,6 +36377,7 @@ let Inst{31-19} = 0b0001100111010; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vyyyy32 = $Vyyyy32in"; } @@ -35432,6 +36391,7 @@ let Inst{13-13} = 0b0; let Inst{31-19} = 0b0001100111110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Rx8 = $Rx8in"; } @@ -35446,6 +36406,7 @@ let Inst{31-19} = 0b0001100111011; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vyyyy32 = $Vyyyy32in, $Rx8 = $Rx8in"; } @@ -35459,6 +36420,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrotr : HInst< @@ -35471,6 +36433,7 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011010100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrotr_alt : HInst< @@ -35480,6 +36443,7 @@ def V6_vrotr_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV66]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35494,6 +36458,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vroundhb_alt : HInst< @@ -35503,6 +36468,7 @@ def V6_vroundhb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35517,6 +36483,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vroundhub_alt : HInst< @@ -35526,6 +36493,7 @@ def V6_vroundhub_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35540,6 +36508,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111111; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrounduhub_alt : HInst< @@ -35549,6 +36518,7 @@ def V6_vrounduhub_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35563,6 +36533,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111111; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrounduwuh_alt : HInst< @@ -35572,6 +36543,7 @@ def V6_vrounduwuh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35586,6 +36558,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vroundwh_alt : HInst< @@ -35595,6 +36568,7 @@ def V6_vroundwh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35609,6 +36583,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vroundwuh_alt : HInst< @@ -35618,6 +36593,7 @@ def V6_vroundwuh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35632,6 +36608,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vrsadubi_acc : HInst< @@ -35645,6 +36622,7 @@ let Inst{31-21} = 0b00011001010; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -35656,6 +36634,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35668,6 +36647,7 @@ def V6_vrsadubi_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35682,18 +36662,20 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011101100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsathub : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.ub = vsat($Vu32.h,$Vv32.h)", -tc_8772086c, TypeCVI_VINLANESAT>, Enc_45364e, Requires<[UseHVXV60]> { +tc_8772086c, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b010; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsathub_alt : HInst< @@ -35703,6 +36685,7 @@ def V6_vsathub_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35717,6 +36700,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsatuwuh_alt : HInst< @@ -35726,6 +36710,7 @@ def V6_vsatuwuh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35734,12 +36719,13 @@ def V6_vsatwh : HInst< (outs HvxVR:$Vd32), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.h = vsat($Vu32.w,$Vv32.w)", -tc_8772086c, TypeCVI_VINLANESAT>, Enc_45364e, Requires<[UseHVXV60]> { +tc_8772086c, TypeCVI_VA>, Enc_45364e, Requires<[UseHVXV60]> { let Inst{7-5} = 0b011; let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsatwh_alt : HInst< @@ -35749,6 +36735,7 @@ def V6_vsatwh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35763,6 +36750,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsb_alt : HInst< @@ -35772,6 +36760,7 @@ def V6_vsb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35784,6 +36773,7 @@ tc_9f363d21, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> { let Inst{7-5} = 0b001; let Inst{31-21} = 0b00101111001; let accessSize = HalfWordAccess; +let isCVI = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; } @@ -35796,6 +36786,7 @@ let Inst{7-5} = 0b101; let Inst{31-21} = 0b00101111001; let accessSize = HalfWordAccess; let isAccumulator = 1; +let isCVI = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; } @@ -35805,6 +36796,7 @@ def V6_vscattermh_add_alt : HInst< "vscatter($Rt32,$Mu2,$Vv32.h) += $Vw32.h", PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35814,6 +36806,7 @@ def V6_vscattermh_alt : HInst< (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32), "vscatter($Rt32,$Mu2,$Vv32.h) = $Vw32.h", PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35826,6 +36819,7 @@ tc_8e420e4d, TypeCVI_SCATTER>, Enc_9be1de, Requires<[UseHVXV65]> { let Inst{7-7} = 0b1; let Inst{31-21} = 0b00101111100; let accessSize = HalfWordAccess; +let isCVI = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; } @@ -35834,6 +36828,7 @@ def V6_vscattermhq_alt : HInst< (ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32), "if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.h) = $Vw32.h", PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35846,6 +36841,7 @@ tc_7273323b, TypeCVI_SCATTER_DV>, Enc_a641d0, Requires<[UseHVXV65]> { let Inst{7-5} = 0b010; let Inst{31-21} = 0b00101111001; let accessSize = HalfWordAccess; +let isCVI = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; } @@ -35858,6 +36854,7 @@ let Inst{7-5} = 0b110; let Inst{31-21} = 0b00101111001; let accessSize = HalfWordAccess; let isAccumulator = 1; +let isCVI = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; } @@ -35869,6 +36866,7 @@ tc_58d21193, TypeCVI_SCATTER_DV>, Enc_3d6d37, Requires<[UseHVXV65]> { let Inst{7-7} = 0b0; let Inst{31-21} = 0b00101111101; let accessSize = HalfWordAccess; +let isCVI = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; } @@ -35880,6 +36878,7 @@ tc_9f363d21, TypeCVI_SCATTER>, Enc_16c48b, Requires<[UseHVXV65]> { let Inst{7-5} = 0b000; let Inst{31-21} = 0b00101111001; let accessSize = WordAccess; +let isCVI = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; } @@ -35892,6 +36891,7 @@ let Inst{7-5} = 0b100; let Inst{31-21} = 0b00101111001; let accessSize = WordAccess; let isAccumulator = 1; +let isCVI = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; } @@ -35901,6 +36901,7 @@ def V6_vscattermw_add_alt : HInst< "vscatter($Rt32,$Mu2,$Vv32.w) += $Vw32.w", PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35910,6 +36911,7 @@ def V6_vscattermw_alt : HInst< (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32), "vscatter($Rt32,$Mu2,$Vv32.w) = $Vw32.w", PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35920,6 +36922,7 @@ def V6_vscattermwh_add_alt : HInst< "vscatter($Rt32,$Mu2,$Vvv32.w) += $Vw32.h", PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35929,6 +36932,7 @@ def V6_vscattermwh_alt : HInst< (ins IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32), "vscatter($Rt32,$Mu2,$Vvv32.w) = $Vw32.h", PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35938,6 +36942,7 @@ def V6_vscattermwhq_alt : HInst< (ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxWR:$Vvv32, HvxVR:$Vw32), "if ($Qs4) vscatter($Rt32,$Mu2,$Vvv32.w) = $Vw32.h", PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35950,6 +36955,7 @@ tc_8e420e4d, TypeCVI_SCATTER>, Enc_9be1de, Requires<[UseHVXV65]> { let Inst{7-7} = 0b0; let Inst{31-21} = 0b00101111100; let accessSize = WordAccess; +let isCVI = 1; let mayStore = 1; let DecoderNamespace = "EXT_mmvec"; } @@ -35958,6 +36964,7 @@ def V6_vscattermwq_alt : HInst< (ins HvxQR:$Qs4, IntRegs:$Rt32, ModRegs:$Mu2, HvxVR:$Vv32, HvxVR:$Vw32), "if ($Qs4) vscatter($Rt32,$Mu2,$Vv32.w) = $Vw32.w", PSEUDO, TypeMAPPING>, Requires<[UseHVXV65]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35972,6 +36979,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsh_alt : HInst< @@ -35981,6 +36989,7 @@ def V6_vsh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -35995,6 +37004,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vshufeh_alt : HInst< @@ -36004,6 +37014,7 @@ def V6_vshufeh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36020,6 +37031,7 @@ let hasNewValue = 1; let opNewValue = 0; let hasNewValue2 = 1; let opNewValue2 = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in"; } @@ -36033,6 +37045,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vshuffb_alt : HInst< @@ -36042,6 +37055,7 @@ def V6_vshuffb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36056,6 +37070,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vshuffeb_alt : HInst< @@ -36065,6 +37080,7 @@ def V6_vshuffeb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36079,6 +37095,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vshuffh_alt : HInst< @@ -36088,6 +37105,7 @@ def V6_vshuffh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36102,6 +37120,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vshuffob_alt : HInst< @@ -36111,6 +37130,7 @@ def V6_vshuffob_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36125,6 +37145,7 @@ let Inst{13-13} = 0b1; let Inst{31-24} = 0b00011011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vshufoeb : HInst< @@ -36137,6 +37158,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vshufoeb_alt : HInst< @@ -36146,6 +37168,7 @@ def V6_vshufoeb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36160,6 +37183,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vshufoeh_alt : HInst< @@ -36169,6 +37193,7 @@ def V6_vshufoeh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36183,6 +37208,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vshufoh_alt : HInst< @@ -36192,6 +37218,7 @@ def V6_vshufoh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36206,6 +37233,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubb_alt : HInst< @@ -36215,6 +37243,7 @@ def V6_vsubb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36229,6 +37258,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubb_dv_alt : HInst< @@ -36238,6 +37268,7 @@ def V6_vsubb_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36253,6 +37284,7 @@ let Inst{21-16} = 0b000010; let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -36263,6 +37295,7 @@ def V6_vsubbnq_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36279,6 +37312,7 @@ let Inst{21-16} = 0b000001; let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -36289,6 +37323,7 @@ def V6_vsubbq_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36304,6 +37339,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubbsat_alt : HInst< @@ -36313,6 +37349,7 @@ def V6_vsubbsat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36327,6 +37364,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011110101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubbsat_dv_alt : HInst< @@ -36336,6 +37374,7 @@ def V6_vsubbsat_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36350,6 +37389,7 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011100101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Qx4 = $Qx4in"; } @@ -36357,7 +37397,7 @@ def V6_vsubcarryo : HInst< (outs HvxVR:$Vd32, HvxQR:$Qe4), (ins HvxVR:$Vu32, HvxVR:$Vv32), "$Vd32.w,$Qe4 = vsub($Vu32.w,$Vv32.w):carry", -tc_e35c1e93, TypeCOPROC_VX>, Enc_c1d806, Requires<[UseHVXV66]> { +tc_e35c1e93, TypeCVI_VA>, Enc_c1d806, Requires<[UseHVXV66]> { let Inst{7-7} = 0b1; let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011101101; @@ -36365,6 +37405,7 @@ let hasNewValue = 1; let opNewValue = 0; let hasNewValue2 = 1; let opNewValue2 = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubh : HInst< @@ -36377,6 +37418,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubh_alt : HInst< @@ -36386,6 +37428,7 @@ def V6_vsubh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36400,6 +37443,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubh_dv_alt : HInst< @@ -36409,6 +37453,7 @@ def V6_vsubh_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36424,6 +37469,7 @@ let Inst{21-16} = 0b000010; let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -36434,6 +37480,7 @@ def V6_vsubhnq_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36450,6 +37497,7 @@ let Inst{21-16} = 0b000001; let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -36460,6 +37508,7 @@ def V6_vsubhq_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36475,6 +37524,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubhsat_alt : HInst< @@ -36484,6 +37534,7 @@ def V6_vsubhsat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36498,6 +37549,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubhsat_dv_alt : HInst< @@ -36507,6 +37559,7 @@ def V6_vsubhsat_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36521,6 +37574,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubhw_alt : HInst< @@ -36530,6 +37584,7 @@ def V6_vsubhw_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36544,6 +37599,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsububh_alt : HInst< @@ -36553,6 +37609,7 @@ def V6_vsububh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36567,6 +37624,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsububsat_alt : HInst< @@ -36576,6 +37634,7 @@ def V6_vsububsat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36590,6 +37649,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsububsat_dv_alt : HInst< @@ -36599,6 +37659,7 @@ def V6_vsububsat_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36613,6 +37674,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011110101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubuhsat : HInst< @@ -36625,6 +37687,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubuhsat_alt : HInst< @@ -36634,6 +37697,7 @@ def V6_vsubuhsat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36648,6 +37712,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubuhsat_dv_alt : HInst< @@ -36657,6 +37722,7 @@ def V6_vsubuhsat_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36671,6 +37737,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubuhw_alt : HInst< @@ -36680,6 +37747,7 @@ def V6_vsubuhw_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36694,6 +37762,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011111110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubuwsat_alt : HInst< @@ -36703,6 +37772,7 @@ def V6_vsubuwsat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36717,6 +37787,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011110101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubuwsat_dv_alt : HInst< @@ -36726,6 +37797,7 @@ def V6_vsubuwsat_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV62]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36740,6 +37812,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubw_alt : HInst< @@ -36749,6 +37822,7 @@ def V6_vsubw_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36763,6 +37837,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100100; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubw_dv_alt : HInst< @@ -36772,6 +37847,7 @@ def V6_vsubw_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36787,6 +37863,7 @@ let Inst{21-16} = 0b000010; let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -36797,6 +37874,7 @@ def V6_vsubwnq_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36813,6 +37891,7 @@ let Inst{21-16} = 0b000010; let Inst{31-24} = 0b00011110; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vx32 = $Vx32in"; } @@ -36823,6 +37902,7 @@ def V6_vsubwq_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36838,6 +37918,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100011; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubwsat_alt : HInst< @@ -36847,6 +37928,7 @@ def V6_vsubwsat_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36861,6 +37943,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vsubwsat_dv_alt : HInst< @@ -36870,6 +37953,7 @@ def V6_vsubwsat_dv_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36884,6 +37968,7 @@ let Inst{13-13} = 0b1; let Inst{31-21} = 0b00011110101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vtmpyb : HInst< @@ -36896,6 +37981,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vtmpyb_acc : HInst< @@ -36909,6 +37995,7 @@ let Inst{31-21} = 0b00011001000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -36920,6 +38007,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36932,6 +38020,7 @@ def V6_vtmpyb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36946,6 +38035,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001000; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vtmpybus_acc : HInst< @@ -36959,6 +38049,7 @@ let Inst{31-21} = 0b00011001000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -36970,6 +38061,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36982,6 +38074,7 @@ def V6_vtmpybus_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -36996,6 +38089,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011001101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vtmpyhb_acc : HInst< @@ -37009,6 +38103,7 @@ let Inst{31-21} = 0b00011001000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -37020,6 +38115,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -37032,6 +38128,7 @@ def V6_vtmpyhb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -37045,6 +38142,7 @@ let hasNewValue = 1; let opNewValue = 0; let hasNewValue2 = 1; let opNewValue2 = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -37060,6 +38158,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vunpackb_alt : HInst< @@ -37069,6 +38168,7 @@ def V6_vunpackb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -37083,6 +38183,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vunpackh_alt : HInst< @@ -37092,6 +38193,7 @@ def V6_vunpackh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -37107,6 +38209,7 @@ let Inst{31-16} = 0b0001111000000000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -37118,6 +38221,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; @@ -37133,6 +38237,7 @@ let Inst{31-16} = 0b0001111000000000; let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; let Constraints = "$Vxx32 = $Vxx32in"; } @@ -37144,6 +38249,7 @@ PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; let isAccumulator = 1; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -37159,6 +38265,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vunpackub_alt : HInst< @@ -37168,6 +38275,7 @@ def V6_vunpackub_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -37182,6 +38290,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vunpackuh_alt : HInst< @@ -37191,6 +38300,7 @@ def V6_vunpackuh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -37202,6 +38312,7 @@ def V6_vwhist128 : HInst< tc_1381a97c, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV62]> { let Inst{13-0} = 0b10010010000000; let Inst{31-16} = 0b0001111000000000; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vwhist128m : HInst< @@ -37212,6 +38323,7 @@ tc_b28e51aa, TypeCVI_HIST>, Enc_efaed8, Requires<[UseHVXV62]> { let Inst{7-0} = 0b10000000; let Inst{13-9} = 0b10011; let Inst{31-16} = 0b0001111000000000; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vwhist128q : HInst< @@ -37222,6 +38334,7 @@ tc_e3f68a46, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV62]> { let Inst{13-0} = 0b10010010000000; let Inst{21-16} = 0b000010; let Inst{31-24} = 0b00011110; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vwhist128qm : HInst< @@ -37233,6 +38346,7 @@ let Inst{7-0} = 0b10000000; let Inst{13-9} = 0b10011; let Inst{21-16} = 0b000010; let Inst{31-24} = 0b00011110; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vwhist256 : HInst< @@ -37242,6 +38356,7 @@ def V6_vwhist256 : HInst< tc_1381a97c, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV62]> { let Inst{13-0} = 0b10001010000000; let Inst{31-16} = 0b0001111000000000; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vwhist256_sat : HInst< @@ -37251,6 +38366,7 @@ def V6_vwhist256_sat : HInst< tc_1381a97c, TypeCVI_HIST>, Enc_e3b0c4, Requires<[UseHVXV62]> { let Inst{13-0} = 0b10001110000000; let Inst{31-16} = 0b0001111000000000; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vwhist256q : HInst< @@ -37261,6 +38377,7 @@ tc_e3f68a46, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV62]> { let Inst{13-0} = 0b10001010000000; let Inst{21-16} = 0b000010; let Inst{31-24} = 0b00011110; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vwhist256q_sat : HInst< @@ -37271,6 +38388,7 @@ tc_e3f68a46, TypeCVI_HIST>, Enc_217147, Requires<[UseHVXV62]> { let Inst{13-0} = 0b10001110000000; let Inst{21-16} = 0b000010; let Inst{31-24} = 0b00011110; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vxor : HInst< @@ -37283,6 +38401,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00011100001; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vzb : HInst< @@ -37295,6 +38414,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vzb_alt : HInst< @@ -37304,6 +38424,7 @@ def V6_vzb_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -37318,6 +38439,7 @@ let Inst{13-13} = 0b0; let Inst{31-16} = 0b0001111000000010; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_vzh_alt : HInst< @@ -37327,6 +38449,7 @@ def V6_vzh_alt : HInst< PSEUDO, TypeMAPPING>, Requires<[UseHVXV60]> { let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -37340,6 +38463,7 @@ let Inst{7-0} = 0b00000000; let Inst{12-11} = 0b00; let Inst{31-21} = 0b00101100000; let addrMode = BaseImmOffset; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let DecoderNamespace = "EXT_mmvec"; @@ -37353,6 +38477,7 @@ let Inst{7-0} = 0b00000000; let Inst{13-11} = 0b000; let Inst{31-21} = 0b00101101000; let addrMode = PostInc; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let DecoderNamespace = "EXT_mmvec"; @@ -37366,6 +38491,7 @@ tc_a0dbea28, TypeCVI_ZW>, Enc_44661f, Requires<[UseHVXV66,UseZReg]> { let Inst{12-0} = 0b0000000000001; let Inst{31-21} = 0b00101101000; let addrMode = PostInc; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let DecoderNamespace = "EXT_mmvec"; @@ -37380,6 +38506,7 @@ let Inst{7-0} = 0b00000000; let Inst{31-21} = 0b00101100100; let isPredicated = 1; let addrMode = BaseImmOffset; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let DecoderNamespace = "EXT_mmvec"; @@ -37394,6 +38521,7 @@ let Inst{13-13} = 0b0; let Inst{31-21} = 0b00101101100; let isPredicated = 1; let addrMode = PostInc; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let DecoderNamespace = "EXT_mmvec"; @@ -37408,6 +38536,7 @@ let Inst{10-0} = 0b00000000001; let Inst{31-21} = 0b00101101100; let isPredicated = 1; let addrMode = PostInc; +let isCVI = 1; let mayLoad = 1; let isRestrictNoSlot1Store = 1; let DecoderNamespace = "EXT_mmvec"; @@ -37422,6 +38551,7 @@ let Inst{13-5} = 0b000001001; let Inst{31-21} = 0b00011001101; let hasNewValue = 1; let opNewValue = 0; +let isCVI = 1; let DecoderNamespace = "EXT_mmvec"; } def V6_zld0 : HInst< @@ -37429,6 +38559,7 @@ def V6_zld0 : HInst< (ins IntRegs:$Rt32), "z = vmem($Rt32)", PSEUDO, TypeMAPPING>, Requires<[UseHVXV66]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -37438,6 +38569,7 @@ def V6_zldp0 : HInst< (ins PredRegs:$Pv4, IntRegs:$Rt32), "if ($Pv4) z = vmem($Rt32)", PSEUDO, TypeMAPPING>, Requires<[UseHVXV66]> { +let isCVI = 1; let isPseudo = 1; let isCodeGenOnly = 1; let DecoderNamespace = "EXT_mmvec"; @@ -37446,7 +38578,7 @@ def Y2_barrier : HInst< (outs), (ins), "barrier", -tc_8c99de45, TypeST>, Enc_e3b0c4 { +tc_77f94a5e, TypeST>, Enc_e3b0c4 { let Inst{13-0} = 0b00000000000000; let Inst{31-16} = 0b1010100000000000; let isSoloAX = 1; @@ -37456,7 +38588,7 @@ def Y2_break : HInst< (outs), (ins), "brkpt", -tc_9ad9998f, TypeCR>, Enc_e3b0c4 { +tc_55255f2b, TypeCR>, Enc_e3b0c4 { let Inst{13-0} = 0b00000000000000; let Inst{31-16} = 0b0110110000100000; let isSolo = 1; @@ -37465,7 +38597,7 @@ def Y2_dccleana : HInst< (outs), (ins IntRegs:$Rs32), "dccleana($Rs32)", -tc_b857bf4e, TypeST>, Enc_ecbcc8 { +tc_b1ae5f67, TypeST>, Enc_ecbcc8 { let Inst{13-0} = 0b00000000000000; let Inst{31-21} = 0b10100000000; let isRestrictSlot1AOK = 1; @@ -37475,7 +38607,7 @@ def Y2_dccleaninva : HInst< (outs), (ins IntRegs:$Rs32), "dccleaninva($Rs32)", -tc_b857bf4e, TypeST>, Enc_ecbcc8 { +tc_b1ae5f67, TypeST>, Enc_ecbcc8 { let Inst{13-0} = 0b00000000000000; let Inst{31-21} = 0b10100000010; let isRestrictSlot1AOK = 1; @@ -37485,7 +38617,7 @@ def Y2_dcfetch : HInst< (outs), (ins IntRegs:$Rs32), "dcfetch($Rs32)", -tc_d63f638c, TypeMAPPING> { +tc_d45ba9cd, TypeMAPPING> { let hasSideEffects = 1; let isPseudo = 1; let isCodeGenOnly = 1; @@ -37494,7 +38626,7 @@ def Y2_dcfetchbo : HInst< (outs), (ins IntRegs:$Rs32, u11_3Imm:$Ii), "dcfetch($Rs32+#$Ii)", -tc_9ca930f7, TypeLD>, Enc_2d829e { +tc_2237d952, TypeLD>, Enc_2d829e { let Inst{13-11} = 0b000; let Inst{31-21} = 0b10010100000; let addrMode = BaseImmOffset; @@ -37505,7 +38637,7 @@ def Y2_dcinva : HInst< (outs), (ins IntRegs:$Rs32), "dcinva($Rs32)", -tc_b857bf4e, TypeST>, Enc_ecbcc8 { +tc_b1ae5f67, TypeST>, Enc_ecbcc8 { let Inst{13-0} = 0b00000000000000; let Inst{31-21} = 0b10100000001; let isRestrictSlot1AOK = 1; @@ -37515,7 +38647,7 @@ def Y2_dczeroa : HInst< (outs), (ins IntRegs:$Rs32), "dczeroa($Rs32)", -tc_b857bf4e, TypeST>, Enc_ecbcc8 { +tc_b1ae5f67, TypeST>, Enc_ecbcc8 { let Inst{13-0} = 0b00000000000000; let Inst{31-21} = 0b10100000110; let isRestrictSlot1AOK = 1; @@ -37526,7 +38658,7 @@ def Y2_icinva : HInst< (outs), (ins IntRegs:$Rs32), "icinva($Rs32)", -tc_5d7f5414, TypeJ>, Enc_ecbcc8 { +tc_0ba0d5da, TypeJ>, Enc_ecbcc8 { let Inst{13-0} = 0b00000000000000; let Inst{31-21} = 0b01010110110; let isSolo = 1; @@ -37535,7 +38667,7 @@ def Y2_isync : HInst< (outs), (ins), "isync", -tc_8b121f4a, TypeJ>, Enc_e3b0c4 { +tc_9b34f5e0, TypeJ>, Enc_e3b0c4 { let Inst{13-0} = 0b00000000000010; let Inst{31-16} = 0b0101011111000000; let isSolo = 1; @@ -37544,7 +38676,7 @@ def Y2_syncht : HInst< (outs), (ins), "syncht", -tc_8c99de45, TypeST>, Enc_e3b0c4 { +tc_77f94a5e, TypeST>, Enc_e3b0c4 { let Inst{13-0} = 0b00000000000000; let Inst{31-16} = 0b1010100001000000; let isSolo = 1; @@ -37553,7 +38685,7 @@ def Y2_wait : HInst< (outs), (ins IntRegs:$Rs32), "wait($Rs32)", -tc_174516e8, TypeCR>, Enc_ecbcc8, Requires<[HasV65]> { +tc_d7718fbe, TypeCR>, Enc_ecbcc8 { let Inst{13-0} = 0b00000000000000; let Inst{31-21} = 0b01100100010; let isSolo = 1; @@ -37562,7 +38694,7 @@ def Y4_l2fetch : HInst< (outs), (ins IntRegs:$Rs32, IntRegs:$Rt32), "l2fetch($Rs32,$Rt32)", -tc_fe211424, TypeST>, Enc_ca3887 { +tc_a3070909, TypeST>, Enc_ca3887 { let Inst{7-0} = 0b00000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10100110000; @@ -37574,7 +38706,7 @@ def Y4_trace : HInst< (outs), (ins IntRegs:$Rs32), "trace($Rs32)", -tc_6b25e783, TypeCR>, Enc_ecbcc8 { +tc_d7718fbe, TypeCR>, Enc_ecbcc8 { let Inst{13-0} = 0b00000000000000; let Inst{31-21} = 0b01100010010; let isSoloAX = 1; @@ -37583,7 +38715,7 @@ def Y5_l2fetch : HInst< (outs), (ins IntRegs:$Rs32, DoubleRegs:$Rtt32), "l2fetch($Rs32,$Rtt32)", -tc_fe211424, TypeST>, Enc_e6abcf { +tc_a3070909, TypeST>, Enc_e6abcf { let Inst{7-0} = 0b00000000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b10100110100; @@ -37591,11 +38723,37 @@ let isSoloAX = 1; let mayStore = 1; let hasSideEffects = 1; } +def Y6_diag : HInst< +(outs), +(ins IntRegs:$Rs32), +"diag($Rs32)", +tc_2c3e17fc, TypeCR>, Enc_ecbcc8, Requires<[HasV67]> { +let Inst{13-0} = 0b00000000100000; +let Inst{31-21} = 0b01100010010; +} +def Y6_diag0 : HInst< +(outs), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"diag0($Rss32,$Rtt32)", +tc_28e55c6f, TypeCR>, Enc_b00112, Requires<[HasV67]> { +let Inst{7-0} = 0b01000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01100010010; +} +def Y6_diag1 : HInst< +(outs), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"diag1($Rss32,$Rtt32)", +tc_28e55c6f, TypeCR>, Enc_b00112, Requires<[HasV67]> { +let Inst{7-0} = 0b01100000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01100010010; +} def dep_A2_addsat : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rd32 = add($Rs32,$Rt32):sat:deprecated", -tc_779080bf, TypeALU64>, Enc_5ab2be { +tc_8a825db2, TypeALU64>, Enc_5ab2be { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101100; @@ -37608,7 +38766,7 @@ def dep_A2_subsat : HInst< (outs IntRegs:$Rd32), (ins IntRegs:$Rt32, IntRegs:$Rs32), "$Rd32 = sub($Rt32,$Rs32):sat:deprecated", -tc_779080bf, TypeALU64>, Enc_bd6011 { +tc_8a825db2, TypeALU64>, Enc_bd6011 { let Inst{7-5} = 0b100; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010101100; @@ -37621,8 +38779,476 @@ def dep_S2_packhl : HInst< (outs DoubleRegs:$Rdd32), (ins IntRegs:$Rs32, IntRegs:$Rt32), "$Rdd32 = packhl($Rs32,$Rt32):deprecated", -tc_946df596, TypeALU64>, Enc_be32a5 { +tc_5da50c4b, TypeALU64>, Enc_be32a5 { let Inst{7-5} = 0b000; let Inst{13-13} = 0b0; let Inst{31-21} = 0b11010100000; } +def dup_A2_add : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = add($Rs32,$Rt32)", +tc_388f9897, TypeALU32_3op>, Requires<[HasV67]> { +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let isPseudo = 1; +} +def dup_A2_addi : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Rd32 = add($Rs32,#$Ii)", +tc_388f9897, TypeALU32_ADDI>, Requires<[HasV67]> { +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 16; +let opExtentAlign = 0; +} +def dup_A2_andir : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Rd32 = and($Rs32,#$Ii)", +tc_388f9897, TypeALU32_2op>, Requires<[HasV67]> { +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 10; +let opExtentAlign = 0; +} +def dup_A2_combineii : HInst< +(outs DoubleRegs:$Rdd32), +(ins s32_0Imm:$Ii, s8_0Imm:$II), +"$Rdd32 = combine(#$Ii,#$II)", +tc_388f9897, TypeALU32_2op>, Requires<[HasV67]> { +let AsmVariantName = "NonParsable"; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def dup_A2_sxtb : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = sxtb($Rs32)", +tc_9124c04f, TypeALU32_2op>, Requires<[HasV67]> { +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let isPseudo = 1; +} +def dup_A2_sxth : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = sxth($Rs32)", +tc_9124c04f, TypeALU32_2op>, Requires<[HasV67]> { +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let isPseudo = 1; +} +def dup_A2_tfr : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = $Rs32", +tc_9124c04f, TypeALU32_2op>, Requires<[HasV67]> { +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let isPseudo = 1; +} +def dup_A2_tfrsi : HInst< +(outs IntRegs:$Rd32), +(ins s32_0Imm:$Ii), +"$Rd32 = #$Ii", +tc_9124c04f, TypeALU32_2op>, Requires<[HasV67]> { +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 16; +let opExtentAlign = 0; +} +def dup_A2_zxtb : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = zxtb($Rs32)", +PSEUDO, TypeMAPPING>, Requires<[HasV67]> { +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let isPseudo = 1; +} +def dup_A2_zxth : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = zxth($Rs32)", +tc_9124c04f, TypeALU32_2op>, Requires<[HasV67]> { +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let isPseudo = 1; +} +def dup_A4_combineii : HInst< +(outs DoubleRegs:$Rdd32), +(ins s8_0Imm:$Ii, u32_0Imm:$II), +"$Rdd32 = combine(#$Ii,#$II)", +tc_388f9897, TypeALU32_2op>, Requires<[HasV67]> { +let AsmVariantName = "NonParsable"; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def dup_A4_combineir : HInst< +(outs DoubleRegs:$Rdd32), +(ins s32_0Imm:$Ii, IntRegs:$Rs32), +"$Rdd32 = combine(#$Ii,$Rs32)", +tc_388f9897, TypeALU32_2op>, Requires<[HasV67]> { +let AsmVariantName = "NonParsable"; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def dup_A4_combineri : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Rdd32 = combine($Rs32,#$Ii)", +tc_388f9897, TypeALU32_2op>, Requires<[HasV67]> { +let AsmVariantName = "NonParsable"; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def dup_C2_cmoveif : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, s32_0Imm:$Ii), +"if (!$Pu4) $Rd32 = #$Ii", +tc_388f9897, TypeALU32_2op>, Requires<[HasV67]> { +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 12; +let opExtentAlign = 0; +} +def dup_C2_cmoveit : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, s32_0Imm:$Ii), +"if ($Pu4) $Rd32 = #$Ii", +tc_388f9897, TypeALU32_2op>, Requires<[HasV67]> { +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 12; +let opExtentAlign = 0; +} +def dup_C2_cmovenewif : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, s32_0Imm:$Ii), +"if (!$Pu4.new) $Rd32 = #$Ii", +tc_4ac61d92, TypeALU32_2op>, Requires<[HasV67]> { +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let isPredicatedNew = 1; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 12; +let opExtentAlign = 0; +} +def dup_C2_cmovenewit : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, s32_0Imm:$Ii), +"if ($Pu4.new) $Rd32 = #$Ii", +tc_4ac61d92, TypeALU32_2op>, Requires<[HasV67]> { +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let isPredicatedNew = 1; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 12; +let opExtentAlign = 0; +} +def dup_C2_cmpeqi : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Pd4 = cmp.eq($Rs32,#$Ii)", +tc_388f9897, TypeALU32_2op>, Requires<[HasV67]> { +let AsmVariantName = "NonParsable"; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 10; +let opExtentAlign = 0; +} +def dup_L2_deallocframe : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = deallocframe($Rs32):raw", +tc_aee6250c, TypeLD>, Requires<[HasV67]> { +let accessSize = DoubleWordAccess; +let AsmVariantName = "NonParsable"; +let mayLoad = 1; +let Uses = [FRAMEKEY]; +let Defs = [R29]; +let isPseudo = 1; +} +def dup_L2_loadrb_io : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Rd32 = memb($Rs32+#$Ii)", +tc_eed07714, TypeLD>, Requires<[HasV67]> { +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let AsmVariantName = "NonParsable"; +let mayLoad = 1; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 0; +} +def dup_L2_loadrd_io : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, s29_3Imm:$Ii), +"$Rdd32 = memd($Rs32+#$Ii)", +tc_eed07714, TypeLD>, Requires<[HasV67]> { +let addrMode = BaseImmOffset; +let accessSize = DoubleWordAccess; +let AsmVariantName = "NonParsable"; +let mayLoad = 1; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 14; +let opExtentAlign = 3; +} +def dup_L2_loadrh_io : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s31_1Imm:$Ii), +"$Rd32 = memh($Rs32+#$Ii)", +tc_eed07714, TypeLD>, Requires<[HasV67]> { +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let AsmVariantName = "NonParsable"; +let mayLoad = 1; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 12; +let opExtentAlign = 1; +} +def dup_L2_loadri_io : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s30_2Imm:$Ii), +"$Rd32 = memw($Rs32+#$Ii)", +tc_eed07714, TypeLD>, Requires<[HasV67]> { +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let AsmVariantName = "NonParsable"; +let mayLoad = 1; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 13; +let opExtentAlign = 2; +} +def dup_L2_loadrub_io : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Rd32 = memub($Rs32+#$Ii)", +tc_eed07714, TypeLD>, Requires<[HasV67]> { +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let AsmVariantName = "NonParsable"; +let mayLoad = 1; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 0; +} +def dup_L2_loadruh_io : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s31_1Imm:$Ii), +"$Rd32 = memuh($Rs32+#$Ii)", +tc_eed07714, TypeLD>, Requires<[HasV67]> { +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let AsmVariantName = "NonParsable"; +let mayLoad = 1; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 12; +let opExtentAlign = 1; +} +def dup_S2_allocframe : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, u11_3Imm:$Ii), +"allocframe($Rx32,#$Ii):raw", +tc_74a42bda, TypeST>, Requires<[HasV67]> { +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = DoubleWordAccess; +let AsmVariantName = "NonParsable"; +let mayStore = 1; +let Uses = [FRAMEKEY, FRAMELIMIT, R30, R31]; +let Defs = [R30]; +let isPseudo = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def dup_S2_storerb_io : HInst< +(outs), +(ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Rt32), +"memb($Rs32+#$Ii) = $Rt32", +tc_a9edeffa, TypeST>, Requires<[HasV67]> { +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let AsmVariantName = "NonParsable"; +let mayStore = 1; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 0; +} +def dup_S2_storerd_io : HInst< +(outs), +(ins IntRegs:$Rs32, s29_3Imm:$Ii, DoubleRegs:$Rtt32), +"memd($Rs32+#$Ii) = $Rtt32", +tc_a9edeffa, TypeST>, Requires<[HasV67]> { +let addrMode = BaseImmOffset; +let accessSize = DoubleWordAccess; +let AsmVariantName = "NonParsable"; +let mayStore = 1; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 14; +let opExtentAlign = 3; +} +def dup_S2_storerh_io : HInst< +(outs), +(ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Rt32), +"memh($Rs32+#$Ii) = $Rt32", +tc_a9edeffa, TypeST>, Requires<[HasV67]> { +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let AsmVariantName = "NonParsable"; +let mayStore = 1; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 12; +let opExtentAlign = 1; +} +def dup_S2_storeri_io : HInst< +(outs), +(ins IntRegs:$Rs32, s30_2Imm:$Ii, IntRegs:$Rt32), +"memw($Rs32+#$Ii) = $Rt32", +tc_a9edeffa, TypeST>, Requires<[HasV67]> { +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let AsmVariantName = "NonParsable"; +let mayStore = 1; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 13; +let opExtentAlign = 2; +} +def dup_S4_storeirb_io : HInst< +(outs), +(ins IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II), +"memb($Rs32+#$Ii) = #$II", +tc_838c4d7a, TypeV4LDST>, Requires<[HasV67]> { +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let AsmVariantName = "NonParsable"; +let mayStore = 1; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def dup_S4_storeiri_io : HInst< +(outs), +(ins IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II), +"memw($Rs32+#$Ii) = #$II", +tc_838c4d7a, TypeV4LDST>, Requires<[HasV67]> { +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let AsmVariantName = "NonParsable"; +let mayStore = 1; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} |