diff options
Diffstat (limited to 'llvm/lib/Target/Hexagon')
57 files changed, 678 insertions, 606 deletions
diff --git a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp index 15eba89eeb55..4553f2fd9228 100644 --- a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp +++ b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp @@ -681,7 +681,7 @@ bool HexagonAsmParser::ParseDirectiveSubsection(SMLoc L) { Subsection = HexagonMCExpr::create( MCConstantExpr::create(8192 + Res, getContext()), getContext()); - getStreamer().SubSection(Subsection); + getStreamer().subSection(Subsection); return false; } @@ -1450,7 +1450,7 @@ int HexagonAsmParser::processInstruction(MCInst &Inst, MCOperand &MO_0 = Inst.getOperand(0); // push section onto section stack - MES->PushSection(); + MES->pushSection(); std::string myCharStr; MCSectionELF *mySection; @@ -1485,7 +1485,7 @@ int HexagonAsmParser::processInstruction(MCInst &Inst, } else llvm_unreachable("unexpected type of machine operand!"); - MES->SwitchSection(mySection); + MES->switchSection(mySection); unsigned byteSize = is32bit ? 4 : 8; getStreamer().emitCodeAlignment(byteSize, &getSTI(), byteSize); @@ -1526,7 +1526,7 @@ int HexagonAsmParser::processInstruction(MCInst &Inst, } else llvm_unreachable("unexpected type of machine operand!"); - MES->PopSection(); + MES->popSection(); if (Sym) { MCInst TmpInst; diff --git a/llvm/lib/Target/Hexagon/BitTracker.cpp b/llvm/lib/Target/Hexagon/BitTracker.cpp index 17adf32750db..4d5789a3c5fe 100644 --- a/llvm/lib/Target/Hexagon/BitTracker.cpp +++ b/llvm/lib/Target/Hexagon/BitTracker.cpp @@ -1056,9 +1056,8 @@ void BT::runEdgeQueue(BitVector &BlockScanned) { CFGEdge Edge = FlowQ.front(); FlowQ.pop(); - if (EdgeExec.count(Edge)) + if (!EdgeExec.insert(Edge).second) return; - EdgeExec.insert(Edge); ReachedBB.insert(Edge.second); const MachineBasicBlock &B = *MF.getBlockNumbered(Edge.second); diff --git a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp index 3c742c98077b..58d5df4c1f71 100644 --- a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp +++ b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp @@ -14,9 +14,9 @@ #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/STLExtras.h" #include "llvm/MC/MCContext.h" +#include "llvm/MC/MCDecoderOps.h" #include "llvm/MC/MCDisassembler/MCDisassembler.h" #include "llvm/MC/MCExpr.h" -#include "llvm/MC/MCFixedLenDisassembler.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" @@ -78,11 +78,12 @@ static uint64_t fullValue(HexagonDisassembler const &Disassembler, MCInst &MI, uint64_t Operand = Upper26 | Lower6; return Operand; } -static HexagonDisassembler const &disassembler(void const *Decoder) { +static HexagonDisassembler const &disassembler(const MCDisassembler *Decoder) { return *static_cast<HexagonDisassembler const *>(Decoder); } template <size_t T> -static void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) { +static void signedDecoder(MCInst &MI, unsigned tmp, + const MCDisassembler *Decoder) { HexagonDisassembler const &Disassembler = disassembler(Decoder); int64_t FullValue = fullValue(Disassembler, MI, SignExtend64<T>(tmp)); int64_t Extended = SignExtend64<32>(FullValue); @@ -95,65 +96,66 @@ static void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) { static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); -static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, - unsigned RegNo, - uint64_t Address, - const void *Decoder); -static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); +static DecodeStatus +DecodeGeneralSubRegsRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const MCDisassembler *Decoder); +static DecodeStatus +DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); -static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); +static DecodeStatus +DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); -static DecodeStatus DecodeHvxVQRRegisterClass(MCInst &Inst, - unsigned RegNo, + const MCDisassembler *Decoder); +static DecodeStatus DecodeHvxVQRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); -static DecodeStatus DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); +static DecodeStatus +DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder); - + const MCDisassembler *Decoder); static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, - uint64_t Address, const void *Decoder); + uint64_t Address, + const MCDisassembler *Decoder); static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t /*Address*/, const void *Decoder); + uint64_t /*Address*/, + const MCDisassembler *Decoder); static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, - const void *Decoder); + const MCDisassembler *Decoder); #include "HexagonDepDecoders.inc" #include "HexagonGenDisassemblerTables.inc" @@ -542,15 +544,15 @@ static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo, return MCDisassembler::Fail; } -static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder) { +static DecodeStatus +DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, + const MCDisassembler *Decoder) { return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder); } static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { static const MCPhysReg IntRegDecoderTable[] = { Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9, @@ -563,10 +565,10 @@ static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, return DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable); } -static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, - unsigned RegNo, - uint64_t Address, - const void *Decoder) { +static DecodeStatus +DecodeGeneralSubRegsRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const MCDisassembler *Decoder) { static const MCPhysReg GeneralSubRegDecoderTable[] = { Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon::R7, @@ -579,7 +581,7 @@ static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, - const void *Decoder) { + const MCDisassembler *Decoder) { static const MCPhysReg HvxVRDecoderTable[] = { Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4, Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9, @@ -592,9 +594,10 @@ static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo, return DecodeRegisterClass(Inst, RegNo, HvxVRDecoderTable); } -static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t /*Address*/, - const void *Decoder) { +static DecodeStatus +DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t /*Address*/, + const MCDisassembler *Decoder) { static const MCPhysReg DoubleRegDecoderTable[] = { Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7, @@ -604,8 +607,10 @@ static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, return DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable); } -static DecodeStatus DecodeGeneralDoubleLow8RegsRegisterClass( - MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { +static DecodeStatus +DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t /*Address*/, + const MCDisassembler *Decoder) { static const MCPhysReg GeneralDoubleLow8RegDecoderTable[] = { Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11}; @@ -615,7 +620,7 @@ static DecodeStatus DecodeGeneralDoubleLow8RegsRegisterClass( static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, - const void *Decoder) { + const MCDisassembler *Decoder) { static const MCPhysReg HvxWRDecoderTable[] = { Hexagon::W0, Hexagon::WR0, Hexagon::W1, Hexagon::WR1, Hexagon::W2, Hexagon::WR2, Hexagon::W3, Hexagon::WR3, Hexagon::W4, Hexagon::WR4, @@ -629,11 +634,11 @@ static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo, return DecodeRegisterClass(Inst, RegNo, HvxWRDecoderTable); } -LLVM_ATTRIBUTE_UNUSED // Suppress warning temporarily. -static DecodeStatus DecodeHvxVQRRegisterClass(MCInst &Inst, - unsigned RegNo, - uint64_t /*Address*/, - const void *Decoder) { +LLVM_ATTRIBUTE_UNUSED // Suppress warning temporarily. + static DecodeStatus + DecodeHvxVQRRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t /*Address*/, + const MCDisassembler *Decoder) { static const MCPhysReg HvxVQRDecoderTable[] = { Hexagon::VQ0, Hexagon::VQ1, Hexagon::VQ2, Hexagon::VQ3, Hexagon::VQ4, Hexagon::VQ5, Hexagon::VQ6, Hexagon::VQ7}; @@ -643,7 +648,7 @@ static DecodeStatus DecodeHvxVQRRegisterClass(MCInst &Inst, static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, - const void *Decoder) { + const MCDisassembler *Decoder) { static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1, Hexagon::P2, Hexagon::P3}; @@ -652,7 +657,7 @@ static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, - const void *Decoder) { + const MCDisassembler *Decoder) { static const MCPhysReg HvxQRDecoderTable[] = {Hexagon::Q0, Hexagon::Q1, Hexagon::Q2, Hexagon::Q3}; @@ -661,7 +666,7 @@ static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, - const void *Decoder) { + const MCDisassembler *Decoder) { using namespace Hexagon; static const MCPhysReg CtrlRegDecoderTable[] = { @@ -687,9 +692,9 @@ static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, return MCDisassembler::Success; } -static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t /*Address*/, - const void *Decoder) { +static DecodeStatus +DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, + const MCDisassembler *Decoder) { using namespace Hexagon; static const MCPhysReg CtrlReg64DecoderTable[] = { @@ -717,7 +722,7 @@ static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, - const void *Decoder) { + const MCDisassembler *Decoder) { unsigned Register = 0; switch (RegNo) { case 0: @@ -735,7 +740,7 @@ static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, uint64_t /*Address*/, - const void *Decoder) { + const MCDisassembler *Decoder) { HexagonDisassembler const &Disassembler = disassembler(Decoder); int64_t FullValue = fullValue(Disassembler, MI, tmp); assert(FullValue >= 0 && "Negative in unsigned decoder"); @@ -744,7 +749,8 @@ static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, } static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t /*Address*/, const void *Decoder) { + uint64_t /*Address*/, + const MCDisassembler *Decoder) { HexagonDisassembler const &Disassembler = disassembler(Decoder); unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI); tmp = SignExtend64(tmp, Bits); @@ -754,7 +760,7 @@ static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, // custom decoder for various jump/call immediates static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, - const void *Decoder) { + const MCDisassembler *Decoder) { HexagonDisassembler const &Disassembler = disassembler(Decoder); unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI); // r13_2 is not extendable, so if there are no extent bits, it's r13_2 @@ -762,7 +768,8 @@ static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, Bits = 15; uint64_t FullValue = fullValue(Disassembler, MI, SignExtend64(tmp, Bits)); uint32_t Extended = FullValue + Address; - if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, 0, 4)) + if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, 0, 0, + 4)) HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext()); return MCDisassembler::Success; } @@ -799,7 +806,7 @@ static const uint16_t SysRegDecoderTable[] = { static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, - const void *Decoder) { + const MCDisassembler *Decoder) { if (RegNo >= sizeof(SysRegDecoderTable) / sizeof(SysRegDecoderTable[0])) return MCDisassembler::Fail; @@ -824,9 +831,9 @@ static const uint16_t SysReg64DecoderTable[] = { Hexagon::S73_72, Hexagon::S75_74, Hexagon::S77_76, Hexagon::S79_78, }; -static DecodeStatus DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t /*Address*/, - const void *Decoder) { +static DecodeStatus +DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, + const MCDisassembler *Decoder) { RegNo = RegNo >> 1; if (RegNo >= sizeof(SysReg64DecoderTable) / sizeof(SysReg64DecoderTable[0])) return MCDisassembler::Fail; @@ -839,9 +846,9 @@ static DecodeStatus DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo, return MCDisassembler::Success; } -static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t /*Address*/, - const void *Decoder) { +static DecodeStatus +DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, + const MCDisassembler *Decoder) { using namespace Hexagon; static const MCPhysReg GuestRegDecoderTable[] = { @@ -865,9 +872,10 @@ static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo, return MCDisassembler::Success; } -static DecodeStatus DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, - uint64_t /*Address*/, - const void *Decoder) { +static DecodeStatus +DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t /*Address*/, + const MCDisassembler *Decoder) { using namespace Hexagon; static const MCPhysReg GuestReg64DecoderTable[] = { diff --git a/llvm/lib/Target/Hexagon/HexagonArch.h b/llvm/lib/Target/Hexagon/HexagonArch.h deleted file mode 100644 index 4a42ec98feb1..000000000000 --- a/llvm/lib/Target/Hexagon/HexagonArch.h +++ /dev/null @@ -1,31 +0,0 @@ -//===- HexagonArch.h ------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONARCH_H -#define LLVM_LIB_TARGET_HEXAGON_HEXAGONARCH_H - -#include "llvm/ADT/ArrayRef.h" -#include "llvm/ADT/Optional.h" -#include "llvm/ADT/StringRef.h" -#include "HexagonDepArch.h" -#include <algorithm> - -namespace llvm { -namespace Hexagon { - -template <class ArchCont, typename Val> -llvm::Optional<ArchEnum> GetCpu(ArchCont const &ArchList, Val CPUString) { - llvm::Optional<ArchEnum> Res; - auto Entry = ArchList.find(CPUString); - if (Entry != ArchList.end()) - Res = Entry->second; - return Res; -} -} // namespace Hexagon -} // namespace llvm -#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONARCH_H diff --git a/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp b/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp index 411078052e0f..48d339234e9e 100644 --- a/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp +++ b/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp @@ -202,7 +202,7 @@ static MCSymbol *smallData(AsmPrinter &AP, const MachineInstr &MI, MCSectionELF *Section = OutStreamer.getContext().getELFSection( sectionName, ELF::SHT_PROGBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC); - OutStreamer.SwitchSection(Section); + OutStreamer.switchSection(Section); Sym = AP.OutContext.getOrCreateSymbol(Twine(symbolName)); if (Sym->isUndefined()) { @@ -231,7 +231,7 @@ static MCSymbol *smallData(AsmPrinter &AP, const MachineInstr &MI, MCSectionELF *Section = OutStreamer.getContext().getELFSection( ".lita", ELF::SHT_PROGBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC); - OutStreamer.SwitchSection(Section); + OutStreamer.switchSection(Section); Sym = AP.OutContext.getOrCreateSymbol(Twine(LitaName)); if (Sym->isUndefined()) { OutStreamer.emitLabel(Sym); @@ -331,7 +331,7 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst, MCSymbol *Sym = smallData(*this, MI, *OutStreamer, Imm, 8, getSubtargetInfo()); - OutStreamer->SwitchSection(Current.first, Current.second); + OutStreamer->switchSection(Current.first, Current.second); MCInst TmpInst; MCOperand &Reg = MappedInst.getOperand(0); TmpInst.setOpcode(Hexagon::L2_loadrdgp); @@ -348,7 +348,7 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst, MCSectionSubPair Current = OutStreamer->getCurrentSection(); MCSymbol *Sym = smallData(*this, MI, *OutStreamer, Imm, 4, getSubtargetInfo()); - OutStreamer->SwitchSection(Current.first, Current.second); + OutStreamer->switchSection(Current.first, Current.second); MCInst TmpInst; MCOperand &Reg = MappedInst.getOperand(0); TmpInst.setOpcode(Hexagon::L2_loadrigp); diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp index b2a842233bb8..673b397ef3c5 100644 --- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp +++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp @@ -39,6 +39,7 @@ #include <algorithm> #include <cassert> #include <cstdint> +#include <deque> #include <iterator> #include <limits> #include <utility> @@ -62,6 +63,9 @@ static cl::opt<unsigned> MaxBitSplit("hexbit-max-bitsplit", cl::Hidden, cl::init(std::numeric_limits<unsigned>::max())); static unsigned CountBitSplit = 0; +static cl::opt<unsigned> RegisterSetLimit("hexbit-registerset-limit", + cl::Hidden, cl::init(1000)); + namespace llvm { void initializeHexagonBitSimplifyPass(PassRegistry& Registry); @@ -72,23 +76,29 @@ namespace llvm { namespace { // Set of virtual registers, based on BitVector. - struct RegisterSet : private BitVector { + struct RegisterSet { RegisterSet() = default; - explicit RegisterSet(unsigned s, bool t = false) : BitVector(s, t) {} + explicit RegisterSet(unsigned s, bool t = false) : Bits(s, t) {} RegisterSet(const RegisterSet &RS) = default; - using BitVector::clear; - using BitVector::count; + void clear() { + Bits.clear(); + LRU.clear(); + } + + unsigned count() const { + return Bits.count(); + } unsigned find_first() const { - int First = BitVector::find_first(); + int First = Bits.find_first(); if (First < 0) return 0; return x2v(First); } unsigned find_next(unsigned Prev) const { - int Next = BitVector::find_next(v2x(Prev)); + int Next = Bits.find_next(v2x(Prev)); if (Next < 0) return 0; return x2v(Next); @@ -97,54 +107,72 @@ namespace { RegisterSet &insert(unsigned R) { unsigned Idx = v2x(R); ensure(Idx); - return static_cast<RegisterSet&>(BitVector::set(Idx)); + bool Exists = Bits.test(Idx); + Bits.set(Idx); + if (!Exists) { + LRU.push_back(Idx); + if (LRU.size() > RegisterSetLimit) { + unsigned T = LRU.front(); + Bits.reset(T); + LRU.pop_front(); + } + } + return *this; } RegisterSet &remove(unsigned R) { unsigned Idx = v2x(R); - if (Idx >= size()) - return *this; - return static_cast<RegisterSet&>(BitVector::reset(Idx)); + if (Idx < Bits.size()) { + bool Exists = Bits.test(Idx); + Bits.reset(Idx); + if (Exists) { + auto F = llvm::find(LRU, Idx); + assert(F != LRU.end()); + LRU.erase(F); + } + } + return *this; } RegisterSet &insert(const RegisterSet &Rs) { - return static_cast<RegisterSet&>(BitVector::operator|=(Rs)); + for (unsigned R = Rs.find_first(); R; R = Rs.find_next(R)) + insert(R); + return *this; } RegisterSet &remove(const RegisterSet &Rs) { - return static_cast<RegisterSet&>(BitVector::reset(Rs)); + for (unsigned R = Rs.find_first(); R; R = Rs.find_next(R)) + remove(R); + return *this; } - reference operator[](unsigned R) { - unsigned Idx = v2x(R); - ensure(Idx); - return BitVector::operator[](Idx); - } bool operator[](unsigned R) const { unsigned Idx = v2x(R); - assert(Idx < size()); - return BitVector::operator[](Idx); + return Idx < Bits.size() ? Bits[Idx] : false; } bool has(unsigned R) const { unsigned Idx = v2x(R); - if (Idx >= size()) + if (Idx >= Bits.size()) return false; - return BitVector::test(Idx); + return Bits.test(Idx); } bool empty() const { - return !BitVector::any(); + return !Bits.any(); } bool includes(const RegisterSet &Rs) const { - // A.BitVector::test(B) <=> A-B != {} - return !Rs.BitVector::test(*this); + // A.test(B) <=> A-B != {} + return !Rs.Bits.test(Bits); } bool intersects(const RegisterSet &Rs) const { - return BitVector::anyCommon(Rs); + return Bits.anyCommon(Rs.Bits); } private: + BitVector Bits; + std::deque<unsigned> LRU; + void ensure(unsigned Idx) { - if (size() <= Idx) - resize(std::max(Idx+1, 32U)); + if (Bits.size() <= Idx) + Bits.resize(std::max(Idx+1, 32U)); } static inline unsigned v2x(unsigned v) { @@ -1997,7 +2025,7 @@ bool BitSimplification::genStoreImmediate(MachineInstr *MI) { if (!isInt<8>(V)) return false; - MI->RemoveOperand(2); + MI->removeOperand(2); switch (Opc) { case Hexagon::S2_storerb_io: MI->setDesc(HII.get(Hexagon::S4_storeirb_io)); diff --git a/llvm/lib/Target/Hexagon/HexagonBranchRelaxation.cpp b/llvm/lib/Target/Hexagon/HexagonBranchRelaxation.cpp index faa48211cd82..ca7fddb0ebe5 100644 --- a/llvm/lib/Target/Hexagon/HexagonBranchRelaxation.cpp +++ b/llvm/lib/Target/Hexagon/HexagonBranchRelaxation.cpp @@ -33,8 +33,9 @@ using namespace llvm; // Since we have no exact knowledge of code layout, allow some safety buffer // for jump target. This is measured in bytes. -static cl::opt<uint32_t> BranchRelaxSafetyBuffer("branch-relax-safety-buffer", - cl::init(200), cl::Hidden, cl::ZeroOrMore, cl::desc("safety buffer size")); +static cl::opt<uint32_t> + BranchRelaxSafetyBuffer("branch-relax-safety-buffer", cl::init(200), + cl::Hidden, cl::desc("safety buffer size")); namespace llvm { diff --git a/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp b/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp index fc5e05d8c9a0..2fe2e032714a 100644 --- a/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp +++ b/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp @@ -52,13 +52,12 @@ using namespace llvm; static cl::opt<bool> OptSpeculate("commgep-speculate", cl::init(true), - cl::Hidden, cl::ZeroOrMore); + cl::Hidden); -static cl::opt<bool> OptEnableInv("commgep-inv", cl::init(true), cl::Hidden, - cl::ZeroOrMore); +static cl::opt<bool> OptEnableInv("commgep-inv", cl::init(true), cl::Hidden); static cl::opt<bool> OptEnableConst("commgep-const", cl::init(true), - cl::Hidden, cl::ZeroOrMore); + cl::Hidden); namespace llvm { diff --git a/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp b/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp index d8af35cbf3a8..56fb50cdb09e 100644 --- a/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp +++ b/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp @@ -9,6 +9,7 @@ #include "HexagonInstrInfo.h" #include "HexagonRegisterInfo.h" #include "HexagonSubtarget.h" +#include "llvm/ADT/SetVector.h" #include "llvm/ADT/SmallVector.h" #include "llvm/CodeGen/MachineDominators.h" #include "llvm/CodeGen/MachineFunctionPass.h" @@ -28,12 +29,13 @@ using namespace llvm; -static cl::opt<unsigned> CountThreshold("hexagon-cext-threshold", - cl::init(3), cl::Hidden, cl::ZeroOrMore, - cl::desc("Minimum number of extenders to trigger replacement")); +static cl::opt<unsigned> CountThreshold( + "hexagon-cext-threshold", cl::init(3), cl::Hidden, + cl::desc("Minimum number of extenders to trigger replacement")); -static cl::opt<unsigned> ReplaceLimit("hexagon-cext-limit", cl::init(0), - cl::Hidden, cl::ZeroOrMore, cl::desc("Maximum number of replacements")); +static cl::opt<unsigned> + ReplaceLimit("hexagon-cext-limit", cl::init(0), cl::Hidden, + cl::desc("Maximum number of replacements")); namespace llvm { void initializeHexagonConstExtendersPass(PassRegistry&); diff --git a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp index 105bf2811a20..8029dcff8052 100644 --- a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp +++ b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp @@ -868,8 +868,8 @@ void MachineConstPropagator::removeCFGEdge(MachineBasicBlock *From, int N = PN.getNumOperands() - 2; while (N > 0) { if (PN.getOperand(N + 1).getMBB() == From) { - PN.RemoveOperand(N + 1); - PN.RemoveOperand(N); + PN.removeOperand(N + 1); + PN.removeOperand(N); } N -= 2; } @@ -1217,8 +1217,8 @@ bool MachineConstEvaluator::evaluateCMPii(uint32_t Cmp, const APInt &A1, unsigned W2 = A2.getBitWidth(); unsigned MaxW = (W1 >= W2) ? W1 : W2; if (Cmp & Comparison::U) { - const APInt Zx1 = A1.zextOrSelf(MaxW); - const APInt Zx2 = A2.zextOrSelf(MaxW); + APInt Zx1 = A1.zext(MaxW); + APInt Zx2 = A2.zext(MaxW); if (Cmp & Comparison::L) Result = Zx1.ult(Zx2); else if (Cmp & Comparison::G) @@ -1227,8 +1227,8 @@ bool MachineConstEvaluator::evaluateCMPii(uint32_t Cmp, const APInt &A1, } // Signed comparison. - const APInt Sx1 = A1.sextOrSelf(MaxW); - const APInt Sx2 = A2.sextOrSelf(MaxW); + APInt Sx1 = A1.sext(MaxW); + APInt Sx2 = A2.sext(MaxW); if (Cmp & Comparison::L) Result = Sx1.slt(Sx2); else if (Cmp & Comparison::G) @@ -1813,7 +1813,7 @@ bool MachineConstEvaluator::evaluateSplati(const APInt &A1, unsigned Bits, unsigned Count, APInt &Result) { assert(Count > 0); unsigned BW = A1.getBitWidth(), SW = Count*Bits; - APInt LoBits = (Bits < BW) ? A1.trunc(Bits) : A1.zextOrSelf(Bits); + APInt LoBits = (Bits < BW) ? A1.trunc(Bits) : A1.zext(Bits); if (Count > 1) LoBits = LoBits.zext(SW); @@ -2510,7 +2510,7 @@ APInt HexagonConstEvaluator::getCmpImm(unsigned Opc, unsigned OpX, void HexagonConstEvaluator::replaceWithNop(MachineInstr &MI) { MI.setDesc(HII.get(Hexagon::A2_nop)); while (MI.getNumOperands() > 0) - MI.RemoveOperand(0); + MI.removeOperand(0); } bool HexagonConstEvaluator::evaluateHexRSEQ32(RegisterSubReg RL, RegisterSubReg RH, @@ -2538,9 +2538,9 @@ bool HexagonConstEvaluator::evaluateHexRSEQ32(RegisterSubReg RL, RegisterSubReg } for (unsigned i = 0; i < HiVs.size(); ++i) { - APInt HV = HiVs[i].zextOrSelf(64) << 32; + APInt HV = HiVs[i].zext(64) << 32; for (unsigned j = 0; j < LoVs.size(); ++j) { - APInt LV = LoVs[j].zextOrSelf(64); + APInt LV = LoVs[j].zext(64); const Constant *C = intToConst(HV | LV); Result.add(C); if (Result.isBottom()) @@ -3165,7 +3165,7 @@ bool HexagonConstEvaluator::rewriteHexBranch(MachineInstr &BrI, .addMBB(TargetB); BrI.setDesc(JD); while (BrI.getNumOperands() > 0) - BrI.RemoveOperand(0); + BrI.removeOperand(0); // This ensures that all implicit operands (e.g. implicit-def %r31, etc) // are present in the rewritten branch. for (auto &Op : NI->operands()) diff --git a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp index 2ee7f1325df9..dc5b674424c8 100644 --- a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp +++ b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp @@ -33,16 +33,14 @@ using namespace llvm; #define DEBUG_TYPE "hexagon-copy-combine" -static -cl::opt<bool> IsCombinesDisabled("disable-merge-into-combines", - cl::Hidden, cl::ZeroOrMore, - cl::init(false), - cl::desc("Disable merging into combines")); -static -cl::opt<bool> IsConst64Disabled("disable-const64", - cl::Hidden, cl::ZeroOrMore, - cl::init(false), - cl::desc("Disable generation of const64")); +static cl::opt<bool> + IsCombinesDisabled("disable-merge-into-combines", cl::Hidden, + + cl::desc("Disable merging into combines")); +static cl::opt<bool> + IsConst64Disabled("disable-const64", cl::Hidden, + + cl::desc("Disable generation of const64")); static cl::opt<unsigned> MaxNumOfInstsBetweenNewValueStoreAndTFR("max-num-inst-between-tfr-and-nv-store", diff --git a/llvm/lib/Target/Hexagon/HexagonDepArch.h b/llvm/lib/Target/Hexagon/HexagonDepArch.h index 56174dc7e136..41ce5c465d41 100644 --- a/llvm/lib/Target/Hexagon/HexagonDepArch.h +++ b/llvm/lib/Target/Hexagon/HexagonDepArch.h @@ -12,82 +12,28 @@ #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPARCH_H #define LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPARCH_H -#include "llvm/ADT/ArrayRef.h" -#include "llvm/ADT/StringRef.h" -#include "llvm/BinaryFormat/ELF.h" - -#include <map> -#include <string> +#include "llvm/ADT/StringSwitch.h" namespace llvm { namespace Hexagon { enum class ArchEnum { NoArch, Generic, V5, V55, V60, V62, V65, V66, V67, V68, V69 }; -static constexpr unsigned ArchValsNumArray[] = {5, 55, 60, 62, 65, 66, 67, 68, 69}; -static constexpr ArrayRef<unsigned> ArchValsNum(ArchValsNumArray); - -static constexpr StringLiteral ArchValsTextArray[] = { "v5", "v55", "v60", "v62", "v65", "v66", "v67", "v68", "v69" }; -static constexpr ArrayRef<StringLiteral> ArchValsText(ArchValsTextArray); - -static constexpr StringLiteral CpuValsTextArray[] = { "hexagonv5", "hexagonv55", "hexagonv60", "hexagonv62", "hexagonv65", "hexagonv66", "hexagonv67", "hexagonv67t", "hexagonv68", "hexagonv69" }; -static constexpr ArrayRef<StringLiteral> CpuValsText(CpuValsTextArray); - -static constexpr StringLiteral CpuNickTextArray[] = { "v5", "v55", "v60", "v62", "v65", "v66", "v67", "v67t", "v68", "v69" }; -static constexpr ArrayRef<StringLiteral> CpuNickText(CpuNickTextArray); - -static const std::map<std::string, ArchEnum> CpuTable{ - {"generic", Hexagon::ArchEnum::V5}, - {"hexagonv5", Hexagon::ArchEnum::V5}, - {"hexagonv55", Hexagon::ArchEnum::V55}, - {"hexagonv60", Hexagon::ArchEnum::V60}, - {"hexagonv62", Hexagon::ArchEnum::V62}, - {"hexagonv65", Hexagon::ArchEnum::V65}, - {"hexagonv66", Hexagon::ArchEnum::V66}, - {"hexagonv67", Hexagon::ArchEnum::V67}, - {"hexagonv67t", Hexagon::ArchEnum::V67}, - {"hexagonv68", Hexagon::ArchEnum::V68}, - {"hexagonv69", Hexagon::ArchEnum::V69}, -}; - -static const std::map<std::string, unsigned> ElfFlagsByCpuStr = { - {"generic", llvm::ELF::EF_HEXAGON_MACH_V5}, - {"hexagonv5", llvm::ELF::EF_HEXAGON_MACH_V5}, - {"hexagonv55", llvm::ELF::EF_HEXAGON_MACH_V55}, - {"hexagonv60", llvm::ELF::EF_HEXAGON_MACH_V60}, - {"hexagonv62", llvm::ELF::EF_HEXAGON_MACH_V62}, - {"hexagonv65", llvm::ELF::EF_HEXAGON_MACH_V65}, - {"hexagonv66", llvm::ELF::EF_HEXAGON_MACH_V66}, - {"hexagonv67", llvm::ELF::EF_HEXAGON_MACH_V67}, - {"hexagonv67t", llvm::ELF::EF_HEXAGON_MACH_V67T}, - {"hexagonv68", llvm::ELF::EF_HEXAGON_MACH_V68}, - {"hexagonv69", llvm::ELF::EF_HEXAGON_MACH_V69}, -}; -static const std::map<unsigned, std::string> ElfArchByMachFlags = { - {llvm::ELF::EF_HEXAGON_MACH_V5, "V5"}, - {llvm::ELF::EF_HEXAGON_MACH_V55, "V55"}, - {llvm::ELF::EF_HEXAGON_MACH_V60, "V60"}, - {llvm::ELF::EF_HEXAGON_MACH_V62, "V62"}, - {llvm::ELF::EF_HEXAGON_MACH_V65, "V65"}, - {llvm::ELF::EF_HEXAGON_MACH_V66, "V66"}, - {llvm::ELF::EF_HEXAGON_MACH_V67, "V67"}, - {llvm::ELF::EF_HEXAGON_MACH_V67T, "V67T"}, - {llvm::ELF::EF_HEXAGON_MACH_V68, "V68"}, - {llvm::ELF::EF_HEXAGON_MACH_V69, "V69"}, -}; -static const std::map<unsigned, std::string> ElfCpuByMachFlags = { - {llvm::ELF::EF_HEXAGON_MACH_V5, "hexagonv5"}, - {llvm::ELF::EF_HEXAGON_MACH_V55, "hexagonv55"}, - {llvm::ELF::EF_HEXAGON_MACH_V60, "hexagonv60"}, - {llvm::ELF::EF_HEXAGON_MACH_V62, "hexagonv62"}, - {llvm::ELF::EF_HEXAGON_MACH_V65, "hexagonv65"}, - {llvm::ELF::EF_HEXAGON_MACH_V66, "hexagonv66"}, - {llvm::ELF::EF_HEXAGON_MACH_V67, "hexagonv67"}, - {llvm::ELF::EF_HEXAGON_MACH_V67T, "hexagonv67t"}, - {llvm::ELF::EF_HEXAGON_MACH_V68, "hexagonv68"}, - {llvm::ELF::EF_HEXAGON_MACH_V69, "hexagonv69"}, -}; - +inline Optional<Hexagon::ArchEnum> getCpu(StringRef CPU) { + return StringSwitch<Optional<Hexagon::ArchEnum>>(CPU) + .Case("generic", Hexagon::ArchEnum::V5) + .Case("hexagonv5", Hexagon::ArchEnum::V5) + .Case("hexagonv55", Hexagon::ArchEnum::V55) + .Case("hexagonv60", Hexagon::ArchEnum::V60) + .Case("hexagonv62", Hexagon::ArchEnum::V62) + .Case("hexagonv65", Hexagon::ArchEnum::V65) + .Case("hexagonv66", Hexagon::ArchEnum::V66) + .Case("hexagonv67", Hexagon::ArchEnum::V67) + .Case("hexagonv67t", Hexagon::ArchEnum::V67) + .Case("hexagonv68", Hexagon::ArchEnum::V68) + .Case("hexagonv69", Hexagon::ArchEnum::V69) + .Default(None); +} } // namespace Hexagon -} // namespace llvm; +} // namespace llvm #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPARCH_H diff --git a/llvm/lib/Target/Hexagon/HexagonDepDecoders.inc b/llvm/lib/Target/Hexagon/HexagonDepDecoders.inc index 7164af3ad5c6..e979cfe6e325 100644 --- a/llvm/lib/Target/Hexagon/HexagonDepDecoders.inc +++ b/llvm/lib/Target/Hexagon/HexagonDepDecoders.inc @@ -14,58 +14,58 @@ #pragma clang diagnostic ignored "-Wunused-function" #endif -static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t, const void *Decoder) { +static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, + const MCDisassembler *Decoder) { signedDecoder<6>(MI, tmp, Decoder); return MCDisassembler::Success; } -static DecodeStatus s31_1ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t, const void *Decoder) { +static DecodeStatus s31_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, + const MCDisassembler *Decoder) { signedDecoder<12>(MI, tmp, Decoder); return MCDisassembler::Success; } -static DecodeStatus s30_2ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t, const void *Decoder) { +static DecodeStatus s30_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, + const MCDisassembler *Decoder) { signedDecoder<13>(MI, tmp, Decoder); return MCDisassembler::Success; } -static DecodeStatus s29_3ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t, const void *Decoder) { +static DecodeStatus s29_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, + const MCDisassembler *Decoder) { signedDecoder<14>(MI, tmp, Decoder); return MCDisassembler::Success; } -static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t, const void *Decoder) { +static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, + const MCDisassembler *Decoder) { signedDecoder<3>(MI, tmp, Decoder); return MCDisassembler::Success; } -static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t, const void *Decoder) { +static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, + const MCDisassembler *Decoder) { signedDecoder<4>(MI, tmp, Decoder); return MCDisassembler::Success; } -static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t, const void *Decoder) { +static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, + const MCDisassembler *Decoder) { signedDecoder<5>(MI, tmp, Decoder); return MCDisassembler::Success; } -static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t, const void *Decoder) { +static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, + const MCDisassembler *Decoder) { signedDecoder<6>(MI, tmp, Decoder); return MCDisassembler::Success; } -static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t, const void *Decoder) { +static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, + const MCDisassembler *Decoder) { signedDecoder<7>(MI, tmp, Decoder); return MCDisassembler::Success; } -static DecodeStatus s6_3ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t, const void *Decoder) { +static DecodeStatus s6_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, + const MCDisassembler *Decoder) { signedDecoder<9>(MI, tmp, Decoder); return MCDisassembler::Success; } -static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t, const void *Decoder) { +static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t, + const MCDisassembler *Decoder) { signedDecoder<8>(MI, tmp, Decoder); return MCDisassembler::Success; } diff --git a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp index 2207925ceeba..f7227dca3b60 100644 --- a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp +++ b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp @@ -826,8 +826,8 @@ void HexagonEarlyIfConversion::updatePhiNodes(MachineBasicBlock *WhereB, FR = RO.getReg(), FSR = RO.getSubReg(); else continue; - PN->RemoveOperand(i+1); - PN->RemoveOperand(i); + PN->removeOperand(i+1); + PN->removeOperand(i); } if (TR == 0) TR = SR, TSR = SSR; diff --git a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp index 2693940bb1e9..853553f57ba4 100644 --- a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp +++ b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp @@ -696,7 +696,7 @@ bool HexagonExpandCondsets::split(MachineInstr &MI, MI.setDesc(HII->get(TargetOpcode::COPY)); unsigned S = getRegState(ST); while (MI.getNumOperands() > 1) - MI.RemoveOperand(MI.getNumOperands()-1); + MI.removeOperand(MI.getNumOperands()-1); MachineFunction &MF = *MI.getParent()->getParent(); MachineInstrBuilder(MF, MI).addReg(RT.Reg, S, RT.Sub); return true; diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp index 989a98571434..0b4a95bc9ce5 100644 --- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp @@ -152,33 +152,38 @@ using namespace llvm; static cl::opt<bool> DisableDeallocRet("disable-hexagon-dealloc-ret", cl::Hidden, cl::desc("Disable Dealloc Return for Hexagon target")); -static cl::opt<unsigned> NumberScavengerSlots("number-scavenger-slots", - cl::Hidden, cl::desc("Set the number of scavenger slots"), cl::init(2), - cl::ZeroOrMore); +static cl::opt<unsigned> + NumberScavengerSlots("number-scavenger-slots", cl::Hidden, + cl::desc("Set the number of scavenger slots"), + cl::init(2)); -static cl::opt<int> SpillFuncThreshold("spill-func-threshold", - cl::Hidden, cl::desc("Specify O2(not Os) spill func threshold"), - cl::init(6), cl::ZeroOrMore); +static cl::opt<int> + SpillFuncThreshold("spill-func-threshold", cl::Hidden, + cl::desc("Specify O2(not Os) spill func threshold"), + cl::init(6)); -static cl::opt<int> SpillFuncThresholdOs("spill-func-threshold-Os", - cl::Hidden, cl::desc("Specify Os spill func threshold"), - cl::init(1), cl::ZeroOrMore); +static cl::opt<int> + SpillFuncThresholdOs("spill-func-threshold-Os", cl::Hidden, + cl::desc("Specify Os spill func threshold"), + cl::init(1)); -static cl::opt<bool> EnableStackOVFSanitizer("enable-stackovf-sanitizer", - cl::Hidden, cl::desc("Enable runtime checks for stack overflow."), - cl::init(false), cl::ZeroOrMore); +static cl::opt<bool> EnableStackOVFSanitizer( + "enable-stackovf-sanitizer", cl::Hidden, + cl::desc("Enable runtime checks for stack overflow."), cl::init(false)); -static cl::opt<bool> EnableShrinkWrapping("hexagon-shrink-frame", - cl::init(true), cl::Hidden, cl::ZeroOrMore, - cl::desc("Enable stack frame shrink wrapping")); +static cl::opt<bool> + EnableShrinkWrapping("hexagon-shrink-frame", cl::init(true), cl::Hidden, + cl::desc("Enable stack frame shrink wrapping")); -static cl::opt<unsigned> ShrinkLimit("shrink-frame-limit", - cl::init(std::numeric_limits<unsigned>::max()), cl::Hidden, cl::ZeroOrMore, - cl::desc("Max count of stack frame shrink-wraps")); +static cl::opt<unsigned> + ShrinkLimit("shrink-frame-limit", + cl::init(std::numeric_limits<unsigned>::max()), cl::Hidden, + cl::desc("Max count of stack frame shrink-wraps")); -static cl::opt<bool> EnableSaveRestoreLong("enable-save-restore-long", - cl::Hidden, cl::desc("Enable long calls for save-restore stubs."), - cl::init(false), cl::ZeroOrMore); +static cl::opt<bool> + EnableSaveRestoreLong("enable-save-restore-long", cl::Hidden, + cl::desc("Enable long calls for save-restore stubs."), + cl::init(false)); static cl::opt<bool> EliminateFramePointer("hexagon-fp-elim", cl::init(true), cl::Hidden, cl::desc("Refrain from using FP whenever possible")); @@ -1018,7 +1023,7 @@ findCFILocation(MachineBasicBlock &B) { void HexagonFrameLowering::insertCFIInstructions(MachineFunction &MF) const { for (auto &B : MF) { auto At = findCFILocation(B); - if (At.hasValue()) + if (At) insertCFIInstructionsAt(B, At.getValue()); } } diff --git a/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp b/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp index 0bb1658e7698..44f21dbacd3c 100644 --- a/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp +++ b/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp @@ -47,34 +47,36 @@ using namespace llvm; -static cl::opt<unsigned> VRegIndexCutoff("insert-vreg-cutoff", cl::init(~0U), - cl::Hidden, cl::ZeroOrMore, cl::desc("Vreg# cutoff for insert generation.")); +static cl::opt<unsigned> + VRegIndexCutoff("insert-vreg-cutoff", cl::init(~0U), cl::Hidden, + cl::desc("Vreg# cutoff for insert generation.")); // The distance cutoff is selected based on the precheckin-perf results: // cutoffs 20, 25, 35, and 40 are worse than 30. -static cl::opt<unsigned> VRegDistCutoff("insert-dist-cutoff", cl::init(30U), - cl::Hidden, cl::ZeroOrMore, cl::desc("Vreg distance cutoff for insert " - "generation.")); +static cl::opt<unsigned> + VRegDistCutoff("insert-dist-cutoff", cl::init(30U), cl::Hidden, + cl::desc("Vreg distance cutoff for insert " + "generation.")); // Limit the container sizes for extreme cases where we run out of memory. -static cl::opt<unsigned> MaxORLSize("insert-max-orl", cl::init(4096), - cl::Hidden, cl::ZeroOrMore, cl::desc("Maximum size of OrderedRegisterList")); +static cl::opt<unsigned> + MaxORLSize("insert-max-orl", cl::init(4096), cl::Hidden, + cl::desc("Maximum size of OrderedRegisterList")); static cl::opt<unsigned> MaxIFMSize("insert-max-ifmap", cl::init(1024), - cl::Hidden, cl::ZeroOrMore, cl::desc("Maximum size of IFMap")); + cl::Hidden, + cl::desc("Maximum size of IFMap")); -static cl::opt<bool> OptTiming("insert-timing", cl::init(false), cl::Hidden, - cl::ZeroOrMore, cl::desc("Enable timing of insert generation")); -static cl::opt<bool> OptTimingDetail("insert-timing-detail", cl::init(false), - cl::Hidden, cl::ZeroOrMore, cl::desc("Enable detailed timing of insert " - "generation")); +static cl::opt<bool> OptTiming("insert-timing", cl::Hidden, + cl::desc("Enable timing of insert generation")); +static cl::opt<bool> + OptTimingDetail("insert-timing-detail", cl::Hidden, + cl::desc("Enable detailed timing of insert " + "generation")); -static cl::opt<bool> OptSelectAll0("insert-all0", cl::init(false), cl::Hidden, - cl::ZeroOrMore); -static cl::opt<bool> OptSelectHas0("insert-has0", cl::init(false), cl::Hidden, - cl::ZeroOrMore); +static cl::opt<bool> OptSelectAll0("insert-all0", cl::init(false), cl::Hidden); +static cl::opt<bool> OptSelectHas0("insert-has0", cl::init(false), cl::Hidden); // Whether to construct constant values via "insert". Could eliminate constant // extenders, but often not practical. -static cl::opt<bool> OptConst("insert-const", cl::init(false), cl::Hidden, - cl::ZeroOrMore); +static cl::opt<bool> OptConst("insert-const", cl::init(false), cl::Hidden); // The preprocessor gets confused when the DEBUG macro is passed larger // chunks of code. Use this function to detect debugging. @@ -92,11 +94,8 @@ namespace { struct RegisterSet : private BitVector { RegisterSet() = default; explicit RegisterSet(unsigned s, bool t = false) : BitVector(s, t) {} - RegisterSet(const RegisterSet &RS) : BitVector(RS) {} - RegisterSet &operator=(const RegisterSet &RS) { - BitVector::operator=(RS); - return *this; - } + RegisterSet(const RegisterSet &RS) = default; + RegisterSet &operator=(const RegisterSet &RS) = default; using BitVector::clear; diff --git a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp index 43afae441457..acc0bb8941c1 100644 --- a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp +++ b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp @@ -81,9 +81,9 @@ static cl::opt<bool> HWCreatePreheader("hexagon-hwloop-preheader", // Turn it off by default. If a preheader block is not created here, the // software pipeliner may be unable to find a block suitable to serve as // a preheader. In that case SWP will not run. -static cl::opt<bool> SpecPreheader("hwloop-spec-preheader", cl::init(false), - cl::Hidden, cl::ZeroOrMore, cl::desc("Allow speculation of preheader " - "instructions")); +static cl::opt<bool> SpecPreheader("hwloop-spec-preheader", cl::Hidden, + cl::desc("Allow speculation of preheader " + "instructions")); STATISTIC(NumHWLoops, "Number of loops converted to hardware loops"); @@ -1911,8 +1911,8 @@ MachineBasicBlock *HexagonHardwareLoops::createPreheaderForLoop( for (int i = PN->getNumOperands()-2; i > 0; i -= 2) { MachineBasicBlock *PredB = PN->getOperand(i+1).getMBB(); if (PredB != Latch) { - PN->RemoveOperand(i+1); - PN->RemoveOperand(i); + PN->removeOperand(i+1); + PN->removeOperand(i); } } PN->addOperand(MachineOperand::CreateReg(NewPR, false)); diff --git a/llvm/lib/Target/Hexagon/HexagonHazardRecognizer.cpp b/llvm/lib/Target/Hexagon/HexagonHazardRecognizer.cpp index e2215c9900d0..577eccd25c19 100644 --- a/llvm/lib/Target/Hexagon/HexagonHazardRecognizer.cpp +++ b/llvm/lib/Target/Hexagon/HexagonHazardRecognizer.cpp @@ -106,7 +106,7 @@ bool HexagonHazardRecognizer::isNewStore(MachineInstr &MI) { if (!TII->mayBeNewStore(MI)) return false; MachineOperand &MO = MI.getOperand(MI.getNumOperands() - 1); - return (MO.isReg() && RegDefs.count(MO.getReg()) != 0); + return MO.isReg() && RegDefs.contains(MO.getReg()); } void HexagonHazardRecognizer::EmitInstruction(SUnit *SU) { diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index 161768b8dc22..b4979c953516 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -1345,7 +1345,8 @@ inline bool HexagonDAGToDAGISel::SelectAnyInt(SDValue &N, SDValue &R) { EVT T = N.getValueType(); if (!T.isInteger() || T.getSizeInBits() != 32 || !isa<ConstantSDNode>(N)) return false; - R = N; + int32_t V = cast<const ConstantSDNode>(N)->getZExtValue(); + R = CurDAG->getTargetConstant(V, SDLoc(N), N.getValueType()); return true; } @@ -1540,7 +1541,7 @@ bool HexagonDAGToDAGISel::keepsLowBits(const SDValue &Val, unsigned NumBits, break; case ISD::AND: { // Check if this is an AND with NumBits of lower bits set to 1. - uint64_t Mask = (1 << NumBits) - 1; + uint64_t Mask = (1ULL << NumBits) - 1; if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(0))) { if (C->getZExtValue() == Mask) { Src = Val.getOperand(1); @@ -1558,7 +1559,7 @@ bool HexagonDAGToDAGISel::keepsLowBits(const SDValue &Val, unsigned NumBits, case ISD::OR: case ISD::XOR: { // OR/XOR with the lower NumBits bits set to 0. - uint64_t Mask = (1 << NumBits) - 1; + uint64_t Mask = (1ULL << NumBits) - 1; if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(0))) { if ((C->getZExtValue() & Mask) == 0) { Src = Val.getOperand(1); @@ -1580,7 +1581,7 @@ bool HexagonDAGToDAGISel::keepsLowBits(const SDValue &Val, unsigned NumBits, } bool HexagonDAGToDAGISel::isAlignedMemNode(const MemSDNode *N) const { - return N->getAlignment() >= N->getMemoryVT().getStoreSize(); + return N->getAlign().value() >= N->getMemoryVT().getStoreSize(); } bool HexagonDAGToDAGISel::isSmallStackStore(const StoreSDNode *N) const { @@ -1655,7 +1656,7 @@ struct WeightedLeaf { int Weight; int InsertionOrder; - WeightedLeaf() : Value(SDValue()) { } + WeightedLeaf() {} WeightedLeaf(SDValue Value, int Weight, int InsertionOrder) : Value(Value), Weight(Weight), InsertionOrder(InsertionOrder) { diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp index 0a6dd727eb82..0848d30e7403 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp @@ -801,7 +801,7 @@ static const HexagonTargetLowering &getHexagonLowering(SelectionDAG &G) { return static_cast<const HexagonTargetLowering&>(G.getTargetLoweringInfo()); } static const HexagonSubtarget &getHexagonSubtarget(SelectionDAG &G) { - return static_cast<const HexagonSubtarget&>(G.getSubtarget()); + return G.getSubtarget<HexagonSubtarget>(); } namespace llvm { diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index d7ca934a23e6..94411b2e4f98 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -72,41 +72,41 @@ static cl::opt<bool> EmitJumpTables("hexagon-emit-jump-tables", cl::init(true), cl::Hidden, cl::desc("Control jump table emission on Hexagon target")); -static cl::opt<bool> EnableHexSDNodeSched("enable-hexagon-sdnode-sched", - cl::Hidden, cl::ZeroOrMore, cl::init(false), - cl::desc("Enable Hexagon SDNode scheduling")); +static cl::opt<bool> + EnableHexSDNodeSched("enable-hexagon-sdnode-sched", cl::Hidden, + cl::desc("Enable Hexagon SDNode scheduling")); -static cl::opt<bool> EnableFastMath("ffast-math", - cl::Hidden, cl::ZeroOrMore, cl::init(false), - cl::desc("Enable Fast Math processing")); +static cl::opt<bool> EnableFastMath("ffast-math", cl::Hidden, + cl::desc("Enable Fast Math processing")); -static cl::opt<int> MinimumJumpTables("minimum-jump-tables", - cl::Hidden, cl::ZeroOrMore, cl::init(5), - cl::desc("Set minimum jump tables")); +static cl::opt<int> MinimumJumpTables("minimum-jump-tables", cl::Hidden, + cl::init(5), + cl::desc("Set minimum jump tables")); -static cl::opt<int> MaxStoresPerMemcpyCL("max-store-memcpy", - cl::Hidden, cl::ZeroOrMore, cl::init(6), - cl::desc("Max #stores to inline memcpy")); +static cl::opt<int> + MaxStoresPerMemcpyCL("max-store-memcpy", cl::Hidden, cl::init(6), + cl::desc("Max #stores to inline memcpy")); -static cl::opt<int> MaxStoresPerMemcpyOptSizeCL("max-store-memcpy-Os", - cl::Hidden, cl::ZeroOrMore, cl::init(4), - cl::desc("Max #stores to inline memcpy")); +static cl::opt<int> + MaxStoresPerMemcpyOptSizeCL("max-store-memcpy-Os", cl::Hidden, cl::init(4), + cl::desc("Max #stores to inline memcpy")); -static cl::opt<int> MaxStoresPerMemmoveCL("max-store-memmove", - cl::Hidden, cl::ZeroOrMore, cl::init(6), - cl::desc("Max #stores to inline memmove")); +static cl::opt<int> + MaxStoresPerMemmoveCL("max-store-memmove", cl::Hidden, cl::init(6), + cl::desc("Max #stores to inline memmove")); -static cl::opt<int> MaxStoresPerMemmoveOptSizeCL("max-store-memmove-Os", - cl::Hidden, cl::ZeroOrMore, cl::init(4), - cl::desc("Max #stores to inline memmove")); +static cl::opt<int> + MaxStoresPerMemmoveOptSizeCL("max-store-memmove-Os", cl::Hidden, + cl::init(4), + cl::desc("Max #stores to inline memmove")); -static cl::opt<int> MaxStoresPerMemsetCL("max-store-memset", - cl::Hidden, cl::ZeroOrMore, cl::init(8), - cl::desc("Max #stores to inline memset")); +static cl::opt<int> + MaxStoresPerMemsetCL("max-store-memset", cl::Hidden, cl::init(8), + cl::desc("Max #stores to inline memset")); -static cl::opt<int> MaxStoresPerMemsetOptSizeCL("max-store-memset-Os", - cl::Hidden, cl::ZeroOrMore, cl::init(4), - cl::desc("Max #stores to inline memset")); +static cl::opt<int> + MaxStoresPerMemsetOptSizeCL("max-store-memset-Os", cl::Hidden, cl::init(4), + cl::desc("Max #stores to inline memset")); static cl::opt<bool> AlignLoads("hexagon-align-loads", cl::Hidden, cl::init(false), @@ -1396,10 +1396,9 @@ HexagonTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, Hexagon::R0, Chain, InFlag); InFlag = Chain.getValue(1); - unsigned Flags = - static_cast<const HexagonSubtarget &>(DAG.getSubtarget()).useLongCalls() - ? HexagonII::MO_GDPLT | HexagonII::HMOTF_ConstExtended - : HexagonII::MO_GDPLT; + unsigned Flags = DAG.getSubtarget<HexagonSubtarget>().useLongCalls() + ? HexagonII::MO_GDPLT | HexagonII::HMOTF_ConstExtended + : HexagonII::MO_GDPLT; return GetDynamicTLSAddr(DAG, Chain, GA, InFlag, PtrVT, Hexagon::R0, Flags); @@ -2164,6 +2163,11 @@ HexagonTargetLowering::getPreferredVectorAction(MVT VT) const { // Always widen (remaining) vectors of i1. if (ElemTy == MVT::i1) return TargetLoweringBase::TypeWidenVector; + // Widen non-power-of-2 vectors. Such types cannot be split right now, + // and computeRegisterProperties will override "split" with "widen", + // which can cause other issues. + if (!isPowerOf2_32(VecLen)) + return TargetLoweringBase::TypeWidenVector; return TargetLoweringBase::TypeSplitVector; } @@ -2423,16 +2427,25 @@ HexagonTargetLowering::buildVector32(ArrayRef<SDValue> Elem, const SDLoc &dl, llvm::all_of(Consts, [](ConstantInt *CI) { return CI->isZero(); })) return getZero(dl, VecTy, DAG); - if (ElemTy == MVT::i16) { + if (ElemTy == MVT::i16 || ElemTy == MVT::f16) { assert(Elem.size() == 2); if (AllConst) { + // The 'Consts' array will have all values as integers regardless + // of the vector element type. uint32_t V = (Consts[0]->getZExtValue() & 0xFFFF) | Consts[1]->getZExtValue() << 16; - return DAG.getBitcast(MVT::v2i16, DAG.getConstant(V, dl, MVT::i32)); + return DAG.getBitcast(VecTy, DAG.getConstant(V, dl, MVT::i32)); + } + SDValue E0, E1; + if (ElemTy == MVT::f16) { + E0 = DAG.getZExtOrTrunc(DAG.getBitcast(MVT::i16, Elem[0]), dl, MVT::i32); + E1 = DAG.getZExtOrTrunc(DAG.getBitcast(MVT::i16, Elem[1]), dl, MVT::i32); + } else { + E0 = Elem[0]; + E1 = Elem[1]; } - SDValue N = getInstr(Hexagon::A2_combine_ll, dl, MVT::i32, - {Elem[1], Elem[0]}, DAG); - return DAG.getBitcast(MVT::v2i16, N); + SDValue N = getInstr(Hexagon::A2_combine_ll, dl, MVT::i32, {E1, E0}, DAG); + return DAG.getBitcast(VecTy, N); } if (ElemTy == MVT::i8) { @@ -2506,7 +2519,7 @@ HexagonTargetLowering::buildVector64(ArrayRef<SDValue> Elem, const SDLoc &dl, return getZero(dl, VecTy, DAG); // First try splat if possible. - if (ElemTy == MVT::i16) { + if (ElemTy == MVT::i16 || ElemTy == MVT::f16) { bool IsSplat = true; for (unsigned i = First+1; i != Num; ++i) { if (Elem[i] == Elem[First] || isUndef(Elem[i])) @@ -2516,7 +2529,9 @@ HexagonTargetLowering::buildVector64(ArrayRef<SDValue> Elem, const SDLoc &dl, } if (IsSplat) { // Legalize the operand of SPLAT_VECTOR - SDValue Ext = DAG.getZExtOrTrunc(Elem[First], dl, MVT::i32); + SDValue S = ElemTy == MVT::f16 ? DAG.getBitcast(MVT::i16, Elem[First]) + : Elem[First]; + SDValue Ext = DAG.getZExtOrTrunc(S, dl, MVT::i32); return DAG.getNode(ISD::SPLAT_VECTOR, dl, VecTy, Ext); } } @@ -2525,8 +2540,7 @@ HexagonTargetLowering::buildVector64(ArrayRef<SDValue> Elem, const SDLoc &dl, if (AllConst) { uint64_t Val = 0; unsigned W = ElemTy.getSizeInBits(); - uint64_t Mask = (ElemTy == MVT::i8) ? 0xFFull - : (ElemTy == MVT::i16) ? 0xFFFFull : 0xFFFFFFFFull; + uint64_t Mask = (1ull << W) - 1; for (unsigned i = 0; i != Num; ++i) Val = (Val << W) | (Consts[Num-1-i]->getZExtValue() & Mask); SDValue V0 = DAG.getConstant(Val, dl, MVT::i64); @@ -3656,9 +3670,12 @@ HexagonTargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const { : AtomicExpansionKind::None; } -bool HexagonTargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const { +TargetLowering::AtomicExpansionKind +HexagonTargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const { // Do not expand loads and stores that don't exceed 64 bits. - return SI->getValueOperand()->getType()->getPrimitiveSizeInBits() > 64; + return SI->getValueOperand()->getType()->getPrimitiveSizeInBits() > 64 + ? AtomicExpansionKind::Expand + : AtomicExpansionKind::None; } TargetLowering::AtomicExpansionKind diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.h b/llvm/lib/Target/Hexagon/HexagonISelLowering.h index f9ce7a9407aa..9561dfe8a35d 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.h +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.h @@ -328,7 +328,7 @@ public: Value *emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override; AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override; - bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override; + AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override; AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override; diff --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp index 0ba75a544c04..da6ad3ca2c93 100755 --- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp @@ -24,7 +24,6 @@ static const MVT LegalW64[] = { MVT::v128i8, MVT::v64i16, MVT::v32i32 }; static const MVT LegalV128[] = { MVT::v128i8, MVT::v64i16, MVT::v32i32 }; static const MVT LegalW128[] = { MVT::v256i8, MVT::v128i16, MVT::v64i32 }; - void HexagonTargetLowering::initializeHVXLowering() { if (Subtarget.useHVX64BOps()) { @@ -79,80 +78,85 @@ HexagonTargetLowering::initializeHVXLowering() { // Handle bitcasts of vector predicates to scalars (e.g. v32i1 to i32). // Note: v16i1 -> i16 is handled in type legalization instead of op // legalization. - setOperationAction(ISD::BITCAST, MVT::i16, Custom); - setOperationAction(ISD::BITCAST, MVT::i32, Custom); - setOperationAction(ISD::BITCAST, MVT::i64, Custom); + setOperationAction(ISD::BITCAST, MVT::i16, Custom); + setOperationAction(ISD::BITCAST, MVT::i32, Custom); + setOperationAction(ISD::BITCAST, MVT::i64, Custom); setOperationAction(ISD::BITCAST, MVT::v16i1, Custom); - setOperationAction(ISD::BITCAST, MVT::v128i1, Custom); - setOperationAction(ISD::BITCAST, MVT::i128, Custom); - setOperationAction(ISD::VECTOR_SHUFFLE, ByteV, Legal); - setOperationAction(ISD::VECTOR_SHUFFLE, ByteW, Legal); + setOperationAction(ISD::BITCAST, MVT::v128i1, Custom); + setOperationAction(ISD::BITCAST, MVT::i128, Custom); + setOperationAction(ISD::VECTOR_SHUFFLE, ByteV, Legal); + setOperationAction(ISD::VECTOR_SHUFFLE, ByteW, Legal); setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); if (Subtarget.useHVX128BOps() && Subtarget.useHVXV68Ops() && Subtarget.useHVXFloatingPoint()) { - setOperationAction(ISD::FMINNUM, MVT::v64f16, Legal); - setOperationAction(ISD::FMAXNUM, MVT::v64f16, Legal); - setOperationAction(ISD::FADD, MVT::v64f16, Legal); - setOperationAction(ISD::FSUB, MVT::v64f16, Legal); - setOperationAction(ISD::FMUL, MVT::v64f16, Legal); - setOperationAction(ISD::FADD, MVT::v32f32, Legal); - setOperationAction(ISD::FSUB, MVT::v32f32, Legal); - setOperationAction(ISD::FMUL, MVT::v32f32, Legal); - setOperationAction(ISD::FMINNUM, MVT::v32f32, Legal); - setOperationAction(ISD::FMAXNUM, MVT::v32f32, Legal); - setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64f16, Custom); - setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v64f16, Custom); - setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32f32, Custom); - setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v32f32, Custom); - // Handle ISD::BUILD_VECTOR for v32f32 in a custom way to generate vsplat - setOperationAction(ISD::BUILD_VECTOR, MVT::v32f32, Custom); + static const MVT FloatV[] = { MVT::v64f16, MVT::v32f32 }; + static const MVT FloatW[] = { MVT::v128f16, MVT::v64f32 }; + + for (MVT T : FloatV) { + setOperationAction(ISD::FADD, T, Legal); + setOperationAction(ISD::FSUB, T, Legal); + setOperationAction(ISD::FMUL, T, Legal); + setOperationAction(ISD::FMINNUM, T, Legal); + setOperationAction(ISD::FMAXNUM, T, Legal); + + setOperationAction(ISD::INSERT_SUBVECTOR, T, Custom); + setOperationAction(ISD::EXTRACT_SUBVECTOR, T, Custom); + + setOperationAction(ISD::SPLAT_VECTOR, T, Legal); + setOperationAction(ISD::SPLAT_VECTOR, T, Legal); + + setOperationAction(ISD::MLOAD, T, Custom); + setOperationAction(ISD::MSTORE, T, Custom); + // Custom-lower BUILD_VECTOR. The standard (target-independent) + // handling of it would convert it to a load, which is not always + // the optimal choice. + setOperationAction(ISD::BUILD_VECTOR, T, Custom); + } + // BUILD_VECTOR with f16 operands cannot be promoted without // promoting the result, so lower the node to vsplat or constant pool - setOperationAction(ISD::BUILD_VECTOR, MVT::f16, Custom); - setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::f16, Custom); - setOperationAction(ISD::SPLAT_VECTOR, MVT::f16, Custom); - setOperationAction(ISD::SPLAT_VECTOR, MVT::v64f16, Legal); - setOperationAction(ISD::SPLAT_VECTOR, MVT::v32f32, Legal); + setOperationAction(ISD::BUILD_VECTOR, MVT::f16, Custom); + setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::f16, Custom); + setOperationAction(ISD::SPLAT_VECTOR, MVT::f16, Custom); + // Vector shuffle is always promoted to ByteV and a bitcast to f16 is // generated. - setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v64f16, ByteV); - setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v64f32, ByteW); - setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v32f32, ByteV); + setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v128f16, ByteW); + setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v64f16, ByteV); + setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v64f32, ByteW); + setPromoteTo(ISD::VECTOR_SHUFFLE, MVT::v32f32, ByteV); - // Custom-lower BUILD_VECTOR for vector pairs. The standard (target- - // independent) handling of it would convert it to a load, which is - // not always the optimal choice. - setOperationAction(ISD::BUILD_VECTOR, MVT::v64f32, Custom); - // Make concat-vectors custom to handle concats of more than 2 vectors. - setOperationAction(ISD::CONCAT_VECTORS, MVT::v128f16, Custom); - setOperationAction(ISD::CONCAT_VECTORS, MVT::v64f32, Custom); + for (MVT P : FloatW) { + setOperationAction(ISD::LOAD, P, Custom); + setOperationAction(ISD::STORE, P, Custom); + setOperationAction(ISD::FADD, P, Custom); + setOperationAction(ISD::FSUB, P, Custom); + setOperationAction(ISD::FMUL, P, Custom); + setOperationAction(ISD::FMINNUM, P, Custom); + setOperationAction(ISD::FMAXNUM, P, Custom); + setOperationAction(ISD::VSELECT, P, Custom); - setOperationAction(ISD::LOAD, MVT::v64f32, Custom); - setOperationAction(ISD::STORE, MVT::v64f32, Custom); - setOperationAction(ISD::FADD, MVT::v64f32, Custom); - setOperationAction(ISD::FSUB, MVT::v64f32, Custom); - setOperationAction(ISD::FMUL, MVT::v64f32, Custom); - setOperationAction(ISD::FMINNUM, MVT::v64f32, Custom); - setOperationAction(ISD::FMAXNUM, MVT::v64f32, Custom); - setOperationAction(ISD::VSELECT, MVT::v64f32, Custom); + // Custom-lower BUILD_VECTOR. The standard (target-independent) + // handling of it would convert it to a load, which is not always + // the optimal choice. + setOperationAction(ISD::BUILD_VECTOR, P, Custom); + // Make concat-vectors custom to handle concats of more than 2 vectors. + setOperationAction(ISD::CONCAT_VECTORS, P, Custom); + + setOperationAction(ISD::MLOAD, P, Custom); + setOperationAction(ISD::MSTORE, P, Custom); + } if (Subtarget.useHVXQFloatOps()) { setOperationAction(ISD::FP_EXTEND, MVT::v64f32, Custom); - setOperationAction(ISD::FP_ROUND, MVT::v64f16, Legal); + setOperationAction(ISD::FP_ROUND, MVT::v64f16, Legal); } else if (Subtarget.useHVXIEEEFPOps()) { setOperationAction(ISD::FP_EXTEND, MVT::v64f32, Legal); - setOperationAction(ISD::FP_ROUND, MVT::v64f16, Legal); + setOperationAction(ISD::FP_ROUND, MVT::v64f16, Legal); } - - setOperationAction(ISD::MLOAD, MVT::v32f32, Custom); - setOperationAction(ISD::MSTORE, MVT::v32f32, Custom); - setOperationAction(ISD::MLOAD, MVT::v64f16, Custom); - setOperationAction(ISD::MSTORE, MVT::v64f16, Custom); - setOperationAction(ISD::MLOAD, MVT::v64f32, Custom); - setOperationAction(ISD::MSTORE, MVT::v64f32, Custom); } for (MVT T : LegalV) { @@ -382,8 +386,7 @@ HexagonTargetLowering::initializeHVXLowering() { } } - setTargetDAGCombine(ISD::SPLAT_VECTOR); - setTargetDAGCombine(ISD::VSELECT); + setTargetDAGCombine({ISD::SPLAT_VECTOR, ISD::VSELECT}); } unsigned @@ -780,7 +783,6 @@ HexagonTargetLowering::buildHvxVectorReg(ArrayRef<SDValue> Values, SDValue N = HalfV0; SDValue M = HalfV1; for (unsigned i = 0; i != NumWords/2; ++i) { - // Rotate by element count since last insertion. if (Words[i] != Words[n] || VecHist[n] <= 1) { Sn = DAG.getConstant(Rn, dl, MVT::i32); @@ -1411,6 +1413,17 @@ HexagonTargetLowering::LowerHvxBuildVector(SDValue Op, SelectionDAG &DAG) for (unsigned i = 0; i != Size; ++i) Ops.push_back(Op.getOperand(i)); + // First, split the BUILD_VECTOR for vector pairs. We could generate + // some pairs directly (via splat), but splats should be generated + // by the combiner prior to getting here. + if (VecTy.getSizeInBits() == 16*Subtarget.getVectorLength()) { + ArrayRef<SDValue> A(Ops); + MVT SingleTy = typeSplit(VecTy).first; + SDValue V0 = buildHvxVectorReg(A.take_front(Size/2), dl, SingleTy, DAG); + SDValue V1 = buildHvxVectorReg(A.drop_front(Size/2), dl, SingleTy, DAG); + return DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, V0, V1); + } + if (VecTy.getVectorElementType() == MVT::i1) return buildHvxVectorPred(Ops, dl, VecTy, DAG); @@ -1427,14 +1440,6 @@ HexagonTargetLowering::LowerHvxBuildVector(SDValue Op, SelectionDAG &DAG) return DAG.getBitcast(tyVector(VecTy, MVT::f16), T0); } - if (VecTy.getSizeInBits() == 16*Subtarget.getVectorLength()) { - ArrayRef<SDValue> A(Ops); - MVT SingleTy = typeSplit(VecTy).first; - SDValue V0 = buildHvxVectorReg(A.take_front(Size/2), dl, SingleTy, DAG); - SDValue V1 = buildHvxVectorReg(A.drop_front(Size/2), dl, SingleTy, DAG); - return DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, V0, V1); - } - return buildHvxVectorReg(Ops, dl, VecTy, DAG); } diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index 9b4e92a16663..c8e6276aa4de 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -77,9 +77,9 @@ cl::opt<bool> ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden, static cl::opt<bool> EnableBranchPrediction("hexagon-enable-branch-prediction", cl::Hidden, cl::init(true), cl::desc("Enable branch prediction")); -static cl::opt<bool> DisableNVSchedule("disable-hexagon-nv-schedule", - cl::Hidden, cl::ZeroOrMore, cl::init(false), - cl::desc("Disable schedule adjustment for new value stores.")); +static cl::opt<bool> DisableNVSchedule( + "disable-hexagon-nv-schedule", cl::Hidden, + cl::desc("Disable schedule adjustment for new value stores.")); static cl::opt<bool> EnableTimingClassLatency( "enable-timing-class-latency", cl::Hidden, cl::init(false), @@ -94,11 +94,12 @@ static cl::opt<bool> EnableACCForwarding( cl::desc("Enable vec acc forwarding")); static cl::opt<bool> BranchRelaxAsmLarge("branch-relax-asm-large", - cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("branch relax asm")); + cl::init(true), cl::Hidden, + cl::desc("branch relax asm")); -static cl::opt<bool> UseDFAHazardRec("dfa-hazard-rec", - cl::init(true), cl::Hidden, cl::ZeroOrMore, - cl::desc("Use the DFA based hazard recognizer.")); +static cl::opt<bool> + UseDFAHazardRec("dfa-hazard-rec", cl::init(true), cl::Hidden, + cl::desc("Use the DFA based hazard recognizer.")); /// Constants for Hexagon instructions. const int Hexagon_MEMW_OFFSET_MAX = 4095; @@ -158,7 +159,7 @@ bool HexagonInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const { auto Op = MI.getOperand(1); // If the instruction has a global address as operand, it is not cheap // since the operand will be constant extended. - if (Op.getType() == MachineOperand::MO_GlobalAddress) + if (Op.isGlobal()) return false; // If the instruction has an operand of size > 16bits, its will be // const-extended and hence, it is not cheap. @@ -1072,6 +1073,43 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { }; switch (Opc) { + case Hexagon::PS_call_instrprof_custom: { + auto Op0 = MI.getOperand(0); + assert(Op0.isGlobal() && + "First operand must be a global containing handler name."); + const GlobalValue *NameVar = Op0.getGlobal(); + const GlobalVariable *GV = dyn_cast<GlobalVariable>(NameVar); + auto *Arr = cast<ConstantDataArray>(GV->getInitializer()); + StringRef NameStr = Arr->isCString() ? Arr->getAsCString() : Arr->getAsString(); + + MachineOperand &Op1 = MI.getOperand(1); + // Set R0 with the imm value to be passed to the custom profiling handler. + BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrsi), Hexagon::R0) + .addImm(Op1.getImm()); + // The call to the custom handler is being treated as a special one as the + // callee is responsible for saving and restoring all the registers + // (including caller saved registers) it needs to modify. This is + // done to reduce the impact of instrumentation on the code being + // instrumented/profiled. + // NOTE: R14, R15 and R28 are reserved for PLT handling. These registers + // are in the Def list of the Hexagon::PS_call_instrprof_custom and + // therefore will be handled appropriately duing register allocation. + + // TODO: It may be a good idea to add a separate pseudo instruction for + // static relocation which doesn't need to reserve r14, r15 and r28. + + auto MIB = BuildMI(MBB, MI, DL, get(Hexagon::J2_call)) + .addUse(Hexagon::R0, RegState::Implicit|RegState::InternalRead) + .addDef(Hexagon::R29, RegState::ImplicitDefine) + .addDef(Hexagon::R30, RegState::ImplicitDefine) + .addDef(Hexagon::R14, RegState::ImplicitDefine) + .addDef(Hexagon::R15, RegState::ImplicitDefine) + .addDef(Hexagon::R28, RegState::ImplicitDefine); + const char *cstr = MF.createExternalSymbolName(NameStr); + MIB.addExternalSymbol(cstr); + MBB.erase(MI); + return true; + } case TargetOpcode::COPY: { MachineOperand &MD = MI.getOperand(0); MachineOperand &MS = MI.getOperand(1); @@ -1392,8 +1430,8 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { // Generate a misaligned load that is guaranteed to cause a crash. class CrashPseudoSourceValue : public PseudoSourceValue { public: - CrashPseudoSourceValue(const TargetInstrInfo &TII) - : PseudoSourceValue(TargetCustom, TII) {} + CrashPseudoSourceValue(const TargetMachine &TM) + : PseudoSourceValue(TargetCustom, TM) {} bool isConstant(const MachineFrameInfo *) const override { return false; @@ -1409,7 +1447,7 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { } }; - static const CrashPseudoSourceValue CrashPSV(*this); + static const CrashPseudoSourceValue CrashPSV(MF.getTarget()); MachineMemOperand *MMO = MF.getMachineMemOperand( MachinePointerInfo(&CrashPSV), MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile, 8, @@ -1662,7 +1700,7 @@ bool HexagonInstrInfo::PredicateInstruction( MI.setDesc(get(PredOpc)); while (unsigned n = MI.getNumOperands()) - MI.RemoveOperand(n-1); + MI.removeOperand(n-1); for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i) MI.addOperand(T->getOperand(i)); @@ -4464,6 +4502,9 @@ unsigned HexagonInstrInfo::getMemAccessSize(const MachineInstr &MI) const { unsigned Size = getMemAccessSizeInBytes(MemAccessSize(S)); if (Size != 0) return Size; + // Y2_dcfetchbo is special + if (MI.getOpcode() == Hexagon::Y2_dcfetchbo) + return HexagonII::DoubleWordAccess; // Handle vector access sizes. const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo(); diff --git a/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp b/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp index ccaf1aac1ce0..2d49fa369642 100644 --- a/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp +++ b/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp @@ -192,10 +192,8 @@ private: void push_back(Value *V) { // Do not push back duplicates. - if (!S.count(V)) { + if (S.insert(V).second) Q.push_back(V); - S.insert(V); - } } Value *pop_front_val() { @@ -1152,9 +1150,8 @@ bool PolynomialMultiplyRecognize::findCycle(Value *Out, Value *In, if (IsPhi && HadPhi) return false; HadPhi |= IsPhi; - if (Cycle.count(I)) + if (!Cycle.insert(I)) return false; - Cycle.insert(I); if (findCycle(I, In, Cycle)) break; Cycle.remove(I); @@ -1487,7 +1484,7 @@ bool PolynomialMultiplyRecognize::convertShiftsToLeft(BasicBlock *LoopB, void PolynomialMultiplyRecognize::cleanupLoopBody(BasicBlock *LoopB) { for (auto &I : *LoopB) - if (Value *SV = SimplifyInstruction(&I, {DL, &TLI, &DT})) + if (Value *SV = simplifyInstruction(&I, {DL, &TLI, &DT})) I.replaceAllUsesWith(SV); for (Instruction &I : llvm::make_early_inc_range(*LoopB)) @@ -2169,7 +2166,7 @@ CleanupAndExit: SCEV::FlagNUW); Value *NumBytes = Expander.expandCodeFor(NumBytesS, IntPtrTy, ExpPt); if (Instruction *In = dyn_cast<Instruction>(NumBytes)) - if (Value *Simp = SimplifyInstruction(In, {*DL, TLI, DT})) + if (Value *Simp = simplifyInstruction(In, {*DL, TLI, DT})) NumBytes = Simp; CallInst *NewCall; @@ -2279,7 +2276,7 @@ CleanupAndExit: Value *NumWords = Expander.expandCodeFor(NumWordsS, Int32Ty, MemmoveB->getTerminator()); if (Instruction *In = dyn_cast<Instruction>(NumWords)) - if (Value *Simp = SimplifyInstruction(In, {*DL, TLI, DT})) + if (Value *Simp = simplifyInstruction(In, {*DL, TLI, DT})) NumWords = Simp; Value *Op0 = (StoreBasePtr->getType() == Int32PtrTy) diff --git a/llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.cpp b/llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.cpp index aabae009d7c3..539db8f55005 100644 --- a/llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.cpp @@ -13,3 +13,9 @@ using namespace llvm; // pin vtable to this file void HexagonMachineFunctionInfo::anchor() {} +MachineFunctionInfo *HexagonMachineFunctionInfo::clone( + BumpPtrAllocator &Allocator, MachineFunction &DestMF, + const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB) + const { + return DestMF.cloneInfo<HexagonMachineFunctionInfo>(*this); +} diff --git a/llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.h b/llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.h index 89ef5c2a891d..a02de24b176a 100644 --- a/llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.h +++ b/llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.h @@ -42,6 +42,10 @@ public: HexagonMachineFunctionInfo() = default; HexagonMachineFunctionInfo(MachineFunction &MF) {} + MachineFunctionInfo * + clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF, + const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB) + const override; unsigned getSRetReturnReg() const { return SRetReturnReg; } void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } diff --git a/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp b/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp index 8edcb745d654..f539717e42d5 100644 --- a/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp +++ b/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp @@ -61,8 +61,7 @@ static cl::opt<int> DbgNVJCount("nvj-count", cl::init(-1), cl::Hidden, "New Value Jump")); static cl::opt<bool> DisableNewValueJumps("disable-nvjump", cl::Hidden, - cl::ZeroOrMore, cl::init(false), - cl::desc("Disable New Value Jumps")); + cl::desc("Disable New Value Jumps")); namespace llvm { diff --git a/llvm/lib/Target/Hexagon/HexagonPatterns.td b/llvm/lib/Target/Hexagon/HexagonPatterns.td index 3abbd896c519..80fbf33d83b7 100644 --- a/llvm/lib/Target/Hexagon/HexagonPatterns.td +++ b/llvm/lib/Target/Hexagon/HexagonPatterns.td @@ -3273,3 +3273,9 @@ let AddedComplexity = 100 in { def: Pat<(i1 (seteq (int_hexagon_S4_stored_locked I32:$Rs, I64:$Rt), 0)), (C2_not (S4_stored_locked I32:$Rs, I64:$Rt))>; } + +def: Pat<(int_hexagon_instrprof_custom (HexagonAtPcrel tglobaladdr:$addr), u32_0ImmPred:$I), + (PS_call_instrprof_custom tglobaladdr:$addr, imm:$I)>; + +def: Pat<(int_hexagon_instrprof_custom (HexagonCONST32 tglobaladdr:$addr), u32_0ImmPred:$I), + (PS_call_instrprof_custom tglobaladdr:$addr, imm:$I)>; diff --git a/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td b/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td index 0a3dff057ccd..6fb1313667a9 100644 --- a/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td +++ b/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td @@ -37,7 +37,7 @@ def SDTHexagonVINSERTW0: SDTypeProfile<1, 2, def HexagonVINSERTW0: SDNode<"HexagonISD::VINSERTW0", SDTHexagonVINSERTW0>; def HwLen2: SDNodeXForm<imm, [{ - const auto &ST = static_cast<const HexagonSubtarget&>(CurDAG->getSubtarget()); + const auto &ST = CurDAG->getSubtarget<HexagonSubtarget>(); return CurDAG->getTargetConstant(ST.getVectorLength()/2, SDLoc(N), MVT::i32); }]>; @@ -92,19 +92,19 @@ def IsVecOff : PatLeaf<(i32 imm), [{ def alignedload: PatFrag<(ops node:$a), (load $a), [{ - return isAlignedMemNode(dyn_cast<MemSDNode>(N)); + return isAlignedMemNode(cast<MemSDNode>(N)); }]>; def unalignedload: PatFrag<(ops node:$a), (load $a), [{ - return !isAlignedMemNode(dyn_cast<MemSDNode>(N)); + return !isAlignedMemNode(cast<MemSDNode>(N)); }]>; def alignedstore: PatFrag<(ops node:$v, node:$a), (store $v, $a), [{ - return isAlignedMemNode(dyn_cast<MemSDNode>(N)); + return isAlignedMemNode(cast<MemSDNode>(N)); }]>; def unalignedstore: PatFrag<(ops node:$v, node:$a), (store $v, $a), [{ - return !isAlignedMemNode(dyn_cast<MemSDNode>(N)); + return !isAlignedMemNode(cast<MemSDNode>(N)); }]>; @@ -738,9 +738,14 @@ let Predicates = [UseHVX] in { def V2Q: OutPatFrag<(ops node:$Vs), (V6_vandvrt $Vs, (A2_tfrsi -1))>; -let Predicates = [UseHVX] in - def: Pat<(select I1:$Pu, VecI1:$Qs, VecI1:$Qt), +let Predicates = [UseHVX] in { + def: Pat<(select I1:$Pu, VecQ8:$Qs, VecQ8:$Qt), + (V2Q (PS_vselect $Pu, (Q2V $Qs), (Q2V $Qt)))>; + def: Pat<(select I1:$Pu, VecQ16:$Qs, VecQ16:$Qt), (V2Q (PS_vselect $Pu, (Q2V $Qs), (Q2V $Qt)))>; + def: Pat<(select I1:$Pu, VecQ32:$Qs, VecQ32:$Qt), + (V2Q (PS_vselect $Pu, (Q2V $Qs), (Q2V $Qt)))>; +} let Predicates = [UseHVX] in { def: Pat<(VecQ8 (qtrue)), (PS_qtrue)>; diff --git a/llvm/lib/Target/Hexagon/HexagonPeephole.cpp b/llvm/lib/Target/Hexagon/HexagonPeephole.cpp index 1ff248200572..ccd90f814813 100644 --- a/llvm/lib/Target/Hexagon/HexagonPeephole.cpp +++ b/llvm/lib/Target/Hexagon/HexagonPeephole.cpp @@ -56,21 +56,21 @@ using namespace llvm; #define DEBUG_TYPE "hexagon-peephole" -static cl::opt<bool> DisableHexagonPeephole("disable-hexagon-peephole", - cl::Hidden, cl::ZeroOrMore, cl::init(false), - cl::desc("Disable Peephole Optimization")); +static cl::opt<bool> + DisableHexagonPeephole("disable-hexagon-peephole", cl::Hidden, + cl::desc("Disable Peephole Optimization")); -static cl::opt<bool> DisablePNotP("disable-hexagon-pnotp", - cl::Hidden, cl::ZeroOrMore, cl::init(false), - cl::desc("Disable Optimization of PNotP")); +static cl::opt<bool> DisablePNotP("disable-hexagon-pnotp", cl::Hidden, + cl::desc("Disable Optimization of PNotP")); -static cl::opt<bool> DisableOptSZExt("disable-hexagon-optszext", - cl::Hidden, cl::ZeroOrMore, cl::init(true), - cl::desc("Disable Optimization of Sign/Zero Extends")); +static cl::opt<bool> + DisableOptSZExt("disable-hexagon-optszext", cl::Hidden, cl::init(true), + cl::desc("Disable Optimization of Sign/Zero Extends")); -static cl::opt<bool> DisableOptExtTo64("disable-hexagon-opt-ext-to-64", - cl::Hidden, cl::ZeroOrMore, cl::init(true), - cl::desc("Disable Optimization of extensions to i64.")); +static cl::opt<bool> + DisableOptExtTo64("disable-hexagon-opt-ext-to-64", cl::Hidden, + cl::init(true), + cl::desc("Disable Optimization of extensions to i64.")); namespace llvm { FunctionPass *createHexagonPeephole(); @@ -208,14 +208,14 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) { // Try to find in the map. if (unsigned PeepholeSrc = PeepholeMap.lookup(SrcReg)) { // Change the 1st operand. - MI.RemoveOperand(1); + MI.removeOperand(1); MI.addOperand(MachineOperand::CreateReg(PeepholeSrc, false)); } else { DenseMap<unsigned, std::pair<unsigned, unsigned> >::iterator DI = PeepholeDoubleRegsMap.find(SrcReg); if (DI != PeepholeDoubleRegsMap.end()) { std::pair<unsigned,unsigned> PeepholeSrc = DI->second; - MI.RemoveOperand(1); + MI.removeOperand(1); MI.addOperand(MachineOperand::CreateReg( PeepholeSrc.first, false /*isDef*/, false /*isImp*/, false /*isKill*/, false /*isDead*/, false /*isUndef*/, diff --git a/llvm/lib/Target/Hexagon/HexagonPseudo.td b/llvm/lib/Target/Hexagon/HexagonPseudo.td index afd63d6d4aa7..7c45568f7734 100644 --- a/llvm/lib/Target/Hexagon/HexagonPseudo.td +++ b/llvm/lib/Target/Hexagon/HexagonPseudo.td @@ -182,6 +182,28 @@ let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, Defs = [PC, R31, R6, R7, P0] in def PS_call_stk : T_Call<"">; +// This pseudo instruction is used to replace int_hexagon_instrprof_custom intrinsic +// with a call to custom handler passed as the first argument to the intrinsic. + +// Pleae Note: +// 1) The call to the custom handler is being treated as a special one as the +// callee is responsible for saving and restoring all the registers it needs +// to modify. This includes caller saved registers as well as r0-r5 argument +// registers. This is done to reduce the impact of instrumentation on the +// code being instrumented/profiled. +// 2) R14, R15 and R28 are reserved for PLT handling and therefore are +// part of the def list. +// 3) R0 is used to pass the unique id associated with an instrumentation site +// to the handler. +// 4) All the other registers (R29, R30, R31, PC) get modified by the call +// instruction. + +// TODO: It may be a good idea to add a separate pseudo instruction for +// static relocation which doesn't need to reserve r14, r15 and r28. + +let hasSideEffects = 1, isCall = 1, Defs = [R0, R14, R15, R28, R29, R30, R31, PC] in +def PS_call_instrprof_custom : Pseudo<(outs), (ins s32_0Imm:$dst, u32_0Imm:$Ii), "">; + // Call, no return. let isCall = 1, hasSideEffects = 1, cofMax1 = 1, isCodeGenOnly = 1 in def PS_callr_nr: InstHexagon<(outs), (ins IntRegs:$Rs), diff --git a/llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp b/llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp index f26e23befde2..fb6918949cce 100644 --- a/llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp +++ b/llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp @@ -201,7 +201,7 @@ void HexagonDCE::removeOperand(NodeAddr<InstrNode*> IA, unsigned OpNum) { for (NodeAddr<RefNode*> RA : Refs) OpMap.insert(std::make_pair(RA.Id, getOpNum(RA.Addr->getOp()))); - MI->RemoveOperand(OpNum); + MI->removeOperand(OpNum); for (NodeAddr<RefNode*> RA : Refs) { unsigned N = OpMap[RA.Id]; diff --git a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp index 6e55bc6b5c2c..f0e56d74fcd1 100644 --- a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp @@ -228,7 +228,7 @@ void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, case Hexagon::PS_fia: MI.setDesc(HII.get(Hexagon::A2_addi)); MI.getOperand(FIOp).ChangeToImmediate(RealOffset); - MI.RemoveOperand(FIOp+1); + MI.removeOperand(FIOp+1); return; case Hexagon::PS_fi: // Set up the instruction for updating below. diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp index bdd2a2cfc5fa..2283d1b7f9c6 100644 --- a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp +++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp @@ -39,45 +39,46 @@ using namespace llvm; #define GET_SUBTARGETINFO_TARGET_DESC #include "HexagonGenSubtargetInfo.inc" -static cl::opt<bool> EnableBSBSched("enable-bsb-sched", - cl::Hidden, cl::ZeroOrMore, cl::init(true)); +static cl::opt<bool> EnableBSBSched("enable-bsb-sched", cl::Hidden, + cl::init(true)); -static cl::opt<bool> EnableTCLatencySched("enable-tc-latency-sched", - cl::Hidden, cl::ZeroOrMore, cl::init(false)); +static cl::opt<bool> EnableTCLatencySched("enable-tc-latency-sched", cl::Hidden, + cl::init(false)); -static cl::opt<bool> EnableDotCurSched("enable-cur-sched", - cl::Hidden, cl::ZeroOrMore, cl::init(true), - cl::desc("Enable the scheduler to generate .cur")); +static cl::opt<bool> + EnableDotCurSched("enable-cur-sched", cl::Hidden, cl::init(true), + cl::desc("Enable the scheduler to generate .cur")); -static cl::opt<bool> DisableHexagonMISched("disable-hexagon-misched", - cl::Hidden, cl::ZeroOrMore, cl::init(false), - cl::desc("Disable Hexagon MI Scheduling")); +static cl::opt<bool> + DisableHexagonMISched("disable-hexagon-misched", cl::Hidden, + cl::desc("Disable Hexagon MI Scheduling")); -static cl::opt<bool> EnableSubregLiveness("hexagon-subreg-liveness", - cl::Hidden, cl::ZeroOrMore, cl::init(true), - cl::desc("Enable subregister liveness tracking for Hexagon")); +static cl::opt<bool> EnableSubregLiveness( + "hexagon-subreg-liveness", cl::Hidden, cl::init(true), + cl::desc("Enable subregister liveness tracking for Hexagon")); -static cl::opt<bool> OverrideLongCalls("hexagon-long-calls", - cl::Hidden, cl::ZeroOrMore, cl::init(false), - cl::desc("If present, forces/disables the use of long calls")); +static cl::opt<bool> OverrideLongCalls( + "hexagon-long-calls", cl::Hidden, + cl::desc("If present, forces/disables the use of long calls")); -static cl::opt<bool> EnablePredicatedCalls("hexagon-pred-calls", - cl::Hidden, cl::ZeroOrMore, cl::init(false), - cl::desc("Consider calls to be predicable")); +static cl::opt<bool> + EnablePredicatedCalls("hexagon-pred-calls", cl::Hidden, + cl::desc("Consider calls to be predicable")); -static cl::opt<bool> SchedPredsCloser("sched-preds-closer", - cl::Hidden, cl::ZeroOrMore, cl::init(true)); +static cl::opt<bool> SchedPredsCloser("sched-preds-closer", cl::Hidden, + cl::init(true)); static cl::opt<bool> SchedRetvalOptimization("sched-retval-optimization", - cl::Hidden, cl::ZeroOrMore, cl::init(true)); + cl::Hidden, cl::init(true)); -static cl::opt<bool> EnableCheckBankConflict("hexagon-check-bank-conflict", - cl::Hidden, cl::ZeroOrMore, cl::init(true), - cl::desc("Enable checking for cache bank conflicts")); +static cl::opt<bool> EnableCheckBankConflict( + "hexagon-check-bank-conflict", cl::Hidden, cl::init(true), + cl::desc("Enable checking for cache bank conflicts")); static cl::opt<bool> EnableV68FloatCodeGen( - "force-hvx-float", cl::Hidden, cl::ZeroOrMore, cl::init(false), - cl::desc("Enable the code-generation for vector float instructions on v68.")); + "force-hvx-float", cl::Hidden, + cl::desc( + "Enable the code-generation for vector float instructions on v68.")); HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM) @@ -95,8 +96,7 @@ HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU, HexagonSubtarget & HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { - Optional<Hexagon::ArchEnum> ArchVer = - Hexagon::GetCpu(Hexagon::CpuTable, CPUString); + Optional<Hexagon::ArchEnum> ArchVer = Hexagon::getCpu(CPUString); if (ArchVer) HexagonArchVersion = *ArchVer; else diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.h b/llvm/lib/Target/Hexagon/HexagonSubtarget.h index db682676cf12..f6c70928c2f6 100644 --- a/llvm/lib/Target/Hexagon/HexagonSubtarget.h +++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.h @@ -13,7 +13,7 @@ #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H #define LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H -#include "HexagonArch.h" +#include "HexagonDepArch.h" #include "HexagonFrameLowering.h" #include "HexagonISelLowering.h" #include "HexagonInstrInfo.h" diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp index c6703bb8a62a..4e04939e6690 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -32,41 +32,44 @@ using namespace llvm; -static cl::opt<bool> EnableCExtOpt("hexagon-cext", cl::Hidden, cl::ZeroOrMore, - cl::init(true), cl::desc("Enable Hexagon constant-extender optimization")); +static cl::opt<bool> + EnableCExtOpt("hexagon-cext", cl::Hidden, cl::init(true), + cl::desc("Enable Hexagon constant-extender optimization")); -static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore, - cl::init(true), cl::desc("Enable RDF-based optimizations")); +static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::init(true), + cl::desc("Enable RDF-based optimizations")); static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops", cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target")); -static cl::opt<bool> DisableAModeOpt("disable-hexagon-amodeopt", - cl::Hidden, cl::ZeroOrMore, cl::init(false), - cl::desc("Disable Hexagon Addressing Mode Optimization")); +static cl::opt<bool> + DisableAModeOpt("disable-hexagon-amodeopt", cl::Hidden, + cl::desc("Disable Hexagon Addressing Mode Optimization")); -static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt", - cl::Hidden, cl::ZeroOrMore, cl::init(false), - cl::desc("Disable Hexagon CFG Optimization")); +static cl::opt<bool> + DisableHexagonCFGOpt("disable-hexagon-cfgopt", cl::Hidden, + cl::desc("Disable Hexagon CFG Optimization")); -static cl::opt<bool> DisableHCP("disable-hcp", cl::init(false), cl::Hidden, - cl::ZeroOrMore, cl::desc("Disable Hexagon constant propagation")); +static cl::opt<bool> + DisableHCP("disable-hcp", cl::Hidden, + cl::desc("Disable Hexagon constant propagation")); static cl::opt<bool> DisableStoreWidening("disable-store-widen", cl::Hidden, cl::init(false), cl::desc("Disable store widening")); static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets", - cl::init(true), cl::Hidden, cl::ZeroOrMore, - cl::desc("Early expansion of MUX")); + cl::init(true), cl::Hidden, + cl::desc("Early expansion of MUX")); static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden, - cl::ZeroOrMore, cl::desc("Enable early if-conversion")); + cl::desc("Enable early if-conversion")); static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true), cl::Hidden, cl::desc("Generate \"insert\" instructions")); -static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true), - cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions")); +static cl::opt<bool> + EnableCommGEP("hexagon-commgep", cl::init(true), cl::Hidden, + cl::desc("Enable commoning of GEP instructions")); static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true), cl::Hidden, cl::desc("Generate \"extract\" instructions")); @@ -78,9 +81,9 @@ static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true), cl::Hidden, cl::desc("Enable conversion of arithmetic operations to " "predicate instructions")); -static cl::opt<bool> EnableLoopPrefetch("hexagon-loop-prefetch", - cl::init(false), cl::Hidden, cl::ZeroOrMore, - cl::desc("Enable loop data prefetch on Hexagon")); +static cl::opt<bool> + EnableLoopPrefetch("hexagon-loop-prefetch", cl::Hidden, + cl::desc("Enable loop data prefetch on Hexagon")); static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden, cl::desc("Disable splitting double registers")); @@ -94,22 +97,24 @@ static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true), static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false), cl::Hidden, cl::desc("Disable backend optimizations")); -static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print", - cl::Hidden, cl::ZeroOrMore, cl::init(false), - cl::desc("Enable Hexagon Vector print instr pass")); +static cl::opt<bool> + EnableVectorPrint("enable-hexagon-vector-print", cl::Hidden, + cl::desc("Enable Hexagon Vector print instr pass")); -static cl::opt<bool> EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden, - cl::ZeroOrMore, cl::init(true), cl::desc("Enable vextract optimization")); +static cl::opt<bool> + EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden, cl::init(true), + cl::desc("Enable vextract optimization")); -static cl::opt<bool> EnableVectorCombine("hexagon-vector-combine", cl::Hidden, - cl::ZeroOrMore, cl::init(true), cl::desc("Enable HVX vector combining")); +static cl::opt<bool> + EnableVectorCombine("hexagon-vector-combine", cl::Hidden, cl::init(true), + cl::desc("Enable HVX vector combining")); -static cl::opt<bool> EnableInitialCFGCleanup("hexagon-initial-cfg-cleanup", - cl::Hidden, cl::ZeroOrMore, cl::init(true), - cl::desc("Simplify the CFG after atomic expansion pass")); +static cl::opt<bool> EnableInitialCFGCleanup( + "hexagon-initial-cfg-cleanup", cl::Hidden, cl::init(true), + cl::desc("Simplify the CFG after atomic expansion pass")); static cl::opt<bool> EnableInstSimplify("hexagon-instsimplify", cl::Hidden, - cl::ZeroOrMore, cl::init(true), + cl::init(true), cl::desc("Enable instsimplify")); /// HexagonTargetMachineModule - Note that this is used on hosts that @@ -189,7 +194,7 @@ namespace llvm { } // end namespace llvm; static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { - return RM.getValueOr(Reloc::Static); + return RM.value_or(Reloc::Static); } extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTarget() { @@ -293,12 +298,11 @@ void HexagonTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) { } TargetTransformInfo -HexagonTargetMachine::getTargetTransformInfo(const Function &F) { +HexagonTargetMachine::getTargetTransformInfo(const Function &F) const { return TargetTransformInfo(HexagonTTIImpl(this, F)); } - -HexagonTargetMachine::~HexagonTargetMachine() {} +HexagonTargetMachine::~HexagonTargetMachine() = default; namespace { /// Hexagon Code Generator Pass Configuration Options. @@ -345,6 +349,7 @@ void HexagonPassConfig::addIRPasses() { if (EnableInitialCFGCleanup) addPass(createCFGSimplificationPass(SimplifyCFGOptions() .forwardSwitchCondToPhi(true) + .convertSwitchRangeToICmp(true) .convertSwitchToLookupTable(true) .needCanonicalLoops(false) .hoistCommonInsts(true) diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.h b/llvm/lib/Target/Hexagon/HexagonTargetMachine.h index 66679df93bd3..947df7574ab3 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.h +++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.h @@ -39,7 +39,7 @@ public: void adjustPassManager(PassManagerBuilder &PMB) override; void registerPassBuilderCallbacks(PassBuilder &PB) override; TargetPassConfig *createPassConfig(PassManagerBase &PM) override; - TargetTransformInfo getTargetTransformInfo(const Function &F) override; + TargetTransformInfo getTargetTransformInfo(const Function &F) const override; HexagonTargetObjectFile *getObjFileLowering() const override { return static_cast<HexagonTargetObjectFile*>(TLOF.get()); diff --git a/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp b/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp index 7df32e4072e3..c83ed16f0272 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp +++ b/llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp @@ -41,9 +41,9 @@ static cl::opt<unsigned> SmallDataThreshold("hexagon-small-data-threshold", static cl::opt<bool> NoSmallDataSorting("mno-sort-sda", cl::init(false), cl::Hidden, cl::desc("Disable small data sections sorting")); -static cl::opt<bool> StaticsInSData("hexagon-statics-in-small-data", - cl::init(false), cl::Hidden, cl::ZeroOrMore, - cl::desc("Allow static variables in .sdata")); +static cl::opt<bool> + StaticsInSData("hexagon-statics-in-small-data", cl::Hidden, + cl::desc("Allow static variables in .sdata")); static cl::opt<bool> TraceGVPlacement("trace-gv-placement", cl::Hidden, cl::init(false), @@ -332,6 +332,7 @@ unsigned HexagonTargetObjectFile::getSmallestAddressableSize(const Type *Ty, case Type::X86_MMXTyID: case Type::X86_AMXTyID: case Type::TokenTyID: + case Type::DXILPointerTyID: return 0; } diff --git a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp index 1bdd8c3c513a..bb0aaa3150fb 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp @@ -223,7 +223,8 @@ HexagonTTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *Src, InstructionCost HexagonTTIImpl::getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, ArrayRef<int> Mask, int Index, - Type *SubTp) { + Type *SubTp, + ArrayRef<const Value *> Args) { return 1; } diff --git a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h index 9e637dfc3e16..7bbaf7ae9cb2 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h +++ b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h @@ -86,12 +86,11 @@ public: unsigned getMinVectorRegisterBitWidth() const; ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const; - bool shouldMaximizeVectorBandwidth() const { + bool + shouldMaximizeVectorBandwidth(TargetTransformInfo::RegisterKind K) const { return true; } - bool supportsEfficientVectorElementLoadStore() { - return false; - } + bool supportsEfficientVectorElementLoadStore() { return false; } bool hasBranchDivergence() { return false; } @@ -125,7 +124,8 @@ public: Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind); InstructionCost getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, - ArrayRef<int> Mask, int Index, Type *SubTp); + ArrayRef<int> Mask, int Index, Type *SubTp, + ArrayRef<const Value *> Args = None); InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, diff --git a/llvm/lib/Target/Hexagon/HexagonVExtract.cpp b/llvm/lib/Target/Hexagon/HexagonVExtract.cpp index b5f06ebd3189..845fa1e49578 100644 --- a/llvm/lib/Target/Hexagon/HexagonVExtract.cpp +++ b/llvm/lib/Target/Hexagon/HexagonVExtract.cpp @@ -27,9 +27,9 @@ using namespace llvm; -static cl::opt<unsigned> VExtractThreshold("hexagon-vextract-threshold", - cl::Hidden, cl::ZeroOrMore, cl::init(1), - cl::desc("Threshold for triggering vextract replacement")); +static cl::opt<unsigned> VExtractThreshold( + "hexagon-vextract-threshold", cl::Hidden, cl::init(1), + cl::desc("Threshold for triggering vextract replacement")); namespace llvm { void initializeHexagonVExtractPass(PassRegistry& Registry); @@ -106,8 +106,7 @@ bool HexagonVExtract::runOnMachineFunction(MachineFunction &MF) { MachineFrameInfo &MFI = MF.getFrameInfo(); Register AR = MF.getInfo<HexagonMachineFunctionInfo>()->getStackAlignBaseVReg(); - std::map<unsigned, SmallVector<MachineInstr*,4>> VExtractMap; - MaybeAlign MaxAlign; + std::map<unsigned, SmallVector<MachineInstr *, 4>> VExtractMap; bool Changed = false; for (MachineBasicBlock &MBB : MF) { @@ -131,6 +130,7 @@ bool HexagonVExtract::runOnMachineFunction(MachineFunction &MF) { return AddrR; }; + MaybeAlign MaxAlign; for (auto &P : VExtractMap) { unsigned VecR = P.first; if (P.second.size() <= VExtractThreshold) @@ -138,7 +138,7 @@ bool HexagonVExtract::runOnMachineFunction(MachineFunction &MF) { const auto &VecRC = *MRI.getRegClass(VecR); Align Alignment = HRI.getSpillAlign(VecRC); - MaxAlign = max(MaxAlign, Alignment); + MaxAlign = std::max(MaxAlign.valueOrOne(), Alignment); // Make sure this is not a spill slot: spill slots cannot be aligned // if there are variable-sized objects on the stack. They must be // accessible via FP (which is not aligned), because SP is unknown, diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp index e9b658d18175..54d33a4113e7 100644 --- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp +++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp @@ -55,24 +55,25 @@ using namespace llvm; #define DEBUG_TYPE "packets" -static cl::opt<bool> DisablePacketizer("disable-packetizer", cl::Hidden, - cl::ZeroOrMore, cl::init(false), - cl::desc("Disable Hexagon packetizer pass")); +static cl::opt<bool> + DisablePacketizer("disable-packetizer", cl::Hidden, + cl::desc("Disable Hexagon packetizer pass")); static cl::opt<bool> Slot1Store("slot1-store-slot0-load", cl::Hidden, - cl::ZeroOrMore, cl::init(true), + cl::init(true), cl::desc("Allow slot1 store and slot0 load")); -static cl::opt<bool> PacketizeVolatiles("hexagon-packetize-volatiles", - cl::ZeroOrMore, cl::Hidden, cl::init(true), - cl::desc("Allow non-solo packetization of volatile memory references")); +static cl::opt<bool> PacketizeVolatiles( + "hexagon-packetize-volatiles", cl::Hidden, cl::init(true), + cl::desc("Allow non-solo packetization of volatile memory references")); -static cl::opt<bool> EnableGenAllInsnClass("enable-gen-insn", cl::init(false), - cl::Hidden, cl::ZeroOrMore, cl::desc("Generate all instruction with TC")); +static cl::opt<bool> + EnableGenAllInsnClass("enable-gen-insn", cl::Hidden, + cl::desc("Generate all instruction with TC")); -static cl::opt<bool> DisableVecDblNVStores("disable-vecdbl-nv-stores", - cl::init(false), cl::Hidden, cl::ZeroOrMore, - cl::desc("Disable vector double new-value-stores")); +static cl::opt<bool> + DisableVecDblNVStores("disable-vecdbl-nv-stores", cl::Hidden, + cl::desc("Disable vector double new-value-stores")); extern cl::opt<bool> ScheduleInlineAsm; diff --git a/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp b/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp index 6aca8d807872..abd84a188cfa 100644 --- a/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp +++ b/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp @@ -1310,7 +1310,7 @@ auto HexagonVectorCombine::calculatePointerDifference(Value *Ptr0, auto Simplify = [&](Value *V) { if (auto *I = dyn_cast<Instruction>(V)) { SimplifyQuery Q(DL, &TLI, &DT, &AC, I); - if (Value *S = SimplifyInstruction(I, Q)) + if (Value *S = simplifyInstruction(I, Q)) return S; } return V; @@ -1404,7 +1404,7 @@ auto HexagonVectorCombine::isSafeToMoveBeforeInBB(const Instruction &In, if (isa<PHINode>(In) || (To != Block.end() && isa<PHINode>(*To))) return false; - if (!mayBeMemoryDependent(In)) + if (!mayHaveNonDefUseDependency(In)) return true; bool MayWrite = In.mayWriteToMemory(); auto MaybeLoc = getLocOrNone(In); diff --git a/llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp b/llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp index 94b878e21f4d..2b004a9c5ad4 100644 --- a/llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp +++ b/llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp @@ -53,10 +53,10 @@ using namespace llvm; STATISTIC(HexagonNumVectorLoopCarriedReuse, "Number of values that were reused from a previous iteration."); -static cl::opt<int> HexagonVLCRIterationLim("hexagon-vlcr-iteration-lim", - cl::Hidden, +static cl::opt<int> HexagonVLCRIterationLim( + "hexagon-vlcr-iteration-lim", cl::Hidden, cl::desc("Maximum distance of loop carried dependences that are handled"), - cl::init(2), cl::ZeroOrMore); + cl::init(2)); namespace llvm { diff --git a/llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.h b/llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.h index f1e0c5804ace..f826b2eb568f 100644 --- a/llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.h +++ b/llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.h @@ -127,7 +127,7 @@ class Loop; /// Hexagon Vector Loop Carried Reuse Pass struct HexagonVectorLoopCarriedReusePass : public PassInfoMixin<HexagonVectorLoopCarriedReusePass> { - HexagonVectorLoopCarriedReusePass() {} + HexagonVectorLoopCarriedReusePass() = default; /// Run pass over the Loop. PreservedAnalyses run(Loop &L, LoopAnalysisManager &LAM, diff --git a/llvm/lib/Target/Hexagon/HexagonVectorPrint.cpp b/llvm/lib/Target/Hexagon/HexagonVectorPrint.cpp index fbc5e5c344ed..b09a393f7dd5 100644 --- a/llvm/lib/Target/Hexagon/HexagonVectorPrint.cpp +++ b/llvm/lib/Target/Hexagon/HexagonVectorPrint.cpp @@ -36,9 +36,9 @@ using namespace llvm; #define DEBUG_TYPE "hexagon-vector-print" -static cl::opt<bool> TraceHexVectorStoresOnly("trace-hex-vector-stores-only", - cl::Hidden, cl::ZeroOrMore, cl::init(false), - cl::desc("Enables tracing of vector stores")); +static cl::opt<bool> + TraceHexVectorStoresOnly("trace-hex-vector-stores-only", cl::Hidden, + cl::desc("Enables tracing of vector stores")); namespace llvm { diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp index 5e5a26fea076..37866a73ed0f 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp @@ -21,6 +21,7 @@ #include "llvm/MC/MCFixupKindInfo.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCObjectWriter.h" +#include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/TargetRegistry.h" #include "llvm/Support/Debug.h" #include "llvm/Support/EndianStream.h" diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp index e5e5d08937ef..f3da67562320 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp @@ -34,5 +34,4 @@ HexagonMCAsmInfo::HexagonMCAsmInfo(const Triple &TT) { UsesELFSectionDirectiveForBSS = true; ExceptionsType = ExceptionHandling::DwarfCFI; UseLogicalShr = false; - UseIntegratedAssembler = false; } diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp index 8a866cfe9161..18ff901d6441 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp @@ -22,6 +22,7 @@ #include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstrDesc.h" #include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCSubtargetInfo.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/SourceMgr.h" #include <cassert> @@ -29,8 +30,8 @@ using namespace llvm; static cl::opt<bool> - RelaxNVChecks("relax-nv-checks", cl::init(false), cl::ZeroOrMore, - cl::Hidden, cl::desc("Relax checks of new-value validity")); + RelaxNVChecks("relax-nv-checks", cl::Hidden, + cl::desc("Relax checks of new-value validity")); const HexagonMCChecker::PredSense HexagonMCChecker::Unconditional(Hexagon::NoRegister, false); diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp index f8ac35aed7c0..ed2856eb1fe9 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp @@ -789,7 +789,6 @@ HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO, } MCCodeEmitter *llvm::createHexagonMCCodeEmitter(MCInstrInfo const &MII, - MCRegisterInfo const &MRI, MCContext &MCT) { return new HexagonMCCodeEmitter(MII, MCT); } diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp index 0624214d284b..49725801f046 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp @@ -108,7 +108,7 @@ void HexagonMCELFStreamer::HexagonMCEmitCommonSymbol(MCSymbol *Symbol, MCSection &Section = *getAssembler().getContext().getELFSection( SectionName, ELF::SHT_NOBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC); MCSectionSubPair P = getCurrentSection(); - SwitchSection(&Section); + switchSection(&Section); if (ELFSymbol->isUndefined()) { emitValueToAlignment(ByteAlignment, 0, 1, 0); @@ -120,7 +120,7 @@ void HexagonMCELFStreamer::HexagonMCEmitCommonSymbol(MCSymbol *Symbol, if (Align(ByteAlignment) > Section.getAlignment()) Section.setAlignment(Align(ByteAlignment)); - SwitchSection(P.first, P.second); + switchSection(P.first, P.second); } else { if (ELFSymbol->declareCommon(Size, ByteAlignment)) report_fatal_error("Symbol: " + Symbol->getName() + diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.cpp index 1e708ba1bcd3..ab5e9eb4eca6 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.cpp @@ -13,6 +13,7 @@ #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSymbolELF.h" #include "llvm/MC/MCValue.h" +#include "llvm/Support/Casting.h" #include "llvm/Support/raw_ostream.h" using namespace llvm; diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp index 6a08d7503bac..d068baf05998 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp @@ -11,7 +11,7 @@ //===----------------------------------------------------------------------===// #include "MCTargetDesc/HexagonMCTargetDesc.h" -#include "HexagonArch.h" +#include "HexagonDepArch.h" #include "HexagonTargetStreamer.h" #include "MCTargetDesc/HexagonInstPrinter.h" #include "MCTargetDesc/HexagonMCAsmInfo.h" @@ -22,6 +22,7 @@ #include "llvm/ADT/StringRef.h" #include "llvm/BinaryFormat/ELF.h" #include "llvm/MC/MCAsmBackend.h" +#include "llvm/MC/MCAssembler.h" #include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCDwarf.h" @@ -409,8 +410,8 @@ std::string selectHexagonFS(StringRef CPU, StringRef FS) { } } -static bool isCPUValid(const std::string &CPU) { - return Hexagon::CpuTable.find(CPU) != Hexagon::CpuTable.cend(); +static bool isCPUValid(StringRef CPU) { + return Hexagon::getCpu(CPU).has_value(); } namespace { @@ -559,12 +560,18 @@ void Hexagon_MC::addArchSubtarget(MCSubtargetInfo const *STI, } unsigned Hexagon_MC::GetELFFlags(const MCSubtargetInfo &STI) { - using llvm::Hexagon::ElfFlagsByCpuStr; - - const std::string CPU(STI.getCPU().str()); - auto F = ElfFlagsByCpuStr.find(CPU); - assert(F != ElfFlagsByCpuStr.end() && "Unrecognized Architecture"); - return F->second; + return StringSwitch<unsigned>(STI.getCPU()) + .Case("generic", llvm::ELF::EF_HEXAGON_MACH_V5) + .Case("hexagonv5", llvm::ELF::EF_HEXAGON_MACH_V5) + .Case("hexagonv55", llvm::ELF::EF_HEXAGON_MACH_V55) + .Case("hexagonv60", llvm::ELF::EF_HEXAGON_MACH_V60) + .Case("hexagonv62", llvm::ELF::EF_HEXAGON_MACH_V62) + .Case("hexagonv65", llvm::ELF::EF_HEXAGON_MACH_V65) + .Case("hexagonv66", llvm::ELF::EF_HEXAGON_MACH_V66) + .Case("hexagonv67", llvm::ELF::EF_HEXAGON_MACH_V67) + .Case("hexagonv67t", llvm::ELF::EF_HEXAGON_MACH_V67T) + .Case("hexagonv68", llvm::ELF::EF_HEXAGON_MACH_V68) + .Case("hexagonv69", llvm::ELF::EF_HEXAGON_MACH_V69); } llvm::ArrayRef<MCPhysReg> Hexagon_MC::GetVectRegRev() { diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h index 5bf7c9a1a908..d717e710f3c0 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h @@ -85,7 +85,6 @@ namespace Hexagon_MC { } MCCodeEmitter *createHexagonMCCodeEmitter(const MCInstrInfo &MCII, - const MCRegisterInfo &MRI, MCContext &MCT); MCAsmBackend *createHexagonAsmBackend(const Target &T, diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp index d82731e153fe..c8805296017d 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp @@ -295,7 +295,7 @@ void HexagonShuffler::restrictBranchOrder(HexagonPacketSummary const &Summary) { Summary.branchInsts[0]->Core.setUnits(jumpSlot.first); Summary.branchInsts[1]->Core.setUnits(jumpSlot.second); - const bool HasShuffledPacket = tryAuction(Summary).hasValue(); + const bool HasShuffledPacket = tryAuction(Summary).has_value(); if (HasShuffledPacket) return; @@ -599,7 +599,7 @@ void HexagonShuffler::restrictPreferSlot3(HexagonPacketSummary const &Summary, // and then pin it to slot #3 const unsigned saveUnits = PrefSlot3Inst->Core.getUnits(); PrefSlot3Inst->Core.setUnits(saveUnits & Slot3Mask); - const bool HasShuffledPacket = tryAuction(Summary).hasValue(); + const bool HasShuffledPacket = tryAuction(Summary).has_value(); if (HasShuffledPacket) return; |