diff options
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCInstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 91 |
1 files changed, 66 insertions, 25 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index eada872c2a7d..59486c323567 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -2218,7 +2218,7 @@ bool PPCInstrInfo::PredicateInstruction(MachineInstr &MI, .addReg(Pred[1].getReg(), RegState::ImplicitDefine); } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) { MachineBasicBlock *MBB = MI.getOperand(0).getMBB(); - MI.RemoveOperand(0); + MI.removeOperand(0); MI.setDesc(get(PPC::BC)); MachineInstrBuilder(*MI.getParent()->getParent(), MI) @@ -2226,7 +2226,7 @@ bool PPCInstrInfo::PredicateInstruction(MachineInstr &MI, .addMBB(MBB); } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) { MachineBasicBlock *MBB = MI.getOperand(0).getMBB(); - MI.RemoveOperand(0); + MI.removeOperand(0); MI.setDesc(get(PPC::BCn)); MachineInstrBuilder(*MI.getParent()->getParent(), MI) @@ -2234,7 +2234,7 @@ bool PPCInstrInfo::PredicateInstruction(MachineInstr &MI, .addMBB(MBB); } else { MachineBasicBlock *MBB = MI.getOperand(0).getMBB(); - MI.RemoveOperand(0); + MI.removeOperand(0); MI.setDesc(get(PPC::BCC)); MachineInstrBuilder(*MI.getParent()->getParent(), MI) @@ -2714,8 +2714,8 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, } // If we've set the mask, we can transform. if (Mask != ~0LLU) { - MI->RemoveOperand(4); - MI->RemoveOperand(3); + MI->removeOperand(4); + MI->removeOperand(3); MI->getOperand(2).setImm(Mask); NumRcRotatesConvertedToRcAnd++; } @@ -2724,7 +2724,7 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, if (MB >= 48) { uint64_t Mask = (1LLU << (63 - MB + 1)) - 1; NewOpC = PPC::ANDI8_rec; - MI->RemoveOperand(3); + MI->removeOperand(3); MI->getOperand(2).setImm(Mask); NumRcRotatesConvertedToRcAnd++; } @@ -3026,8 +3026,8 @@ bool PPCInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { } case PPC::KILL_PAIR: { MI.setDesc(get(PPC::UNENCODED_NOP)); - MI.RemoveOperand(1); - MI.RemoveOperand(0); + MI.removeOperand(1); + MI.removeOperand(0); return true; } case TargetOpcode::LOAD_STACK_GUARD: { @@ -3122,7 +3122,7 @@ bool PPCInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { .addReg(PPC::CR7) .addImm(1); MI.setDesc(get(PPC::ISYNC)); - MI.RemoveOperand(0); + MI.removeOperand(0); return true; } } @@ -3188,7 +3188,7 @@ void PPCInstrInfo::replaceInstrOperandWithImm(MachineInstr &MI, // - implicit reg uses // Therefore, removing the implicit operand won't change the explicit // operands layout. - MI.RemoveOperand(UseOpIdx); + MI.removeOperand(UseOpIdx); } } @@ -3199,7 +3199,7 @@ void PPCInstrInfo::replaceInstrWithLI(MachineInstr &MI, // Remove existing operands. int OperandToKeep = LII.SetCR ? 1 : 0; for (int i = MI.getNumOperands() - 1; i > OperandToKeep; i--) - MI.RemoveOperand(i); + MI.removeOperand(i); // Replace the instruction. if (LII.SetCR) { @@ -3234,6 +3234,47 @@ MachineInstr *PPCInstrInfo::getDefMIPostRA(unsigned Reg, MachineInstr &MI, return nullptr; } +void PPCInstrInfo::materializeImmPostRA(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + const DebugLoc &DL, Register Reg, + int64_t Imm) const { + assert(!MBB.getParent()->getRegInfo().isSSA() && + "Register should be in non-SSA form after RA"); + bool isPPC64 = Subtarget.isPPC64(); + // FIXME: Materialization here is not optimal. + // For some special bit patterns we can use less instructions. + // See `selectI64ImmDirect` in PPCISelDAGToDAG.cpp. + if (isInt<16>(Imm)) { + BuildMI(MBB, MBBI, DL, get(isPPC64 ? PPC::LI8 : PPC::LI), Reg).addImm(Imm); + } else if (isInt<32>(Imm)) { + BuildMI(MBB, MBBI, DL, get(isPPC64 ? PPC::LIS8 : PPC::LIS), Reg) + .addImm(Imm >> 16); + if (Imm & 0xFFFF) + BuildMI(MBB, MBBI, DL, get(isPPC64 ? PPC::ORI8 : PPC::ORI), Reg) + .addReg(Reg, RegState::Kill) + .addImm(Imm & 0xFFFF); + } else { + assert(isPPC64 && "Materializing 64-bit immediate to single register is " + "only supported in PPC64"); + BuildMI(MBB, MBBI, DL, get(PPC::LIS8), Reg).addImm(Imm >> 48); + if ((Imm >> 32) & 0xFFFF) + BuildMI(MBB, MBBI, DL, get(PPC::ORI8), Reg) + .addReg(Reg, RegState::Kill) + .addImm((Imm >> 32) & 0xFFFF); + BuildMI(MBB, MBBI, DL, get(PPC::RLDICR), Reg) + .addReg(Reg, RegState::Kill) + .addImm(32) + .addImm(31); + BuildMI(MBB, MBBI, DL, get(PPC::ORIS8), Reg) + .addReg(Reg, RegState::Kill) + .addImm((Imm >> 16) & 0xFFFF); + if (Imm & 0xFFFF) + BuildMI(MBB, MBBI, DL, get(PPC::ORI8), Reg) + .addReg(Reg, RegState::Kill) + .addImm(Imm & 0xFFFF); + } +} + MachineInstr *PPCInstrInfo::getForwardingDefMI( MachineInstr &MI, unsigned &OpNoForForwarding, @@ -3790,15 +3831,15 @@ bool PPCInstrInfo::combineRLWINM(MachineInstr &MI, if (MI.getOpcode() == PPC::RLWINM || MI.getOpcode() == PPC::RLWINM8) { // Replace MI with "LI 0" - MI.RemoveOperand(4); - MI.RemoveOperand(3); - MI.RemoveOperand(2); + MI.removeOperand(4); + MI.removeOperand(3); + MI.removeOperand(2); MI.getOperand(1).ChangeToImmediate(0); MI.setDesc(get(Is64Bit ? PPC::LI8 : PPC::LI)); } else { // Replace MI with "ANDI_rec reg, 0" - MI.RemoveOperand(4); - MI.RemoveOperand(3); + MI.removeOperand(4); + MI.removeOperand(3); MI.getOperand(2).setImm(0); MI.setDesc(get(Is64Bit ? PPC::ANDI8_rec : PPC::ANDI_rec)); MI.getOperand(1).setReg(SrcMI->getOperand(1).getReg()); @@ -4282,8 +4323,8 @@ static void swapMIOperands(MachineInstr &MI, unsigned Op1, unsigned Op2) { unsigned MinOp = std::min(Op1, Op2); MachineOperand MOp1 = MI.getOperand(MinOp); MachineOperand MOp2 = MI.getOperand(MaxOp); - MI.RemoveOperand(std::max(Op1, Op2)); - MI.RemoveOperand(std::min(Op1, Op2)); + MI.removeOperand(std::max(Op1, Op2)); + MI.removeOperand(std::min(Op1, Op2)); // If the operands we are swapping are the two at the end (the common case) // we can just remove both and add them in the opposite order. @@ -4297,7 +4338,7 @@ static void swapMIOperands(MachineInstr &MI, unsigned Op1, unsigned Op2) { unsigned TotalOps = MI.getNumOperands() + 2; // We've already removed 2 ops. for (unsigned i = MI.getNumOperands() - 1; i >= MinOp; i--) { MOps.push_back(MI.getOperand(i)); - MI.RemoveOperand(i); + MI.removeOperand(i); } // MOp2 needs to be added next. MI.addOperand(MOp2); @@ -4532,8 +4573,8 @@ bool PPCInstrInfo::simplifyToLI(MachineInstr &MI, MachineInstr &DefMI, if (RegToCopy == PPC::ZERO || RegToCopy == PPC::ZERO8) { CompareUseMI.setDesc(get(UseOpc == PPC::ISEL8 ? PPC::LI8 : PPC::LI)); replaceInstrOperandWithImm(CompareUseMI, 1, 0); - CompareUseMI.RemoveOperand(3); - CompareUseMI.RemoveOperand(2); + CompareUseMI.removeOperand(3); + CompareUseMI.removeOperand(2); continue; } LLVM_DEBUG( @@ -4542,8 +4583,8 @@ bool PPCInstrInfo::simplifyToLI(MachineInstr &MI, MachineInstr &DefMI, LLVM_DEBUG(dbgs() << "Is converted to:\n"); // Convert to copy and remove unneeded operands. CompareUseMI.setDesc(get(PPC::COPY)); - CompareUseMI.RemoveOperand(3); - CompareUseMI.RemoveOperand(RegToCopy == TrueReg ? 2 : 1); + CompareUseMI.removeOperand(3); + CompareUseMI.removeOperand(RegToCopy == TrueReg ? 2 : 1); CmpIselsConverted++; Changed = true; LLVM_DEBUG(CompareUseMI.dump()); @@ -4887,7 +4928,7 @@ bool PPCInstrInfo::transformToImmFormFedByAdd( SmallVector<MachineOperand, 2> MOps; for (unsigned i = MI.getNumOperands() - 1; i >= III.ZeroIsSpecialOrig; i--) { MOps.push_back(MI.getOperand(i)); - MI.RemoveOperand(i); + MI.removeOperand(i); } // Remove the last MO in the list, which is ZERO operand in fact. @@ -5010,7 +5051,7 @@ bool PPCInstrInfo::transformToImmFormFedByLI(MachineInstr &MI, // just convert this to a COPY. Can't do this post-RA since we've already // cleaned up the copies. else if (!SetCR && ShAmt == 0 && !PostRA) { - MI.RemoveOperand(2); + MI.removeOperand(2); MI.setDesc(get(PPC::COPY)); } else { // The 32 bit and 64 bit instructions are quite different. |