diff options
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCV.td')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCV.td | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td index 82afa13aece3..770e883221d1 100644 --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -92,10 +92,13 @@ include "RISCVSystemOperands.td" // Registers, calling conventions, instruction descriptions. //===----------------------------------------------------------------------===// +include "RISCVSchedule.td" include "RISCVRegisterInfo.td" include "RISCVCallingConv.td" include "RISCVInstrInfo.td" include "RISCVRegisterBanks.td" +include "RISCVSchedRocket32.td" +include "RISCVSchedRocket64.td" //===----------------------------------------------------------------------===// // RISC-V processors supported. @@ -106,6 +109,12 @@ def : ProcessorModel<"generic-rv32", NoSchedModel, [FeatureRVCHints]>; def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit, FeatureRVCHints]>; +def : ProcessorModel<"rocket-rv32", Rocket32Model, [FeatureRVCHints]>; + +def : ProcessorModel<"rocket-rv64", Rocket64Model, [Feature64Bit, + FeatureRVCHints]>; + + //===----------------------------------------------------------------------===// // Define the RISC-V target. //===----------------------------------------------------------------------===// |