diff options
Diffstat (limited to 'llvm/lib/Target/VE/VVPInstrInfo.td')
| -rw-r--r-- | llvm/lib/Target/VE/VVPInstrInfo.td | 111 |
1 files changed, 109 insertions, 2 deletions
diff --git a/llvm/lib/Target/VE/VVPInstrInfo.td b/llvm/lib/Target/VE/VVPInstrInfo.td index ef9c238066c0..a4e4984e3d12 100644 --- a/llvm/lib/Target/VE/VVPInstrInfo.td +++ b/llvm/lib/Target/VE/VVPInstrInfo.td @@ -18,7 +18,40 @@ // TODO explain how VVP nodes relate to VP SDNodes once VP ISel is uptream. //===----------------------------------------------------------------------===// -// Binary Operators { +// vvp_load(ptr, stride, mask, avl) +def SDTLoadVVP : SDTypeProfile<1, 4, [ + SDTCisVec<0>, + SDTCisPtrTy<1>, + SDTCisInt<2>, + SDTCisVec<3>, + IsVLVT<4> +]>; + +// vvp_store(data, ptr, stride, mask, avl) +def SDTStoreVVP: SDTypeProfile<0, 5, [ + SDTCisVec<0>, + SDTCisPtrTy<1>, + SDTCisInt<2>, + SDTCisVec<3>, + IsVLVT<4> +]>; + +// vvp_scatter(chain, data, addr, mask, avl) +def SDTScatterVVP: SDTypeProfile<0, 4, [ + SDTCisVec<0>, + SDTCisVec<1>, + SDTCisVec<2>, + SDTCisSameNumEltsAs<0, 2>, + IsVLVT<3> +]>; + +// vvp_gather(chain, addr, mask, avl) +def SDTGatherVVP: SDTypeProfile<1, 3, [ + SDTCisVec<0>, + SDTCisVec<1>, + SDTCisSameNumEltsAs<0, 2>, + IsVLVT<3> +]>; // BinaryOp(x,y,mask,vl) def SDTIntBinOpVVP : SDTypeProfile<1, 4, [ // vp_add, vp_and, etc. @@ -29,6 +62,15 @@ def SDTIntBinOpVVP : SDTypeProfile<1, 4, [ // vp_add, vp_and, etc. IsVLVT<4> ]>; +// UnaryFPOp(x,mask,vl) +def SDTFPUnaryOpVVP : SDTypeProfile<1, 3, [ + SDTCisSameAs<0, 1>, + SDTCisFP<0>, + SDTCisInt<2>, + SDTCisSameNumEltsAs<0, 2>, + IsVLVT<3> +]>; + // BinaryFPOp(x,y,mask,vl) def SDTFPBinOpVVP : SDTypeProfile<1, 4, [ // vvp_fadd, etc. SDTCisSameAs<0, 1>, @@ -39,6 +81,17 @@ def SDTFPBinOpVVP : SDTypeProfile<1, 4, [ // vvp_fadd, etc. IsVLVT<4> ]>; +// TernaryFPOp(x,y,z,mask,vl) +def SDTFPTernaryOpVVP : SDTypeProfile<1, 5, [ + SDTCisSameAs<0, 1>, + SDTCisSameAs<0, 2>, + SDTCisSameAs<0, 3>, + SDTCisFP<0>, + SDTCisInt<4>, + SDTCisSameNumEltsAs<0, 4>, + IsVLVT<5> +]>; + // Select(OnTrue, OnFalse, SelMask, vl) def SDTSelectVVP : SDTypeProfile<1, 4, [ // vp_select, vp_merge SDTCisVec<0>, @@ -48,6 +101,28 @@ def SDTSelectVVP : SDTypeProfile<1, 4, [ // vp_select, vp_merge IsVLVT<4> ]>; +// SetCC (lhs, rhs, cc, mask, vl) +def SDTSetCCVVP : SDTypeProfile<1, 5, [ // vp_setcc + SDTCisVec<0>, + SDTCisVec<1>, + SDTCisSameNumEltsAs<0, 1>, + SDTCisSameAs<1, 2>, + SDTCisVT<3, OtherVT>, + SDTCisInt<4>, + SDTCisSameNumEltsAs<0, 4>, + IsVLVT<5> +]>; + +// vvp_reduce(vector, mask, vl) +def SDTReduceVVP : SDTypeProfile<1, 3, [ + SDTCisVec<1>, + SDTCisInt<2>, + SDTCisVec<2>, + SDTCisSameNumEltsAs<1,2>, + IsVLVT<3> +]>; + + // Binary operator commutative pattern. class vvp_commutative<SDNode RootOp> : PatFrags< @@ -55,6 +130,12 @@ class vvp_commutative<SDNode RootOp> : [(RootOp node:$lhs, node:$rhs, node:$mask, node:$vlen), (RootOp node:$rhs, node:$lhs, node:$mask, node:$vlen)]>; +class vvp_fma_commutative<SDNode RootOp> : + PatFrags< + (ops node:$X, node:$Y, node:$Z, node:$mask, node:$vlen), + [(RootOp node:$X, node:$Y, node:$Z, node:$mask, node:$vlen), + (RootOp node:$X, node:$Z, node:$Y, node:$mask, node:$vlen)]>; + // VVP node definitions. def vvp_add : SDNode<"VEISD::VVP_ADD", SDTIntBinOpVVP>; def c_vvp_add : vvp_commutative<vvp_add>; @@ -80,6 +161,8 @@ def vvp_srl : SDNode<"VEISD::VVP_SRL", SDTIntBinOpVVP>; def vvp_sra : SDNode<"VEISD::VVP_SRA", SDTIntBinOpVVP>; def vvp_shl : SDNode<"VEISD::VVP_SHL", SDTIntBinOpVVP>; +def vvp_fneg : SDNode<"VEISD::VVP_FNEG", SDTFPUnaryOpVVP>; + def vvp_fadd : SDNode<"VEISD::VVP_FADD", SDTFPBinOpVVP>; def c_vvp_fadd : vvp_commutative<vvp_fadd>; def vvp_fsub : SDNode<"VEISD::VVP_FSUB", SDTFPBinOpVVP>; @@ -87,6 +170,30 @@ def vvp_fmul : SDNode<"VEISD::VVP_FMUL", SDTFPBinOpVVP>; def c_vvp_fmul : vvp_commutative<vvp_fmul>; def vvp_fdiv : SDNode<"VEISD::VVP_FDIV", SDTFPBinOpVVP>; -// } Binary Operators +def vvp_ffma : SDNode<"VEISD::VVP_FFMA", SDTFPTernaryOpVVP>; +def c_vvp_ffma : vvp_fma_commutative<vvp_ffma>; + +def vvp_scatter : SDNode<"VEISD::VVP_SCATTER", SDTScatterVVP, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def vvp_gather : SDNode<"VEISD::VVP_GATHER", SDTGatherVVP, + [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; + +def vvp_load : SDNode<"VEISD::VVP_LOAD", SDTLoadVVP, + [SDNPHasChain, SDNPMayLoad, SDNPMemOperand ]>; +def vvp_store : SDNode<"VEISD::VVP_STORE", SDTStoreVVP, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; + +// Reductions + +// int reductions +def vvp_reduce_add : SDNode<"VEISD::VVP_REDUCE_ADD", SDTReduceVVP>; +def vvp_reduce_and : SDNode<"VEISD::VVP_REDUCE_AND", SDTReduceVVP>; +def vvp_reduce_or : SDNode<"VEISD::VVP_REDUCE_OR", SDTReduceVVP>; +def vvp_reduce_xor : SDNode<"VEISD::VVP_REDUCE_XOR", SDTReduceVVP>; +def vvp_reduce_smax : SDNode<"VEISD::VVP_REDUCE_SMAX", SDTReduceVVP>; + def vvp_select : SDNode<"VEISD::VVP_SELECT", SDTSelectVVP>; + +// setcc (lhs, rhs, cc, mask, vl) +def vvp_setcc : SDNode<"VEISD::VVP_SETCC", SDTSetCCVVP>; |