diff options
Diffstat (limited to 'llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp | 513 |
1 files changed, 181 insertions, 332 deletions
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp index e9ecff3bf514..871b23f80efe 100644 --- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp +++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp @@ -9,6 +9,7 @@ #include "MCTargetDesc/X86BaseInfo.h" #include "MCTargetDesc/X86IntelInstPrinter.h" #include "MCTargetDesc/X86MCExpr.h" +#include "MCTargetDesc/X86MCTargetDesc.h" #include "MCTargetDesc/X86TargetStreamer.h" #include "TargetInfo/X86TargetInfo.h" #include "X86AsmParserCommon.h" @@ -124,12 +125,12 @@ private: bool matchingInlineAsm, unsigned VariantID = 0) { // In Code16GCC mode, match as 32-bit. if (Code16GCC) - SwitchMode(X86::Mode32Bit); + SwitchMode(X86::Is32Bit); unsigned rv = MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures, matchingInlineAsm, VariantID); if (Code16GCC) - SwitchMode(X86::Mode16Bit); + SwitchMode(X86::Is16Bit); return rv; } @@ -422,16 +423,18 @@ private: }; class IntelExprStateMachine { - IntelExprState State, PrevState; - unsigned BaseReg, IndexReg, TmpReg, Scale; - int64_t Imm; - const MCExpr *Sym; + IntelExprState State = IES_INIT, PrevState = IES_ERROR; + unsigned BaseReg = 0, IndexReg = 0, TmpReg = 0, Scale = 0; + int64_t Imm = 0; + const MCExpr *Sym = nullptr; StringRef SymName; InfixCalculator IC; InlineAsmIdentifierInfo Info; - short BracCount; - bool MemExpr; - bool OffsetOperator; + short BracCount = 0; + bool MemExpr = false; + bool OffsetOperator = false; + bool AttachToOperandIdx = false; + bool IsPIC = false; SMLoc OffsetOperatorLoc; AsmTypeInfo CurType; @@ -446,10 +449,7 @@ private: } public: - IntelExprStateMachine() - : State(IES_INIT), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), - TmpReg(0), Scale(0), Imm(0), Sym(nullptr), BracCount(0), - MemExpr(false), OffsetOperator(false) {} + IntelExprStateMachine() = default; void addImm(int64_t imm) { Imm += imm; } short getBracCount() const { return BracCount; } @@ -469,9 +469,29 @@ private: bool isValidEndState() const { return State == IES_RBRAC || State == IES_INTEGER; } + + // Is the intel expression appended after an operand index. + // [OperandIdx][Intel Expression] + // This is neccessary for checking if it is an independent + // intel expression at back end when parse inline asm. + void setAppendAfterOperand() { AttachToOperandIdx = true; } + + bool isPIC() const { return IsPIC; } + void setPIC() { IsPIC = true; } + bool hadError() const { return State == IES_ERROR; } const InlineAsmIdentifierInfo &getIdentifierInfo() const { return Info; } + bool regsUseUpError(StringRef &ErrMsg) { + // This case mostly happen in inline asm, e.g. Arr[BaseReg + IndexReg] + // can not intruduce additional register in inline asm in PIC model. + if (IsPIC && AttachToOperandIdx) + ErrMsg = "Don't use 2 or more regs for mem offset in PIC model!"; + else + ErrMsg = "BaseReg/IndexReg already set!"; + return true; + } + void onOr() { IntelExprState CurrState = State; switch (State) { @@ -655,10 +675,8 @@ private: if (!BaseReg) { BaseReg = TmpReg; } else { - if (IndexReg) { - ErrMsg = "BaseReg/IndexReg already set!"; - return true; - } + if (IndexReg) + return regsUseUpError(ErrMsg); IndexReg = TmpReg; Scale = 0; } @@ -716,10 +734,8 @@ private: if (!BaseReg) { BaseReg = TmpReg; } else { - if (IndexReg) { - ErrMsg = "BaseReg/IndexReg already set!"; - return true; - } + if (IndexReg) + return regsUseUpError(ErrMsg); IndexReg = TmpReg; Scale = 0; } @@ -777,10 +793,8 @@ private: case IES_MULTIPLY: // Index Register - Scale * Register if (PrevState == IES_INTEGER) { - if (IndexReg) { - ErrMsg = "BaseReg/IndexReg already set!"; - return true; - } + if (IndexReg) + return regsUseUpError(ErrMsg); State = IES_REGISTER; IndexReg = Reg; // Get the scale and replace the 'Scale * Register' with '0'. @@ -861,10 +875,8 @@ private: State = IES_INTEGER; if (PrevState == IES_REGISTER && CurrState == IES_MULTIPLY) { // Index Register - Register * Scale - if (IndexReg) { - ErrMsg = "BaseReg/IndexReg already set!"; - return true; - } + if (IndexReg) + return regsUseUpError(ErrMsg); IndexReg = TmpReg; Scale = TmpInt; if (checkScale(Scale, ErrMsg)) @@ -945,7 +957,7 @@ private: BracCount++; return false; } - bool onRBrac() { + bool onRBrac(StringRef &ErrMsg) { IntelExprState CurrState = State; switch (State) { default: @@ -955,8 +967,10 @@ private: case IES_OFFSET: case IES_REGISTER: case IES_RPAREN: - if (BracCount-- != 1) + if (BracCount-- != 1) { + ErrMsg = "unexpected bracket encountered"; return true; + } State = IES_RBRAC; if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) { // If we already have a BaseReg, then assume this is the IndexReg with @@ -964,7 +978,8 @@ private: if (!BaseReg) { BaseReg = TmpReg; } else { - assert (!IndexReg && "BaseReg/IndexReg already set!"); + if (IndexReg) + return regsUseUpError(ErrMsg); IndexReg = TmpReg; Scale = 0; } @@ -1089,9 +1104,9 @@ private: std::unique_ptr<llvm::MCParsedAsmOperand> &&Dst); bool VerifyAndAdjustOperands(OperandVector &OrigOperands, OperandVector &FinalOperands); - bool ParseOperand(OperandVector &Operands); - bool ParseATTOperand(OperandVector &Operands); - bool ParseIntelOperand(OperandVector &Operands); + bool parseOperand(OperandVector &Operands, StringRef Name); + bool parseATTOperand(OperandVector &Operands); + bool parseIntelOperand(OperandVector &Operands, StringRef Name); bool ParseIntelOffsetOperator(const MCExpr *&Val, StringRef &ID, InlineAsmIdentifierInfo &Info, SMLoc &End); bool ParseIntelDotOperator(IntelExprStateMachine &SM, SMLoc &End); @@ -1111,6 +1126,8 @@ private: InlineAsmIdentifierInfo &Info, bool IsUnevaluatedOperand, SMLoc &End, bool IsParsingOffsetOperator = false); + void tryParseOperandIdx(AsmToken::TokenKind PrevTK, + IntelExprStateMachine &SM); bool ParseMemOperand(unsigned SegReg, const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc, OperandVector &Operands); @@ -1193,19 +1210,19 @@ private: bool is64BitMode() const { // FIXME: Can tablegen auto-generate this? - return getSTI().getFeatureBits()[X86::Mode64Bit]; + return getSTI().getFeatureBits()[X86::Is64Bit]; } bool is32BitMode() const { // FIXME: Can tablegen auto-generate this? - return getSTI().getFeatureBits()[X86::Mode32Bit]; + return getSTI().getFeatureBits()[X86::Is32Bit]; } bool is16BitMode() const { // FIXME: Can tablegen auto-generate this? - return getSTI().getFeatureBits()[X86::Mode16Bit]; + return getSTI().getFeatureBits()[X86::Is16Bit]; } void SwitchMode(unsigned mode) { MCSubtargetInfo &STI = copySTI(); - FeatureBitset AllModes({X86::Mode64Bit, X86::Mode32Bit, X86::Mode16Bit}); + FeatureBitset AllModes({X86::Is64Bit, X86::Is32Bit, X86::Is16Bit}); FeatureBitset OldMode = STI.getFeatureBits() & AllModes; FeatureBitset FB = ComputeAvailableFeatures( STI.ToggleFeature(OldMode.flip(mode))); @@ -1716,11 +1733,11 @@ bool X86AsmParser::VerifyAndAdjustOperands(OperandVector &OrigOperands, return false; } -bool X86AsmParser::ParseOperand(OperandVector &Operands) { +bool X86AsmParser::parseOperand(OperandVector &Operands, StringRef Name) { if (isParsingIntelSyntax()) - return ParseIntelOperand(Operands); + return parseIntelOperand(Operands, Name); - return ParseATTOperand(Operands); + return parseATTOperand(Operands); } bool X86AsmParser::CreateMemForMSInlineAsm( @@ -1759,8 +1776,8 @@ bool X86AsmParser::CreateMemForMSInlineAsm( // registers in a mmory expression, and though unaccessible via rip/eip. if (IsGlobalLV && (BaseReg || IndexReg)) { Operands.push_back(X86Operand::CreateMem(getPointerWidth(), Disp, Start, - End, Size, Identifier, Decl, - FrontendSize)); + End, Size, Identifier, Decl, 0, + BaseReg && IndexReg)); return false; } // Otherwise, we set the base register to a non-zero value @@ -1841,11 +1858,25 @@ bool X86AsmParser::ParseMasmNamedOperator(StringRef Name, return true; } +// Check if current intel expression append after an operand. +// Like: [Operand][Intel Expression] +void X86AsmParser::tryParseOperandIdx(AsmToken::TokenKind PrevTK, + IntelExprStateMachine &SM) { + if (PrevTK != AsmToken::RBrac) + return; + + SM.setAppendAfterOperand(); +} + bool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) { MCAsmParser &Parser = getParser(); StringRef ErrMsg; AsmToken::TokenKind PrevTK = AsmToken::Error; + + if (getContext().getObjectFileInfo()->isPositionIndependent()) + SM.setPIC(); + bool Done = false; while (!Done) { // Get a fresh reference on each loop iteration in case the previous @@ -2123,10 +2154,12 @@ bool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) { case AsmToken::LBrac: if (SM.onLBrac()) return Error(Tok.getLoc(), "unexpected bracket encountered"); + tryParseOperandIdx(PrevTK, SM); break; case AsmToken::RBrac: - if (SM.onRBrac()) - return Error(Tok.getLoc(), "unexpected bracket encountered"); + if (SM.onRBrac(ErrMsg)) { + return Error(Tok.getLoc(), ErrMsg); + } break; case AsmToken::LParen: SM.onLParen(); break; case AsmToken::RParen: SM.onRParen(); break; @@ -2477,7 +2510,7 @@ bool X86AsmParser::ParseIntelMemoryOperandSize(unsigned &Size) { return false; } -bool X86AsmParser::ParseIntelOperand(OperandVector &Operands) { +bool X86AsmParser::parseIntelOperand(OperandVector &Operands, StringRef Name) { MCAsmParser &Parser = getParser(); const AsmToken &Tok = Parser.getTok(); SMLoc Start, End; @@ -2552,6 +2585,8 @@ bool X86AsmParser::ParseIntelOperand(OperandVector &Operands) { StringRef ErrMsg; unsigned BaseReg = SM.getBaseReg(); unsigned IndexReg = SM.getIndexReg(); + if (IndexReg && BaseReg == X86::RIP) + BaseReg = 0; unsigned Scale = SM.getScale(); if (!PtrInOperand) Size = SM.getElementSize() << 3; @@ -2597,25 +2632,49 @@ bool X86AsmParser::ParseIntelOperand(OperandVector &Operands) { // When parsing x64 MS-style assembly, all non-absolute references to a named // variable default to RIP-relative. - if (Parser.isParsingMasm() && is64BitMode() && SM.getElementSize() > 0) { - Operands.push_back(X86Operand::CreateMem(getPointerWidth(), RegNo, Disp, - BaseReg, IndexReg, Scale, Start, - End, Size, - /*DefaultBaseReg=*/X86::RIP)); - return false; + unsigned DefaultBaseReg = X86::NoRegister; + bool MaybeDirectBranchDest = true; + + if (Parser.isParsingMasm()) { + bool IsUnconditionalBranch = + Name.equals_insensitive("jmp") || Name.equals_insensitive("call"); + if (is64BitMode() && SM.getElementSize() > 0) { + DefaultBaseReg = X86::RIP; + } + if (IsUnconditionalBranch) { + if (PtrInOperand) { + MaybeDirectBranchDest = false; + if (is64BitMode()) + DefaultBaseReg = X86::RIP; + } else if (!BaseReg && !IndexReg && Disp && + Disp->getKind() == MCExpr::SymbolRef) { + if (is64BitMode()) { + if (SM.getSize() == 8) { + MaybeDirectBranchDest = false; + DefaultBaseReg = X86::RIP; + } + } else { + if (SM.getSize() == 4 || SM.getSize() == 2) + MaybeDirectBranchDest = false; + } + } + } } - if ((BaseReg || IndexReg || RegNo)) - Operands.push_back(X86Operand::CreateMem(getPointerWidth(), RegNo, Disp, - BaseReg, IndexReg, Scale, Start, - End, Size)); + if ((BaseReg || IndexReg || RegNo || DefaultBaseReg != X86::NoRegister)) + Operands.push_back(X86Operand::CreateMem( + getPointerWidth(), RegNo, Disp, BaseReg, IndexReg, Scale, Start, End, + Size, DefaultBaseReg, /*SymName=*/StringRef(), /*OpDecl=*/nullptr, + /*FrontendSize=*/0, /*UseUpRegs=*/false, MaybeDirectBranchDest)); else - Operands.push_back( - X86Operand::CreateMem(getPointerWidth(), Disp, Start, End, Size)); + Operands.push_back(X86Operand::CreateMem( + getPointerWidth(), Disp, Start, End, Size, /*SymName=*/StringRef(), + /*OpDecl=*/nullptr, /*FrontendSize=*/0, /*UseUpRegs=*/false, + MaybeDirectBranchDest)); return false; } -bool X86AsmParser::ParseATTOperand(OperandVector &Operands) { +bool X86AsmParser::parseATTOperand(OperandVector &Operands) { MCAsmParser &Parser = getParser(); switch (getLexer().getKind()) { case AsmToken::Dollar: { @@ -2722,7 +2781,7 @@ bool X86AsmParser::ParseZ(std::unique_ptr<X86Operand> &Z, if (!getLexer().is(AsmToken::RCurly)) return Error(getLexer().getLoc(), "Expected } at this point"); Parser.Lex(); // Eat '}' - // Assign Z with the {z} mark opernad + // Assign Z with the {z} mark operand Z = X86Operand::CreateToken("{z}", StartLoc); return false; } @@ -3346,7 +3405,7 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, Name = Next; PatchedName = Name; - ForcedDataPrefix = X86::Mode32Bit; + ForcedDataPrefix = X86::Is32Bit; IsPrefix = false; } } @@ -3371,7 +3430,7 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, // Read the operands. while (true) { - if (ParseOperand(Operands)) + if (parseOperand(Operands, Name)) return true; if (HandleAVX512Operand(Operands)) return true; @@ -3774,84 +3833,27 @@ bool X86AsmParser::processInstruction(MCInst &Inst, const OperandVector &Ops) { } bool X86AsmParser::validateInstruction(MCInst &Inst, const OperandVector &Ops) { + using namespace X86; const MCRegisterInfo *MRI = getContext().getRegisterInfo(); - - switch (Inst.getOpcode()) { - case X86::VGATHERDPDYrm: - case X86::VGATHERDPDrm: - case X86::VGATHERDPSYrm: - case X86::VGATHERDPSrm: - case X86::VGATHERQPDYrm: - case X86::VGATHERQPDrm: - case X86::VGATHERQPSYrm: - case X86::VGATHERQPSrm: - case X86::VPGATHERDDYrm: - case X86::VPGATHERDDrm: - case X86::VPGATHERDQYrm: - case X86::VPGATHERDQrm: - case X86::VPGATHERQDYrm: - case X86::VPGATHERQDrm: - case X86::VPGATHERQQYrm: - case X86::VPGATHERQQrm: { - unsigned Dest = MRI->getEncodingValue(Inst.getOperand(0).getReg()); - unsigned Mask = MRI->getEncodingValue(Inst.getOperand(1).getReg()); - unsigned Index = - MRI->getEncodingValue(Inst.getOperand(3 + X86::AddrIndexReg).getReg()); - if (Dest == Mask || Dest == Index || Mask == Index) - return Warning(Ops[0]->getStartLoc(), "mask, index, and destination " - "registers should be distinct"); - break; - } - case X86::VGATHERDPDZ128rm: - case X86::VGATHERDPDZ256rm: - case X86::VGATHERDPDZrm: - case X86::VGATHERDPSZ128rm: - case X86::VGATHERDPSZ256rm: - case X86::VGATHERDPSZrm: - case X86::VGATHERQPDZ128rm: - case X86::VGATHERQPDZ256rm: - case X86::VGATHERQPDZrm: - case X86::VGATHERQPSZ128rm: - case X86::VGATHERQPSZ256rm: - case X86::VGATHERQPSZrm: - case X86::VPGATHERDDZ128rm: - case X86::VPGATHERDDZ256rm: - case X86::VPGATHERDDZrm: - case X86::VPGATHERDQZ128rm: - case X86::VPGATHERDQZ256rm: - case X86::VPGATHERDQZrm: - case X86::VPGATHERQDZ128rm: - case X86::VPGATHERQDZ256rm: - case X86::VPGATHERQDZrm: - case X86::VPGATHERQQZ128rm: - case X86::VPGATHERQQZ256rm: - case X86::VPGATHERQQZrm: { - unsigned Dest = MRI->getEncodingValue(Inst.getOperand(0).getReg()); - unsigned Index = - MRI->getEncodingValue(Inst.getOperand(4 + X86::AddrIndexReg).getReg()); - if (Dest == Index) - return Warning(Ops[0]->getStartLoc(), "index and destination registers " - "should be distinct"); - break; - } - case X86::V4FMADDPSrm: - case X86::V4FMADDPSrmk: - case X86::V4FMADDPSrmkz: - case X86::V4FMADDSSrm: - case X86::V4FMADDSSrmk: - case X86::V4FMADDSSrmkz: - case X86::V4FNMADDPSrm: - case X86::V4FNMADDPSrmk: - case X86::V4FNMADDPSrmkz: - case X86::V4FNMADDSSrm: - case X86::V4FNMADDSSrmk: - case X86::V4FNMADDSSrmkz: - case X86::VP4DPWSSDSrm: - case X86::VP4DPWSSDSrmk: - case X86::VP4DPWSSDSrmkz: - case X86::VP4DPWSSDrm: - case X86::VP4DPWSSDrmk: - case X86::VP4DPWSSDrmkz: { + unsigned Opcode = Inst.getOpcode(); + uint64_t TSFlags = MII.get(Opcode).TSFlags; + if (isVFCMADDCPH(Opcode) || isVFCMADDCSH(Opcode) || isVFMADDCPH(Opcode) || + isVFMADDCSH(Opcode)) { + unsigned Dest = Inst.getOperand(0).getReg(); + for (unsigned i = 2; i < Inst.getNumOperands(); i++) + if (Inst.getOperand(i).isReg() && Dest == Inst.getOperand(i).getReg()) + return Warning(Ops[0]->getStartLoc(), "Destination register should be " + "distinct from source registers"); + } else if (isVFCMULCPH(Opcode) || isVFCMULCSH(Opcode) || isVFMULCPH(Opcode) || + isVFMULCSH(Opcode)) { + unsigned Dest = Inst.getOperand(0).getReg(); + for (unsigned i = 1; i < Inst.getNumOperands(); i++) + if (Inst.getOperand(i).isReg() && Dest == Inst.getOperand(i).getReg()) + return Warning(Ops[0]->getStartLoc(), "Destination register should be " + "distinct from source registers"); + } else if (isV4FMADDPS(Opcode) || isV4FMADDSS(Opcode) || + isV4FNMADDPS(Opcode) || isV4FNMADDSS(Opcode) || + isVP4DPWSSDS(Opcode) || isVP4DPWSSD(Opcode)) { unsigned Src2 = Inst.getOperand(Inst.getNumOperands() - X86::AddrNumOperands - 1).getReg(); unsigned Src2Enc = MRI->getEncodingValue(Src2); @@ -3865,186 +3867,34 @@ bool X86AsmParser::validateInstruction(MCInst &Inst, const OperandVector &Ops) { RegName.take_front(3) + Twine(GroupEnd) + "' source group"); } - break; - } - case X86::VFCMADDCPHZ128m: - case X86::VFCMADDCPHZ256m: - case X86::VFCMADDCPHZm: - case X86::VFCMADDCPHZ128mb: - case X86::VFCMADDCPHZ256mb: - case X86::VFCMADDCPHZmb: - case X86::VFCMADDCPHZ128mbk: - case X86::VFCMADDCPHZ256mbk: - case X86::VFCMADDCPHZmbk: - case X86::VFCMADDCPHZ128mbkz: - case X86::VFCMADDCPHZ256mbkz: - case X86::VFCMADDCPHZmbkz: - case X86::VFCMADDCPHZ128mk: - case X86::VFCMADDCPHZ256mk: - case X86::VFCMADDCPHZmk: - case X86::VFCMADDCPHZ128mkz: - case X86::VFCMADDCPHZ256mkz: - case X86::VFCMADDCPHZmkz: - case X86::VFCMADDCPHZ128r: - case X86::VFCMADDCPHZ256r: - case X86::VFCMADDCPHZr: - case X86::VFCMADDCPHZ128rk: - case X86::VFCMADDCPHZ256rk: - case X86::VFCMADDCPHZrk: - case X86::VFCMADDCPHZ128rkz: - case X86::VFCMADDCPHZ256rkz: - case X86::VFCMADDCPHZrkz: - case X86::VFCMADDCPHZrb: - case X86::VFCMADDCPHZrbk: - case X86::VFCMADDCPHZrbkz: - case X86::VFCMADDCSHZm: - case X86::VFCMADDCSHZmk: - case X86::VFCMADDCSHZmkz: - case X86::VFCMADDCSHZr: - case X86::VFCMADDCSHZrb: - case X86::VFCMADDCSHZrbk: - case X86::VFCMADDCSHZrbkz: - case X86::VFCMADDCSHZrk: - case X86::VFCMADDCSHZrkz: - case X86::VFMADDCPHZ128m: - case X86::VFMADDCPHZ256m: - case X86::VFMADDCPHZm: - case X86::VFMADDCPHZ128mb: - case X86::VFMADDCPHZ256mb: - case X86::VFMADDCPHZmb: - case X86::VFMADDCPHZ128mbk: - case X86::VFMADDCPHZ256mbk: - case X86::VFMADDCPHZmbk: - case X86::VFMADDCPHZ128mbkz: - case X86::VFMADDCPHZ256mbkz: - case X86::VFMADDCPHZmbkz: - case X86::VFMADDCPHZ128mk: - case X86::VFMADDCPHZ256mk: - case X86::VFMADDCPHZmk: - case X86::VFMADDCPHZ128mkz: - case X86::VFMADDCPHZ256mkz: - case X86::VFMADDCPHZmkz: - case X86::VFMADDCPHZ128r: - case X86::VFMADDCPHZ256r: - case X86::VFMADDCPHZr: - case X86::VFMADDCPHZ128rk: - case X86::VFMADDCPHZ256rk: - case X86::VFMADDCPHZrk: - case X86::VFMADDCPHZ128rkz: - case X86::VFMADDCPHZ256rkz: - case X86::VFMADDCPHZrkz: - case X86::VFMADDCPHZrb: - case X86::VFMADDCPHZrbk: - case X86::VFMADDCPHZrbkz: - case X86::VFMADDCSHZm: - case X86::VFMADDCSHZmk: - case X86::VFMADDCSHZmkz: - case X86::VFMADDCSHZr: - case X86::VFMADDCSHZrb: - case X86::VFMADDCSHZrbk: - case X86::VFMADDCSHZrbkz: - case X86::VFMADDCSHZrk: - case X86::VFMADDCSHZrkz: { - unsigned Dest = Inst.getOperand(0).getReg(); - for (unsigned i = 2; i < Inst.getNumOperands(); i++) - if (Inst.getOperand(i).isReg() && Dest == Inst.getOperand(i).getReg()) - return Warning(Ops[0]->getStartLoc(), "Destination register should be " - "distinct from source registers"); - break; - } - case X86::VFCMULCPHZ128rm: - case X86::VFCMULCPHZ256rm: - case X86::VFCMULCPHZrm: - case X86::VFCMULCPHZ128rmb: - case X86::VFCMULCPHZ256rmb: - case X86::VFCMULCPHZrmb: - case X86::VFCMULCPHZ128rmbk: - case X86::VFCMULCPHZ256rmbk: - case X86::VFCMULCPHZrmbk: - case X86::VFCMULCPHZ128rmbkz: - case X86::VFCMULCPHZ256rmbkz: - case X86::VFCMULCPHZrmbkz: - case X86::VFCMULCPHZ128rmk: - case X86::VFCMULCPHZ256rmk: - case X86::VFCMULCPHZrmk: - case X86::VFCMULCPHZ128rmkz: - case X86::VFCMULCPHZ256rmkz: - case X86::VFCMULCPHZrmkz: - case X86::VFCMULCPHZ128rr: - case X86::VFCMULCPHZ256rr: - case X86::VFCMULCPHZrr: - case X86::VFCMULCPHZ128rrk: - case X86::VFCMULCPHZ256rrk: - case X86::VFCMULCPHZrrk: - case X86::VFCMULCPHZ128rrkz: - case X86::VFCMULCPHZ256rrkz: - case X86::VFCMULCPHZrrkz: - case X86::VFCMULCPHZrrb: - case X86::VFCMULCPHZrrbk: - case X86::VFCMULCPHZrrbkz: - case X86::VFCMULCSHZrm: - case X86::VFCMULCSHZrmk: - case X86::VFCMULCSHZrmkz: - case X86::VFCMULCSHZrr: - case X86::VFCMULCSHZrrb: - case X86::VFCMULCSHZrrbk: - case X86::VFCMULCSHZrrbkz: - case X86::VFCMULCSHZrrk: - case X86::VFCMULCSHZrrkz: - case X86::VFMULCPHZ128rm: - case X86::VFMULCPHZ256rm: - case X86::VFMULCPHZrm: - case X86::VFMULCPHZ128rmb: - case X86::VFMULCPHZ256rmb: - case X86::VFMULCPHZrmb: - case X86::VFMULCPHZ128rmbk: - case X86::VFMULCPHZ256rmbk: - case X86::VFMULCPHZrmbk: - case X86::VFMULCPHZ128rmbkz: - case X86::VFMULCPHZ256rmbkz: - case X86::VFMULCPHZrmbkz: - case X86::VFMULCPHZ128rmk: - case X86::VFMULCPHZ256rmk: - case X86::VFMULCPHZrmk: - case X86::VFMULCPHZ128rmkz: - case X86::VFMULCPHZ256rmkz: - case X86::VFMULCPHZrmkz: - case X86::VFMULCPHZ128rr: - case X86::VFMULCPHZ256rr: - case X86::VFMULCPHZrr: - case X86::VFMULCPHZ128rrk: - case X86::VFMULCPHZ256rrk: - case X86::VFMULCPHZrrk: - case X86::VFMULCPHZ128rrkz: - case X86::VFMULCPHZ256rrkz: - case X86::VFMULCPHZrrkz: - case X86::VFMULCPHZrrb: - case X86::VFMULCPHZrrbk: - case X86::VFMULCPHZrrbkz: - case X86::VFMULCSHZrm: - case X86::VFMULCSHZrmk: - case X86::VFMULCSHZrmkz: - case X86::VFMULCSHZrr: - case X86::VFMULCSHZrrb: - case X86::VFMULCSHZrrbk: - case X86::VFMULCSHZrrbkz: - case X86::VFMULCSHZrrk: - case X86::VFMULCSHZrrkz: { - unsigned Dest = Inst.getOperand(0).getReg(); - for (unsigned i = 1; i < Inst.getNumOperands(); i++) - if (Inst.getOperand(i).isReg() && Dest == Inst.getOperand(i).getReg()) - return Warning(Ops[0]->getStartLoc(), "Destination register should be " - "distinct from source registers"); - break; - } + } else if (isVGATHERDPD(Opcode) || isVGATHERDPS(Opcode) || + isVGATHERQPD(Opcode) || isVGATHERQPS(Opcode) || + isVPGATHERDD(Opcode) || isVPGATHERDQ(Opcode) || + isVPGATHERQD(Opcode) || isVPGATHERQQ(Opcode)) { + bool HasEVEX = (TSFlags & X86II::EncodingMask) == X86II::EVEX; + if (HasEVEX) { + unsigned Dest = MRI->getEncodingValue(Inst.getOperand(0).getReg()); + unsigned Index = MRI->getEncodingValue( + Inst.getOperand(4 + X86::AddrIndexReg).getReg()); + if (Dest == Index) + return Warning(Ops[0]->getStartLoc(), "index and destination registers " + "should be distinct"); + } else { + unsigned Dest = MRI->getEncodingValue(Inst.getOperand(0).getReg()); + unsigned Mask = MRI->getEncodingValue(Inst.getOperand(1).getReg()); + unsigned Index = MRI->getEncodingValue( + Inst.getOperand(3 + X86::AddrIndexReg).getReg()); + if (Dest == Mask || Dest == Index || Mask == Index) + return Warning(Ops[0]->getStartLoc(), "mask, index, and destination " + "registers should be distinct"); + } } - const MCInstrDesc &MCID = MII.get(Inst.getOpcode()); // Check that we aren't mixing AH/BH/CH/DH with REX prefix. We only need to // check this with the legacy encoding, VEX/EVEX/XOP don't use REX. - if ((MCID.TSFlags & X86II::EncodingMask) == 0) { + if ((TSFlags & X86II::EncodingMask) == 0) { MCPhysReg HReg = X86::NoRegister; - bool UsesRex = MCID.TSFlags & X86II::REX_W; + bool UsesRex = TSFlags & X86II::REX_W; unsigned NumOps = Inst.getNumOperands(); for (unsigned i = 0; i != NumOps; ++i) { const MCOperand &MO = Inst.getOperand(i); @@ -4313,15 +4163,15 @@ bool X86AsmParser::MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode, // In 16-bit mode, if data32 is specified, temporarily switch to 32-bit mode // when matching the instruction. - if (ForcedDataPrefix == X86::Mode32Bit) - SwitchMode(X86::Mode32Bit); + if (ForcedDataPrefix == X86::Is32Bit) + SwitchMode(X86::Is32Bit); // First, try a direct match. FeatureBitset MissingFeatures; unsigned OriginalError = MatchInstruction(Operands, Inst, ErrorInfo, MissingFeatures, MatchingInlineAsm, isParsingIntelSyntax()); - if (ForcedDataPrefix == X86::Mode32Bit) { - SwitchMode(X86::Mode16Bit); + if (ForcedDataPrefix == X86::Is32Bit) { + SwitchMode(X86::Is16Bit); ForcedDataPrefix = 0; } switch (OriginalError) { @@ -4840,8 +4690,7 @@ bool X86AsmParser::parseDirectiveNops(SMLoc L) { if (getParser().parseAbsoluteExpression(Control)) return true; } - if (getParser().parseToken(AsmToken::EndOfStatement, - "unexpected token in '.nops' directive")) + if (getParser().parseEOL()) return true; if (NumBytes <= 0) { @@ -4863,7 +4712,7 @@ bool X86AsmParser::parseDirectiveNops(SMLoc L) { /// parseDirectiveEven /// ::= .even bool X86AsmParser::parseDirectiveEven(SMLoc L) { - if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive")) + if (parseEOL()) return false; const MCSection *Section = getStreamer().getCurrentSectionOnly(); @@ -4871,7 +4720,7 @@ bool X86AsmParser::parseDirectiveEven(SMLoc L) { getStreamer().initSections(false, getSTI()); Section = getStreamer().getCurrentSectionOnly(); } - if (Section->UseCodeAlign()) + if (Section->useCodeAlign()) getStreamer().emitCodeAlignment(2, &getSTI(), 0); else getStreamer().emitValueToAlignment(2, 0, 1, 0); @@ -4886,7 +4735,7 @@ bool X86AsmParser::ParseDirectiveCode(StringRef IDVal, SMLoc L) { if (IDVal == ".code16") { Parser.Lex(); if (!is16BitMode()) { - SwitchMode(X86::Mode16Bit); + SwitchMode(X86::Is16Bit); getParser().getStreamer().emitAssemblerFlag(MCAF_Code16); } } else if (IDVal == ".code16gcc") { @@ -4894,19 +4743,19 @@ bool X86AsmParser::ParseDirectiveCode(StringRef IDVal, SMLoc L) { Parser.Lex(); Code16GCC = true; if (!is16BitMode()) { - SwitchMode(X86::Mode16Bit); + SwitchMode(X86::Is16Bit); getParser().getStreamer().emitAssemblerFlag(MCAF_Code16); } } else if (IDVal == ".code32") { Parser.Lex(); if (!is32BitMode()) { - SwitchMode(X86::Mode32Bit); + SwitchMode(X86::Is32Bit); getParser().getStreamer().emitAssemblerFlag(MCAF_Code32); } } else if (IDVal == ".code64") { Parser.Lex(); if (!is64BitMode()) { - SwitchMode(X86::Mode64Bit); + SwitchMode(X86::Is64Bit); getParser().getStreamer().emitAssemblerFlag(MCAF_Code64); } } else { @@ -5035,7 +4884,7 @@ bool X86AsmParser::parseDirectiveSEHPushReg(SMLoc Loc) { return TokError("unexpected token in directive"); getParser().Lex(); - getStreamer().EmitWinCFIPushReg(Reg, Loc); + getStreamer().emitWinCFIPushReg(Reg, Loc); return false; } @@ -5055,7 +4904,7 @@ bool X86AsmParser::parseDirectiveSEHSetFrame(SMLoc Loc) { return TokError("unexpected token in directive"); getParser().Lex(); - getStreamer().EmitWinCFISetFrame(Reg, Off, Loc); + getStreamer().emitWinCFISetFrame(Reg, Off, Loc); return false; } @@ -5075,7 +4924,7 @@ bool X86AsmParser::parseDirectiveSEHSaveReg(SMLoc Loc) { return TokError("unexpected token in directive"); getParser().Lex(); - getStreamer().EmitWinCFISaveReg(Reg, Off, Loc); + getStreamer().emitWinCFISaveReg(Reg, Off, Loc); return false; } @@ -5095,7 +4944,7 @@ bool X86AsmParser::parseDirectiveSEHSaveXMM(SMLoc Loc) { return TokError("unexpected token in directive"); getParser().Lex(); - getStreamer().EmitWinCFISaveXMM(Reg, Off, Loc); + getStreamer().emitWinCFISaveXMM(Reg, Off, Loc); return false; } @@ -5116,7 +4965,7 @@ bool X86AsmParser::parseDirectiveSEHPushFrame(SMLoc Loc) { return TokError("unexpected token in directive"); getParser().Lex(); - getStreamer().EmitWinCFIPushFrame(Code, Loc); + getStreamer().emitWinCFIPushFrame(Code, Loc); return false; } |