1 files changed, 7 insertions, 2 deletions
diff --git a/llvm/utils/TableGen/TableGen.cpp b/llvm/utils/TableGen/TableGen.cpp
index efd641887232..746e2dd1db16 100644
--- a/llvm/utils/TableGen/TableGen.cpp
+++ b/llvm/utils/TableGen/TableGen.cpp
@@ -58,6 +58,7 @@ enum ActionType {
   GenDirectivesEnumDecl,
   GenDirectivesEnumImpl,
   GenDXILOperation,
+  GenRISCVTargetDef,
 };
 
 namespace llvm {
@@ -141,8 +142,9 @@ cl::opt<ActionType> Action(
         clEnumValN(GenDirectivesEnumImpl, "gen-directive-impl",
                    "Generate directive related implementation code"),
         clEnumValN(GenDXILOperation, "gen-dxil-operation",
-                   "Generate DXIL operation information")));
-
+                   "Generate DXIL operation information"),
+        clEnumValN(GenRISCVTargetDef, "gen-riscv-target-def",
+                   "Generate the list of CPU for RISCV")));
 cl::OptionCategory PrintEnumsCat("Options for -print-enums");
 cl::opt<std::string> Class("class", cl::desc("Print Enum list for this class"),
                            cl::value_desc("class name"),
@@ -278,6 +280,9 @@ bool LLVMTableGenMain(raw_ostream &OS, RecordKeeper &Records) {
   case GenDXILOperation:
     EmitDXILOperation(Records, OS);
     break;
+  case GenRISCVTargetDef:
+    EmitRISCVTargetDef(Records, OS);
+    break;
   }
 
   return false;