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-rw-r--r--share/man/man3/snl.32
-rw-r--r--share/man/man4/aacraid.412
-rw-r--r--share/man/man4/bridge.4210
-rw-r--r--share/man/man4/ice.426
-rw-r--r--share/man/man4/umass.456
-rw-r--r--share/man/man5/periodic.conf.52
-rw-r--r--share/man/man5/pf.conf.56
-rw-r--r--share/man/man5/rc.conf.59
-rw-r--r--share/man/man5/src.conf.543
-rw-r--r--share/man/man7/arch.7124
10 files changed, 363 insertions, 127 deletions
diff --git a/share/man/man3/snl.3 b/share/man/man3/snl.3
index f678d6cb2cea..04bae46691bf 100644
--- a/share/man/man3/snl.3
+++ b/share/man/man3/snl.3
@@ -288,7 +288,7 @@ main(int ac, char *argv[])
struct nl_parsed_link link = {};
if (!snl_parse_nlmsg(&ss, hdr, &link_parser, &link))
continue;
- printf("Link#%u %s mtu %u\\n", link.ifi_index, link.ifla_ifname, link.ifla_mtu);
+ printf("Link#%u %s mtu %u\en", link.ifi_index, link.ifla_ifname, link.ifla_mtu);
}
return (0);
diff --git a/share/man/man4/aacraid.4 b/share/man/man4/aacraid.4
index 3bf683ac40c8..0f64f36c493a 100644
--- a/share/man/man4/aacraid.4
+++ b/share/man/man4/aacraid.4
@@ -1,3 +1,6 @@
+.\"
+.\" SPDX-License-Identifier: BSD-2-Clause
+.\"
.\" Copyright (c) 2013 Achim Leubner
.\" All rights reserved.
.\"
@@ -21,12 +24,12 @@
.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
-.Dd June 19, 2015
+.Dd September 29, 2025
.Dt AACRAID 4
.Os
.Sh NAME
.Nm aacraid
-.Nd Adaptec AACRAID Controller driver
+.Nd Adaptec Series 6/7/8 6G and 12G SAS+SATA RAID controller driver
.Sh SYNOPSIS
To compile this driver into the kernel,
place the following lines in your
@@ -78,9 +81,10 @@ Linux-compatible
interface for the management device will be enabled and will allow
Linux-based management applications to control the card.
.Sh HARDWARE
-Controllers supported by the
+The
.Nm
-driver include:
+driver supports the following
+Adaptec 6G and 12G SAS/SATA RAID controllers:
.Pp
.Bl -bullet -compact
.It
diff --git a/share/man/man4/bridge.4 b/share/man/man4/bridge.4
index 7048df4593bf..3af952256d3a 100644
--- a/share/man/man4/bridge.4
+++ b/share/man/man4/bridge.4
@@ -36,7 +36,7 @@
.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
.\" POSSIBILITY OF SUCH DAMAGE.
.\"
-.Dd July 28, 2025
+.Dd October 13, 2025
.Dt IF_BRIDGE 4
.Os
.Sh NAME
@@ -272,53 +272,149 @@ by setting the
node using
.Xr sysctl 8 .
.Sh VLAN SUPPORT
-The
+Virtual LANs (VLANs), defined in the IEEE 802.1Q standard, allow traffic
+on a bridge to be segregated into separate logical networks which cannot
+communicate with each other.
+For example, two interfaces in VLAN 10 would be able to communicate
+with each other, but not with another interface in VLAN 20.
+.Pp
+Each VLAN is identified by a number between 1 and 4094 inclusive.
+By default, all traffic on the bridge is assigned to "VLAN 0",
+a pseudo-VLAN used for historical compatibility.
+When VLANs are in use on a bridge, it is recommended to explicitly
+assign all traffic to a VLAN rather than using VLAN 0.
+.Pp
+The bridge implements Independent VLAN Learning (IVL), meaning that
+host addresses are learned separately for each VLAN, and the same host
+address may exist on several different ports in different VLANs.
+.Pp
+If a
+.Xr vlan 4
+interface is configured on an interface which is also an
.Nm
-driver has full support for virtual LANs (VLANs).
-The bridge implements independent VLAN learning, i.e. MAC addresses are
-learned on a per-VLAN basis, and the same MAC address may be learned on
-multiple interfaces on different VLANs.
-Incoming frames with an 802.1Q tag will be assigned to the appropriate
-VLAN.
-.Pp
-Traffic sent to or from the host is not assigned to a VLAN by default.
-To allow the host to communicate on a VLAN, configure a
+member interface, all tagged frames will be processed by the
.Xr vlan 4
-interface on the bridge and (if necessary) assign IP addresses there.
-.Pp
-By default no access control is enabled, so any interface may
-participate in any VLAN.
-.Pp
-VLAN filtering may be enabled on a bridge using the
+interface and will not be visible to the bridge.
+This configuration is not recommended and may be unsupported in a
+future release.
+.Ss Tagged and untagged traffic
+Incoming frames on a member interface may be either tagged or untagged.
+Tagged frames contain an 802.1Q header indicating which VLAN the
+frame belongs to, while untagged frames do not.
+When a tagged frame is received, the frame is automatically assigned to
+the VLAN in the tag (subject to any configured VLAN access list),
+while untagged frames are assigned to the interface's configured
+Port VLAN ID (PVID), or to VLAN 0 if no PVID is configured.
+.Ss Assigning interfaces to VLANs
+An interface's PVID may be configured using the
.Xr ifconfig 8
-.Cm vlanfilter
-option.
-When VLAN filtering is enabled, an interface may only send and receive
-frames based on its configured VLAN access list.
+.Cm ifuntagged
+command:
+.Bd -literal -offset indent
+ifconfig bridge0 ifuntagged ix0 10
+.Ed
.Pp
-The interface's untagged VLAN ID may be configured using the
-.Xr ifconfig 8
+Or by using the
.Cm untagged
-option.
-If an untagged VLAN ID is configured, incoming frames will be assigned
-to that VLAN, and the interface may receive outgoing untagged frames
-in that VLAN.
-.Pp
-The tagged VLAN access list may be configured using the
-.Cm tagged ,
-.Cm +tagged
-and
-.Cm -tagged
-options to
-.Xr ifconfig 8 .
-An interface may send and receive tagged frames for any VLAN in its
-access list.
+option to
+.Cm addm :
+.Bd -literal -offset indent
+ifconfig bridge0 addm ix0 untagged 10
+.Ed
.Pp
-The bridge will automatically insert or remove 802.1q tags as needed,
-based on the interface configuration, when forwarding frames between
-interfaces.
-This tag processing is only done for interfaces with VLAN filtering
-enabled.
+This will assign all untagged traffic received on the interface to the
+specified VLAN, and any traffic transmitted on the interface in this
+VLAN will have its VLAN tag (if present) removed.
+Conversely, any traffic transmitted on the interface in a different
+VLAN will have a tag added, to allow the remote system to assign the
+traffic to the appropriate VLAN.
+.Ss Host communication in a VLAN
+Sometimes it is useful to allow the host itself to communicate in a VLAN,
+for example to provide routing to other hosts in the VLAN.
+To do this, create a
+.Xr vlan 4
+interface on top of the
+.Nm
+interface with the appropriate VLAN tag.
+For example, to allow the host to communicate in VLAN 10:
+.Bd -literal -offset indent
+ifconfig bridge0.10 create inet6 2001:db8::1/64
+.Ed
+.Ss Configuring the VLAN access list (VLAN filtering)
+For historical reasons, the default
+.Nm
+configuration allows all interfaces to send tagged traffic for any VLAN,
+meaning that VLANs do not provide security separation.
+To restrict which interfaces may communicate in which VLANs,
+enable VLAN filtering on the bridge:
+.Bd -literal -offset indent
+ifconfig bridge0 vlanfilter
+.Ed
+.Pp
+This has the following effects on bridge members:
+.Bl -bullet -offset indent
+.It
+No untagged frames will be accepted from a member interface unless
+the interface has a PVID configured.
+.It
+No tagged frames will be accepted from a member interface unless
+the VLAN identifier is present in the interface's VLAN access list.
+.It
+Frames with stacked tags (Q-in-Q) will not be accepted from a
+member interface unless the
+.Cm qinq
+option (see below) has been configured for that member.
+.El
+.Pp
+To configure the VLAN access list, use the
+.Xr ifconfig 8
+.Cm iftagged ,
+.Cm +iftagged
+or
+.Cm -iftagged
+commands.
+For example, to allow an interface to communicate in VLANs 10, 20,
+and any VLAN from 100 to 199:
+.Bd -literal -offset indent
+ifconfig bridge0 iftagged ix0 10,20,100-199
+.Ed
+.Ss IEEE 802.1ad (Q-in-Q) configuration
+IEEE 802.1ad, also called Q-in-Q or
+.Dq tag stacking ,
+allows a single Ethernet frame to contain multiple tags.
+This allows one Ethernet network to transport traffic between endpoints
+using its own VLAN tags without interfering with any pre-existing tags,
+and is often used in service provider networks to provide
+.Dq virtual wire
+Ethernet services.
+.Pp
+When VLAN filtering is enabled,
+.Nm
+does not permit member interfaces to send Q-in-Q frames, because in
+certain configuration this allows
+.Dq VLAN-hopping
+attacks on the bridge.
+For example, consider a bridge with port ix0 configured as a tagged
+port in VLAN 10, and port ix1 configured as untagged in VLAN 10 and
+tagged in VLAN 20.
+If ix0 is allowed to send Q-in-Q frames, then it can send a frame with
+two tags: one for VLAN 10, followed by one for VLAN 20.
+When the bridge forwards the frame to ix1, it will strip the VLAN tag
+for VLAN 10, then forward the frame to ix1 with the tag for VLAN 20
+intact, effectively allowing ix1 to send traffic on VLAN 20 even
+though the bridge configuration should not permit that.
+.Pp
+To permit an interface to send Q-in-Q frames, set the
+.Xr ifconfig 8
+.Cm qinq
+flag on the interface.
+This is only required on the interface which will send Q-in-Q frames,
+not the interface receiving the frames.
+.Pp
+Alternatively, set the
+.Cm defqinq
+flag on the bridge itself to enable Q-in-Q for all newly-added
+interfaces by default.
.Sh PACKET FILTERING
Packet filtering can be used with any firewall package that hooks in via the
.Xr pfil 9
@@ -537,6 +633,36 @@ ifconfig_wlan0="up ssid my_ap mode 11g"
ifconfig_fxp0="up"
.Ed
.Pp
+The following will cause a bridge to be created with two VLANs,
+10 and 20, where the
+.Dq Li em
+interfaces can only communicate in their assigned VLANs,
+while
+.Dq Li ix0
+is a trunk port which can communicate in either VLAN:
+.Bd -literal -offset indent
+cloned_interfaces="bridge0"
+ifconfig_bridge0="vlanfilter \e
+ addm em0 untagged 10 \e
+ addm em1 untagged 10 \e
+ addm em2 untagged 20 \e
+ addm em3 untagged 20 \e
+ addm ix0 tagged 10,20"
+ifconfig_em0="up"
+ifconfig_em1="up"
+ifconfig_em2="up"
+ifconfig_em3="up"
+ifconfig_ix0="up"
+.Ed
+.Pp
+The previous example could be extended to allow the host to
+communicate in VLANs 10 and 20:
+.Bd -literal -offset indent
+vlans_bridge0="10 20"
+ifconfig_bridge0_10_ipv6="inet6 2001:db8:0:10::1/64"
+ifconfig_bridge0_20_ipv6="inet6 2001:db8:0:20::1/64"
+.Ed
+.Pp
Consider a system with two 4-port Ethernet boards.
The following will cause a bridge consisting of all 8 ports with
Rapid Spanning Tree enabled to be created:
diff --git a/share/man/man4/ice.4 b/share/man/man4/ice.4
index 13ad304a2d5a..c7675e627726 100644
--- a/share/man/man4/ice.4
+++ b/share/man/man4/ice.4
@@ -39,18 +39,28 @@
.Nm ice
.Nd Intel Ethernet 800 Series Driver
.Sh SYNOPSIS
-To compile this driver into the kernel, place the following lines in your
-kernel configuration file:
-.Bd -literal -offset indent
.Cd device iflib
.Cd device ice
-.Ed
.Pp
-To load the driver as a module at boot time, place the following lines in
+In
.Xr loader.conf 5 :
-.Bd -literal -offset indent
-if_ice_load="YES"
-.Ed
+.Cd if_ice_load
+.Cd hw.ice.enable_health_events
+.Cd hw.ice.irdma
+.Cd hw.ice.irdma_max_msix
+.Cd hw.ice.debug.enable_tx_fc_filter
+.Cd hw.ice.debug.enable_tx_lldp_filter
+.Cd hw.ice.debug.ice_tx_balance_en
+.Pp
+In
+.Xr sysctl.conf 5
+or
+.Xr loader.conf 5 :
+.Cd dev.ice.#.current_speed
+.Cd dev.ice.#.fw_version
+.Cd dev.ice.#.ddp_version
+.Cd dev.ice.#.pba_number
+.Cd dev.ice.#.hw.mac.*
.Sh DESCRIPTION
.Ss Features
The
diff --git a/share/man/man4/umass.4 b/share/man/man4/umass.4
index db4e6f0890f2..8c6b03a3afea 100644
--- a/share/man/man4/umass.4
+++ b/share/man/man4/umass.4
@@ -25,44 +25,44 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.Dd October 2, 2025
+.Dd October 9, 2025
.Dt UMASS 4
.Os
.Sh NAME
.Nm umass
.Nd USB Mass Storage Devices driver
.Sh SYNOPSIS
-To compile this driver into the kernel,
-place the following line in your
-kernel configuration file:
-.Bd -ragged -offset indent
+.Cd "device da"
.Cd "device scbus"
+.Cd "device pass"
.Cd "device usb"
.Cd "device umass"
-.Ed
.Pp
-Alternatively, to load the driver as a
-module at boot time, place the following line in
+In
.Xr loader.conf 5 :
-.Bd -literal -offset indent
-umass_load="YES"
-.Ed
+.Cd umass_load
.Sh DESCRIPTION
The
.Nm
driver provides support for Mass Storage devices that attach to the USB
-port.
+interface.
.Pp
-To use the
-.Nm
-driver,
+If the appropriate hardware is detected,
+the driver will be loaded automatically by
+.Xr devmatch 8 .
+To load the driver manually at boot time, use the
+.Cm umass_load
+command at the
+.Xr loader 8
+prompt, or add it to
+.Xr loader.conf 5 .
+.Pp
+To use the driver in a custom kernel,
.Xr usb 4
-and one of
-.Xr uhci 4
-or
-.Xr ohci 4
-or
-.Xr ehci 4
+and at least one of
+.Xr uhci 4 ,
+.Xr ohci 4 ,
+.Xr ehci 4 ,
or
.Xr xhci 4
must be configured in the kernel.
@@ -88,16 +88,8 @@ USB hard disk drives
USB floppy drives
.El
.Sh EXAMPLES
-.Bd -literal -offset indent
-device umass
-device scbus
-device da
-device pass
-.Ed
-.Pp
-Add the
-.Nm
-driver to the kernel.
+Rescan all slots on a multi-slot flash reader,
+where the slots map to separate LUNs on a single SCSI ID:
.Bd -literal -offset indent
camcontrol rescan 0:0:0
camcontrol rescan 0:0:1
@@ -105,8 +97,6 @@ camcontrol rescan 0:0:2
camcontrol rescan 0:0:3
.Ed
.Pp
-Rescan all slots on a multi-slot flash reader, where the slots map to separate
-LUNs on a single SCSI ID.
Typically only the first slot will be enabled at boot time.
This assumes that
the flash reader is the first SCSI bus in the system and has 4 slots.
diff --git a/share/man/man5/periodic.conf.5 b/share/man/man5/periodic.conf.5
index a2ed2b09d772..8910895d9b89 100644
--- a/share/man/man5/periodic.conf.5
+++ b/share/man/man5/periodic.conf.5
@@ -981,7 +981,7 @@ since yesterday's check.
Space-separated list of additional anchors whose denied packets log entries to
show.
The main ruleset (i.e., the empty-string anchor) and any
-.Xr blacklistd 8
+.Xr blocklistd 8
anchors, if present, are always shown.
.It Va security_status_pfdenied_period
.Pq Vt str
diff --git a/share/man/man5/pf.conf.5 b/share/man/man5/pf.conf.5
index da02f10aac01..41410d6bc0fa 100644
--- a/share/man/man5/pf.conf.5
+++ b/share/man/man5/pf.conf.5
@@ -27,7 +27,7 @@
.\" ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
.\" POSSIBILITY OF SUCH DAMAGE.
.\"
-.Dd August 28, 2025
+.Dd October 7, 2025
.Dt PF.CONF 5
.Os
.Sh NAME
@@ -2377,7 +2377,7 @@ packets matching the same connection.
.It Ar route-to
The
.Ar route-to
-option routes the packet to the specified interface with an optional address
+option routes the packet to the specified interface with an address
for the next hop.
When a
.Ar route-to
@@ -3552,7 +3552,7 @@ hosts = "all" |
ipspec = "any" | host | "{" host-list "}"
host = [ "!" ] ( address [ "/" mask-bits ] | "<" string ">" )
redirhost = address [ "/" mask-bits ]
-routehost = "(" interface-name [ address [ "/" mask-bits ] ] ")"
+routehost = "(" interface-name address [ "/" mask-bits ] ")"
address = ( interface-name | interface-group |
"(" ( interface-name | interface-group ) ")" |
hostname | ipv4-dotted-quad | ipv6-coloned-hex )
diff --git a/share/man/man5/rc.conf.5 b/share/man/man5/rc.conf.5
index c0048f27c740..edbfa937f8df 100644
--- a/share/man/man5/rc.conf.5
+++ b/share/man/man5/rc.conf.5
@@ -22,7 +22,7 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.Dd October 2, 2025
+.Dd October 5, 2025
.Dt RC.CONF 5
.Os
.Sh NAME
@@ -4618,8 +4618,11 @@ Set to
to enable waiting for DAD to complete.
.It Va netwait_dad_timeout
.Pq Vt int
-Indicates the total number of seconds to wait for DAD to complete.
-The default is 10.
+Unset by default.
+Indicates the maximum number of seconds to wait for DAD to complete.
+If zero or unset, the timeout will be one more than the value of the
+.Va net.inet6.ip6.dad_count
+sysctl variable.
.It Va rctl_enable
.Pq Vt bool
If set to
diff --git a/share/man/man5/src.conf.5 b/share/man/man5/src.conf.5
index 5c8ae5b83e5f..1bb609336532 100644
--- a/share/man/man5/src.conf.5
+++ b/share/man/man5/src.conf.5
@@ -1,5 +1,5 @@
.\" DO NOT EDIT-- this file is @generated by tools/build/options/makeman.
-.Dd September 25, 2025
+.Dd October 1, 2025
.Dt SRC.CONF 5
.Os
.Sh NAME
@@ -226,10 +226,15 @@ options provide "full" Relocation Read-Only (RELRO) support.
With full RELRO the entire GOT is made read-only after performing relocation at
startup, avoiding GOT overwrite attacks.
.It Va WITHOUT_BLACKLIST
-Set this if you do not want to build
-.Xr blacklistd 8
-and
-.Xr blacklistctl 8 .
+This option has been renamed to
+.Va WITHOUT_BLOCKLIST .
+When set, it enforces these options:
+.Pp
+.Bl -item -compact
+.It
+.Va WITHOUT_BLOCKLIST
+.El
+.Pp
When set, these options are also in effect:
.Pp
.Bl -inset -compact
@@ -237,10 +242,36 @@ When set, these options are also in effect:
(unless
.Va WITH_BLACKLIST_SUPPORT
is set explicitly)
+.It Va WITHOUT_BLOCKLIST_SUPPORT
+(unless
+.Va WITH_BLOCKLIST_SUPPORT
+is set explicitly)
.El
.It Va WITHOUT_BLACKLIST_SUPPORT
+This option has been renamed to
+.Va WITHOUT_BLOCKLIST_SUPPORT .
+When set, it enforces these options:
+.Pp
+.Bl -item -compact
+.It
+.Va WITHOUT_BLOCKLIST_SUPPORT
+.El
+.It Va WITHOUT_BLOCKLIST
+Set this if you do not want to build
+.Xr blocklistd 8
+and
+.Xr blocklistctl 8 .
+When set, these options are also in effect:
+.Pp
+.Bl -inset -compact
+.It Va WITHOUT_BLOCKLIST_SUPPORT
+(unless
+.Va WITH_BLOCKLIST_SUPPORT
+is set explicitly)
+.El
+.It Va WITHOUT_BLOCKLIST_SUPPORT
Build some programs without
-.Xr libblacklist 3
+.Xr libblocklist 3
support, like
.Xr fingerd 8
and
diff --git a/share/man/man7/arch.7 b/share/man/man7/arch.7
index 5de441aed699..668f5aa23155 100644
--- a/share/man/man7/arch.7
+++ b/share/man/man7/arch.7
@@ -48,23 +48,35 @@ and later, unless otherwise noted.
.Fx
uses a flat address space.
Variables of types
-.Vt unsigned long ,
-.Vt uintptr_t ,
+.Vt unsigned long
and
.Vt size_t
-and pointers all have the same representation.
+have the same representation.
.Pp
In order to maximize compatibility with future pointer integrity mechanisms,
manipulations of pointers as integers should be performed via
.Vt uintptr_t
or
.Vt intptr_t
-and no other types.
-In particular,
-.Vt long
+and no other types as these types are the only integer types where the
+C standard guarantees that a pointer may be cast to it and then cast back
+to the original type.
+On CHERI systems,
+.Vt uintptr_t
and
-.Vt ptrdiff_t
-should be avoided.
+.Vt intptr_t
+are defined as
+.Vt __uintcap_t
+and
+.Vt __intcap_t
+which represent capabilities that can be manipulated by integer operations.
+Pointers should not be cast to
+.Vt long ,
+.Vt ptrdiff_t ,
+or
+.Vt size_t
+if they will later be cast back to a pointer that is expected to be
+dereferencable as they remain bare integer types on all architectures.
.Pp
On some architectures, e.g.,
AIM variants of
@@ -85,11 +97,13 @@ release to support each architecture.
.Bl -column -offset indent "Architecture" "Initial Release"
.It Sy Architecture Ta Sy Initial Release
.It aarch64 Ta 11.0
+.It aarch64c Ta 16.0 (planned)
.It amd64 Ta 5.1
.It armv7 Ta 12.0
.It powerpc64 Ta 9.0
.It powerpc64le Ta 13.0
.It riscv64 Ta 12.0
+.It riscv64c Ta 16.0 (planned)
.El
.Pp
Discontinued architectures are shown in the following table.
@@ -123,21 +137,33 @@ architectures use some variant of the ELF (see
.Xr elf 5 )
.Sy Application Binary Interface
(ABI) for the machine processor.
-All supported ABIs can be divided into two groups:
-.Bl -tag -width "Dv ILP32"
+Supported ABIs can be divided into three main groups:
+.Bl -tag -width "Dv L64PC128"
.It Dv ILP32
.Vt int ,
+.Vt intptr_t ,
.Vt long ,
+and
.Vt void *
types machine representations all have 4-byte size.
.It Dv LP64
.Vt int
type machine representation uses 4 bytes,
while
-.Vt long
+.Vt intptr_t ,
+.Vt long ,
and
.Vt void *
are 8 bytes.
+.It Dv L64PC128
+.Vt int
+type machine representation uses 4 bytes.
+.Vt long
+type machine representation uses 8 bytes.
+.Vt intptr_t
+and
+.Vt void *
+are 16 byte capabilities.
.El
.Pp
Some machines support more than one
@@ -169,12 +195,23 @@ Binaries targeting
and earlier are no longer supported by
.Fx .
.Pp
+Architectures with 128-bit capabilities support both a
+.Dq native
+.Dv L64PC128
+execution environment and a
+.Dv LP64
+environment:
+.Bl -column -offset indent "aarch64c" "LP64 counterpart"
+.It Sy L64PC128 Ta Sy LP64 counterpart
+.It Dv aarch64c Ta Dv aarch64
+.It Dv riscv64c Ta Dv riscv64
+.El
+.Pp
On all supported architectures:
.Bl -column -offset indent "long long" "Size"
.It Sy Type Ta Sy Size
.It short Ta 2
.It int Ta 4
-.It long Ta sizeof(void*)
.It long long Ta 8
.It float Ta 4
.It double Ta 8
@@ -188,17 +225,19 @@ The sole exception is that
requires only 4-byte alignment for 64-bit integers.
.Pp
Machine-dependent type sizes:
-.Bl -column -offset indent "Architecture" "void *" "long double" "time_t"
-.It Sy Architecture Ta Sy void * Ta Sy long double Ta Sy time_t
-.It aarch64 Ta 8 Ta 16 Ta 8
-.It amd64 Ta 8 Ta 16 Ta 8
-.It armv7 Ta 4 Ta 8 Ta 8
-.It i386 Ta 4 Ta 12 Ta 4
-.It powerpc Ta 4 Ta 8 Ta 8
-.It powerpcspe Ta 4 Ta 8 Ta 8
-.It powerpc64 Ta 8 Ta 8 Ta 8
-.It powerpc64le Ta 8 Ta 8 Ta 8
-.It riscv64 Ta 8 Ta 16 Ta 8
+.Bl -column -offset indent "Architecture" "long" "void *" "long double" "time_t"
+.It Sy Architecture Ta Sy long Ta Sy void * Ta Sy long double Ta Sy time_t
+.It aarch64 Ta 8 Ta 8 Ta 16 Ta 8
+.It aarch64c Ta 8 Ta 16 Ta 16 Ta 8
+.It amd64 Ta 8 Ta 8 Ta 16 Ta 8
+.It armv7 Ta 4 Ta 4 Ta 8 Ta 8
+.It i386 Ta 4 Ta 4 Ta 12 Ta 4
+.It powerpc Ta 4 Ta 4 Ta 8 Ta 8
+.It powerpcspe Ta 4 Ta 4 Ta 8 Ta 8
+.It powerpc64 Ta 8 Ta 8 Ta 8 Ta 8
+.It powerpc64le Ta 8 Ta 8 Ta 8 Ta 8
+.It riscv64 Ta 8 Ta 8 Ta 16 Ta 8
+.It riscv64c Ta 8 Ta 16 Ta 16 Ta 8
.El
.Pp
.Sy time_t
@@ -207,6 +246,7 @@ is 8 bytes on all supported architectures except i386.
.Bl -column -offset indent "Architecture" "Endianness" "char Signedness"
.It Sy Architecture Ta Sy Endianness Ta Sy char Signedness
.It aarch64 Ta little Ta unsigned
+.It aarch64c Ta little Ta unsigned
.It amd64 Ta little Ta signed
.It armv7 Ta little Ta unsigned
.It i386 Ta little Ta signed
@@ -215,11 +255,13 @@ is 8 bytes on all supported architectures except i386.
.It powerpc64 Ta big Ta unsigned
.It powerpc64le Ta little Ta unsigned
.It riscv64 Ta little Ta signed
+.It riscv64c Ta little Ta signed
.El
.Ss Page Size
.Bl -column -offset indent "Architecture" "Page Sizes"
.It Sy Architecture Ta Sy Page Sizes
.It aarch64 Ta 4K, 64K, 2M, 1G
+.It aarch64c Ta 4K, 64K, 2M, 1G
.It amd64 Ta 4K, 2M, 1G
.It armv7 Ta 4K, 1M
.It i386 Ta 4K, 2M (PAE), 4M
@@ -228,11 +270,13 @@ is 8 bytes on all supported architectures except i386.
.It powerpc64 Ta 4K
.It powerpc64le Ta 4K
.It riscv64 Ta 4K, 2M, 1G
+.It riscv64c Ta 4K, 2M, 1G
.El
.Ss User Address Space Layout
.Bl -column -offset indent "riscv64 (Sv48)" "0x0001000000000000" "NNNU"
.It Sy Architecture Ta Sy Maximum Address Ta Sy Address Space Size
.It aarch64 Ta 0x0001000000000000 Ta 256TiB
+.It aarch64c Ta 0x0001000000000000 Ta 256TiB
.It amd64 (LA48) Ta 0x0000800000000000 Ta 128TiB
.It amd64 (LA57) Ta 0x0100000000000000 Ta 64PiB
.It armv7 Ta 0xbfc00000 Ta 3GiB
@@ -242,7 +286,9 @@ is 8 bytes on all supported architectures except i386.
.It powerpc64 Ta 0x000fffffc0000000 Ta 4PiB
.It powerpc64le Ta 0x000fffffc0000000 Ta 4PiB
.It riscv64 (Sv39) Ta 0x0000004000000000 Ta 256GiB
+.It riscv64c (Sv39) Ta 0x0000004000000000 Ta 256GiB
.It riscv64 (Sv48) Ta 0x0000800000000000 Ta 128TiB
+.It riscv64c (Sv48) Ta 0x0000800000000000 Ta 128TiB
.El
.Pp
The layout of a process' address space can be queried via the
@@ -287,6 +333,7 @@ currently supports Sv39 and Sv48 and defaults to using Sv39.
.Bl -column -offset indent "Architecture" "float, double" "long double"
.It Sy Architecture Ta Sy float, double Ta Sy long double
.It aarch64 Ta hard Ta soft, quad precision
+.It aarch64c Ta hard Ta soft, quad precision
.It amd64 Ta hard Ta hard, 80 bit
.It armv7 Ta hard Ta hard, double precision
.It i386 Ta hard Ta hard, 80 bit
@@ -295,6 +342,7 @@ currently supports Sv39 and Sv48 and defaults to using Sv39.
.It powerpc64 Ta hard Ta hard, double precision
.It powerpc64le Ta hard Ta hard, double precision
.It riscv64 Ta hard Ta hard, quad precision
+.It riscv64c Ta hard Ta hard, quad precision
.El
.Ss Default Tool Chain
.Fx
@@ -321,12 +369,12 @@ when referring to the kernel, interfaces dependent on a specific type of kernel
or similar things like boot sequences.
.Bl -column -offset indent "Dv MACHINE" "Dv MACHINE_CPUARCH" "Dv MACHINE_ARCH"
.It Dv MACHINE Ta Dv MACHINE_CPUARCH Ta Dv MACHINE_ARCH
-.It arm64 Ta aarch64 Ta aarch64
+.It arm64 Ta aarch64 Ta aarch64, aarch64c
.It amd64 Ta amd64 Ta amd64
.It arm Ta arm Ta armv7
.It i386 Ta i386 Ta i386
.It powerpc Ta powerpc Ta powerpc, powerpcspe, powerpc64, powerpc64le
-.It riscv Ta riscv Ta riscv64
+.It riscv Ta riscv Ta riscv64, riscv64c
.El
.Ss Predefined Macros
The compiler provides a number of predefined macros.
@@ -340,17 +388,40 @@ cc -x c -dM -E /dev/null
.Ed
.Pp
Common type size and endianness macros:
-.Bl -column -offset indent "BYTE_ORDER" "Meaning"
+.Bl -column -offset indent "__SIZEOF_POINTER__" "Meaning"
.It Sy Macro Ta Sy Meaning
+.It Dv __SIZEOF_LONG__ Ta size in bytes of long
+.It Dv __SIZEOF_POINTER__ Ta size in bytes of intptr_t and pointers
+.It Dv __SIZEOF_SIZE_T__ Ta size in bytes of size_t
.It Dv __LP64__ Ta 64-bit (8-byte) long and pointer, 32-bit (4-byte) int
.It Dv __ILP32__ Ta 32-bit (4-byte) int, long and pointer
+.It Dv __CHERI__ Ta 128-bit (16-byte) capability pointer, 64-bit (8-byte) long
.It Dv BYTE_ORDER Ta Either Dv BIG_ENDIAN or Dv LITTLE_ENDIAN .
.El
.Pp
+Because systems were historically either
+.Dv __ILP32__
+or
+.Dv __LP64__
+it has been common for programmers to test only one and assume the other
+one in an else branch.
+With the arrival of CHERI architectures, this is no longer the case.
+.Dv __SIZEOF_*__
+macros should be used instead.
+New uses of
+.Dv __ILP32__
+and
+.Dv __LP64__
+should be avoided.
+Compilers for CHERI targets do not define
+.Dv __LP64__
+as their pointers are 128-bit capabilities.
+.Pp
Architecture-specific macros:
.Bl -column -offset indent "Architecture" "Predefined macros"
.It Sy Architecture Ta Sy Predefined macros
.It aarch64 Ta Dv __aarch64__
+.It aarch64c Ta Dv __aarch64__ , Dv __CHERI__
.It amd64 Ta Dv __amd64__ , Dv __x86_64__
.It armv7 Ta Dv __arm__ , Dv __ARM_ARCH >= 7
.It i386 Ta Dv __i386__
@@ -359,6 +430,7 @@ Architecture-specific macros:
.It powerpc64 Ta Dv __powerpc__ , Dv __powerpc64__
.It powerpc64le Ta Dv __powerpc__ , Dv __powerpc64__
.It riscv64 Ta Dv __riscv , Dv __riscv_xlen == 64
+.It riscv64c Ta Dv __riscv , Dv __riscv_xlen == 64 , Dv __CHERI__
.El
.Pp
Compilers may define additional variants of architecture-specific macros.
generated by cgit v1.2.3 (git 2.25.1) at 2025-10-15 07:57:55 +0000