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-rw-r--r--share/man/man3/snl.32
-rw-r--r--share/man/man4/ice.4122
-rw-r--r--share/man/man5/pf.conf.56
-rw-r--r--share/man/man5/rc.conf.59
-rw-r--r--share/man/man7/arch.7124
5 files changed, 173 insertions, 90 deletions
diff --git a/share/man/man3/snl.3 b/share/man/man3/snl.3
index f678d6cb2cea..04bae46691bf 100644
--- a/share/man/man3/snl.3
+++ b/share/man/man3/snl.3
@@ -288,7 +288,7 @@ main(int ac, char *argv[])
struct nl_parsed_link link = {};
if (!snl_parse_nlmsg(&ss, hdr, &link_parser, &link))
continue;
- printf("Link#%u %s mtu %u\\n", link.ifi_index, link.ifla_ifname, link.ifla_mtu);
+ printf("Link#%u %s mtu %u\en", link.ifi_index, link.ifla_ifname, link.ifla_mtu);
}
return (0);
diff --git a/share/man/man4/ice.4 b/share/man/man4/ice.4
index 3f7a9017756d..c7675e627726 100644
--- a/share/man/man4/ice.4
+++ b/share/man/man4/ice.4
@@ -1,4 +1,4 @@
-.\"-
+.\"
.\" SPDX-License-Identifier: BSD-3-Clause
.\"
.\" Copyright (c) 2019-2020, Intel Corporation
@@ -32,25 +32,35 @@
.\"
.\" * Other names and brands may be claimed as the property of others.
.\"
-.Dd March 28, 2025
+.Dd October 3, 2025
.Dt ICE 4
.Os
.Sh NAME
.Nm ice
-.Nd "Intel\(rg Ethernet 800 Series Driver"
+.Nd Intel Ethernet 800 Series Driver
.Sh SYNOPSIS
-To compile this driver into the kernel, place the following lines in your
-kernel configuration file:
-.Bd -literal -offset indent
.Cd device iflib
.Cd device ice
-.Ed
.Pp
-To load the driver as a module at boot time, place the following lines in
+In
.Xr loader.conf 5 :
-.Bd -literal -offset indent
-if_ice_load="YES"
-.Ed
+.Cd if_ice_load
+.Cd hw.ice.enable_health_events
+.Cd hw.ice.irdma
+.Cd hw.ice.irdma_max_msix
+.Cd hw.ice.debug.enable_tx_fc_filter
+.Cd hw.ice.debug.enable_tx_lldp_filter
+.Cd hw.ice.debug.ice_tx_balance_en
+.Pp
+In
+.Xr sysctl.conf 5
+or
+.Xr loader.conf 5 :
+.Cd dev.ice.#.current_speed
+.Cd dev.ice.#.fw_version
+.Cd dev.ice.#.ddp_version
+.Cd dev.ice.#.pba_number
+.Cd dev.ice.#.hw.mac.*
.Sh DESCRIPTION
.Ss Features
The
@@ -86,7 +96,7 @@ Intel\(rg Ethernet Connection E830\-XXV
.El
.Pp
For questions related to hardware requirements, refer to the documentation
-supplied with your adapter.
+supplied with the adapter.
.Pp
Support for Jumbo Frames is provided via the interface MTU setting.
Selecting an MTU larger than 1500 bytes with the
@@ -134,17 +144,16 @@ See the
.Dq Intel\(rg Ethernet Adapters and Devices User Guide
for more details on DDP and Safe Mode.
.Pp
-If you encounter issues with the DDP package file, you may need to download
-an updated driver or
+If issues are encountered with the DDP package file, an updated driver or
.Sy ice_ddp
-module.
+module may need to be downloaded.
See the log messages for more information.
.Pp
-You cannot update the DDP package if any PF drivers are already loaded.
+The DDP package cannot be updated if any PF drivers are already loaded.
To overwrite a package, unload all PFs and then reload the driver with the
new package.
.Pp
-You can only use one DDP package per driver, even if you have more than one
+Only one DDP package can be used per driver, even if more than one
device installed that uses the driver.
.Pp
Only the first loaded PF per device can download a package for that device.
@@ -164,9 +173,9 @@ each jumbo packet.
This should help to avoid buffer starvation issues when allocating receive
packets.
.Pp
-Packet loss may have a greater impact on throughput when you use jumbo
-frames.
-If you observe a drop in performance after enabling jumbo frames, enabling
+Packet loss may have a greater impact on throughput when jumbo frames are in
+use.
+If a drop in performance is observed after enabling jumbo frames, enabling
flow control may mitigate the issue.
.Ss Remote Direct Memory Access
Remote Direct Memory Access, or RDMA, allows a network device to transfer data
@@ -184,14 +193,14 @@ operating in multiport mode with more than 4 ports.
For detailed installation and configuration information for RDMA, see
.Xr irdma 4 .
.Ss RDMA Monitoring
-For debugging/testing purposes, you can use sysctl to set up a mirroring
+For debugging/testing purposes, a sysctl can be used to set up a mirroring
interface on a port.
The interface can receive mirrored RDMA traffic for packet
analysis tools like
.Xr tcpdump 1 .
This mirroring may impact performance.
.Pp
-To use RDMA monitoring, you may need to reserve more MSI\-X interrupts.
+To use RDMA monitoring, more MSI\-X interrupts may need to be reserved.
Before the
.Nm
driver loads, configure the following tunable provided by
@@ -200,7 +209,7 @@ driver loads, configure the following tunable provided by
dev.ice.<interface #>.iflib.use_extra_msix_vectors=4
.Ed
.Pp
-You may need to adjust the number of extra MSI\-X interrupt vectors.
+The number of extra MSI\-X interrupt vectors may need to be adjusted.
.Pp
To create/delete the interface:
.Bd -literal -offset indent
@@ -276,7 +285,7 @@ To enable/disable priority flow control in software\-based DCBX mode:
sysctl dev.ice.<interface #>.pfc=1 (or 0 to disable)
.Ed
.Pp
-Enhanced Transmission Selection (ETS) allows you to assign bandwidth to certain
+Enhanced Transmission Selection (ETS) allows bandwidth to be assigned to certain
TCs, to help ensure traffic reliability.
To view the assigned ETS configuration, use the following:
.Bd -literal -offset indent
@@ -310,7 +319,7 @@ Use the following sysctl to enable or disable L3 QoS:
sysctl dev.ice.<interface #>.pfc_mode=1 (or 0 to disable)
.Ed
.Pp
-If you disable L3 QoS mode, it returns to L2 QoS mode.
+If the L3 QoS mode is disabled, it returns to L2 QoS mode.
.Pp
To map a DSCP value to a traffic class, separate the values by commas.
For example, to map DSCPs 0\-3 and DSCP 8 to DCB TCs 0\-3 and 4, respectively:
@@ -329,7 +338,7 @@ sysctl dev.ice.<interface #>.dscp2tc_map
.Pp
L3 QoS mode is not available when FW\-LLDP is enabled.
.Pp
-You also cannot enable FW\-LLDP if L3 QoS mode is active.
+FW\-LLDP cannot be enabled if L3 QoS mode is active.
.Pp
Disable FW\-LLDP before switching to L3 QoS mode.
.Pp
@@ -355,11 +364,11 @@ To check the current LLDP setting:
sysctl dev.ice.<interface #>.fw_lldp_agent
.Ed
.Pp
-You must enable the UEFI HII LLDP Agent attribute for this setting
+The UEFI HII LLDP Agent attribute must be enabled for this setting
to take effect.
If the
.Dq LLDP AGENT
-attribute is set to disabled, you cannot enable the FW\-LLDP Agent from the
+attribute is set to disabled, the FW\-LLDP Agent cannot be enabled from the
driver.
.Ss Link\-Level Flow Control (LFC)
Ethernet Flow Control (IEEE 802.3x) can be configured with sysctl to enable
@@ -416,11 +425,11 @@ provide a stable link without FEC.
.Pp
For devices to benefit from this feature, link partners must have FEC enabled.
.Pp
-If you enable the sysctl
-.Em allow_no_fec_modules_in_auto
-Auto FEC negotiation will include
+If the
+.Va allow_no_fec_modules_in_auto
+sysctl is enabled Auto FEC negotiation will include
.Dq No FEC
-in case your link partner does not have FEC enabled or is not FEC capable:
+in case the link partner does not have FEC enabled or is not FEC capable:
.Bd -literal -offset indent
sysctl dev.ice.<interface #>.allow_no_fec_modules_in_auto=1
.Ed
@@ -443,16 +452,16 @@ To see the valid FEC modes for the link:
sysctl \-d dev.ice.<interface #>.requested_fec
.Ed
.Ss Speed and Duplex Configuration
-You cannot set duplex or autonegotiation settings.
+The speed and duplex settings cannot be hard set.
.Pp
-To have your device change the speeds it will use in auto-negotiation or
+To have the device change the speeds it will use in auto-negotiation or
force link with:
.Bd -literal -offset indent
sysctl dev.ice.<interface #>.advertise_speed=<mask>
.Ed
.Pp
Supported speeds will vary by device.
-Depending on the speeds your device supports, valid bits used in a speed mask
+Depending on the speeds the device supports, valid bits used in a speed mask
could include:
.Bd -literal -offset indent
0x0 \- Auto
@@ -493,13 +502,13 @@ At a high level, to capture a firmware log:
.It
Set the configuration for the firmware log.
.It
-Perform the necessary steps to generate the issue you are trying to debug.
+Perform the necessary steps to reproduce the issue.
.It
Capture the firmware log.
.It
Stop capturing the firmware log.
.It
-Reset your firmware log settings as needed.
+Reset the firmware log settings as needed.
.It
Work with Customer Support to debug the issue.
.El
@@ -583,8 +592,8 @@ PF Registration (Bit 30)
Module Version (Bit 31)
.El
.Pp
-You can change the verbosity level of the firmware logs.
-You can set only one log level per module, and each level includes the
+The verbosity level of the firmware logs can be modified.
+It is possible to set only one log level per module, and each level includes the
verbosity levels lower than it.
For instance, setting the level to
.Dq normal
@@ -640,8 +649,8 @@ dmesg > log_output
NOTE: Logging a large number of modules or too high of a verbosity level will
add extraneous messages to dmesg and could hinder debug efforts.
.Ss Debug Dump
-Intel\(rg Ethernet 800 Series devices support debug dump, which allows you to
-obtain runtime register values from the firmware for
+Intel\(rg Ethernet 800 Series devices support debug dump, which allows
+gathering of runtime register values from the firmware for
.Dq clusters
of events and then write the results to a single dump file, for debugging
complicated issues in the field.
@@ -654,7 +663,7 @@ stateless snapshot of the whole device.
.Pp
NOTE: Like with firmware logs, the contents of the debug dump are not
human\-readable.
-You must work with Customer Support to decode the file.
+Work with Customer Support to decode the file.
.Pp
Debug dump is per device, not per PF.
.Pp
@@ -717,20 +726,19 @@ sysctl dev.ice.0.debug.dump.clusters=0
.Pp
NOTE: Using 0 will skip Manageability Transactions data.
.Pp
-If you don't specify a cluster, the driver will dump all clusters to a
+If a single cluster is not specified, the driver will dump all clusters to a
single file.
Issue the debug dump command, using the following:
.Bd -literal -offset indent
sysctl \-b dev.ice.<interface #>.debug.dump.dump=1 > dump.bin
.Ed
.Pp
-NOTE: The driver will not receive the command if you do not write
-.Dq 1
-to the sysctl.
+NOTE: The driver will not receive the command if the sysctl is not set to
+.Dq 1 .
.Pp
Replace
.Dq dump.bin
-above with the file name you want to use.
+above with the preferred file name.
.Pp
To clear the
.Va clusters
@@ -744,7 +752,7 @@ The ice driver supports the ability to obtain the values of the PHY registers
from Intel(R) Ethernet 810 Series devices in order to debug link and
connection issues during runtime.
.Pp
-The driver allows you to obtain information about:
+The driver provides information about:
.Bl -bullet
.It
Rx and Tx Equalization parameters
@@ -758,12 +766,12 @@ sysctl dev.ice.<interface #>.debug.phy_statistics
.Ed
.Pp
NOTE: The contents of the registers are not human\-readable.
-Like with firmware logs and debug dump, you must work with Customer Support
+Like with firmware logs and debug dump, work with Customer Support
to decode the file.
.Ss Transmit Balancing
-Some Intel(R) Ethernet 800 Series devices allow you to enable a transmit
+Some Intel(R) Ethernet 800 Series devices allow for enabling a transmit
balancing feature to improve transmit performance under certain conditions.
-When the feature is enabled, you should experience more consistent transmit
+When enabled, the feature should provide more consistent transmit
performance across queues and/or PFs and VFs.
.Pp
By default, transmit balancing is disabled in the NVM.
@@ -784,7 +792,7 @@ configures the device accordingly.
.Pp
NOTE: The user selection for transmit balancing in EPCT or HII is persistent
across reboots.
-You must reboot the system for the selected setting to take effect.
+The system must be rebooted for the selected setting to take effect.
.Pp
This setting is device wide.
.Pp
@@ -801,7 +809,7 @@ sysctl dev.ice.<interface #>.temp
may have a low number of network memory buffers (mbufs) by default.
If the number of mbufs available is too low, it may cause the driver to fail
to initialize and/or cause the system to become unresponsive.
-You can check to see if the system is mbuf\-starved by running
+Check to see if the system is mbuf\-starved by running
.Ic netstat Fl m .
Increase the number of mbufs by editing the lines below in
.Pa /etc/sysctl.conf :
@@ -813,7 +821,7 @@ kern.ipc.nmbjumbo16
kern.ipc.nmbufs
.Ed
.Pp
-The amount of memory that you allocate is system specific, and may require some
+The amount of memory that should be allocated is system specific, and may require some
trial and error.
Also, increasing the following in
.Pa /etc/sysctl.conf
@@ -908,8 +916,8 @@ link partner's switch ports.
Some PCIe x8 slots are actually configured as x4 slots.
These slots have insufficient bandwidth for full line rate with dual port and
quad port devices.
-In addition, if you put a PCIe v4.0 or v3.0\-capable adapter into a PCIe v2.x
-slot, you cannot get full bandwidth.
+In addition, if a PCIe v4.0 or v3.0\-capable adapter is placed into a PCIe v2.x
+slot, full bandwidth will not be possible.
.Pp
The driver detects this situation and writes the following message in the
system log:
@@ -920,7 +928,7 @@ Please move the device to a different PCI\-e link with more lanes and/or
higher transfer rate.
.Ed
.Pp
-If this error occurs, moving your adapter to a true PCIe x8 or x16 slot will
+If this error occurs, moving the adapter to a true PCIe x8 or x16 slot will
resolve the issue.
For best performance, install devices in the following PCI slots:
.Bl -bullet
diff --git a/share/man/man5/pf.conf.5 b/share/man/man5/pf.conf.5
index da02f10aac01..41410d6bc0fa 100644
--- a/share/man/man5/pf.conf.5
+++ b/share/man/man5/pf.conf.5
@@ -27,7 +27,7 @@
.\" ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
.\" POSSIBILITY OF SUCH DAMAGE.
.\"
-.Dd August 28, 2025
+.Dd October 7, 2025
.Dt PF.CONF 5
.Os
.Sh NAME
@@ -2377,7 +2377,7 @@ packets matching the same connection.
.It Ar route-to
The
.Ar route-to
-option routes the packet to the specified interface with an optional address
+option routes the packet to the specified interface with an address
for the next hop.
When a
.Ar route-to
@@ -3552,7 +3552,7 @@ hosts = "all" |
ipspec = "any" | host | "{" host-list "}"
host = [ "!" ] ( address [ "/" mask-bits ] | "<" string ">" )
redirhost = address [ "/" mask-bits ]
-routehost = "(" interface-name [ address [ "/" mask-bits ] ] ")"
+routehost = "(" interface-name address [ "/" mask-bits ] ")"
address = ( interface-name | interface-group |
"(" ( interface-name | interface-group ) ")" |
hostname | ipv4-dotted-quad | ipv6-coloned-hex )
diff --git a/share/man/man5/rc.conf.5 b/share/man/man5/rc.conf.5
index c0048f27c740..edbfa937f8df 100644
--- a/share/man/man5/rc.conf.5
+++ b/share/man/man5/rc.conf.5
@@ -22,7 +22,7 @@
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
.\" SUCH DAMAGE.
.\"
-.Dd October 2, 2025
+.Dd October 5, 2025
.Dt RC.CONF 5
.Os
.Sh NAME
@@ -4618,8 +4618,11 @@ Set to
to enable waiting for DAD to complete.
.It Va netwait_dad_timeout
.Pq Vt int
-Indicates the total number of seconds to wait for DAD to complete.
-The default is 10.
+Unset by default.
+Indicates the maximum number of seconds to wait for DAD to complete.
+If zero or unset, the timeout will be one more than the value of the
+.Va net.inet6.ip6.dad_count
+sysctl variable.
.It Va rctl_enable
.Pq Vt bool
If set to
diff --git a/share/man/man7/arch.7 b/share/man/man7/arch.7
index 5de441aed699..668f5aa23155 100644
--- a/share/man/man7/arch.7
+++ b/share/man/man7/arch.7
@@ -48,23 +48,35 @@ and later, unless otherwise noted.
.Fx
uses a flat address space.
Variables of types
-.Vt unsigned long ,
-.Vt uintptr_t ,
+.Vt unsigned long
and
.Vt size_t
-and pointers all have the same representation.
+have the same representation.
.Pp
In order to maximize compatibility with future pointer integrity mechanisms,
manipulations of pointers as integers should be performed via
.Vt uintptr_t
or
.Vt intptr_t
-and no other types.
-In particular,
-.Vt long
+and no other types as these types are the only integer types where the
+C standard guarantees that a pointer may be cast to it and then cast back
+to the original type.
+On CHERI systems,
+.Vt uintptr_t
and
-.Vt ptrdiff_t
-should be avoided.
+.Vt intptr_t
+are defined as
+.Vt __uintcap_t
+and
+.Vt __intcap_t
+which represent capabilities that can be manipulated by integer operations.
+Pointers should not be cast to
+.Vt long ,
+.Vt ptrdiff_t ,
+or
+.Vt size_t
+if they will later be cast back to a pointer that is expected to be
+dereferencable as they remain bare integer types on all architectures.
.Pp
On some architectures, e.g.,
AIM variants of
@@ -85,11 +97,13 @@ release to support each architecture.
.Bl -column -offset indent "Architecture" "Initial Release"
.It Sy Architecture Ta Sy Initial Release
.It aarch64 Ta 11.0
+.It aarch64c Ta 16.0 (planned)
.It amd64 Ta 5.1
.It armv7 Ta 12.0
.It powerpc64 Ta 9.0
.It powerpc64le Ta 13.0
.It riscv64 Ta 12.0
+.It riscv64c Ta 16.0 (planned)
.El
.Pp
Discontinued architectures are shown in the following table.
@@ -123,21 +137,33 @@ architectures use some variant of the ELF (see
.Xr elf 5 )
.Sy Application Binary Interface
(ABI) for the machine processor.
-All supported ABIs can be divided into two groups:
-.Bl -tag -width "Dv ILP32"
+Supported ABIs can be divided into three main groups:
+.Bl -tag -width "Dv L64PC128"
.It Dv ILP32
.Vt int ,
+.Vt intptr_t ,
.Vt long ,
+and
.Vt void *
types machine representations all have 4-byte size.
.It Dv LP64
.Vt int
type machine representation uses 4 bytes,
while
-.Vt long
+.Vt intptr_t ,
+.Vt long ,
and
.Vt void *
are 8 bytes.
+.It Dv L64PC128
+.Vt int
+type machine representation uses 4 bytes.
+.Vt long
+type machine representation uses 8 bytes.
+.Vt intptr_t
+and
+.Vt void *
+are 16 byte capabilities.
.El
.Pp
Some machines support more than one
@@ -169,12 +195,23 @@ Binaries targeting
and earlier are no longer supported by
.Fx .
.Pp
+Architectures with 128-bit capabilities support both a
+.Dq native
+.Dv L64PC128
+execution environment and a
+.Dv LP64
+environment:
+.Bl -column -offset indent "aarch64c" "LP64 counterpart"
+.It Sy L64PC128 Ta Sy LP64 counterpart
+.It Dv aarch64c Ta Dv aarch64
+.It Dv riscv64c Ta Dv riscv64
+.El
+.Pp
On all supported architectures:
.Bl -column -offset indent "long long" "Size"
.It Sy Type Ta Sy Size
.It short Ta 2
.It int Ta 4
-.It long Ta sizeof(void*)
.It long long Ta 8
.It float Ta 4
.It double Ta 8
@@ -188,17 +225,19 @@ The sole exception is that
requires only 4-byte alignment for 64-bit integers.
.Pp
Machine-dependent type sizes:
-.Bl -column -offset indent "Architecture" "void *" "long double" "time_t"
-.It Sy Architecture Ta Sy void * Ta Sy long double Ta Sy time_t
-.It aarch64 Ta 8 Ta 16 Ta 8
-.It amd64 Ta 8 Ta 16 Ta 8
-.It armv7 Ta 4 Ta 8 Ta 8
-.It i386 Ta 4 Ta 12 Ta 4
-.It powerpc Ta 4 Ta 8 Ta 8
-.It powerpcspe Ta 4 Ta 8 Ta 8
-.It powerpc64 Ta 8 Ta 8 Ta 8
-.It powerpc64le Ta 8 Ta 8 Ta 8
-.It riscv64 Ta 8 Ta 16 Ta 8
+.Bl -column -offset indent "Architecture" "long" "void *" "long double" "time_t"
+.It Sy Architecture Ta Sy long Ta Sy void * Ta Sy long double Ta Sy time_t
+.It aarch64 Ta 8 Ta 8 Ta 16 Ta 8
+.It aarch64c Ta 8 Ta 16 Ta 16 Ta 8
+.It amd64 Ta 8 Ta 8 Ta 16 Ta 8
+.It armv7 Ta 4 Ta 4 Ta 8 Ta 8
+.It i386 Ta 4 Ta 4 Ta 12 Ta 4
+.It powerpc Ta 4 Ta 4 Ta 8 Ta 8
+.It powerpcspe Ta 4 Ta 4 Ta 8 Ta 8
+.It powerpc64 Ta 8 Ta 8 Ta 8 Ta 8
+.It powerpc64le Ta 8 Ta 8 Ta 8 Ta 8
+.It riscv64 Ta 8 Ta 8 Ta 16 Ta 8
+.It riscv64c Ta 8 Ta 16 Ta 16 Ta 8
.El
.Pp
.Sy time_t
@@ -207,6 +246,7 @@ is 8 bytes on all supported architectures except i386.
.Bl -column -offset indent "Architecture" "Endianness" "char Signedness"
.It Sy Architecture Ta Sy Endianness Ta Sy char Signedness
.It aarch64 Ta little Ta unsigned
+.It aarch64c Ta little Ta unsigned
.It amd64 Ta little Ta signed
.It armv7 Ta little Ta unsigned
.It i386 Ta little Ta signed
@@ -215,11 +255,13 @@ is 8 bytes on all supported architectures except i386.
.It powerpc64 Ta big Ta unsigned
.It powerpc64le Ta little Ta unsigned
.It riscv64 Ta little Ta signed
+.It riscv64c Ta little Ta signed
.El
.Ss Page Size
.Bl -column -offset indent "Architecture" "Page Sizes"
.It Sy Architecture Ta Sy Page Sizes
.It aarch64 Ta 4K, 64K, 2M, 1G
+.It aarch64c Ta 4K, 64K, 2M, 1G
.It amd64 Ta 4K, 2M, 1G
.It armv7 Ta 4K, 1M
.It i386 Ta 4K, 2M (PAE), 4M
@@ -228,11 +270,13 @@ is 8 bytes on all supported architectures except i386.
.It powerpc64 Ta 4K
.It powerpc64le Ta 4K
.It riscv64 Ta 4K, 2M, 1G
+.It riscv64c Ta 4K, 2M, 1G
.El
.Ss User Address Space Layout
.Bl -column -offset indent "riscv64 (Sv48)" "0x0001000000000000" "NNNU"
.It Sy Architecture Ta Sy Maximum Address Ta Sy Address Space Size
.It aarch64 Ta 0x0001000000000000 Ta 256TiB
+.It aarch64c Ta 0x0001000000000000 Ta 256TiB
.It amd64 (LA48) Ta 0x0000800000000000 Ta 128TiB
.It amd64 (LA57) Ta 0x0100000000000000 Ta 64PiB
.It armv7 Ta 0xbfc00000 Ta 3GiB
@@ -242,7 +286,9 @@ is 8 bytes on all supported architectures except i386.
.It powerpc64 Ta 0x000fffffc0000000 Ta 4PiB
.It powerpc64le Ta 0x000fffffc0000000 Ta 4PiB
.It riscv64 (Sv39) Ta 0x0000004000000000 Ta 256GiB
+.It riscv64c (Sv39) Ta 0x0000004000000000 Ta 256GiB
.It riscv64 (Sv48) Ta 0x0000800000000000 Ta 128TiB
+.It riscv64c (Sv48) Ta 0x0000800000000000 Ta 128TiB
.El
.Pp
The layout of a process' address space can be queried via the
@@ -287,6 +333,7 @@ currently supports Sv39 and Sv48 and defaults to using Sv39.
.Bl -column -offset indent "Architecture" "float, double" "long double"
.It Sy Architecture Ta Sy float, double Ta Sy long double
.It aarch64 Ta hard Ta soft, quad precision
+.It aarch64c Ta hard Ta soft, quad precision
.It amd64 Ta hard Ta hard, 80 bit
.It armv7 Ta hard Ta hard, double precision
.It i386 Ta hard Ta hard, 80 bit
@@ -295,6 +342,7 @@ currently supports Sv39 and Sv48 and defaults to using Sv39.
.It powerpc64 Ta hard Ta hard, double precision
.It powerpc64le Ta hard Ta hard, double precision
.It riscv64 Ta hard Ta hard, quad precision
+.It riscv64c Ta hard Ta hard, quad precision
.El
.Ss Default Tool Chain
.Fx
@@ -321,12 +369,12 @@ when referring to the kernel, interfaces dependent on a specific type of kernel
or similar things like boot sequences.
.Bl -column -offset indent "Dv MACHINE" "Dv MACHINE_CPUARCH" "Dv MACHINE_ARCH"
.It Dv MACHINE Ta Dv MACHINE_CPUARCH Ta Dv MACHINE_ARCH
-.It arm64 Ta aarch64 Ta aarch64
+.It arm64 Ta aarch64 Ta aarch64, aarch64c
.It amd64 Ta amd64 Ta amd64
.It arm Ta arm Ta armv7
.It i386 Ta i386 Ta i386
.It powerpc Ta powerpc Ta powerpc, powerpcspe, powerpc64, powerpc64le
-.It riscv Ta riscv Ta riscv64
+.It riscv Ta riscv Ta riscv64, riscv64c
.El
.Ss Predefined Macros
The compiler provides a number of predefined macros.
@@ -340,17 +388,40 @@ cc -x c -dM -E /dev/null
.Ed
.Pp
Common type size and endianness macros:
-.Bl -column -offset indent "BYTE_ORDER" "Meaning"
+.Bl -column -offset indent "__SIZEOF_POINTER__" "Meaning"
.It Sy Macro Ta Sy Meaning
+.It Dv __SIZEOF_LONG__ Ta size in bytes of long
+.It Dv __SIZEOF_POINTER__ Ta size in bytes of intptr_t and pointers
+.It Dv __SIZEOF_SIZE_T__ Ta size in bytes of size_t
.It Dv __LP64__ Ta 64-bit (8-byte) long and pointer, 32-bit (4-byte) int
.It Dv __ILP32__ Ta 32-bit (4-byte) int, long and pointer
+.It Dv __CHERI__ Ta 128-bit (16-byte) capability pointer, 64-bit (8-byte) long
.It Dv BYTE_ORDER Ta Either Dv BIG_ENDIAN or Dv LITTLE_ENDIAN .
.El
.Pp
+Because systems were historically either
+.Dv __ILP32__
+or
+.Dv __LP64__
+it has been common for programmers to test only one and assume the other
+one in an else branch.
+With the arrival of CHERI architectures, this is no longer the case.
+.Dv __SIZEOF_*__
+macros should be used instead.
+New uses of
+.Dv __ILP32__
+and
+.Dv __LP64__
+should be avoided.
+Compilers for CHERI targets do not define
+.Dv __LP64__
+as their pointers are 128-bit capabilities.
+.Pp
Architecture-specific macros:
.Bl -column -offset indent "Architecture" "Predefined macros"
.It Sy Architecture Ta Sy Predefined macros
.It aarch64 Ta Dv __aarch64__
+.It aarch64c Ta Dv __aarch64__ , Dv __CHERI__
.It amd64 Ta Dv __amd64__ , Dv __x86_64__
.It armv7 Ta Dv __arm__ , Dv __ARM_ARCH >= 7
.It i386 Ta Dv __i386__
@@ -359,6 +430,7 @@ Architecture-specific macros:
.It powerpc64 Ta Dv __powerpc__ , Dv __powerpc64__
.It powerpc64le Ta Dv __powerpc__ , Dv __powerpc64__
.It riscv64 Ta Dv __riscv , Dv __riscv_xlen == 64
+.It riscv64c Ta Dv __riscv , Dv __riscv_xlen == 64 , Dv __CHERI__
.El
.Pp
Compilers may define additional variants of architecture-specific macros.
generated by cgit v1.2.3 (git 2.25.1) at 2025-10-08 13:26:57 +0000