diff options
Diffstat (limited to 'sys/contrib/device-tree/include/dt-bindings/clock/starfive,jh7110-crg.h')
| -rw-r--r-- | sys/contrib/device-tree/include/dt-bindings/clock/starfive,jh7110-crg.h | 80 |
1 files changed, 80 insertions, 0 deletions
diff --git a/sys/contrib/device-tree/include/dt-bindings/clock/starfive,jh7110-crg.h b/sys/contrib/device-tree/include/dt-bindings/clock/starfive,jh7110-crg.h index 06257bfd9ac1..467ccab3bfaa 100644 --- a/sys/contrib/device-tree/include/dt-bindings/clock/starfive,jh7110-crg.h +++ b/sys/contrib/device-tree/include/dt-bindings/clock/starfive,jh7110-crg.h @@ -1,11 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0 OR MIT */ /* * Copyright 2022 Emil Renner Berthing <kernel@esmil.dk> + * Copyright 2022 StarFive Technology Co., Ltd. */ #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ #define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ +/* PLL clocks */ +#define JH7110_PLLCLK_PLL0_OUT 0 +#define JH7110_PLLCLK_PLL1_OUT 1 +#define JH7110_PLLCLK_PLL2_OUT 2 +#define JH7110_PLLCLK_END 3 + /* SYSCRG clocks */ #define JH7110_SYSCLK_CPU_ROOT 0 #define JH7110_SYSCLK_CPU_CORE 1 @@ -218,4 +225,77 @@ #define JH7110_AONCLK_END 14 +/* STGCRG clocks */ +#define JH7110_STGCLK_HIFI4_CLK_CORE 0 +#define JH7110_STGCLK_USB0_APB 1 +#define JH7110_STGCLK_USB0_UTMI_APB 2 +#define JH7110_STGCLK_USB0_AXI 3 +#define JH7110_STGCLK_USB0_LPM 4 +#define JH7110_STGCLK_USB0_STB 5 +#define JH7110_STGCLK_USB0_APP_125 6 +#define JH7110_STGCLK_USB0_REFCLK 7 +#define JH7110_STGCLK_PCIE0_AXI_MST0 8 +#define JH7110_STGCLK_PCIE0_APB 9 +#define JH7110_STGCLK_PCIE0_TL 10 +#define JH7110_STGCLK_PCIE1_AXI_MST0 11 +#define JH7110_STGCLK_PCIE1_APB 12 +#define JH7110_STGCLK_PCIE1_TL 13 +#define JH7110_STGCLK_PCIE_SLV_MAIN 14 +#define JH7110_STGCLK_SEC_AHB 15 +#define JH7110_STGCLK_SEC_MISC_AHB 16 +#define JH7110_STGCLK_GRP0_MAIN 17 +#define JH7110_STGCLK_GRP0_BUS 18 +#define JH7110_STGCLK_GRP0_STG 19 +#define JH7110_STGCLK_GRP1_MAIN 20 +#define JH7110_STGCLK_GRP1_BUS 21 +#define JH7110_STGCLK_GRP1_STG 22 +#define JH7110_STGCLK_GRP1_HIFI 23 +#define JH7110_STGCLK_E2_RTC 24 +#define JH7110_STGCLK_E2_CORE 25 +#define JH7110_STGCLK_E2_DBG 26 +#define JH7110_STGCLK_DMA1P_AXI 27 +#define JH7110_STGCLK_DMA1P_AHB 28 + +#define JH7110_STGCLK_END 29 + +/* ISPCRG clocks */ +#define JH7110_ISPCLK_DOM4_APB_FUNC 0 +#define JH7110_ISPCLK_MIPI_RX0_PXL 1 +#define JH7110_ISPCLK_DVP_INV 2 +#define JH7110_ISPCLK_M31DPHY_CFG_IN 3 +#define JH7110_ISPCLK_M31DPHY_REF_IN 4 +#define JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0 5 +#define JH7110_ISPCLK_VIN_APB 6 +#define JH7110_ISPCLK_VIN_SYS 7 +#define JH7110_ISPCLK_VIN_PIXEL_IF0 8 +#define JH7110_ISPCLK_VIN_PIXEL_IF1 9 +#define JH7110_ISPCLK_VIN_PIXEL_IF2 10 +#define JH7110_ISPCLK_VIN_PIXEL_IF3 11 +#define JH7110_ISPCLK_VIN_P_AXI_WR 12 +#define JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C 13 + +#define JH7110_ISPCLK_END 14 + +/* VOUTCRG clocks */ +#define JH7110_VOUTCLK_APB 0 +#define JH7110_VOUTCLK_DC8200_PIX 1 +#define JH7110_VOUTCLK_DSI_SYS 2 +#define JH7110_VOUTCLK_TX_ESC 3 +#define JH7110_VOUTCLK_DC8200_AXI 4 +#define JH7110_VOUTCLK_DC8200_CORE 5 +#define JH7110_VOUTCLK_DC8200_AHB 6 +#define JH7110_VOUTCLK_DC8200_PIX0 7 +#define JH7110_VOUTCLK_DC8200_PIX1 8 +#define JH7110_VOUTCLK_DOM_VOUT_TOP_LCD 9 +#define JH7110_VOUTCLK_DSITX_APB 10 +#define JH7110_VOUTCLK_DSITX_SYS 11 +#define JH7110_VOUTCLK_DSITX_DPI 12 +#define JH7110_VOUTCLK_DSITX_TXESC 13 +#define JH7110_VOUTCLK_MIPITX_DPHY_TXESC 14 +#define JH7110_VOUTCLK_HDMI_TX_MCLK 15 +#define JH7110_VOUTCLK_HDMI_TX_BCLK 16 +#define JH7110_VOUTCLK_HDMI_TX_SYS 17 + +#define JH7110_VOUTCLK_END 18 + #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */ |