aboutsummaryrefslogtreecommitdiff
path: root/sys/contrib/device-tree/src/arm64/freescale/imx8mm-venice-gw73xx.dtsi
diff options
context:
space:
mode:
Diffstat (limited to 'sys/contrib/device-tree/src/arm64/freescale/imx8mm-venice-gw73xx.dtsi')
-rw-r--r--sys/contrib/device-tree/src/arm64/freescale/imx8mm-venice-gw73xx.dtsi40
1 files changed, 27 insertions, 13 deletions
diff --git a/sys/contrib/device-tree/src/arm64/freescale/imx8mm-venice-gw73xx.dtsi b/sys/contrib/device-tree/src/arm64/freescale/imx8mm-venice-gw73xx.dtsi
index 1800c6a4b1fc..2aa6c1090fc7 100644
--- a/sys/contrib/device-tree/src/arm64/freescale/imx8mm-venice-gw73xx.dtsi
+++ b/sys/contrib/device-tree/src/arm64/freescale/imx8mm-venice-gw73xx.dtsi
@@ -104,8 +104,15 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
+ <&gpio1 10 GPIO_ACTIVE_LOW>;
status = "okay";
+
+ tpm@1 {
+ compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";
+ reg = <0x1>;
+ spi-max-frequency = <36000000>;
+ };
};
&gpio1 {
@@ -138,7 +145,6 @@
st,drdy-int-pin = <1>;
interrupt-parent = <&gpio4>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
- interrupt-names = "INT1";
};
};
@@ -173,23 +179,30 @@
pcie@0,0 {
reg = <0x0000 0 0 0 0>;
- #address-cells = <1>;
- #size-cells = <0>;
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
- pcie@1,0 {
+ pcie@0,0 {
reg = <0x0000 0 0 0 0>;
- #address-cells = <1>;
- #size-cells = <0>;
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
- pcie@2,4 {
+ pcie@4,0 {
reg = <0x2000 0 0 0 0>;
- #address-cells = <1>;
- #size-cells = <0>;
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
- eth1: pcie@6,0 {
+ eth1: ethernet@0,0 {
reg = <0x0000 0 0 0 0>;
- #address-cells = <1>;
- #size-cells = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
local-mac-address = [00 00 00 00 00 00];
};
@@ -362,6 +375,7 @@
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6
>;
};