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-rw-r--r--sys/contrib/device-tree/src/arm64/qcom/sm6115.dtsi578
1 files changed, 494 insertions, 84 deletions
diff --git a/sys/contrib/device-tree/src/arm64/qcom/sm6115.dtsi b/sys/contrib/device-tree/src/arm64/qcom/sm6115.dtsi
index 55118577bf92..f9849b8befbf 100644
--- a/sys/contrib/device-tree/src/arm64/qcom/sm6115.dtsi
+++ b/sys/contrib/device-tree/src/arm64/qcom/sm6115.dtsi
@@ -10,6 +10,8 @@
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interconnect/qcom,rpm-icc.h>
+#include <dt-bindings/interconnect/qcom,sm6115.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
@@ -264,6 +266,8 @@
scm: scm {
compatible = "qcom,scm-sm6115", "qcom,scm";
#reset-cells = <1>;
+ interconnects = <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
};
};
@@ -273,6 +277,25 @@
reg = <0 0x80000000 0 0>;
};
+ qup_opp_table: opp-table-qup {
+ compatible = "operating-points-v2";
+
+ opp-75000000 {
+ opp-hz = /bits/ 64 <75000000>;
+ required-opps = <&rpmpd_opp_low_svs>;
+ };
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmpd_opp_svs>;
+ };
+
+ opp-128000000 {
+ opp-hz = /bits/ 64 <128000000>;
+ required-opps = <&rpmpd_opp_nom>;
+ };
+ };
+
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
@@ -341,6 +364,72 @@
};
};
+ rpm: remoteproc {
+ compatible = "qcom,sm6115-rpm-proc", "qcom,rpm-proc";
+
+ glink-edge {
+ compatible = "qcom,glink-rpm";
+
+ interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
+ mboxes = <&apcs_glb 0>;
+
+ rpm_requests: rpm-requests {
+ compatible = "qcom,rpm-sm6115";
+ qcom,glink-channels = "rpm_requests";
+
+ rpmcc: clock-controller {
+ compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc";
+ clocks = <&xo_board>;
+ clock-names = "xo";
+ #clock-cells = <1>;
+ };
+
+ rpmpd: power-controller {
+ compatible = "qcom,sm6115-rpmpd";
+ #power-domain-cells = <1>;
+ operating-points-v2 = <&rpmpd_opp_table>;
+
+ rpmpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ rpmpd_opp_min_svs: opp1 {
+ opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
+ };
+
+ rpmpd_opp_low_svs: opp2 {
+ opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
+ };
+
+ rpmpd_opp_svs: opp3 {
+ opp-level = <RPM_SMD_LEVEL_SVS>;
+ };
+
+ rpmpd_opp_svs_plus: opp4 {
+ opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
+ };
+
+ rpmpd_opp_nom: opp5 {
+ opp-level = <RPM_SMD_LEVEL_NOM>;
+ };
+
+ rpmpd_opp_nom_plus: opp6 {
+ opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
+ };
+
+ rpmpd_opp_turbo: opp7 {
+ opp-level = <RPM_SMD_LEVEL_TURBO>;
+ };
+
+ rpmpd_opp_turbo_plus: opp8 {
+ opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
+ };
+ };
+ };
+ };
+ };
+ };
+
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@@ -440,68 +529,6 @@
};
};
- rpm-glink {
- compatible = "qcom,glink-rpm";
-
- interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
- qcom,rpm-msg-ram = <&rpm_msg_ram>;
- mboxes = <&apcs_glb 0>;
-
- rpm_requests: rpm-requests {
- compatible = "qcom,rpm-sm6115";
- qcom,glink-channels = "rpm_requests";
-
- rpmcc: clock-controller {
- compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc";
- clocks = <&xo_board>;
- clock-names = "xo";
- #clock-cells = <1>;
- };
-
- rpmpd: power-controller {
- compatible = "qcom,sm6115-rpmpd";
- #power-domain-cells = <1>;
- operating-points-v2 = <&rpmpd_opp_table>;
-
- rpmpd_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- rpmpd_opp_min_svs: opp1 {
- opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
- };
-
- rpmpd_opp_low_svs: opp2 {
- opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
- };
-
- rpmpd_opp_svs: opp3 {
- opp-level = <RPM_SMD_LEVEL_SVS>;
- };
-
- rpmpd_opp_svs_plus: opp4 {
- opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
- };
-
- rpmpd_opp_nom: opp5 {
- opp-level = <RPM_SMD_LEVEL_NOM>;
- };
-
- rpmpd_opp_nom_plus: opp6 {
- opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
- };
-
- rpmpd_opp_turbo: opp7 {
- opp-level = <RPM_SMD_LEVEL_TURBO>;
- };
-
- rpmpd_opp_turbo_plus: opp8 {
- opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
- };
- };
- };
- };
- };
-
smp2p-adsp {
compatible = "qcom,smp2p";
qcom,smem = <443>, <429>;
@@ -855,6 +882,43 @@
status = "disabled";
};
+ system_noc: interconnect@1880000 {
+ compatible = "qcom,sm6115-snoc";
+ reg = <0x0 0x01880000 0x0 0x5f080>;
+ clocks = <&gcc GCC_SYS_NOC_CPUSS_AHB_CLK>,
+ <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
+ <&rpmcc RPM_SMD_IPA_CLK>;
+ clock-names = "cpu_axi",
+ "ufs_axi",
+ "usb_axi",
+ "ipa";
+ #interconnect-cells = <2>;
+
+ clk_virt: interconnect-clk {
+ compatible = "qcom,sm6115-clk-virt";
+ #interconnect-cells = <2>;
+ };
+
+ mmrt_virt: interconnect-mmrt {
+ compatible = "qcom,sm6115-mmrt-virt";
+ #interconnect-cells = <2>;
+ };
+
+ mmnrt_virt: interconnect-mmnrt {
+ compatible = "qcom,sm6115-mmnrt-virt";
+ #interconnect-cells = <2>;
+ };
+ };
+
+ config_noc: interconnect@1900000 {
+ compatible = "qcom,sm6115-cnoc";
+ reg = <0x0 0x01900000 0x0 0x6200>;
+ clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>;
+ clock-names = "usb_axi";
+ #interconnect-cells = <2>;
+ };
+
qfprom@1b40000 {
compatible = "qcom,sm6115-qfprom", "qcom,qfprom";
reg = <0x0 0x01b40000 0x0 0x7000>;
@@ -865,6 +929,11 @@
reg = <0x25b 0x1>;
bits = <1 4>;
};
+
+ gpu_speed_bin: gpu-speed-bin@6006 {
+ reg = <0x6006 0x2>;
+ bits = <5 8>;
+ };
};
rng: rng@1b53000 {
@@ -874,6 +943,60 @@
clock-names = "core";
};
+ pmu@1b8e300 {
+ compatible = "qcom,sm6115-cpu-bwmon", "qcom,sdm845-bwmon";
+ reg = <0x0 0x01b8e300 0x0 0x600>;
+ interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
+
+ operating-points-v2 = <&cpu_bwmon_opp_table>;
+ interconnects = <&bimc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
+ &bimc SLAVE_EBI_CH0 RPM_ACTIVE_TAG>;
+
+ cpu_bwmon_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-0 {
+ opp-peak-kBps = <(200 * 4 * 1000)>;
+ };
+
+ opp-1 {
+ opp-peak-kBps = <(300 * 4 * 1000)>;
+ };
+
+ opp-2 {
+ opp-peak-kBps = <(451 * 4 * 1000)>;
+ };
+
+ opp-3 {
+ opp-peak-kBps = <(547 * 4 * 1000)>;
+ };
+
+ opp-4 {
+ opp-peak-kBps = <(681 * 4 * 1000)>;
+ };
+
+ opp-5 {
+ opp-peak-kBps = <(768 * 4 * 1000)>;
+ };
+
+ opp-6 {
+ opp-peak-kBps = <(1017 * 4 * 1000)>;
+ };
+
+ opp-7 {
+ opp-peak-kBps = <(1353 * 4 * 1000)>;
+ };
+
+ opp-8 {
+ opp-peak-kBps = <(1555 * 4 * 1000)>;
+ };
+
+ opp-9 {
+ opp-peak-kBps = <(1804 * 4 * 1000)>;
+ };
+ };
+ };
+
spmi_bus: spmi@1c40000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0 0x01c40000 0x0 0x1100>,
@@ -903,6 +1026,12 @@
#thermal-sensor-cells = <1>;
};
+ bimc: interconnect@4480000 {
+ compatible = "qcom,sm6115-bimc";
+ reg = <0x0 0x04480000 0x0 0x80000>;
+ #interconnect-cells = <2>;
+ };
+
rpm_msg_ram: sram@45f0000 {
compatible = "qcom,rpm-msg-ram";
reg = <0x0 0x045f0000 0x0 0x7000>;
@@ -930,8 +1059,42 @@
<&gcc GCC_SDCC1_ICE_CORE_CLK>;
clock-names = "iface", "core", "xo", "ice";
+ power-domains = <&rpmpd SM6115_VDDCX>;
+ operating-points-v2 = <&sdhc1_opp_table>;
+ interconnects = <&system_noc MASTER_SDCC_1 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_SDCC_1 RPM_ALWAYS_TAG>;
+ interconnect-names = "sdhc-ddr",
+ "cpu-sdhc";
+
bus-width = <8>;
status = "disabled";
+
+ sdhc1_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmpd_opp_low_svs>;
+ opp-peak-kBps = <250000 133320>;
+ opp-avg-kBps = <102400 65000>;
+ };
+
+ opp-192000000 {
+ opp-hz = /bits/ 64 <192000000>;
+ required-opps = <&rpmpd_opp_low_svs>;
+ opp-peak-kBps = <800000 300000>;
+ opp-avg-kBps = <204800 200000>;
+ };
+
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ required-opps = <&rpmpd_opp_svs_plus>;
+ opp-peak-kBps = <800000 300000>;
+ opp-avg-kBps = <204800 200000>;
+ };
+ };
};
sdhc_2: mmc@4784000 {
@@ -952,6 +1115,12 @@
operating-points-v2 = <&sdhc2_opp_table>;
iommus = <&apps_smmu 0x00a0 0x0>;
resets = <&gcc GCC_SDCC2_BCR>;
+ interconnects = <&system_noc MASTER_SDCC_2 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_SDCC_2 RPM_ALWAYS_TAG>;
+ interconnect-names = "sdhc-ddr",
+ "cpu-sdhc";
bus-width = <4>;
qcom,dll-config = <0x0007642c>;
@@ -964,11 +1133,15 @@
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmpd_opp_low_svs>;
+ opp-peak-kBps = <250000 133320>;
+ opp-avg-kBps = <261438 150000>;
};
opp-202000000 {
opp-hz = /bits/ 64 <202000000>;
required-opps = <&rpmpd_opp_nom>;
+ opp-peak-kBps = <800000 300000>;
+ opp-avg-kBps = <261438 300000>;
};
};
};
@@ -978,7 +1151,7 @@
reg = <0x0 0x04804000 0x0 0x3000>, <0x0 0x04810000 0x0 0x8000>;
reg-names = "std", "ice";
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&ufs_mem_phy_lanes>;
+ phys = <&ufs_mem_phy>;
phy-names = "ufsphy";
lanes-per-direction = <1>;
#reset-cells = <1>;
@@ -1019,24 +1192,17 @@
ufs_mem_phy: phy@4807000 {
compatible = "qcom,sm6115-qmp-ufs-phy";
- reg = <0x0 0x04807000 0x0 0x1c4>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ reg = <0x0 0x04807000 0x0 0x1000>;
clocks = <&gcc GCC_UFS_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
clock-names = "ref", "ref_aux";
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
- status = "disabled";
- ufs_mem_phy_lanes: phy@4807400 {
- reg = <0x0 0x04807400 0x0 0x098>,
- <0x0 0x04807600 0x0 0x130>,
- <0x0 0x04807c00 0x0 0x16c>;
- #phy-cells = <0>;
- };
+ #phy-cells = <0>;
+
+ status = "disabled";
};
gpi_dma0: dma-controller@4a00000 {
@@ -1052,7 +1218,7 @@
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
- dma-channels = <10>;
+ dma-channels = <10>;
dma-channel-mask = <0xf>;
iommus = <&apps_smmu 0xf6 0x0>;
#dma-cells = <3>;
@@ -1082,6 +1248,15 @@
dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
<&gpi_dma0 1 0 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1098,6 +1273,15 @@
dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
<&gpi_dma0 1 0 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1114,6 +1298,15 @@
dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
<&gpi_dma0 1 1 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1130,6 +1323,15 @@
dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
<&gpi_dma0 1 1 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1146,6 +1348,15 @@
dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
<&gpi_dma0 1 2 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1162,6 +1373,15 @@
dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
<&gpi_dma0 1 2 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1178,6 +1398,15 @@
dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
<&gpi_dma0 1 3 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1194,11 +1423,37 @@
dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
<&gpi_dma0 1 3 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
+ uart3: serial@4a8c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04a8c000 0x0 0x4000>;
+ interrupts-extended = <&intc GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ clock-names = "se";
+ power-domains = <&rpmpd SM6115_VDDCX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+ status = "disabled";
+ };
+
i2c4: i2c@4a90000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x04a90000 0x0 0x4000>;
@@ -1210,6 +1465,15 @@
dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
<&gpi_dma0 1 4 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1226,6 +1490,15 @@
dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
<&gpi_dma0 1 4 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1237,6 +1510,12 @@
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
status = "disabled";
};
@@ -1251,6 +1530,15 @@
dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
<&gpi_dma0 1 5 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1267,6 +1555,15 @@
dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
<&gpi_dma0 1 5 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1298,6 +1595,14 @@
resets = <&gcc GCC_USB30_PRIM_BCR>;
power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
+ /* TODO: USB<->IPA path */
+ interconnects = <&system_noc MASTER_USB3 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_USB3 RPM_ALWAYS_TAG>;
+ interconnect-names = "usb-ddr",
+ "apps-usb";
+
qcom,select-utmi-as-pipe-clk;
status = "disabled";
@@ -1316,6 +1621,104 @@
};
};
+ gpu: gpu@5900000 {
+ compatible = "qcom,adreno-610.0", "qcom,adreno";
+ reg = <0x0 0x05900000 0x0 0x40000>;
+ reg-names = "kgsl_3d0_reg_memory";
+
+ /* There's no (real) GMU, so we have to handle quite a bunch of clocks! */
+ clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
+ <&gpucc GPU_CC_AHB_CLK>,
+ <&gcc GCC_BIMC_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>;
+ clock-names = "core",
+ "iface",
+ "mem_iface",
+ "alt_mem_iface",
+ "gmu",
+ "xo";
+
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+
+ iommus = <&adreno_smmu 0 1>;
+ operating-points-v2 = <&gpu_opp_table>;
+ power-domains = <&rpmpd SM6115_VDDCX>;
+ qcom,gmu = <&gmu_wrapper>;
+
+ nvmem-cells = <&gpu_speed_bin>;
+ nvmem-cell-names = "speed_bin";
+
+ status = "disabled";
+
+ zap-shader {
+ memory-region = <&pil_gpu_mem>;
+ };
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-320000000 {
+ opp-hz = /bits/ 64 <320000000>;
+ required-opps = <&rpmpd_opp_low_svs>;
+ opp-supported-hw = <0x1f>;
+ };
+
+ opp-465000000 {
+ opp-hz = /bits/ 64 <465000000>;
+ required-opps = <&rpmpd_opp_svs>;
+ opp-supported-hw = <0x1f>;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ required-opps = <&rpmpd_opp_svs_plus>;
+ opp-supported-hw = <0x1f>;
+ };
+
+ opp-745000000 {
+ opp-hz = /bits/ 64 <745000000>;
+ required-opps = <&rpmpd_opp_nom>;
+ opp-supported-hw = <0xf>;
+ };
+
+ opp-820000000 {
+ opp-hz = /bits/ 64 <820000000>;
+ required-opps = <&rpmpd_opp_nom_plus>;
+ opp-supported-hw = <0x7>;
+ };
+
+ opp-900000000 {
+ opp-hz = /bits/ 64 <900000000>;
+ required-opps = <&rpmpd_opp_turbo>;
+ opp-supported-hw = <0x7>;
+ };
+
+ /* Speed bin 2 can reach 950 Mhz instead of 980 like the rest. */
+ opp-950000000 {
+ opp-hz = /bits/ 64 <950000000>;
+ required-opps = <&rpmpd_opp_turbo_plus>;
+ opp-supported-hw = <0x4>;
+ };
+
+ opp-980000000 {
+ opp-hz = /bits/ 64 <980000000>;
+ required-opps = <&rpmpd_opp_turbo_plus>;
+ opp-supported-hw = <0x3>;
+ };
+ };
+ };
+
+ gmu_wrapper: gmu@596a000 {
+ compatible = "qcom,adreno-gmu-wrapper";
+ reg = <0x0 0x0596a000 0x0 0x30000>;
+ reg-names = "gmu";
+ power-domains = <&gpucc GPU_CX_GDSC>,
+ <&gpucc GPU_GX_GDSC>;
+ power-domain-names = "cx", "gx";
+ };
+
gpucc: clock-controller@5990000 {
compatible = "qcom,sm6115-gpucc";
reg = <0x0 0x05990000 0x0 0x9000>;
@@ -1371,6 +1774,13 @@
iommus = <&apps_smmu 0x420 0x2>,
<&apps_smmu 0x421 0x0>;
+ interconnects = <&mmrt_virt MASTER_MDP_PORT0 RPM_ALWAYS_TAG
+ &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
+ <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_DISPLAY_CFG RPM_ALWAYS_TAG>;
+ interconnect-names = "mdp0-mem",
+ "cpu-cfg";
+
#address-cells = <2>;
#size-cells = <2>;
ranges;
@@ -2459,54 +2869,54 @@
compatible = "arm,armv7-timer-mem";
reg = <0x0 0x0f120000 0x0 0x1000>;
#address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x0 0x0 0x20000000>;
clock-frequency = <19200000>;
frame@f121000 {
- reg = <0x0 0x0f121000 0x0 0x1000>, <0x0 0x0f122000 0x0 0x1000>;
+ reg = <0x0 0x0f121000 0x1000>, <0x0 0x0f122000 0x1000>;
frame-number = <0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
frame@f123000 {
- reg = <0x0 0x0f123000 0x0 0x1000>;
+ reg = <0x0 0x0f123000 0x1000>;
frame-number = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
frame@f124000 {
- reg = <0x0 0x0f124000 0x0 0x1000>;
+ reg = <0x0 0x0f124000 0x1000>;
frame-number = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
frame@f125000 {
- reg = <0x0 0x0f125000 0x0 0x1000>;
+ reg = <0x0 0x0f125000 0x1000>;
frame-number = <3>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
frame@f126000 {
- reg = <0x0 0x0f126000 0x0 0x1000>;
+ reg = <0x0 0x0f126000 0x1000>;
frame-number = <4>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
frame@f127000 {
- reg = <0x0 0x0f127000 0x0 0x1000>;
+ reg = <0x0 0x0f127000 0x1000>;
frame-number = <5>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
frame@f128000 {
- reg = <0x0 0x0f128000 0x0 0x1000>;
+ reg = <0x0 0x0f128000 0x1000>;
frame-number = <6>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-16 22:55:32 +0000