diff options
Diffstat (limited to 'sys/contrib/device-tree/src/arm64/renesas/rzg2lc-smarc.dtsi')
| -rw-r--r-- | sys/contrib/device-tree/src/arm64/renesas/rzg2lc-smarc.dtsi | 34 |
1 files changed, 33 insertions, 1 deletions
diff --git a/sys/contrib/device-tree/src/arm64/renesas/rzg2lc-smarc.dtsi b/sys/contrib/device-tree/src/arm64/renesas/rzg2lc-smarc.dtsi index 6818fd49b2be..859bc8745e66 100644 --- a/sys/contrib/device-tree/src/arm64/renesas/rzg2lc-smarc.dtsi +++ b/sys/contrib/device-tree/src/arm64/renesas/rzg2lc-smarc.dtsi @@ -11,7 +11,6 @@ #include "rzg2lc-smarc-pinfunction.dtsi" #include "rz-smarc-common.dtsi" - / { aliases { serial1 = &scif1; @@ -127,8 +126,41 @@ #sound-dai-cells = <0>; reg = <0x1a>; }; + + versa3: clock-generator@68 { + compatible = "renesas,5p35023"; + reg = <0x68>; + #clock-cells = <1>; + clocks = <&x1>; + + renesas,settings = [ + 80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf + 00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6 + 80 b0 45 c4 95 + ]; + + assigned-clocks = <&versa3 0>, <&versa3 1>, + <&versa3 2>, <&versa3 3>, + <&versa3 4>, <&versa3 5>; + assigned-clock-rates = <24000000>, <11289600>, + <11289600>, <12000000>, + <25000000>, <12288000>; + }; }; +#if PMOD_MTU3 +&mtu3 { + pinctrl-0 = <&mtu3_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&spi1 { + status = "disabled"; +}; +#endif + /* * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board * SW1 should be at position 2->3 so that SER0_CTS# line is activated |