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-rw-r--r--sys/dev/e1000/e1000_82575.c42
-rw-r--r--sys/dev/e1000/e1000_api.c4
-rw-r--r--sys/dev/e1000/e1000_base.c5
-rw-r--r--sys/dev/e1000/e1000_defines.h1
-rw-r--r--sys/dev/e1000/e1000_hw.h4
-rw-r--r--sys/dev/e1000/e1000_i210.c14
-rw-r--r--sys/dev/e1000/e1000_osdep.c10
-rw-r--r--sys/dev/e1000/e1000_osdep.h6
-rw-r--r--sys/dev/e1000/e1000_phy.c7
-rw-r--r--sys/dev/e1000/em_txrx.c103
-rw-r--r--sys/dev/e1000/if_em.c1624
-rw-r--r--sys/dev/e1000/if_em.h29
-rw-r--r--sys/dev/e1000/igb_txrx.c78
13 files changed, 1305 insertions, 622 deletions
diff --git a/sys/dev/e1000/e1000_82575.c b/sys/dev/e1000/e1000_82575.c
index fded5dc2b04e..47b8006314f8 100644
--- a/sys/dev/e1000/e1000_82575.c
+++ b/sys/dev/e1000/e1000_82575.c
@@ -1686,14 +1686,10 @@ static s32 e1000_get_media_type_82575(struct e1000_hw *hw)
break;
}
- /* do not change link mode for 100BaseFX */
- if (dev_spec->eth_flags.e100_base_fx)
- break;
-
/* change current link mode setting */
ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
- if (hw->phy.media_type == e1000_media_type_copper)
+ if (dev_spec->sgmii_active)
ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
else
ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
@@ -1701,6 +1697,9 @@ static s32 e1000_get_media_type_82575(struct e1000_hw *hw)
E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
break;
+ default:
+ DEBUGOUT("e1000_get_media_type_82575 unknown link type\n");
+ break;
}
return ret_val;
@@ -1750,24 +1749,27 @@ static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
/* Check if there is some SFP module plugged and powered */
if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
- (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
+ (tranceiver_type == E1000_SFF_IDENTIFIER_SFF))
dev_spec->module_plugged = true;
- if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
- hw->phy.media_type = e1000_media_type_internal_serdes;
- } else if (eth_flags->e100_base_fx) {
- dev_spec->sgmii_active = true;
- hw->phy.media_type = e1000_media_type_internal_serdes;
- } else if (eth_flags->e1000_base_t) {
- dev_spec->sgmii_active = true;
- hw->phy.media_type = e1000_media_type_copper;
- } else {
- hw->phy.media_type = e1000_media_type_unknown;
- DEBUGOUT("PHY module has not been recognized\n");
- goto out;
- }
+ else
+ DEBUGOUT("PHY module is not SFP/SFF %x\n", tranceiver_type);
+
+ if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
+ hw->phy.media_type = e1000_media_type_internal_serdes;
+ DEBUGOUT("PHY module is 1000_base_lxsx\n");
+ } else if (eth_flags->e100_base_fx || eth_flags->e100_base_lx) {
+ dev_spec->sgmii_active = true;
+ hw->phy.media_type = e1000_media_type_internal_serdes;
+ DEBUGOUT("PHY module is 100_base_fxlx\n");
+ } else if (eth_flags->e1000_base_t) {
+ dev_spec->sgmii_active = true;
+ hw->phy.media_type = e1000_media_type_copper;
+ DEBUGOUT("PHY module is 1000_base_t\n");
} else {
hw->phy.media_type = e1000_media_type_unknown;
+ DEBUGOUT("PHY module has not been recognized\n");
}
+
ret_val = E1000_SUCCESS;
out:
/* Restore I2C interface setting */
@@ -2425,7 +2427,7 @@ static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
}
if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
- /* if chekcsums compatibility bit is set validate checksums
+ /* if checksums compatibility bit is set validate checksums
* for all 4 ports. */
eeprom_regions_count = 4;
}
diff --git a/sys/dev/e1000/e1000_api.c b/sys/dev/e1000/e1000_api.c
index cace8e563331..6c6cb999f29f 100644
--- a/sys/dev/e1000/e1000_api.c
+++ b/sys/dev/e1000/e1000_api.c
@@ -338,6 +338,8 @@ s32 e1000_set_mac_type(struct e1000_hw *hw)
case E1000_DEV_ID_PCH_ADL_I219_V16:
case E1000_DEV_ID_PCH_ADL_I219_LM17:
case E1000_DEV_ID_PCH_ADL_I219_V17:
+ case E1000_DEV_ID_PCH_ADL_I219_LM19:
+ case E1000_DEV_ID_PCH_ADL_I219_V19:
case E1000_DEV_ID_PCH_RPL_I219_LM22:
case E1000_DEV_ID_PCH_RPL_I219_V22:
case E1000_DEV_ID_PCH_RPL_I219_LM23:
@@ -346,8 +348,6 @@ s32 e1000_set_mac_type(struct e1000_hw *hw)
break;
case E1000_DEV_ID_PCH_MTP_I219_LM18:
case E1000_DEV_ID_PCH_MTP_I219_V18:
- case E1000_DEV_ID_PCH_MTP_I219_LM19:
- case E1000_DEV_ID_PCH_MTP_I219_V19:
case E1000_DEV_ID_PCH_LNL_I219_LM20:
case E1000_DEV_ID_PCH_LNL_I219_V20:
case E1000_DEV_ID_PCH_LNL_I219_LM21:
diff --git a/sys/dev/e1000/e1000_base.c b/sys/dev/e1000/e1000_base.c
index ff810821d9e9..ae44a0b91aac 100644
--- a/sys/dev/e1000/e1000_base.c
+++ b/sys/dev/e1000/e1000_base.c
@@ -137,7 +137,7 @@ void e1000_power_down_phy_copper_base(struct e1000_hw *hw)
return;
/* If the management interface is not enabled, then power down */
- if (phy->ops.check_reset_block(hw))
+ if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))
e1000_power_down_phy_copper(hw);
}
@@ -162,7 +162,8 @@ void e1000_rx_fifo_flush_base(struct e1000_hw *hw)
rfctl |= E1000_RFCTL_IPV6_EX_DIS;
E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
- if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
+ if (hw->mac.type != e1000_82575 ||
+ !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
return;
/* Disable all Rx queues */
diff --git a/sys/dev/e1000/e1000_defines.h b/sys/dev/e1000/e1000_defines.h
index 92f676932636..f1b1008764a1 100644
--- a/sys/dev/e1000/e1000_defines.h
+++ b/sys/dev/e1000/e1000_defines.h
@@ -130,7 +130,6 @@
#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
-#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
#define E1000_RXDEXT_STATERR_TST 0x00000100 /* Time Stamp taken */
#define E1000_RXDEXT_STATERR_LB 0x00040000
diff --git a/sys/dev/e1000/e1000_hw.h b/sys/dev/e1000/e1000_hw.h
index f17877f3e463..b4a9592cd89b 100644
--- a/sys/dev/e1000/e1000_hw.h
+++ b/sys/dev/e1000/e1000_hw.h
@@ -172,8 +172,8 @@ struct e1000_hw;
#define E1000_DEV_ID_PCH_ADL_I219_V17 0x1A1D
#define E1000_DEV_ID_PCH_MTP_I219_LM18 0x550A
#define E1000_DEV_ID_PCH_MTP_I219_V18 0x550B
-#define E1000_DEV_ID_PCH_MTP_I219_LM19 0x550C
-#define E1000_DEV_ID_PCH_MTP_I219_V19 0x550D
+#define E1000_DEV_ID_PCH_ADL_I219_LM19 0x550C
+#define E1000_DEV_ID_PCH_ADL_I219_V19 0x550D
#define E1000_DEV_ID_PCH_LNL_I219_LM20 0x550E
#define E1000_DEV_ID_PCH_LNL_I219_V20 0x550F
#define E1000_DEV_ID_PCH_LNL_I219_LM21 0x5510
diff --git a/sys/dev/e1000/e1000_i210.c b/sys/dev/e1000/e1000_i210.c
index c7ca56914dba..4005034d7d31 100644
--- a/sys/dev/e1000/e1000_i210.c
+++ b/sys/dev/e1000/e1000_i210.c
@@ -362,7 +362,7 @@ s32 e1000_read_invm_version(struct e1000_hw *hw,
E1000_INVM_RECORD_SIZE_IN_BYTES);
u32 buffer[E1000_INVM_SIZE];
s32 status = -E1000_ERR_INVM_VALUE_NOT_FOUND;
- u16 version = 0;
+ u16 nvm_version = 0;
DEBUGFUNC("e1000_read_invm_version");
@@ -379,14 +379,14 @@ s32 e1000_read_invm_version(struct e1000_hw *hw,
/* Check if we have first version location used */
if ((i == 1) && ((*record & E1000_INVM_VER_FIELD_ONE) == 0)) {
- version = 0;
+ nvm_version = 0;
status = E1000_SUCCESS;
break;
}
/* Check if we have second version location used */
else if ((i == 1) &&
((*record & E1000_INVM_VER_FIELD_TWO) == 0)) {
- version = (*record & E1000_INVM_VER_FIELD_ONE) >> 3;
+ nvm_version = (*record & E1000_INVM_VER_FIELD_ONE) >> 3;
status = E1000_SUCCESS;
break;
}
@@ -397,7 +397,7 @@ s32 e1000_read_invm_version(struct e1000_hw *hw,
else if ((((*record & E1000_INVM_VER_FIELD_ONE) == 0) &&
((*record & 0x3) == 0)) || (((*record & 0x3) != 0) &&
(i != 1))) {
- version = (*next_record & E1000_INVM_VER_FIELD_TWO)
+ nvm_version = (*next_record & E1000_INVM_VER_FIELD_TWO)
>> 13;
status = E1000_SUCCESS;
break;
@@ -408,16 +408,16 @@ s32 e1000_read_invm_version(struct e1000_hw *hw,
*/
else if (((*record & E1000_INVM_VER_FIELD_TWO) == 0) &&
((*record & 0x3) == 0)) {
- version = (*record & E1000_INVM_VER_FIELD_ONE) >> 3;
+ nvm_version = (*record & E1000_INVM_VER_FIELD_ONE) >> 3;
status = E1000_SUCCESS;
break;
}
}
if (status == E1000_SUCCESS) {
- invm_ver->invm_major = (version & E1000_INVM_MAJOR_MASK)
+ invm_ver->invm_major = (nvm_version & E1000_INVM_MAJOR_MASK)
>> E1000_INVM_MAJOR_SHIFT;
- invm_ver->invm_minor = version & E1000_INVM_MINOR_MASK;
+ invm_ver->invm_minor = nvm_version & E1000_INVM_MINOR_MASK;
}
/* Read Image Type */
for (i = 1; i < invm_blocks; i++) {
diff --git a/sys/dev/e1000/e1000_osdep.c b/sys/dev/e1000/e1000_osdep.c
index 8016ee352068..8b598f18cf12 100644
--- a/sys/dev/e1000/e1000_osdep.c
+++ b/sys/dev/e1000/e1000_osdep.c
@@ -34,6 +34,16 @@
#include "e1000_api.h"
+int e1000_use_pause_delay = 0;
+
+static void
+e1000_enable_pause_delay(void *use_pause_delay)
+{
+ *((int *)use_pause_delay) = 1;
+}
+
+SYSINIT(enable_pause_delay, SI_SUB_CLOCKS, SI_ORDER_ANY, e1000_enable_pause_delay, &e1000_use_pause_delay);
+
/*
* NOTE: the following routines using the e1000
* naming style are provided to the shared
diff --git a/sys/dev/e1000/e1000_osdep.h b/sys/dev/e1000/e1000_osdep.h
index bddb97afd8b9..893979025f01 100644
--- a/sys/dev/e1000/e1000_osdep.h
+++ b/sys/dev/e1000/e1000_osdep.h
@@ -79,9 +79,11 @@ ms_scale(int x) {
}
}
+extern int e1000_use_pause_delay;
+
static inline void
safe_pause_us(int x) {
- if (cold) {
+ if (!e1000_use_pause_delay) {
DELAY(x);
} else {
pause("e1000_delay", max(1, x/(1000000/hz)));
@@ -90,7 +92,7 @@ safe_pause_us(int x) {
static inline void
safe_pause_ms(int x) {
- if (cold) {
+ if (!e1000_use_pause_delay) {
DELAY(x*1000);
} else {
pause("e1000_delay", ms_scale(x));
diff --git a/sys/dev/e1000/e1000_phy.c b/sys/dev/e1000/e1000_phy.c
index 0aaf32125bbe..c34897e3b31a 100644
--- a/sys/dev/e1000/e1000_phy.c
+++ b/sys/dev/e1000/e1000_phy.c
@@ -1037,7 +1037,7 @@ static s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
break;
case e1000_ms_auto:
phy_data &= ~CR_1000T_MS_ENABLE;
- /* FALLTHROUGH */
+ break;
default:
break;
}
@@ -1707,9 +1707,10 @@ s32 e1000_setup_copper_link_generic(struct e1000_hw *hw)
* autonegotiation.
*/
ret_val = e1000_copper_link_autoneg(hw);
- if (ret_val)
+ if (ret_val && !hw->mac.forced_speed_duplex)
return ret_val;
- } else {
+ }
+ if (!hw->mac.autoneg || (ret_val && hw->mac.forced_speed_duplex)) {
/* PHY will be set to 10H, 10F, 100H or 100F
* depending on user settings.
*/
diff --git a/sys/dev/e1000/em_txrx.c b/sys/dev/e1000/em_txrx.c
index eec198df7466..ced8d0f41d14 100644
--- a/sys/dev/e1000/em_txrx.c
+++ b/sys/dev/e1000/em_txrx.c
@@ -43,29 +43,26 @@
/*********************************************************************
* Local Function prototypes
*********************************************************************/
-static int em_tso_setup(struct e1000_softc *sc, if_pkt_info_t pi,
- uint32_t *txd_upper, uint32_t *txd_lower);
-static int em_transmit_checksum_setup(struct e1000_softc *sc,
- if_pkt_info_t pi, uint32_t *txd_upper, uint32_t *txd_lower);
-static int em_isc_txd_encap(void *arg, if_pkt_info_t pi);
-static void em_isc_txd_flush(void *arg, uint16_t txqid, qidx_t pidx);
-static int em_isc_txd_credits_update(void *arg, uint16_t txqid, bool clear);
-static void em_isc_rxd_refill(void *arg, if_rxd_update_t iru);
-static void em_isc_rxd_flush(void *arg, uint16_t rxqid, uint8_t flid __unused,
- qidx_t pidx);
-static int em_isc_rxd_available(void *arg, uint16_t rxqid, qidx_t idx,
- qidx_t budget);
-static int em_isc_rxd_pkt_get(void *arg, if_rxd_info_t ri);
-
-static void lem_isc_rxd_refill(void *arg, if_rxd_update_t iru);
-
-static int lem_isc_rxd_available(void *arg, uint16_t rxqid, qidx_t idx,
- qidx_t budget);
-static int lem_isc_rxd_pkt_get(void *arg, if_rxd_info_t ri);
+static int em_tso_setup(struct e1000_softc *, if_pkt_info_t, uint32_t *,
+ uint32_t *);
+static int em_transmit_checksum_setup(struct e1000_softc *, if_pkt_info_t,
+ uint32_t *, uint32_t *);
+static int em_isc_txd_encap(void *, if_pkt_info_t);
+static void em_isc_txd_flush(void *, uint16_t, qidx_t);
+static int em_isc_txd_credits_update(void *, uint16_t, bool);
+static void em_isc_rxd_refill(void *, if_rxd_update_t);
+static void em_isc_rxd_flush(void *, uint16_t, uint8_t, qidx_t);
+static int em_isc_rxd_available(void *, uint16_t, qidx_t, qidx_t);
+static int em_isc_rxd_pkt_get(void *, if_rxd_info_t);
+
+static void lem_isc_rxd_refill(void *, if_rxd_update_t);
+
+static int lem_isc_rxd_available(void *, uint16_t, qidx_t, qidx_t);
+static int lem_isc_rxd_pkt_get(void *, if_rxd_info_t);
static void em_receive_checksum(uint16_t, uint8_t, if_rxd_info_t);
-static int em_determine_rsstype(uint32_t pkt_info);
-extern int em_intr(void *arg);
+static int em_determine_rsstype(uint32_t);
+extern int em_intr(void *);
struct if_txrx em_txrx = {
.ift_txd_encap = em_isc_txd_encap,
@@ -111,16 +108,19 @@ em_dump_rs(struct e1000_softc *sc)
cur = txr->tx_rsq[rs_cidx];
status = txr->tx_base[cur].upper.fields.status;
if (!(status & E1000_TXD_STAT_DD))
- printf("qid[%d]->tx_rsq[%d]: %d clear ", qid, rs_cidx, cur);
+ printf("qid[%d]->tx_rsq[%d]: %d clear ",
+ qid, rs_cidx, cur);
} else {
rs_cidx = (rs_cidx-1)&(ntxd-1);
cur = txr->tx_rsq[rs_cidx];
- printf("qid[%d]->tx_rsq[rs_cidx-1=%d]: %d ", qid, rs_cidx, cur);
+ printf("qid[%d]->tx_rsq[rs_cidx-1=%d]: %d ",
+ qid, rs_cidx, cur);
}
printf("cidx_prev=%d rs_pidx=%d ",txr->tx_cidx_processed,
txr->tx_rs_pidx);
for (i = 0; i < ntxd; i++) {
- if (txr->tx_base[i].upper.fields.status & E1000_TXD_STAT_DD)
+ if (txr->tx_base[i].upper.fields.status &
+ E1000_TXD_STAT_DD)
printf("%d set ", i);
}
printf("\n");
@@ -146,8 +146,8 @@ em_tso_setup(struct e1000_softc *sc, if_pkt_info_t pi, uint32_t *txd_upper,
hdr_len = pi->ipi_ehdrlen + pi->ipi_ip_hlen + pi->ipi_tcp_hlen;
*txd_lower = (E1000_TXD_CMD_DEXT | /* Extended descr type */
- E1000_TXD_DTYP_D | /* Data descr type */
- E1000_TXD_CMD_TSE); /* Do TSE on this packet */
+ E1000_TXD_DTYP_D | /* Data descr type */
+ E1000_TXD_CMD_TSE); /* Do TSE on this packet */
cur = pi->ipi_pidx;
TXD = (struct e1000_context_desc *)&txr->tx_base[cur];
@@ -160,7 +160,8 @@ em_tso_setup(struct e1000_softc *sc, if_pkt_info_t pi, uint32_t *txd_upper,
switch(pi->ipi_etype) {
case ETHERTYPE_IP:
/* IP and/or TCP header checksum calculation and insertion. */
- *txd_upper = (E1000_TXD_POPTS_IXSM | E1000_TXD_POPTS_TXSM) << 8;
+ *txd_upper =
+ (E1000_TXD_POPTS_IXSM | E1000_TXD_POPTS_TXSM) << 8;
TXD->lower_setup.ip_fields.ipcse =
htole16(pi->ipi_ehdrlen + pi->ipi_ip_hlen - 1);
@@ -186,7 +187,8 @@ em_tso_setup(struct e1000_softc *sc, if_pkt_info_t pi, uint32_t *txd_upper,
TXD->upper_setup.tcp_fields.tucss = pi->ipi_ehdrlen + pi->ipi_ip_hlen;
TXD->upper_setup.tcp_fields.tucse = 0;
TXD->upper_setup.tcp_fields.tucso =
- pi->ipi_ehdrlen + pi->ipi_ip_hlen + offsetof(struct tcphdr, th_sum);
+ pi->ipi_ehdrlen + pi->ipi_ip_hlen +
+ offsetof(struct tcphdr, th_sum);
/*
* Payload size per packet w/o any headers.
@@ -214,8 +216,8 @@ em_tso_setup(struct e1000_softc *sc, if_pkt_info_t pi, uint32_t *txd_upper,
if (++cur == scctx->isc_ntxd[0]) {
cur = 0;
}
- DPRINTF(iflib_get_dev(sc->ctx), "%s: pidx: %d cur: %d\n", __FUNCTION__,
- pi->ipi_pidx, cur);
+ DPRINTF(iflib_get_dev(sc->ctx), "%s: pidx: %d cur: %d\n",
+ __FUNCTION__, pi->ipi_pidx, cur);
return (cur);
}
@@ -280,8 +282,8 @@ em_transmit_checksum_setup(struct e1000_softc *sc, if_pkt_info_t pi,
* ipcse - End offset for header checksum calculation.
* ipcso - Offset of place to put the checksum.
*
- * We set ipcsX values regardless of IP version to work around HW issues
- * and ipcse must be 0 for IPv6 per "PCIe GbE SDM 2.5" page 61.
+ * We set ipcsX values regardless of IP version to work around HW
+ * issues and ipcse must be 0 for IPv6 per "PCIe GbE SDM 2.5" page 61.
* IXSM controls whether it's inserted.
*/
TXD->lower_setup.ip_fields.ipcss = pi->ipi_ehdrlen;
@@ -299,7 +301,8 @@ em_transmit_checksum_setup(struct e1000_softc *sc, if_pkt_info_t pi,
* tucse - End offset for payload checksum calculation.
* tucso - Offset of place to put the checksum.
*/
- if (csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_IP6_TCP | CSUM_IP6_UDP)) {
+ if (csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_IP6_TCP |
+ CSUM_IP6_UDP)) {
uint8_t tucso;
*txd_upper |= E1000_TXD_POPTS_TXSM << 8;
@@ -329,7 +332,8 @@ em_transmit_checksum_setup(struct e1000_softc *sc, if_pkt_info_t pi,
cur = 0;
}
DPRINTF(iflib_get_dev(sc->ctx),
- "checksum_setup csum_flags=%x txd_upper=%x txd_lower=%x hdr_len=%d cmd=%x\n",
+ "checksum_setup csum_flags=%x txd_upper=%x txd_lower=%x"
+ " hdr_len=%d cmd=%x\n",
csum_flags, *txd_upper, *txd_lower, hdr_len, cmd);
return (cur);
}
@@ -375,7 +379,8 @@ em_isc_txd_encap(void *arg, if_pkt_info_t pi)
i = em_tso_setup(sc, pi, &txd_upper, &txd_lower);
tso_desc = true;
} else if (csum_flags & EM_CSUM_OFFLOAD) {
- i = em_transmit_checksum_setup(sc, pi, &txd_upper, &txd_lower);
+ i = em_transmit_checksum_setup(sc, pi, &txd_upper,
+ &txd_lower);
}
if (pi->ipi_mflags & M_VLANTAG) {
@@ -417,7 +422,8 @@ em_isc_txd_encap(void *arg, if_pkt_info_t pi)
/* Now make the sentinel */
ctxd = &txr->tx_base[i];
ctxd->buffer_addr = htole64(seg_addr + seg_len);
- ctxd->lower.data = htole32(cmd | txd_lower | TSO_WORKAROUND);
+ ctxd->lower.data =
+ htole32(cmd | txd_lower | TSO_WORKAROUND);
ctxd->upper.data = htole32(txd_upper);
pidx_last = i;
if (++i == scctx->isc_ntxd[0])
@@ -432,7 +438,8 @@ em_isc_txd_encap(void *arg, if_pkt_info_t pi)
pidx_last = i;
if (++i == scctx->isc_ntxd[0])
i = 0;
- DPRINTF(iflib_get_dev(sc->ctx), "pidx_last=%d i=%d ntxd[0]=%d\n",
+ DPRINTF(iflib_get_dev(sc->ctx),
+ "pidx_last=%d i=%d ntxd[0]=%d\n",
pidx_last, i, scctx->isc_ntxd[0]);
}
}
@@ -452,9 +459,14 @@ em_isc_txd_encap(void *arg, if_pkt_info_t pi)
}
ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | txd_flags);
DPRINTF(iflib_get_dev(sc->ctx),
- "tx_buffers[%d]->eop = %d ipi_new_pidx=%d\n", first, pidx_last, i);
+ "tx_buffers[%d]->eop = %d ipi_new_pidx=%d\n",
+ first, pidx_last, i);
pi->ipi_new_pidx = i;
+ /* Sent data accounting for AIM */
+ txr->tx_bytes += pi->ipi_len;
+ ++txr->tx_packets;
+
return (0);
}
@@ -507,8 +519,8 @@ em_isc_txd_credits_update(void *arg, uint16_t txqid, bool clear)
delta += ntxd;
MPASS(delta > 0);
DPRINTF(iflib_get_dev(sc->ctx),
- "%s: cidx_processed=%u cur=%u clear=%d delta=%d\n",
- __FUNCTION__, prev, cur, clear, delta);
+ "%s: cidx_processed=%u cur=%u clear=%d delta=%d\n",
+ __FUNCTION__, prev, cur, clear, delta);
processed += delta;
prev = cur;
@@ -669,6 +681,7 @@ lem_isc_rxd_pkt_get(void *arg, if_rxd_info_t ri)
len = le16toh(rxd->length);
ri->iri_len += len;
+ rxr->rx_bytes += ri->iri_len;
eop = (status & E1000_RXD_STAT_EOP) != 0;
@@ -690,12 +703,14 @@ lem_isc_rxd_pkt_get(void *arg, if_rxd_info_t ri)
i++;
} while (!eop);
+ rxr->rx_packets++;
+
if (scctx->isc_capenable & IFCAP_RXCSUM)
em_receive_checksum(status, errors, ri);
if (scctx->isc_capenable & IFCAP_VLAN_HWTAGGING &&
status & E1000_RXD_STAT_VP) {
- ri->iri_vtag = le16toh(rxd->special & E1000_RXD_SPC_VLAN_MASK);
+ ri->iri_vtag = le16toh(rxd->special);
ri->iri_flags |= M_VLANTAG;
}
@@ -732,6 +747,7 @@ em_isc_rxd_pkt_get(void *arg, if_rxd_info_t ri)
len = le16toh(rxd->wb.upper.length);
ri->iri_len += len;
+ rxr->rx_bytes += ri->iri_len;
eop = (staterr & E1000_RXD_STAT_EOP) != 0;
@@ -752,6 +768,8 @@ em_isc_rxd_pkt_get(void *arg, if_rxd_info_t ri)
i++;
} while (!eop);
+ rxr->rx_packets++;
+
if (scctx->isc_capenable & IFCAP_RXCSUM)
em_receive_checksum(staterr, staterr >> 24, ri);
@@ -782,7 +800,8 @@ em_receive_checksum(uint16_t status, uint8_t errors, if_rxd_info_t ri)
return;
/* If there is a layer 3 or 4 error we are done */
- if (__predict_false(errors & (E1000_RXD_ERR_IPE | E1000_RXD_ERR_TCPE)))
+ if (__predict_false(errors & (E1000_RXD_ERR_IPE |
+ E1000_RXD_ERR_TCPE)))
return;
/* IP Checksum Good */
diff --git a/sys/dev/e1000/if_em.c b/sys/dev/e1000/if_em.c
index 690d6dfa3218..f0ef6051fab1 100644
--- a/sys/dev/e1000/if_em.c
+++ b/sys/dev/e1000/if_em.c
@@ -1,8 +1,9 @@
/*-
* SPDX-License-Identifier: BSD-2-Clause
*
+ * Copyright (c) 2001-2024, Intel Corporation
* Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org>
- * All rights reserved.
+ * Copyright (c) 2024 Kevin Bowling <kbowling@FreeBSD.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -37,7 +38,7 @@
* Driver version:
*********************************************************************/
static const char em_driver_version[] = "7.7.8-fbsd";
-static const char igb_driver_version[] = "2.5.19-fbsd";
+static const char igb_driver_version[] = "2.5.28-fbsd";
/*********************************************************************
* PCI Device ID Table
@@ -52,73 +53,129 @@ static const char igb_driver_version[] = "2.5.19-fbsd";
static const pci_vendor_info_t em_vendor_info_array[] =
{
/* Intel(R) - lem-class legacy devices */
- PVID(0x8086, E1000_DEV_ID_82540EM, "Intel(R) Legacy PRO/1000 MT 82540EM"),
- PVID(0x8086, E1000_DEV_ID_82540EM_LOM, "Intel(R) Legacy PRO/1000 MT 82540EM (LOM)"),
- PVID(0x8086, E1000_DEV_ID_82540EP, "Intel(R) Legacy PRO/1000 MT 82540EP"),
- PVID(0x8086, E1000_DEV_ID_82540EP_LOM, "Intel(R) Legacy PRO/1000 MT 82540EP (LOM)"),
- PVID(0x8086, E1000_DEV_ID_82540EP_LP, "Intel(R) Legacy PRO/1000 MT 82540EP (Mobile)"),
-
- PVID(0x8086, E1000_DEV_ID_82541EI, "Intel(R) Legacy PRO/1000 MT 82541EI (Copper)"),
- PVID(0x8086, E1000_DEV_ID_82541ER, "Intel(R) Legacy PRO/1000 82541ER"),
- PVID(0x8086, E1000_DEV_ID_82541ER_LOM, "Intel(R) Legacy PRO/1000 MT 82541ER"),
- PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541EI (Mobile)"),
- PVID(0x8086, E1000_DEV_ID_82541GI, "Intel(R) Legacy PRO/1000 MT 82541GI"),
- PVID(0x8086, E1000_DEV_ID_82541GI_LF, "Intel(R) Legacy PRO/1000 GT 82541PI"),
- PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE, "Intel(R) Legacy PRO/1000 MT 82541GI (Mobile)"),
-
- PVID(0x8086, E1000_DEV_ID_82542, "Intel(R) Legacy PRO/1000 82542 (Fiber)"),
-
- PVID(0x8086, E1000_DEV_ID_82543GC_FIBER, "Intel(R) Legacy PRO/1000 F 82543GC (Fiber)"),
- PVID(0x8086, E1000_DEV_ID_82543GC_COPPER, "Intel(R) Legacy PRO/1000 T 82543GC (Copper)"),
-
- PVID(0x8086, E1000_DEV_ID_82544EI_COPPER, "Intel(R) Legacy PRO/1000 XT 82544EI (Copper)"),
- PVID(0x8086, E1000_DEV_ID_82544EI_FIBER, "Intel(R) Legacy PRO/1000 XF 82544EI (Fiber)"),
- PVID(0x8086, E1000_DEV_ID_82544GC_COPPER, "Intel(R) Legacy PRO/1000 T 82544GC (Copper)"),
- PVID(0x8086, E1000_DEV_ID_82544GC_LOM, "Intel(R) Legacy PRO/1000 XT 82544GC (LOM)"),
-
- PVID(0x8086, E1000_DEV_ID_82545EM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545EM (Copper)"),
- PVID(0x8086, E1000_DEV_ID_82545EM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545EM (Fiber)"),
- PVID(0x8086, E1000_DEV_ID_82545GM_COPPER, "Intel(R) Legacy PRO/1000 MT 82545GM (Copper)"),
- PVID(0x8086, E1000_DEV_ID_82545GM_FIBER, "Intel(R) Legacy PRO/1000 MF 82545GM (Fiber)"),
- PVID(0x8086, E1000_DEV_ID_82545GM_SERDES, "Intel(R) Legacy PRO/1000 MB 82545GM (SERDES)"),
-
- PVID(0x8086, E1000_DEV_ID_82546EB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Copper)"),
- PVID(0x8086, E1000_DEV_ID_82546EB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546EB (Fiber)"),
- PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 MT 82546EB (Quad Copper"),
- PVID(0x8086, E1000_DEV_ID_82546GB_COPPER, "Intel(R) Legacy PRO/1000 MT 82546GB (Copper)"),
- PVID(0x8086, E1000_DEV_ID_82546GB_FIBER, "Intel(R) Legacy PRO/1000 MF 82546GB (Fiber)"),
- PVID(0x8086, E1000_DEV_ID_82546GB_SERDES, "Intel(R) Legacy PRO/1000 MB 82546GB (SERDES)"),
- PVID(0x8086, E1000_DEV_ID_82546GB_PCIE, "Intel(R) Legacy PRO/1000 P 82546GB (PCIe)"),
- PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"),
- PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"),
-
- PVID(0x8086, E1000_DEV_ID_82547EI, "Intel(R) Legacy PRO/1000 CT 82547EI"),
- PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE, "Intel(R) Legacy PRO/1000 CT 82547EI (Mobile)"),
- PVID(0x8086, E1000_DEV_ID_82547GI, "Intel(R) Legacy PRO/1000 CT 82547GI"),
+ PVID(0x8086, E1000_DEV_ID_82540EM,
+ "Intel(R) Legacy PRO/1000 MT 82540EM"),
+ PVID(0x8086, E1000_DEV_ID_82540EM_LOM,
+ "Intel(R) Legacy PRO/1000 MT 82540EM (LOM)"),
+ PVID(0x8086, E1000_DEV_ID_82540EP,
+ "Intel(R) Legacy PRO/1000 MT 82540EP"),
+ PVID(0x8086, E1000_DEV_ID_82540EP_LOM,
+ "Intel(R) Legacy PRO/1000 MT 82540EP (LOM)"),
+ PVID(0x8086, E1000_DEV_ID_82540EP_LP,
+ "Intel(R) Legacy PRO/1000 MT 82540EP (Mobile)"),
+
+ PVID(0x8086, E1000_DEV_ID_82541EI,
+ "Intel(R) Legacy PRO/1000 MT 82541EI (Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82541ER,
+ "Intel(R) Legacy PRO/1000 82541ER"),
+ PVID(0x8086, E1000_DEV_ID_82541ER_LOM,
+ "Intel(R) Legacy PRO/1000 MT 82541ER"),
+ PVID(0x8086, E1000_DEV_ID_82541EI_MOBILE,
+ "Intel(R) Legacy PRO/1000 MT 82541EI (Mobile)"),
+ PVID(0x8086, E1000_DEV_ID_82541GI,
+ "Intel(R) Legacy PRO/1000 MT 82541GI"),
+ PVID(0x8086, E1000_DEV_ID_82541GI_LF,
+ "Intel(R) Legacy PRO/1000 GT 82541PI"),
+ PVID(0x8086, E1000_DEV_ID_82541GI_MOBILE,
+ "Intel(R) Legacy PRO/1000 MT 82541GI (Mobile)"),
+
+ PVID(0x8086, E1000_DEV_ID_82542,
+ "Intel(R) Legacy PRO/1000 82542 (Fiber)"),
+
+ PVID(0x8086, E1000_DEV_ID_82543GC_FIBER,
+ "Intel(R) Legacy PRO/1000 F 82543GC (Fiber)"),
+ PVID(0x8086, E1000_DEV_ID_82543GC_COPPER,
+ "Intel(R) Legacy PRO/1000 T 82543GC (Copper)"),
+
+ PVID(0x8086, E1000_DEV_ID_82544EI_COPPER,
+ "Intel(R) Legacy PRO/1000 XT 82544EI (Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82544EI_FIBER,
+ "Intel(R) Legacy PRO/1000 XF 82544EI (Fiber)"),
+ PVID(0x8086, E1000_DEV_ID_82544GC_COPPER,
+ "Intel(R) Legacy PRO/1000 T 82544GC (Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82544GC_LOM,
+ "Intel(R) Legacy PRO/1000 XT 82544GC (LOM)"),
+
+ PVID(0x8086, E1000_DEV_ID_82545EM_COPPER,
+ "Intel(R) Legacy PRO/1000 MT 82545EM (Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82545EM_FIBER,
+ "Intel(R) Legacy PRO/1000 MF 82545EM (Fiber)"),
+ PVID(0x8086, E1000_DEV_ID_82545GM_COPPER,
+ "Intel(R) Legacy PRO/1000 MT 82545GM (Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82545GM_FIBER,
+ "Intel(R) Legacy PRO/1000 MF 82545GM (Fiber)"),
+ PVID(0x8086, E1000_DEV_ID_82545GM_SERDES,
+ "Intel(R) Legacy PRO/1000 MB 82545GM (SERDES)"),
+
+ PVID(0x8086, E1000_DEV_ID_82546EB_COPPER,
+ "Intel(R) Legacy PRO/1000 MT 82546EB (Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82546EB_FIBER,
+ "Intel(R) Legacy PRO/1000 MF 82546EB (Fiber)"),
+ PVID(0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER,
+ "Intel(R) Legacy PRO/1000 MT 82546EB (Quad Copper"),
+ PVID(0x8086, E1000_DEV_ID_82546GB_COPPER,
+ "Intel(R) Legacy PRO/1000 MT 82546GB (Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82546GB_FIBER,
+ "Intel(R) Legacy PRO/1000 MF 82546GB (Fiber)"),
+ PVID(0x8086, E1000_DEV_ID_82546GB_SERDES,
+ "Intel(R) Legacy PRO/1000 MB 82546GB (SERDES)"),
+ PVID(0x8086, E1000_DEV_ID_82546GB_PCIE,
+ "Intel(R) Legacy PRO/1000 P 82546GB (PCIe)"),
+ PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER,
+ "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3,
+ "Intel(R) Legacy PRO/1000 GT 82546GB (Quad Copper)"),
+
+ PVID(0x8086, E1000_DEV_ID_82547EI,
+ "Intel(R) Legacy PRO/1000 CT 82547EI"),
+ PVID(0x8086, E1000_DEV_ID_82547EI_MOBILE,
+ "Intel(R) Legacy PRO/1000 CT 82547EI (Mobile)"),
+ PVID(0x8086, E1000_DEV_ID_82547GI,
+ "Intel(R) Legacy PRO/1000 CT 82547GI"),
/* Intel(R) - em-class devices */
- PVID(0x8086, E1000_DEV_ID_82571EB_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Copper)"),
- PVID(0x8086, E1000_DEV_ID_82571EB_FIBER, "Intel(R) PRO/1000 PF 82571EB/82571GB (Fiber)"),
- PVID(0x8086, E1000_DEV_ID_82571EB_SERDES, "Intel(R) PRO/1000 PB 82571EB (SERDES)"),
- PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL, "Intel(R) PRO/1000 82571EB (Dual Mezzanine)"),
- PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD, "Intel(R) PRO/1000 82571EB (Quad Mezzanine)"),
- PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"),
- PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"),
- PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, "Intel(R) PRO/1000 PF 82571EB (Quad Fiber)"),
- PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, "Intel(R) PRO/1000 PT 82571PT (Quad Copper)"),
- PVID(0x8086, E1000_DEV_ID_82572EI, "Intel(R) PRO/1000 PT 82572EI (Copper)"),
- PVID(0x8086, E1000_DEV_ID_82572EI_COPPER, "Intel(R) PRO/1000 PT 82572EI (Copper)"),
- PVID(0x8086, E1000_DEV_ID_82572EI_FIBER, "Intel(R) PRO/1000 PF 82572EI (Fiber)"),
- PVID(0x8086, E1000_DEV_ID_82572EI_SERDES, "Intel(R) PRO/1000 82572EI (SERDES)"),
- PVID(0x8086, E1000_DEV_ID_82573E, "Intel(R) PRO/1000 82573E (Copper)"),
- PVID(0x8086, E1000_DEV_ID_82573E_IAMT, "Intel(R) PRO/1000 82573E AMT (Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82571EB_COPPER,
+ "Intel(R) PRO/1000 PT 82571EB/82571GB (Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82571EB_FIBER,
+ "Intel(R) PRO/1000 PF 82571EB/82571GB (Fiber)"),
+ PVID(0x8086, E1000_DEV_ID_82571EB_SERDES,
+ "Intel(R) PRO/1000 PB 82571EB (SERDES)"),
+ PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_DUAL,
+ "Intel(R) PRO/1000 82571EB (Dual Mezzanine)"),
+ PVID(0x8086, E1000_DEV_ID_82571EB_SERDES_QUAD,
+ "Intel(R) PRO/1000 82571EB (Quad Mezzanine)"),
+ PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER,
+ "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP,
+ "Intel(R) PRO/1000 PT 82571EB/82571GB (Quad Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER,
+ "Intel(R) PRO/1000 PF 82571EB (Quad Fiber)"),
+ PVID(0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER,
+ "Intel(R) PRO/1000 PT 82571PT (Quad Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82572EI,
+ "Intel(R) PRO/1000 PT 82572EI (Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82572EI_COPPER,
+ "Intel(R) PRO/1000 PT 82572EI (Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82572EI_FIBER,
+ "Intel(R) PRO/1000 PF 82572EI (Fiber)"),
+ PVID(0x8086, E1000_DEV_ID_82572EI_SERDES,
+ "Intel(R) PRO/1000 82572EI (SERDES)"),
+ PVID(0x8086, E1000_DEV_ID_82573E,
+ "Intel(R) PRO/1000 82573E (Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82573E_IAMT,
+ "Intel(R) PRO/1000 82573E AMT (Copper)"),
PVID(0x8086, E1000_DEV_ID_82573L, "Intel(R) PRO/1000 82573L"),
PVID(0x8086, E1000_DEV_ID_82583V, "Intel(R) 82583V"),
- PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, "Intel(R) 80003ES2LAN (Copper)"),
- PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, "Intel(R) 80003ES2LAN (SERDES)"),
- PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, "Intel(R) 80003ES2LAN (Dual Copper)"),
- PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, "Intel(R) 80003ES2LAN (Dual SERDES)"),
- PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, "Intel(R) 82566MM ICH8 AMT (Mobile)"),
+ PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT,
+ "Intel(R) 80003ES2LAN (Copper)"),
+ PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT,
+ "Intel(R) 80003ES2LAN (SERDES)"),
+ PVID(0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT,
+ "Intel(R) 80003ES2LAN (Dual Copper)"),
+ PVID(0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT,
+ "Intel(R) 80003ES2LAN (Dual SERDES)"),
+ PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT,
+ "Intel(R) 82566MM ICH8 AMT (Mobile)"),
PVID(0x8086, E1000_DEV_ID_ICH8_IGP_AMT, "Intel(R) 82566DM ICH8 AMT"),
PVID(0x8086, E1000_DEV_ID_ICH8_IGP_C, "Intel(R) 82566DC ICH8"),
PVID(0x8086, E1000_DEV_ID_ICH8_IFE, "Intel(R) 82562V ICH8"),
@@ -126,8 +183,10 @@ static const pci_vendor_info_t em_vendor_info_array[] =
PVID(0x8086, E1000_DEV_ID_ICH8_IFE_G, "Intel(R) 82562G ICH8"),
PVID(0x8086, E1000_DEV_ID_ICH8_IGP_M, "Intel(R) 82566MC ICH8"),
PVID(0x8086, E1000_DEV_ID_ICH8_82567V_3, "Intel(R) 82567V-3 ICH8"),
- PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT, "Intel(R) 82567LM ICH9 AMT"),
- PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT, "Intel(R) 82566DM-2 ICH9 AMT"),
+ PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_AMT,
+ "Intel(R) 82567LM ICH9 AMT"),
+ PVID(0x8086, E1000_DEV_ID_ICH9_IGP_AMT,
+ "Intel(R) 82566DM-2 ICH9 AMT"),
PVID(0x8086, E1000_DEV_ID_ICH9_IGP_C, "Intel(R) 82566DC-2 ICH9"),
PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M, "Intel(R) 82567LF ICH9"),
PVID(0x8086, E1000_DEV_ID_ICH9_IGP_M_V, "Intel(R) 82567V ICH9"),
@@ -151,7 +210,8 @@ static const pci_vendor_info_t em_vendor_info_array[] =
PVID(0x8086, E1000_DEV_ID_PCH2_LV_V, "Intel(R) 82579V"),
PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_LM, "Intel(R) I217-LM LPT"),
PVID(0x8086, E1000_DEV_ID_PCH_LPT_I217_V, "Intel(R) I217-V LPT"),
- PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM, "Intel(R) I218-LM LPTLP"),
+ PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_LM,
+ "Intel(R) I218-LM LPTLP"),
PVID(0x8086, E1000_DEV_ID_PCH_LPTLP_I218_V, "Intel(R) I218-V LPTLP"),
PVID(0x8086, E1000_DEV_ID_PCH_I218_LM2, "Intel(R) I218-LM (2)"),
PVID(0x8086, E1000_DEV_ID_PCH_I218_V2, "Intel(R) I218-V (2)"),
@@ -159,57 +219,102 @@ static const pci_vendor_info_t em_vendor_info_array[] =
PVID(0x8086, E1000_DEV_ID_PCH_I218_V3, "Intel(R) I218-V (3)"),
PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM, "Intel(R) I219-LM SPT"),
PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V, "Intel(R) I219-V SPT"),
- PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2, "Intel(R) I219-LM SPT-H(2)"),
- PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2, "Intel(R) I219-V SPT-H(2)"),
- PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3, "Intel(R) I219-LM LBG(3)"),
- PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4, "Intel(R) I219-LM SPT(4)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM2,
+ "Intel(R) I219-LM SPT-H(2)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V2,
+ "Intel(R) I219-V SPT-H(2)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_LBG_I219_LM3,
+ "Intel(R) I219-LM LBG(3)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM4,
+ "Intel(R) I219-LM SPT(4)"),
PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V4, "Intel(R) I219-V SPT(4)"),
- PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5, "Intel(R) I219-LM SPT(5)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_LM5,
+ "Intel(R) I219-LM SPT(5)"),
PVID(0x8086, E1000_DEV_ID_PCH_SPT_I219_V5, "Intel(R) I219-V SPT(5)"),
- PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6, "Intel(R) I219-LM CNP(6)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM6,
+ "Intel(R) I219-LM CNP(6)"),
PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V6, "Intel(R) I219-V CNP(6)"),
- PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7, "Intel(R) I219-LM CNP(7)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_LM7,
+ "Intel(R) I219-LM CNP(7)"),
PVID(0x8086, E1000_DEV_ID_PCH_CNP_I219_V7, "Intel(R) I219-V CNP(7)"),
- PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8, "Intel(R) I219-LM ICP(8)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM8,
+ "Intel(R) I219-LM ICP(8)"),
PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V8, "Intel(R) I219-V ICP(8)"),
- PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9, "Intel(R) I219-LM ICP(9)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_LM9,
+ "Intel(R) I219-LM ICP(9)"),
PVID(0x8086, E1000_DEV_ID_PCH_ICP_I219_V9, "Intel(R) I219-V ICP(9)"),
- PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10, "Intel(R) I219-LM CMP(10)"),
- PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10, "Intel(R) I219-V CMP(10)"),
- PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11, "Intel(R) I219-LM CMP(11)"),
- PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11, "Intel(R) I219-V CMP(11)"),
- PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12, "Intel(R) I219-LM CMP(12)"),
- PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12, "Intel(R) I219-V CMP(12)"),
- PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM13, "Intel(R) I219-LM TGP(13)"),
- PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V13, "Intel(R) I219-V TGP(13)"),
- PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM14, "Intel(R) I219-LM TGP(14)"),
- PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V14, "Intel(R) I219-V GTP(14)"),
- PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM15, "Intel(R) I219-LM TGP(15)"),
- PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V15, "Intel(R) I219-V TGP(15)"),
- PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM16, "Intel(R) I219-LM ADL(16)"),
- PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V16, "Intel(R) I219-V ADL(16)"),
- PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM17, "Intel(R) I219-LM ADL(17)"),
- PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V17, "Intel(R) I219-V ADL(17)"),
- PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM18, "Intel(R) I219-LM MTP(18)"),
- PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V18, "Intel(R) I219-V MTP(18)"),
- PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM19, "Intel(R) I219-LM MTP(19)"),
- PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V19, "Intel(R) I219-V MTP(19)"),
- PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM20, "Intel(R) I219-LM LNL(20)"),
- PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V20, "Intel(R) I219-V LNL(20)"),
- PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM21, "Intel(R) I219-LM LNL(21)"),
- PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V21, "Intel(R) I219-V LNL(21)"),
- PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM22, "Intel(R) I219-LM RPL(22)"),
- PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V22, "Intel(R) I219-V RPL(22)"),
- PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM23, "Intel(R) I219-LM RPL(23)"),
- PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V23, "Intel(R) I219-V RPL(23)"),
- PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_LM24, "Intel(R) I219-LM ARL(24)"),
- PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_V24, "Intel(R) I219-V ARL(24)"),
- PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM25, "Intel(R) I219-LM PTP(25)"),
- PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V25, "Intel(R) I219-V PTP(25)"),
- PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM26, "Intel(R) I219-LM PTP(26)"),
- PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V26, "Intel(R) I219-V PTP(26)"),
- PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM27, "Intel(R) I219-LM PTP(27)"),
- PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V27, "Intel(R) I219-V PTP(27)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM10,
+ "Intel(R) I219-LM CMP(10)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V10,
+ "Intel(R) I219-V CMP(10)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM11,
+ "Intel(R) I219-LM CMP(11)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V11,
+ "Intel(R) I219-V CMP(11)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_LM12,
+ "Intel(R) I219-LM CMP(12)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_CMP_I219_V12,
+ "Intel(R) I219-V CMP(12)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM13,
+ "Intel(R) I219-LM TGP(13)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V13,
+ "Intel(R) I219-V TGP(13)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM14,
+ "Intel(R) I219-LM TGP(14)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V14,
+ "Intel(R) I219-V GTP(14)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_LM15,
+ "Intel(R) I219-LM TGP(15)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_TGP_I219_V15,
+ "Intel(R) I219-V TGP(15)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM16,
+ "Intel(R) I219-LM ADL(16)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V16,
+ "Intel(R) I219-V ADL(16)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM17,
+ "Intel(R) I219-LM ADL(17)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V17,
+ "Intel(R) I219-V ADL(17)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_LM18,
+ "Intel(R) I219-LM MTP(18)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_MTP_I219_V18,
+ "Intel(R) I219-V MTP(18)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_LM19,
+ "Intel(R) I219-LM ADL(19)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_ADL_I219_V19,
+ "Intel(R) I219-V ADL(19)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM20,
+ "Intel(R) I219-LM LNL(20)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V20,
+ "Intel(R) I219-V LNL(20)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_LM21,
+ "Intel(R) I219-LM LNL(21)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_LNL_I219_V21,
+ "Intel(R) I219-V LNL(21)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM22,
+ "Intel(R) I219-LM RPL(22)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V22,
+ "Intel(R) I219-V RPL(22)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_LM23,
+ "Intel(R) I219-LM RPL(23)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_RPL_I219_V23,
+ "Intel(R) I219-V RPL(23)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_LM24,
+ "Intel(R) I219-LM ARL(24)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_ARL_I219_V24,
+ "Intel(R) I219-V ARL(24)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM25,
+ "Intel(R) I219-LM PTP(25)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V25,
+ "Intel(R) I219-V PTP(25)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM26,
+ "Intel(R) I219-LM PTP(26)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V26,
+ "Intel(R) I219-V PTP(26)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_LM27,
+ "Intel(R) I219-LM PTP(27)"),
+ PVID(0x8086, E1000_DEV_ID_PCH_PTP_I219_V27,
+ "Intel(R) I219-V PTP(27)"),
/* required last entry */
PVID_END
};
@@ -217,45 +322,68 @@ static const pci_vendor_info_t em_vendor_info_array[] =
static const pci_vendor_info_t igb_vendor_info_array[] =
{
/* Intel(R) - igb-class devices */
- PVID(0x8086, E1000_DEV_ID_82575EB_COPPER, "Intel(R) PRO/1000 82575EB (Copper)"),
- PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, "Intel(R) PRO/1000 82575EB (SERDES)"),
- PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, "Intel(R) PRO/1000 VT 82575GB (Quad Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82575EB_COPPER,
+ "Intel(R) PRO/1000 82575EB (Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES,
+ "Intel(R) PRO/1000 82575EB (SERDES)"),
+ PVID(0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER,
+ "Intel(R) PRO/1000 VT 82575GB (Quad Copper)"),
PVID(0x8086, E1000_DEV_ID_82576, "Intel(R) PRO/1000 82576"),
PVID(0x8086, E1000_DEV_ID_82576_NS, "Intel(R) PRO/1000 82576NS"),
- PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES, "Intel(R) PRO/1000 82576NS (SERDES)"),
- PVID(0x8086, E1000_DEV_ID_82576_FIBER, "Intel(R) PRO/1000 EF 82576 (Dual Fiber)"),
- PVID(0x8086, E1000_DEV_ID_82576_SERDES, "Intel(R) PRO/1000 82576 (Dual SERDES)"),
- PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD, "Intel(R) PRO/1000 ET 82576 (Quad SERDES)"),
- PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER, "Intel(R) PRO/1000 ET 82576 (Quad Copper)"),
- PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2, "Intel(R) PRO/1000 ET(2) 82576 (Quad Copper)"),
- PVID(0x8086, E1000_DEV_ID_82576_VF, "Intel(R) PRO/1000 82576 Virtual Function"),
- PVID(0x8086, E1000_DEV_ID_82580_COPPER, "Intel(R) I340 82580 (Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82576_NS_SERDES,
+ "Intel(R) PRO/1000 82576NS (SERDES)"),
+ PVID(0x8086, E1000_DEV_ID_82576_FIBER,
+ "Intel(R) PRO/1000 EF 82576 (Dual Fiber)"),
+ PVID(0x8086, E1000_DEV_ID_82576_SERDES,
+ "Intel(R) PRO/1000 82576 (Dual SERDES)"),
+ PVID(0x8086, E1000_DEV_ID_82576_SERDES_QUAD,
+ "Intel(R) PRO/1000 ET 82576 (Quad SERDES)"),
+ PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER,
+ "Intel(R) PRO/1000 ET 82576 (Quad Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82576_QUAD_COPPER_ET2,
+ "Intel(R) PRO/1000 ET(2) 82576 (Quad Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82576_VF,
+ "Intel(R) PRO/1000 82576 Virtual Function"),
+ PVID(0x8086, E1000_DEV_ID_82580_COPPER,
+ "Intel(R) I340 82580 (Copper)"),
PVID(0x8086, E1000_DEV_ID_82580_FIBER, "Intel(R) I340 82580 (Fiber)"),
- PVID(0x8086, E1000_DEV_ID_82580_SERDES, "Intel(R) I340 82580 (SERDES)"),
+ PVID(0x8086, E1000_DEV_ID_82580_SERDES,
+ "Intel(R) I340 82580 (SERDES)"),
PVID(0x8086, E1000_DEV_ID_82580_SGMII, "Intel(R) I340 82580 (SGMII)"),
- PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL, "Intel(R) I340-T2 82580 (Dual Copper)"),
- PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER, "Intel(R) I340-F4 82580 (Quad Fiber)"),
- PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES, "Intel(R) DH89XXCC (SERDES)"),
- PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII, "Intel(R) I347-AT4 DH89XXCC"),
+ PVID(0x8086, E1000_DEV_ID_82580_COPPER_DUAL,
+ "Intel(R) I340-T2 82580 (Dual Copper)"),
+ PVID(0x8086, E1000_DEV_ID_82580_QUAD_FIBER,
+ "Intel(R) I340-F4 82580 (Quad Fiber)"),
+ PVID(0x8086, E1000_DEV_ID_DH89XXCC_SERDES,
+ "Intel(R) DH89XXCC (SERDES)"),
+ PVID(0x8086, E1000_DEV_ID_DH89XXCC_SGMII,
+ "Intel(R) I347-AT4 DH89XXCC"),
PVID(0x8086, E1000_DEV_ID_DH89XXCC_SFP, "Intel(R) DH89XXCC (SFP)"),
- PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE, "Intel(R) DH89XXCC (Backplane)"),
+ PVID(0x8086, E1000_DEV_ID_DH89XXCC_BACKPLANE,
+ "Intel(R) DH89XXCC (Backplane)"),
PVID(0x8086, E1000_DEV_ID_I350_COPPER, "Intel(R) I350 (Copper)"),
PVID(0x8086, E1000_DEV_ID_I350_FIBER, "Intel(R) I350 (Fiber)"),
PVID(0x8086, E1000_DEV_ID_I350_SERDES, "Intel(R) I350 (SERDES)"),
PVID(0x8086, E1000_DEV_ID_I350_SGMII, "Intel(R) I350 (SGMII)"),
PVID(0x8086, E1000_DEV_ID_I350_VF, "Intel(R) I350 Virtual Function"),
PVID(0x8086, E1000_DEV_ID_I210_COPPER, "Intel(R) I210 (Copper)"),
- PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT, "Intel(R) I210 IT (Copper)"),
+ PVID(0x8086, E1000_DEV_ID_I210_COPPER_IT,
+ "Intel(R) I210 IT (Copper)"),
PVID(0x8086, E1000_DEV_ID_I210_COPPER_OEM1, "Intel(R) I210 (OEM)"),
- PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS, "Intel(R) I210 Flashless (Copper)"),
- PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS, "Intel(R) I210 Flashless (SERDES)"),
- PVID(0x8086, E1000_DEV_ID_I210_SGMII_FLASHLESS, "Intel(R) I210 Flashless (SGMII)"),
+ PVID(0x8086, E1000_DEV_ID_I210_COPPER_FLASHLESS,
+ "Intel(R) I210 Flashless (Copper)"),
+ PVID(0x8086, E1000_DEV_ID_I210_SERDES_FLASHLESS,
+ "Intel(R) I210 Flashless (SERDES)"),
+ PVID(0x8086, E1000_DEV_ID_I210_SGMII_FLASHLESS,
+ "Intel(R) I210 Flashless (SGMII)"),
PVID(0x8086, E1000_DEV_ID_I210_FIBER, "Intel(R) I210 (Fiber)"),
PVID(0x8086, E1000_DEV_ID_I210_SERDES, "Intel(R) I210 (SERDES)"),
PVID(0x8086, E1000_DEV_ID_I210_SGMII, "Intel(R) I210 (SGMII)"),
PVID(0x8086, E1000_DEV_ID_I211_COPPER, "Intel(R) I211 (Copper)"),
- PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS, "Intel(R) I354 (1.0 GbE Backplane)"),
- PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS, "Intel(R) I354 (2.5 GbE Backplane)"),
+ PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_1GBPS,
+ "Intel(R) I354 (1.0 GbE Backplane)"),
+ PVID(0x8086, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS,
+ "Intel(R) I354 (2.5 GbE Backplane)"),
PVID(0x8086, E1000_DEV_ID_I354_SGMII, "Intel(R) I354 (SGMII)"),
/* required last entry */
PVID_END
@@ -273,8 +401,10 @@ static int em_if_shutdown(if_ctx_t);
static int em_if_suspend(if_ctx_t);
static int em_if_resume(if_ctx_t);
-static int em_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int);
-static int em_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int);
+static int em_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int,
+ int);
+static int em_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int,
+ int);
static void em_if_queues_free(if_ctx_t);
static uint64_t em_if_get_counter(if_ctx_t, ift_counter);
@@ -329,10 +459,13 @@ static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
static int em_get_rs(SYSCTL_HANDLER_ARGS);
static void em_print_debug_info(struct e1000_softc *);
static int em_is_valid_ether_addr(u8 *);
+static void em_newitr(struct e1000_softc *, struct em_rx_queue *,
+ struct tx_ring *, struct rx_ring *);
static bool em_automask_tso(if_ctx_t);
+static int em_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS);
static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS);
static void em_add_int_delay_sysctl(struct e1000_softc *, const char *,
- const char *, struct em_int_delay_info *, int, int);
+ const char *, struct em_int_delay_info *, int, int);
/* Management and WOL Support */
static void em_init_manageability(struct e1000_softc *);
static void em_release_manageability(struct e1000_softc *);
@@ -354,6 +487,7 @@ static void em_enable_vectors_82574(if_ctx_t);
static int em_set_flowcntl(SYSCTL_HANDLER_ARGS);
static int em_sysctl_eee(SYSCTL_HANDLER_ARGS);
+static int igb_sysctl_dmac(SYSCTL_HANDLER_ARGS);
static void em_if_led_func(if_ctx_t, int);
static int em_get_regs(SYSCTL_HANDLER_ARGS);
@@ -498,9 +632,6 @@ static driver_t igb_if_driver = {
#define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000)
#define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024)
-#define MAX_INTS_PER_SEC 8000
-#define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256))
-
/* Allow common code without TSO */
#ifndef CSUM_TSO
#define CSUM_TSO 0
@@ -515,10 +646,10 @@ SYSCTL_INT(_hw_em, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN,
static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV);
static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR);
-SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &em_tx_int_delay_dflt,
- 0, "Default transmit interrupt delay in usecs");
-SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &em_rx_int_delay_dflt,
- 0, "Default receive interrupt delay in usecs");
+SYSCTL_INT(_hw_em, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN,
+ &em_tx_int_delay_dflt, 0, "Default transmit interrupt delay in usecs");
+SYSCTL_INT(_hw_em, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN,
+ &em_rx_int_delay_dflt, 0, "Default receive interrupt delay in usecs");
static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV);
static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV);
@@ -530,7 +661,8 @@ SYSCTL_INT(_hw_em, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN,
"Default receive interrupt delay limit in usecs");
static int em_smart_pwr_down = false;
-SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &em_smart_pwr_down,
+SYSCTL_INT(_hw_em, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN,
+ &em_smart_pwr_down,
0, "Set to true to leave smart power down enabled on newer adapters");
static bool em_unsupported_tso = false;
@@ -548,9 +680,18 @@ SYSCTL_INT(_hw_em, OID_AUTO, eee_setting, CTLFLAG_RDTUN, &eee_setting, 0,
"Enable Energy Efficient Ethernet");
/*
+ * AIM: Adaptive Interrupt Moderation
+ * which means that the interrupt rate is varied over time based on the
+ * traffic for that interrupt vector
+ */
+static int em_enable_aim = 1;
+SYSCTL_INT(_hw_em, OID_AUTO, enable_aim, CTLFLAG_RWTUN, &em_enable_aim,
+ 0, "Enable adaptive interrupt moderation (1=normal, 2=lowlatency)");
+
+/*
** Tuneable Interrupt rate
*/
-static int em_max_interrupt_rate = 8000;
+static int em_max_interrupt_rate = EM_INTS_DEFAULT;
SYSCTL_INT(_hw_em, OID_AUTO, max_interrupt_rate, CTLFLAG_RDTUN,
&em_max_interrupt_rate, 0, "Maximum interrupts per second");
@@ -578,7 +719,8 @@ static struct if_shared_ctx em_sctx_init = {
.isc_vendor_info = em_vendor_info_array,
.isc_driver_version = em_driver_version,
.isc_driver = &em_if_driver,
- .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
+ .isc_flags =
+ IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
.isc_nrxd_min = {EM_MIN_RXD},
.isc_ntxd_min = {EM_MIN_TXD},
@@ -605,7 +747,8 @@ static struct if_shared_ctx igb_sctx_init = {
.isc_vendor_info = igb_vendor_info_array,
.isc_driver_version = igb_driver_version,
.isc_driver = &igb_if_driver,
- .isc_flags = IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
+ .isc_flags =
+ IFLIB_NEED_SCRATCH | IFLIB_TSO_INIT_IP | IFLIB_NEED_ZERO_CSUM,
.isc_nrxd_min = {EM_MIN_RXD},
.isc_ntxd_min = {EM_MIN_TXD},
@@ -715,15 +858,21 @@ static int em_get_regs(SYSCTL_HANDLER_ARGS)
for (j = 0; j < nrxd; j++) {
u32 staterr = le32toh(rxr->rx_base[j].wb.upper.status_error);
u32 length = le32toh(rxr->rx_base[j].wb.upper.length);
- sbuf_printf(sb, "\tReceive Descriptor Address %d: %08" PRIx64 " Error:%d Length:%d\n", j, rxr->rx_base[j].read.buffer_addr, staterr, length);
+ sbuf_printf(sb, "\tReceive Descriptor Address %d: %08"
+ PRIx64 " Error:%d Length:%d\n",
+ j, rxr->rx_base[j].read.buffer_addr, staterr, length);
}
for (j = 0; j < min(ntxd, 256); j++) {
unsigned int *ptr = (unsigned int *)&txr->tx_base[j];
- sbuf_printf(sb, "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x eop: %d DD=%d\n",
- j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop,
- buf->eop != -1 ? txr->tx_base[buf->eop].upper.fields.status & E1000_TXD_STAT_DD : 0);
+ sbuf_printf(sb,
+ "\tTXD[%03d] [0]: %08x [1]: %08x [2]: %08x [3]: %08x"
+ " eop: %d DD=%d\n",
+ j, ptr[0], ptr[1], ptr[2], ptr[3], buf->eop,
+ buf->eop != -1 ?
+ txr->tx_base[buf->eop].upper.fields.status &
+ E1000_TXD_STAT_DD : 0);
}
}
@@ -831,16 +980,21 @@ em_if_attach_pre(if_ctx_t ctx)
child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "nvm",
- CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
+ CTLTYPE_INT | CTLFLAG_RW, sc, 0,
em_sysctl_nvm_info, "I", "NVM Information");
+ sc->enable_aim = em_enable_aim;
+ SYSCTL_ADD_INT(ctx_list, child, OID_AUTO, "enable_aim",
+ CTLFLAG_RW, &sc->enable_aim, 0,
+ "Interrupt Moderation (1=normal, 2=lowlatency)");
+
SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fw_version",
- CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0,
+ CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
em_sysctl_print_fw_version, "A",
"Prints FW/NVM Versions");
SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "debug",
- CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
+ CTLTYPE_INT | CTLFLAG_RW, sc, 0,
em_sysctl_debug_info, "I", "Debug Information");
SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "fc",
@@ -855,15 +1009,42 @@ em_if_attach_pre(if_ctx_t ctx)
CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
em_get_rs, "I", "Dump RS indexes");
+ if (hw->mac.type >= e1000_i350) {
+ SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "dmac",
+ CTLTYPE_INT | CTLFLAG_RW, sc, 0,
+ igb_sysctl_dmac, "I", "DMA Coalesce");
+ }
+
+ SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO,
+ "tso_tcp_flags_mask_first_segment",
+ CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
+ sc, 0, em_sysctl_tso_tcp_flags_mask, "IU",
+ "TSO TCP flags mask for first segment");
+
+ SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO,
+ "tso_tcp_flags_mask_middle_segment",
+ CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
+ sc, 1, em_sysctl_tso_tcp_flags_mask, "IU",
+ "TSO TCP flags mask for middle segment");
+
+ SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO,
+ "tso_tcp_flags_mask_last_segment",
+ CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
+ sc, 2, em_sysctl_tso_tcp_flags_mask, "IU",
+ "TSO TCP flags mask for last segment");
+
scctx->isc_tx_nsegments = EM_MAX_SCATTER;
- scctx->isc_nrxqsets_max = scctx->isc_ntxqsets_max = em_set_num_queues(ctx);
+ scctx->isc_nrxqsets_max =
+ scctx->isc_ntxqsets_max = em_set_num_queues(ctx);
if (bootverbose)
device_printf(dev, "attach_pre capping queues at %d\n",
scctx->isc_ntxqsets_max);
if (hw->mac.type >= igb_mac_min) {
- scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] * sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN);
- scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN);
+ scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] *
+ sizeof(union e1000_adv_tx_desc), EM_DBA_ALIGN);
+ scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] *
+ sizeof(union e1000_adv_rx_desc), EM_DBA_ALIGN);
scctx->isc_txd_size[0] = sizeof(union e1000_adv_tx_desc);
scctx->isc_rxd_size[0] = sizeof(union e1000_adv_rx_desc);
scctx->isc_txrx = &igb_txrx;
@@ -882,8 +1063,10 @@ em_if_attach_pre(if_ctx_t ctx)
*/
scctx->isc_msix_bar = pci_msix_table_bar(dev);
} else if (hw->mac.type >= em_mac_min) {
- scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0]* sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
- scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN);
+ scctx->isc_txqsizes[0] = roundup2(scctx->isc_ntxd[0] *
+ sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
+ scctx->isc_rxqsizes[0] = roundup2(scctx->isc_nrxd[0] *
+ sizeof(union e1000_rx_desc_extended), EM_DBA_ALIGN);
scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
scctx->isc_rxd_size[0] = sizeof(union e1000_rx_desc_extended);
scctx->isc_txrx = &em_txrx;
@@ -894,11 +1077,12 @@ em_if_attach_pre(if_ctx_t ctx)
scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO |
CSUM_IP6_TCP | CSUM_IP6_UDP;
- /* Disable TSO on all em(4) until ring stalls can be debugged */
+ /* Disable TSO on all em(4) until ring stalls are debugged */
scctx->isc_capenable &= ~IFCAP_TSO;
/*
- * Disable TSO on SPT due to errata that downclocks DMA performance
+ * Disable TSO on SPT due to errata that downclocks DMA
+ * performance
* i218-i219 Specification Update 1.5.4.5
*/
if (hw->mac.type == e1000_pch_spt)
@@ -915,8 +1099,10 @@ em_if_attach_pre(if_ctx_t ctx)
scctx->isc_disable_msix = 1;
}
} else {
- scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) * sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
- scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) * sizeof(struct e1000_rx_desc), EM_DBA_ALIGN);
+ scctx->isc_txqsizes[0] = roundup2((scctx->isc_ntxd[0] + 1) *
+ sizeof(struct e1000_tx_desc), EM_DBA_ALIGN);
+ scctx->isc_rxqsizes[0] = roundup2((scctx->isc_nrxd[0] + 1) *
+ sizeof(struct e1000_rx_desc), EM_DBA_ALIGN);
scctx->isc_txd_size[0] = sizeof(struct e1000_tx_desc);
scctx->isc_rxd_size[0] = sizeof(struct e1000_rx_desc);
scctx->isc_txrx = &lem_txrx;
@@ -929,7 +1115,7 @@ em_if_attach_pre(if_ctx_t ctx)
scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO |
CSUM_IP6_TCP | CSUM_IP6_UDP;
- /* Disable TSO on all lem(4) until ring stalls can be debugged */
+ /* Disable TSO on all lem(4) until ring stalls debugged */
scctx->isc_capenable &= ~IFCAP_TSO;
/* 82541ER doesn't do HW tagging */
@@ -940,15 +1126,18 @@ em_if_attach_pre(if_ctx_t ctx)
}
/* This is the first e1000 chip and it does not do offloads */
if (hw->mac.type == e1000_82542) {
- scctx->isc_capabilities &= ~(IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM |
- IFCAP_HWCSUM_IPV6 | IFCAP_VLAN_HWTAGGING |
- IFCAP_VLAN_HWFILTER | IFCAP_TSO | IFCAP_VLAN_HWTSO);
+ scctx->isc_capabilities &= ~(IFCAP_HWCSUM |
+ IFCAP_VLAN_HWCSUM | IFCAP_HWCSUM_IPV6 |
+ IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWFILTER |
+ IFCAP_TSO | IFCAP_VLAN_HWTSO);
scctx->isc_capenable = scctx->isc_capabilities;
}
/* These can't do TSO for various reasons */
- if (hw->mac.type < e1000_82544 || hw->mac.type == e1000_82547 ||
+ if (hw->mac.type < e1000_82544 ||
+ hw->mac.type == e1000_82547 ||
hw->mac.type == e1000_82547_rev_2) {
- scctx->isc_capabilities &= ~(IFCAP_TSO | IFCAP_VLAN_HWTSO);
+ scctx->isc_capabilities &=
+ ~(IFCAP_TSO |IFCAP_VLAN_HWTSO);
scctx->isc_capenable = scctx->isc_capabilities;
}
/* XXXKB: No IPv6 before this? */
@@ -956,10 +1145,14 @@ em_if_attach_pre(if_ctx_t ctx)
scctx->isc_capabilities &= ~IFCAP_HWCSUM_IPV6;
scctx->isc_capenable = scctx->isc_capabilities;
}
- /* "PCI/PCI-X SDM 4.0" page 33 (b) - FDX requirement on these chips */
- if (hw->mac.type == e1000_82547 || hw->mac.type == e1000_82547_rev_2)
- scctx->isc_capenable &= ~(IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM |
- IFCAP_HWCSUM_IPV6);
+ /*
+ * "PCI/PCI-X SDM 4.0" page 33 (b):
+ * FDX requirement on these chips
+ */
+ if (hw->mac.type == e1000_82547 ||
+ hw->mac.type == e1000_82547_rev_2)
+ scctx->isc_capenable &= ~(IFCAP_HWCSUM |
+ IFCAP_VLAN_HWCSUM | IFCAP_HWCSUM_IPV6);
/* INTx only */
scctx->isc_msix_bar = 0;
@@ -1006,11 +1199,9 @@ em_if_attach_pre(if_ctx_t ctx)
** FLASH read/write macros in the shared code.
*/
else if (hw->mac.type >= e1000_pch_spt) {
- sc->osdep.flash_bus_space_tag =
- sc->osdep.mem_bus_space_tag;
+ sc->osdep.flash_bus_space_tag = sc->osdep.mem_bus_space_tag;
sc->osdep.flash_bus_space_handle =
- sc->osdep.mem_bus_space_handle
- + E1000_FLASH_BASE_ADDR;
+ sc->osdep.mem_bus_space_handle + E1000_FLASH_BASE_ADDR;
}
/* Do Shared Code initialization */
@@ -1026,27 +1217,24 @@ em_if_attach_pre(if_ctx_t ctx)
e1000_get_bus_info(hw);
/* Set up some sysctls for the tunable interrupt delays */
- em_add_int_delay_sysctl(sc, "rx_int_delay",
- "receive interrupt delay in usecs", &sc->rx_int_delay,
- E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt);
- em_add_int_delay_sysctl(sc, "tx_int_delay",
- "transmit interrupt delay in usecs", &sc->tx_int_delay,
- E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt);
- em_add_int_delay_sysctl(sc, "rx_abs_int_delay",
- "receive interrupt delay limit in usecs",
- &sc->rx_abs_int_delay,
- E1000_REGISTER(hw, E1000_RADV),
- em_rx_abs_int_delay_dflt);
- em_add_int_delay_sysctl(sc, "tx_abs_int_delay",
- "transmit interrupt delay limit in usecs",
- &sc->tx_abs_int_delay,
- E1000_REGISTER(hw, E1000_TADV),
- em_tx_abs_int_delay_dflt);
- em_add_int_delay_sysctl(sc, "itr",
- "interrupt delay limit in usecs/4",
- &sc->tx_itr,
- E1000_REGISTER(hw, E1000_ITR),
- DEFAULT_ITR);
+ if (hw->mac.type < igb_mac_min) {
+ em_add_int_delay_sysctl(sc, "rx_int_delay",
+ "receive interrupt delay in usecs", &sc->rx_int_delay,
+ E1000_REGISTER(hw, E1000_RDTR), em_rx_int_delay_dflt);
+ em_add_int_delay_sysctl(sc, "tx_int_delay",
+ "transmit interrupt delay in usecs", &sc->tx_int_delay,
+ E1000_REGISTER(hw, E1000_TIDV), em_tx_int_delay_dflt);
+ }
+ if (hw->mac.type >= e1000_82540 && hw->mac.type < igb_mac_min) {
+ em_add_int_delay_sysctl(sc, "rx_abs_int_delay",
+ "receive interrupt delay limit in usecs",
+ &sc->rx_abs_int_delay,
+ E1000_REGISTER(hw, E1000_RADV), em_rx_abs_int_delay_dflt);
+ em_add_int_delay_sysctl(sc, "tx_abs_int_delay",
+ "transmit interrupt delay limit in usecs",
+ &sc->tx_abs_int_delay,
+ E1000_REGISTER(hw, E1000_TADV), em_tx_abs_int_delay_dflt);
+ }
hw->mac.autoneg = DO_AUTO_NEG;
hw->phy.autoneg_wait_to_complete = false;
@@ -1080,7 +1268,8 @@ em_if_attach_pre(if_ctx_t ctx)
sc->mta = malloc(sizeof(u8) * ETHER_ADDR_LEN *
MAX_NUM_MULTICAST_ADDRESSES, M_DEVBUF, M_NOWAIT);
if (sc->mta == NULL) {
- device_printf(dev, "Can not allocate multicast setup array\n");
+ device_printf(dev,
+ "Can not allocate multicast setup array\n");
error = ENOMEM;
goto err_late;
}
@@ -1090,11 +1279,14 @@ em_if_attach_pre(if_ctx_t ctx)
/* Check SOL/IDER usage */
if (e1000_check_reset_block(hw))
- device_printf(dev, "PHY reset is blocked"
- " due to SOL/IDER session.\n");
+ device_printf(dev,
+ "PHY reset is blocked due to SOL/IDER session.\n");
/* Sysctl for setting Energy Efficient Ethernet */
- hw->dev_spec.ich8lan.eee_disable = eee_setting;
+ if (hw->mac.type < igb_mac_min)
+ hw->dev_spec.ich8lan.eee_disable = eee_setting;
+ else
+ hw->dev_spec._82575.eee_disable = eee_setting;
SYSCTL_ADD_PROC(ctx_list, child, OID_AUTO, "eee_control",
CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0,
em_sysctl_eee, "I", "Disable Energy Efficient Ethernet");
@@ -1123,8 +1315,8 @@ em_if_attach_pre(if_ctx_t ctx)
/* Copy the permanent MAC address out of the EEPROM */
if (e1000_read_mac_addr(hw) < 0) {
- device_printf(dev, "EEPROM read error while reading MAC"
- " address\n");
+ device_printf(dev,
+ "EEPROM read error while reading MAC address\n");
error = EIO;
goto err_late;
}
@@ -1199,7 +1391,10 @@ em_if_attach_post(if_ctx_t ctx)
return (0);
err_late:
- /* upon attach_post() error, iflib calls _if_detach() to free resources. */
+ /*
+ * Upon em_if_attach_post() error, iflib calls em_if_detach() to
+ * free resources
+ */
return (error);
}
@@ -1341,8 +1536,7 @@ em_if_init(if_ctx_t ctx)
INIT_DEBUGOUT("em_if_init: begin");
/* Get the latest mac address, User can use a LAA */
- bcopy(if_getlladdr(ifp), sc->hw.mac.addr,
- ETHER_ADDR_LEN);
+ bcopy(if_getlladdr(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
/* Put the address into the Receive Address Array */
e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
@@ -1363,7 +1557,8 @@ em_if_init(if_ctx_t ctx)
em_reset(ctx);
em_if_update_admin_status(ctx);
- for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues; i++, tx_que++) {
+ for (i = 0, tx_que = sc->tx_queues; i < sc->tx_num_queues;
+ i++, tx_que++) {
struct tx_ring *txr = &tx_que->txr;
txr->tx_rs_cidx = txr->tx_rs_pidx;
@@ -1410,8 +1605,10 @@ em_if_init(if_ctx_t ctx)
E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp);
/* Set the IVAR - interrupt vector routing. */
E1000_WRITE_REG(&sc->hw, E1000_IVAR, sc->ivars);
- } else if (sc->intr_type == IFLIB_INTR_MSIX) /* Set up queue routing */
+ } else if (sc->intr_type == IFLIB_INTR_MSIX) {
+ /* Set up queue routing */
igb_configure_queues(sc);
+ }
/* this clears any pending interrupts */
E1000_READ_REG(&sc->hw, E1000_ICR);
@@ -1431,6 +1628,169 @@ em_if_init(if_ctx_t ctx)
}
}
+enum itr_latency_target {
+ itr_latency_disabled = 0,
+ itr_latency_lowest = 1,
+ itr_latency_low = 2,
+ itr_latency_bulk = 3
+};
+/*********************************************************************
+ *
+ * Helper to calculate next (E)ITR value for AIM
+ *
+ *********************************************************************/
+static void
+em_newitr(struct e1000_softc *sc, struct em_rx_queue *que,
+ struct tx_ring *txr, struct rx_ring *rxr)
+{
+ struct e1000_hw *hw = &sc->hw;
+ unsigned long bytes, bytes_per_packet, packets;
+ unsigned long rxbytes, rxpackets, txbytes, txpackets;
+ u32 newitr;
+ u8 nextlatency;
+
+ rxbytes = atomic_load_long(&rxr->rx_bytes);
+ txbytes = atomic_load_long(&txr->tx_bytes);
+
+ /* Idle, do nothing */
+ if (txbytes == 0 && rxbytes == 0)
+ return;
+
+ newitr = 0;
+
+ if (sc->enable_aim) {
+ nextlatency = rxr->rx_nextlatency;
+
+ /* Use half default (4K) ITR if sub-gig */
+ if (sc->link_speed != 1000) {
+ newitr = EM_INTS_4K;
+ goto em_set_next_itr;
+ }
+ /* Want at least enough packet buffer for two frames to AIM */
+ if (sc->shared->isc_max_frame_size * 2 > (sc->pba << 10)) {
+ newitr = em_max_interrupt_rate;
+ sc->enable_aim = 0;
+ goto em_set_next_itr;
+ }
+
+ bytes = bytes_per_packet = 0;
+ /* Get largest values from the associated tx and rx ring */
+ txpackets = atomic_load_long(&txr->tx_packets);
+ if (txpackets != 0) {
+ bytes = txbytes;
+ bytes_per_packet = txbytes / txpackets;
+ packets = txpackets;
+ }
+ rxpackets = atomic_load_long(&rxr->rx_packets);
+ if (rxpackets != 0) {
+ bytes = lmax(bytes, rxbytes);
+ bytes_per_packet =
+ lmax(bytes_per_packet, rxbytes / rxpackets);
+ packets = lmax(packets, rxpackets);
+ }
+
+ /* Latency state machine */
+ switch (nextlatency) {
+ case itr_latency_disabled: /* Bootstrapping */
+ nextlatency = itr_latency_low;
+ break;
+ case itr_latency_lowest: /* 70k ints/s */
+ /* TSO and jumbo frames */
+ if (bytes_per_packet > 8000)
+ nextlatency = itr_latency_bulk;
+ else if ((packets < 5) && (bytes > 512))
+ nextlatency = itr_latency_low;
+ break;
+ case itr_latency_low: /* 20k ints/s */
+ if (bytes > 10000) {
+ /* Handle TSO */
+ if (bytes_per_packet > 8000)
+ nextlatency = itr_latency_bulk;
+ else if ((packets < 10) ||
+ (bytes_per_packet > 1200))
+ nextlatency = itr_latency_bulk;
+ else if (packets > 35)
+ nextlatency = itr_latency_lowest;
+ } else if (bytes_per_packet > 2000) {
+ nextlatency = itr_latency_bulk;
+ } else if (packets < 3 && bytes < 512) {
+ nextlatency = itr_latency_lowest;
+ }
+ break;
+ case itr_latency_bulk: /* 4k ints/s */
+ if (bytes > 25000) {
+ if (packets > 35)
+ nextlatency = itr_latency_low;
+ } else if (bytes < 1500)
+ nextlatency = itr_latency_low;
+ break;
+ default:
+ nextlatency = itr_latency_low;
+ device_printf(sc->dev,
+ "Unexpected newitr transition %d\n", nextlatency);
+ break;
+ }
+
+ /* Trim itr_latency_lowest for default AIM setting */
+ if (sc->enable_aim == 1 && nextlatency == itr_latency_lowest)
+ nextlatency = itr_latency_low;
+
+ /* Request new latency */
+ rxr->rx_nextlatency = nextlatency;
+ } else {
+ /* We may have toggled to AIM disabled */
+ nextlatency = itr_latency_disabled;
+ rxr->rx_nextlatency = nextlatency;
+ }
+
+ /* ITR state machine */
+ switch(nextlatency) {
+ case itr_latency_lowest:
+ newitr = EM_INTS_70K;
+ break;
+ case itr_latency_low:
+ newitr = EM_INTS_20K;
+ break;
+ case itr_latency_bulk:
+ newitr = EM_INTS_4K;
+ break;
+ case itr_latency_disabled:
+ default:
+ newitr = em_max_interrupt_rate;
+ break;
+ }
+
+em_set_next_itr:
+ if (hw->mac.type >= igb_mac_min) {
+ newitr = IGB_INTS_TO_EITR(newitr);
+
+ if (hw->mac.type == e1000_82575)
+ newitr |= newitr << 16;
+ else
+ newitr |= E1000_EITR_CNT_IGNR;
+
+ if (newitr != que->itr_setting) {
+ que->itr_setting = newitr;
+ E1000_WRITE_REG(hw, E1000_EITR(que->msix),
+ que->itr_setting);
+ }
+ } else {
+ newitr = EM_INTS_TO_ITR(newitr);
+
+ if (newitr != que->itr_setting) {
+ que->itr_setting = newitr;
+ if (hw->mac.type == e1000_82574 && que->msix) {
+ E1000_WRITE_REG(hw,
+ E1000_EITR_82574(que->msix),
+ que->itr_setting);
+ } else {
+ E1000_WRITE_REG(hw, E1000_ITR,
+ que->itr_setting);
+ }
+ }
+ }
+}
+
/*********************************************************************
*
* Fast Legacy/MSI Combined Interrupt Service routine
@@ -1440,10 +1800,14 @@ int
em_intr(void *arg)
{
struct e1000_softc *sc = arg;
+ struct e1000_hw *hw = &sc->hw;
+ struct em_rx_queue *que = &sc->rx_queues[0];
+ struct tx_ring *txr = &sc->tx_queues[0].txr;
+ struct rx_ring *rxr = &que->rxr;
if_ctx_t ctx = sc->ctx;
u32 reg_icr;
- reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
+ reg_icr = E1000_READ_REG(hw, E1000_ICR);
/* Hot eject? */
if (reg_icr == 0xffffffff)
@@ -1457,7 +1821,7 @@ em_intr(void *arg)
* Starting with the 82571 chip, bit 31 should be used to
* determine whether the interrupt belongs to us.
*/
- if (sc->hw.mac.type >= e1000_82571 &&
+ if (hw->mac.type >= e1000_82571 &&
(reg_icr & E1000_ICR_INT_ASSERTED) == 0)
return FILTER_STRAY;
@@ -1476,6 +1840,15 @@ em_intr(void *arg)
if (reg_icr & E1000_ICR_RXO)
sc->rx_overruns++;
+ if (hw->mac.type >= e1000_82540)
+ em_newitr(sc, que, txr, rxr);
+
+ /* Reset state */
+ txr->tx_bytes = 0;
+ txr->tx_packets = 0;
+ rxr->rx_bytes = 0;
+ rxr->rx_packets = 0;
+
return (FILTER_SCHEDULE_THREAD);
}
@@ -1528,9 +1901,20 @@ static int
em_msix_que(void *arg)
{
struct em_rx_queue *que = arg;
+ struct e1000_softc *sc = que->sc;
+ struct tx_ring *txr = &sc->tx_queues[que->msix].txr;
+ struct rx_ring *rxr = &que->rxr;
++que->irqs;
+ em_newitr(sc, que, txr, rxr);
+
+ /* Reset state */
+ txr->tx_bytes = 0;
+ txr->tx_packets = 0;
+ rxr->rx_bytes = 0;
+ rxr->rx_packets = 0;
+
return (FILTER_SCHEDULE_THREAD);
}
@@ -1560,8 +1944,8 @@ em_msix_link(void *arg)
E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->link_mask);
} else if (sc->hw.mac.type == e1000_82574) {
- E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC |
- E1000_IMS_OTHER);
+ E1000_WRITE_REG(&sc->hw, E1000_IMS,
+ E1000_IMS_LSC | E1000_IMS_OTHER);
/*
* Because we must read the ICR for this interrupt it may
* clear other causes using autoclear, for this reason we
@@ -1616,7 +2000,18 @@ em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr)
(sc->hw.phy.media_type == e1000_media_type_internal_serdes)) {
if (sc->hw.mac.type == e1000_82545)
fiber_type = IFM_1000_LX;
- ifmr->ifm_active |= fiber_type | IFM_FDX;
+ switch (sc->link_speed) {
+ case 10:
+ ifmr->ifm_active |= IFM_10_FL;
+ break;
+ case 100:
+ ifmr->ifm_active |= IFM_100_FX;
+ break;
+ case 1000:
+ default:
+ ifmr->ifm_active |= fiber_type | IFM_FDX;
+ break;
+ }
} else {
switch (sc->link_speed) {
case 10:
@@ -1629,11 +2024,12 @@ em_if_media_status(if_ctx_t ctx, struct ifmediareq *ifmr)
ifmr->ifm_active |= IFM_1000_T;
break;
}
- if (sc->link_duplex == FULL_DUPLEX)
- ifmr->ifm_active |= IFM_FDX;
- else
- ifmr->ifm_active |= IFM_HDX;
}
+
+ if (sc->link_duplex == FULL_DUPLEX)
+ ifmr->ifm_active |= IFM_FDX;
+ else
+ ifmr->ifm_active |= IFM_HDX;
}
/*********************************************************************
@@ -1667,6 +2063,26 @@ em_if_media_change(if_ctx_t ctx)
sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
break;
case IFM_100_TX:
+ sc->hw.mac.autoneg = DO_AUTO_NEG;
+ if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
+ sc->hw.phy.autoneg_advertised = ADVERTISE_100_FULL;
+ sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
+ } else {
+ sc->hw.phy.autoneg_advertised = ADVERTISE_100_HALF;
+ sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
+ }
+ break;
+ case IFM_10_T:
+ sc->hw.mac.autoneg = DO_AUTO_NEG;
+ if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
+ sc->hw.phy.autoneg_advertised = ADVERTISE_10_FULL;
+ sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
+ } else {
+ sc->hw.phy.autoneg_advertised = ADVERTISE_10_HALF;
+ sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
+ }
+ break;
+ case IFM_100_FX:
sc->hw.mac.autoneg = false;
sc->hw.phy.autoneg_advertised = 0;
if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
@@ -1674,7 +2090,7 @@ em_if_media_change(if_ctx_t ctx)
else
sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
break;
- case IFM_10_T:
+ case IFM_10_FL:
sc->hw.mac.autoneg = false;
sc->hw.phy.autoneg_advertised = 0;
if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
@@ -1704,7 +2120,8 @@ em_if_set_promisc(if_ctx_t ctx, int flags)
if (flags & IFF_ALLMULTI)
mcnt = MAX_NUM_MULTICAST_ADDRESSES;
else
- mcnt = min(if_llmaddr_count(ifp), MAX_NUM_MULTICAST_ADDRESSES);
+ mcnt = min(if_llmaddr_count(ifp),
+ MAX_NUM_MULTICAST_ADDRESSES);
if (mcnt < MAX_NUM_MULTICAST_ADDRESSES)
reg_rctl &= (~E1000_RCTL_MPE);
@@ -1753,7 +2170,7 @@ em_if_multi_set(if_ctx_t ctx)
{
struct e1000_softc *sc = iflib_get_softc(ctx);
if_t ifp = iflib_get_ifp(ctx);
- u8 *mta; /* Multicast array memory */
+ u8 *mta; /* Multicast array memory */
u32 reg_rctl = 0;
int mcnt = 0;
@@ -1812,7 +2229,6 @@ em_if_multi_set(if_ctx_t ctx)
static void
em_if_timer(if_ctx_t ctx, uint16_t qid)
{
-
if (qid != 0)
return;
@@ -1846,8 +2262,8 @@ em_if_update_admin_status(if_ctx_t ctx)
break;
case e1000_media_type_fiber:
e1000_check_for_link(hw);
- link_check = (E1000_READ_REG(hw, E1000_STATUS) &
- E1000_STATUS_LU);
+ link_check =
+ (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU);
break;
case e1000_media_type_internal_serdes:
e1000_check_for_link(hw);
@@ -1904,11 +2320,11 @@ em_if_update_admin_status(if_ctx_t ctx)
sc->flags |= IGB_MEDIA_RESET;
em_reset(ctx);
}
- /* Only do TSO on gigabit Ethernet for older chips due to errata */
+ /* Only do TSO on gigabit for older chips due to errata */
if (hw->mac.type < igb_mac_min)
automasked = em_automask_tso(ctx);
- /* Automasking resets the interface, so don't mark it up yet */
+ /* Automasking resets the interface so don't mark it up yet */
if (!automasked)
iflib_link_state_change(ctx, LINK_STATE_UP,
IF_Mbps(sc->link_speed));
@@ -1983,10 +2399,8 @@ em_identify_hardware(if_ctx_t ctx)
sc->hw.vendor_id = pci_get_vendor(dev);
sc->hw.device_id = pci_get_device(dev);
sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
- sc->hw.subsystem_vendor_id =
- pci_read_config(dev, PCIR_SUBVEND_0, 2);
- sc->hw.subsystem_device_id =
- pci_read_config(dev, PCIR_SUBDEV_0, 2);
+ sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
+ sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
/* Do Shared Code Init and Setup */
if (e1000_set_mac_type(&sc->hw)) {
@@ -2010,15 +2424,15 @@ em_allocate_pci_resources(if_ctx_t ctx)
int rid, val;
rid = PCIR_BAR(0);
- sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
- &rid, RF_ACTIVE);
+ sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
+ RF_ACTIVE);
if (sc->memory == NULL) {
- device_printf(dev, "Unable to allocate bus resource: memory\n");
+ device_printf(dev,
+ "Unable to allocate bus resource: memory\n");
return (ENXIO);
}
sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
- sc->osdep.mem_bus_space_handle =
- rman_get_bushandle(sc->memory);
+ sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory);
sc->hw.hw_addr = (u8 *)&sc->osdep.mem_bus_space_handle;
/* Only older adapters use IO mapping */
@@ -2041,8 +2455,8 @@ em_allocate_pci_resources(if_ctx_t ctx)
sc->ioport = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
&rid, RF_ACTIVE);
if (sc->ioport == NULL) {
- device_printf(dev, "Unable to allocate bus resource: "
- "ioport\n");
+ device_printf(dev,
+ "Unable to allocate bus resource: ioport\n");
return (ENXIO);
}
sc->hw.io_base = 0;
@@ -2075,9 +2489,12 @@ em_if_msix_intr_assign(if_ctx_t ctx, int msix)
for (i = 0; i < sc->rx_num_queues; i++, rx_que++, vector++) {
rid = vector + 1;
snprintf(buf, sizeof(buf), "rxq%d", i);
- error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid, IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf);
+ error = iflib_irq_alloc_generic(ctx, &rx_que->que_irq, rid,
+ IFLIB_INTR_RXTX, em_msix_que, rx_que, rx_que->me, buf);
if (error) {
- device_printf(iflib_get_dev(ctx), "Failed to allocate que int %d err: %d", i, error);
+ device_printf(iflib_get_dev(ctx),
+ "Failed to allocate que int %d err: %d",
+ i, error);
sc->rx_num_queues = i + 1;
goto fail;
}
@@ -2130,10 +2547,12 @@ em_if_msix_intr_assign(if_ctx_t ctx, int msix)
/* Link interrupt */
rid = rx_vectors + 1;
- error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, IFLIB_INTR_ADMIN, em_msix_link, sc, 0, "aq");
+ error = iflib_irq_alloc_generic(ctx, &sc->irq, rid, IFLIB_INTR_ADMIN,
+ em_msix_link, sc, 0, "aq");
if (error) {
- device_printf(iflib_get_dev(ctx), "Failed to register admin handler");
+ device_printf(iflib_get_dev(ctx),
+ "Failed to register admin handler");
goto fail;
}
sc->linkvec = rx_vectors;
@@ -2183,7 +2602,8 @@ igb_configure_queues(struct e1000_softc *sc)
rx_que = &sc->rx_queues[i];
if (i & 1) {
ivar &= 0xFF00FFFF;
- ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
+ ivar |= (rx_que->msix | E1000_IVAR_VALID) <<
+ 16;
} else {
ivar &= 0xFFFFFF00;
ivar |= rx_que->msix | E1000_IVAR_VALID;
@@ -2197,10 +2617,12 @@ igb_configure_queues(struct e1000_softc *sc)
tx_que = &sc->tx_queues[i];
if (i & 1) {
ivar &= 0x00FFFFFF;
- ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
+ ivar |= (tx_que->msix | E1000_IVAR_VALID) <<
+ 24;
} else {
ivar &= 0xFFFF00FF;
- ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
+ ivar |= (tx_que->msix | E1000_IVAR_VALID) <<
+ 8;
}
E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
sc->que_mask |= tx_que->eims;
@@ -2222,7 +2644,8 @@ igb_configure_queues(struct e1000_softc *sc)
ivar |= rx_que->msix | E1000_IVAR_VALID;
} else {
ivar &= 0xFF00FFFF;
- ivar |= (rx_que->msix | E1000_IVAR_VALID) << 16;
+ ivar |= (rx_que->msix | E1000_IVAR_VALID) <<
+ 16;
}
E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
sc->que_mask |= rx_que->eims;
@@ -2234,10 +2657,12 @@ igb_configure_queues(struct e1000_softc *sc)
tx_que = &sc->tx_queues[i];
if (i < 8) {
ivar &= 0xFFFF00FF;
- ivar |= (tx_que->msix | E1000_IVAR_VALID) << 8;
+ ivar |= (tx_que->msix | E1000_IVAR_VALID) <<
+ 8;
} else {
ivar &= 0x00FFFFFF;
- ivar |= (tx_que->msix | E1000_IVAR_VALID) << 24;
+ ivar |= (tx_que->msix | E1000_IVAR_VALID) <<
+ 24;
}
E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
sc->que_mask |= tx_que->eims;
@@ -2264,8 +2689,8 @@ igb_configure_queues(struct e1000_softc *sc)
tmp = E1000_EICR_RX_QUEUE0 << i;
tmp |= E1000_EICR_TX_QUEUE0 << i;
rx_que->eims = tmp;
- E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0),
- i, rx_que->eims);
+ E1000_WRITE_REG_ARRAY(hw, E1000_MSIXBM(0), i,
+ rx_que->eims);
sc->que_mask |= rx_que->eims;
}
@@ -2277,18 +2702,19 @@ igb_configure_queues(struct e1000_softc *sc)
break;
}
- /* Set the starting interrupt rate */
- if (em_max_interrupt_rate > 0)
- newitr = (4000000 / em_max_interrupt_rate) & 0x7FFC;
+ /* Set the igb starting interrupt rate */
+ if (em_max_interrupt_rate > 0) {
+ newitr = IGB_INTS_TO_EITR(em_max_interrupt_rate);
- if (hw->mac.type == e1000_82575)
- newitr |= newitr << 16;
- else
- newitr |= E1000_EITR_CNT_IGNR;
+ if (hw->mac.type == e1000_82575)
+ newitr |= newitr << 16;
+ else
+ newitr |= E1000_EITR_CNT_IGNR;
- for (int i = 0; i < sc->rx_num_queues; i++) {
- rx_que = &sc->rx_queues[i];
- E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr);
+ for (int i = 0; i < sc->rx_num_queues; i++) {
+ rx_que = &sc->rx_queues[i];
+ E1000_WRITE_REG(hw, E1000_EITR(rx_que->msix), newitr);
+ }
}
return;
@@ -2524,11 +2950,11 @@ igb_init_dmac(struct e1000_softc *sc, u32 pba)
static void
em_flush_tx_ring(struct e1000_softc *sc)
{
- struct e1000_hw *hw = &sc->hw;
- struct tx_ring *txr = &sc->tx_queues->txr;
- struct e1000_tx_desc *txd;
- u32 tctl, txd_lower = E1000_TXD_CMD_IFCS;
- u16 size = 512;
+ struct e1000_hw *hw = &sc->hw;
+ struct tx_ring *txr = &sc->tx_queues->txr;
+ struct e1000_tx_desc *txd;
+ u32 tctl, txd_lower = E1000_TXD_CMD_IFCS;
+ u16 size = 512;
tctl = E1000_READ_REG(hw, E1000_TCTL);
E1000_WRITE_REG(hw, E1000_TCTL, tctl | E1000_TCTL_EN);
@@ -2556,8 +2982,8 @@ em_flush_tx_ring(struct e1000_softc *sc)
static void
em_flush_rx_ring(struct e1000_softc *sc)
{
- struct e1000_hw *hw = &sc->hw;
- u32 rctl, rxdctl;
+ struct e1000_hw *hw = &sc->hw;
+ u32 rctl, rxdctl;
rctl = E1000_READ_REG(hw, E1000_RCTL);
E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
@@ -2569,7 +2995,8 @@ em_flush_rx_ring(struct e1000_softc *sc)
rxdctl &= 0xffffc000;
/*
* update thresholds: prefetch threshold to 31, host threshold to 1
- * and make sure the granularity is "descriptors" and not "cache lines"
+ * and make sure the granularity is "descriptors" and not
+ * "cache lines"
*/
rxdctl |= (0x1F | (1 << 8) | E1000_RXDCTL_THRESH_UNIT_DESC);
E1000_WRITE_REG(hw, E1000_RXDCTL(0), rxdctl);
@@ -2596,15 +3023,15 @@ em_flush_desc_rings(struct e1000_softc *sc)
{
struct e1000_hw *hw = &sc->hw;
device_t dev = sc->dev;
- u16 hang_state;
- u32 fext_nvm11, tdlen;
+ u16 hang_state;
+ u32 fext_nvm11, tdlen;
/* First, disable MULR fix in FEXTNVM11 */
fext_nvm11 = E1000_READ_REG(hw, E1000_FEXTNVM11);
fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX;
E1000_WRITE_REG(hw, E1000_FEXTNVM11, fext_nvm11);
- /* do nothing if we're not in faulty state, or if the queue is empty */
+ /* do nothing if we're not in faulty state, or the queue is empty */
tdlen = E1000_READ_REG(hw, E1000_TDLEN(0));
hang_state = pci_read_config(dev, PCICFG_DESC_RING_STATUS, 2);
if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen)
@@ -2719,7 +3146,7 @@ em_reset(if_ctx_t ctx)
pba = E1000_PBA_34K;
break;
default:
- /* Remaining devices assumed to have a Packet Buffer of 64K. */
+ /* Remaining devices assumed to have Packet Buffer of 64K. */
if (hw->mac.max_frame_size > 8192)
pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
else
@@ -2762,7 +3189,8 @@ em_reset(if_ctx_t ctx)
* response (Rx) to Ethernet PAUSE frames.
* - High water mark should allow for at least two frames to be
* received after sending an XOFF.
- * - Low water mark works best when it is very near the high water mark.
+ * - Low water mark works best when it is very near the high water
+ mark.
* This allows the receiver to restart by sending XON when it has
* drained a bit. Here we use an arbitrary value of 1500 which will
* restart after one full frame is pulled from the buffer. There
@@ -2875,6 +3303,9 @@ em_reset(if_ctx_t ctx)
if (hw->mac.type >= igb_mac_min)
igb_init_dmac(sc, pba);
+ /* Save the final PBA off if it needs to be used elsewhere i.e. AIM */
+ sc->pba = pba;
+
E1000_WRITE_REG(hw, E1000_VET, ETHERTYPE_VLAN);
e1000_get_phy_info(hw);
e1000_check_for_link(hw);
@@ -2889,9 +3320,9 @@ em_reset(if_ctx_t ctx)
static void
em_initialize_rss_mapping(struct e1000_softc *sc)
{
- uint8_t rss_key[4 * RSSKEYLEN];
+ uint8_t rss_key[4 * RSSKEYLEN];
uint32_t reta = 0;
- struct e1000_hw *hw = &sc->hw;
+ struct e1000_hw *hw = &sc->hw;
int i;
/*
@@ -3052,16 +3483,21 @@ em_setup_interface(if_ctx_t ctx)
if (sc->hw.mac.type == e1000_82545)
fiber_type = IFM_1000_LX;
- ifmedia_add(sc->media, IFM_ETHER | fiber_type | IFM_FDX, 0, NULL);
+ ifmedia_add(sc->media,
+ IFM_ETHER | fiber_type | IFM_FDX, 0, NULL);
ifmedia_add(sc->media, IFM_ETHER | fiber_type, 0, NULL);
} else {
ifmedia_add(sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
- ifmedia_add(sc->media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
+ ifmedia_add(sc->media,
+ IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
- ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
+ ifmedia_add(sc->media,
+ IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
if (sc->hw.phy.type != e1000_phy_ife) {
- ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
- ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL);
+ ifmedia_add(sc->media,
+ IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
+ ifmedia_add(sc->media,
+ IFM_ETHER | IFM_1000_T, 0, NULL);
}
}
ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
@@ -3070,7 +3506,8 @@ em_setup_interface(if_ctx_t ctx)
}
static int
-em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs, int ntxqsets)
+em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs,
+ int ntxqs, int ntxqsets)
{
struct e1000_softc *sc = iflib_get_softc(ctx);
if_softc_ctx_t scctx = sc->shared;
@@ -3085,7 +3522,8 @@ em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs
if (!(sc->tx_queues =
(struct em_tx_queue *) malloc(sizeof(struct em_tx_queue) *
sc->tx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
- device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
+ device_printf(iflib_get_dev(ctx),
+ "Unable to allocate queue memory\n");
return(ENOMEM);
}
@@ -3097,14 +3535,17 @@ em_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int ntxqs
que->me = txr->me = i;
/* Allocate report status array */
- if (!(txr->tx_rsq = (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0], M_DEVBUF, M_NOWAIT | M_ZERO))) {
- device_printf(iflib_get_dev(ctx), "failed to allocate rs_idxs memory\n");
+ if (!(txr->tx_rsq =
+ (qidx_t *) malloc(sizeof(qidx_t) * scctx->isc_ntxd[0],
+ M_DEVBUF, M_NOWAIT | M_ZERO))) {
+ device_printf(iflib_get_dev(ctx),
+ "failed to allocate rs_idxs memory\n");
error = ENOMEM;
goto fail;
}
for (j = 0; j < scctx->isc_ntxd[0]; j++)
txr->tx_rsq[j] = QIDX_INVALID;
- /* get the virtual and physical address of the hardware queues */
+ /* get the virtual and physical address of hardware queues */
txr->tx_base = (struct e1000_tx_desc *)vaddrs[i*ntxqs];
txr->tx_paddr = paddrs[i*ntxqs];
}
@@ -3119,7 +3560,8 @@ fail:
}
static int
-em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs, int nrxqsets)
+em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs,
+ int nrxqs, int nrxqsets)
{
struct e1000_softc *sc = iflib_get_softc(ctx);
int error = E1000_SUCCESS;
@@ -3133,7 +3575,8 @@ em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs
if (!(sc->rx_queues =
(struct em_rx_queue *) malloc(sizeof(struct em_rx_queue) *
sc->rx_num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
- device_printf(iflib_get_dev(ctx), "Unable to allocate queue memory\n");
+ device_printf(iflib_get_dev(ctx),
+ "Unable to allocate queue memory\n");
error = ENOMEM;
goto fail;
}
@@ -3145,8 +3588,9 @@ em_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *vaddrs, uint64_t *paddrs, int nrxqs
rxr->que = que;
que->me = rxr->me = i;
- /* get the virtual and physical address of the hardware queues */
- rxr->rx_base = (union e1000_rx_desc_extended *)vaddrs[i*nrxqs];
+ /* get the virtual and physical address of hardware queues */
+ rxr->rx_base =
+ (union e1000_rx_desc_extended *)vaddrs[i*nrxqs];
rxr->rx_paddr = paddrs[i*nrxqs];
}
@@ -3219,10 +3663,8 @@ em_initialize_transmit_unit(if_ctx_t ctx)
/* Base and Len of TX Ring */
E1000_WRITE_REG(hw, E1000_TDLEN(i),
scctx->isc_ntxd[0] * sizeof(struct e1000_tx_desc));
- E1000_WRITE_REG(hw, E1000_TDBAH(i),
- (u32)(bus_addr >> 32));
- E1000_WRITE_REG(hw, E1000_TDBAL(i),
- (u32)bus_addr);
+ E1000_WRITE_REG(hw, E1000_TDBAH(i), (u32)(bus_addr >> 32));
+ E1000_WRITE_REG(hw, E1000_TDBAL(i), (u32)bus_addr);
/* Init the HEAD/TAIL indices */
E1000_WRITE_REG(hw, E1000_TDT(i), 0);
E1000_WRITE_REG(hw, E1000_TDH(i), 0);
@@ -3264,12 +3706,16 @@ em_initialize_transmit_unit(if_ctx_t ctx)
tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
}
- E1000_WRITE_REG(hw, E1000_TIPG, tipg);
- E1000_WRITE_REG(hw, E1000_TIDV, sc->tx_int_delay.value);
+ if (hw->mac.type < igb_mac_min) {
+ E1000_WRITE_REG(hw, E1000_TIPG, tipg);
+ E1000_WRITE_REG(hw, E1000_TIDV, sc->tx_int_delay.value);
- if(hw->mac.type >= e1000_82540)
- E1000_WRITE_REG(hw, E1000_TADV,
- sc->tx_abs_int_delay.value);
+ if (sc->tx_int_delay.value > 0)
+ sc->txd_cmd |= E1000_TXD_CMD_IDE;
+ }
+
+ if (hw->mac.type >= e1000_82540)
+ E1000_WRITE_REG(hw, E1000_TADV, sc->tx_abs_int_delay.value);
if (hw->mac.type == e1000_82571 || hw->mac.type == e1000_82572) {
tarc = E1000_READ_REG(hw, E1000_TARC(0));
@@ -3294,16 +3740,13 @@ em_initialize_transmit_unit(if_ctx_t ctx)
E1000_WRITE_REG(hw, E1000_TARC(0), tarc);
}
- if (sc->tx_int_delay.value > 0)
- sc->txd_cmd |= E1000_TXD_CMD_IDE;
-
/* Program the Transmit Control Register */
tctl = E1000_READ_REG(hw, E1000_TCTL);
tctl &= ~E1000_TCTL_CT;
tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
(E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
- if (hw->mac.type >= e1000_82571)
+ if (hw->mac.type >= e1000_82571 && hw->mac.type < igb_mac_min)
tctl |= E1000_TCTL_MULR;
/* This write will effectively turn on the transmit unit. */
@@ -3336,7 +3779,7 @@ em_initialize_receive_unit(if_ctx_t ctx)
struct e1000_softc *sc = iflib_get_softc(ctx);
if_softc_ctx_t scctx = sc->shared;
if_t ifp = iflib_get_ifp(ctx);
- struct e1000_hw *hw = &sc->hw;
+ struct e1000_hw *hw = &sc->hw;
struct em_rx_queue *que;
int i;
uint32_t rctl, rxcsum;
@@ -3371,17 +3814,29 @@ em_initialize_receive_unit(if_ctx_t ctx)
if (!em_disable_crc_stripping)
rctl |= E1000_RCTL_SECRC;
- if (hw->mac.type >= e1000_82540) {
- E1000_WRITE_REG(hw, E1000_RADV,
- sc->rx_abs_int_delay.value);
+ /* lem/em default interrupt moderation */
+ if (hw->mac.type < igb_mac_min) {
+ if (hw->mac.type >= e1000_82540) {
+ E1000_WRITE_REG(hw, E1000_RADV,
+ sc->rx_abs_int_delay.value);
- /*
- * Set the interrupt throttling rate. Value is calculated
- * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns)
+ /* Set the default interrupt throttling rate */
+ E1000_WRITE_REG(hw, E1000_ITR,
+ EM_INTS_TO_ITR(em_max_interrupt_rate));
+ }
+
+ /* XXX TEMPORARY WORKAROUND: on some systems with 82573
+ * long latencies are observed, like Lenovo X60. This
+ * change eliminates the problem, but since having positive
+ * values in RDTR is a known source of problems on other
+ * platforms another solution is being sought.
*/
- E1000_WRITE_REG(hw, E1000_ITR, DEFAULT_ITR);
+ if (hw->mac.type == e1000_82573)
+ E1000_WRITE_REG(hw, E1000_RDTR, 0x20);
+ else
+ E1000_WRITE_REG(hw, E1000_RDTR,
+ sc->rx_int_delay.value);
}
- E1000_WRITE_REG(hw, E1000_RDTR, sc->rx_int_delay.value);
if (hw->mac.type >= em_mac_min) {
uint32_t rfctl;
@@ -3396,7 +3851,7 @@ em_initialize_receive_unit(if_ctx_t ctx)
if (hw->mac.type == e1000_82574) {
for (int i = 0; i < 4; i++)
E1000_WRITE_REG(hw, E1000_EITR_82574(i),
- DEFAULT_ITR);
+ EM_INTS_TO_ITR(em_max_interrupt_rate));
/* Disable accelerated acknowledge */
rfctl |= E1000_RFCTL_ACK_DIS;
}
@@ -3431,16 +3886,6 @@ em_initialize_receive_unit(if_ctx_t ctx)
}
E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
- /*
- * XXX TEMPORARY WORKAROUND: on some systems with 82573
- * long latencies are observed, like Lenovo X60. This
- * change eliminates the problem, but since having positive
- * values in RDTR is a known source of problems on other
- * platforms another solution is being sought.
- */
- if (hw->mac.type == e1000_82573)
- E1000_WRITE_REG(hw, E1000_RDTR, 0x20);
-
for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) {
struct rx_ring *rxr = &que->rxr;
/* Setup the Base and Length of the Rx Descriptor Ring */
@@ -3450,7 +3895,8 @@ em_initialize_receive_unit(if_ctx_t ctx)
#endif
E1000_WRITE_REG(hw, E1000_RDLEN(i),
- scctx->isc_nrxd[0] * sizeof(union e1000_rx_desc_extended));
+ scctx->isc_nrxd[0] *
+ sizeof(union e1000_rx_desc_extended));
E1000_WRITE_REG(hw, E1000_RDBAH(i), (u32)(bus_addr >> 32));
E1000_WRITE_REG(hw, E1000_RDBAL(i), (u32)bus_addr);
/* Setup the Head and Tail Descriptor Pointers */
@@ -3498,18 +3944,20 @@ em_initialize_receive_unit(if_ctx_t ctx)
E1000_SRRCTL_BSIZEPKT_SHIFT;
/*
- * If TX flow control is disabled and there's >1 queue defined,
- * enable DROP.
+ * If TX flow control is disabled and there's >1 queue
+ * defined, enable DROP.
*
- * This drops frames rather than hanging the RX MAC for all queues.
+ * This drops frames rather than hanging the RX MAC for all
+ * queues.
*/
if ((sc->rx_num_queues > 1) &&
(sc->fc == e1000_fc_none ||
sc->fc == e1000_fc_rx_pause)) {
srrctl |= E1000_SRRCTL_DROP_EN;
}
- /* Setup the Base and Length of the Rx Descriptor Rings */
- for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues; i++, que++) {
+ /* Setup the Base and Length of the Rx Descriptor Rings */
+ for (i = 0, que = sc->rx_queues; i < sc->rx_num_queues;
+ i++, que++) {
struct rx_ring *rxr = &que->rxr;
u64 bus_addr = rxr->rx_paddr;
u32 rxdctl;
@@ -3522,11 +3970,12 @@ em_initialize_receive_unit(if_ctx_t ctx)
#endif
E1000_WRITE_REG(hw, E1000_RDLEN(i),
- scctx->isc_nrxd[0] * sizeof(struct e1000_rx_desc));
+ scctx->isc_nrxd[0] *
+ sizeof(struct e1000_rx_desc));
E1000_WRITE_REG(hw, E1000_RDBAH(i),
- (uint32_t)(bus_addr >> 32));
+ (uint32_t)(bus_addr >> 32));
E1000_WRITE_REG(hw, E1000_RDBAL(i),
- (uint32_t)bus_addr);
+ (uint32_t)bus_addr);
E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
/* Enable this Queue */
rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
@@ -3661,15 +4110,16 @@ em_if_vlan_filter_write(struct e1000_softc *sc)
if (sc->vf_ifp)
return;
- /* Disable interrupts for lem-class devices during the filter change */
+ /* Disable interrupts for lem(4) devices during the filter change */
if (hw->mac.type < em_mac_min)
em_if_intr_disable(sc->ctx);
for (int i = 0; i < EM_VFTA_SIZE; i++)
if (sc->shadow_vfta[i] != 0) {
- /* XXXKB: incomplete VF support, we return early above */
+ /* XXXKB: incomplete VF support, we returned above */
if (sc->vf_ifp)
- e1000_vfta_set_vf(hw, sc->shadow_vfta[i], true);
+ e1000_vfta_set_vf(hw, sc->shadow_vfta[i],
+ true);
else
e1000_write_vfta(hw, i, sc->shadow_vfta[i]);
}
@@ -3687,8 +4137,8 @@ em_setup_vlan_hw_support(if_ctx_t ctx)
if_t ifp = iflib_get_ifp(ctx);
u32 reg;
- /* XXXKB: Return early if we are a VF until VF decap and filter management
- * is ready and tested.
+ /* XXXKB: Return early if we are a VF until VF decap and filter
+ * management is ready and tested.
*/
if (sc->vf_ifp)
return;
@@ -3733,6 +4183,7 @@ em_if_intr_enable(if_ctx_t ctx)
E1000_WRITE_REG(hw, EM_EIAC, sc->ims);
ims_mask |= sc->ims;
}
+
E1000_WRITE_REG(hw, E1000_IMS, ims_mask);
E1000_WRITE_FLUSH(hw);
}
@@ -3900,8 +4351,10 @@ em_automask_tso(if_ctx_t ctx)
if_t ifp = iflib_get_ifp(ctx);
if (!em_unsupported_tso && sc->link_speed &&
- sc->link_speed != SPEED_1000 && scctx->isc_capenable & IFCAP_TSO) {
- device_printf(sc->dev, "Disabling TSO for 10/100 Ethernet.\n");
+ sc->link_speed != SPEED_1000 &&
+ scctx->isc_capenable & IFCAP_TSO) {
+ device_printf(sc->dev,
+ "Disabling TSO for 10/100 Ethernet.\n");
sc->tso_automasked = scctx->isc_capenable & IFCAP_TSO;
scctx->isc_capenable &= ~IFCAP_TSO;
if_setcapenablebit(ifp, 0, IFCAP_TSO);
@@ -4055,10 +4508,9 @@ em_enable_wakeup(if_ctx_t ctx)
device_t dev = iflib_get_dev(ctx);
if_t ifp = iflib_get_ifp(ctx);
int error = 0;
- u32 pmc, ctrl, ctrl_ext, rctl;
- u16 status;
+ u32 ctrl, ctrl_ext, rctl;
- if (pci_find_cap(dev, PCIY_PMG, &pmc) != 0)
+ if (!pci_has_pm(dev))
return;
/*
@@ -4115,11 +4567,8 @@ em_enable_wakeup(if_ctx_t ctx)
e1000_igp3_phy_powerdown_workaround_ich8lan(&sc->hw);
pme:
- status = pci_read_config(dev, pmc + PCIR_POWER_STATUS, 2);
- status &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
if (!error && (if_getcapenable(ifp) & IFCAP_WOL))
- status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
- pci_write_config(dev, pmc + PCIR_POWER_STATUS, status, 2);
+ pci_enable_pme(dev);
return;
}
@@ -4304,6 +4753,10 @@ em_update_stats_counters(struct e1000_softc *sc)
sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC);
sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC);
+ sc->stats.mgprc += E1000_READ_REG(&sc->hw, E1000_MGTPRC);
+ sc->stats.mgpdc += E1000_READ_REG(&sc->hw, E1000_MGTPDC);
+ sc->stats.mgptc += E1000_READ_REG(&sc->hw, E1000_MGTPTC);
+
sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH);
sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH);
@@ -4398,6 +4851,58 @@ em_sysctl_reg_handler(SYSCTL_HANDLER_ARGS)
return (sysctl_handle_int(oidp, &val, 0, req));
}
+/* Per queue holdoff interrupt rate handler */
+static int
+em_sysctl_interrupt_rate_handler(SYSCTL_HANDLER_ARGS)
+{
+ struct em_rx_queue *rque;
+ struct em_tx_queue *tque;
+ struct e1000_hw *hw;
+ int error;
+ u32 reg, usec, rate;
+
+ bool tx = oidp->oid_arg2;
+
+ if (tx) {
+ tque = oidp->oid_arg1;
+ hw = &tque->sc->hw;
+ if (hw->mac.type >= igb_mac_min)
+ reg = E1000_READ_REG(hw, E1000_EITR(tque->me));
+ else if (hw->mac.type == e1000_82574 && tque->msix)
+ reg = E1000_READ_REG(hw, E1000_EITR_82574(tque->me));
+ else
+ reg = E1000_READ_REG(hw, E1000_ITR);
+ } else {
+ rque = oidp->oid_arg1;
+ hw = &rque->sc->hw;
+ if (hw->mac.type >= igb_mac_min)
+ reg = E1000_READ_REG(hw, E1000_EITR(rque->msix));
+ else if (hw->mac.type == e1000_82574 && rque->msix)
+ reg = E1000_READ_REG(hw,
+ E1000_EITR_82574(rque->msix));
+ else
+ reg = E1000_READ_REG(hw, E1000_ITR);
+ }
+
+ if (hw->mac.type < igb_mac_min) {
+ if (reg > 0)
+ rate = EM_INTS_TO_ITR(reg);
+ else
+ rate = 0;
+ } else {
+ usec = (reg & IGB_QVECTOR_MASK);
+ if (usec > 0)
+ rate = IGB_INTS_TO_EITR(usec);
+ else
+ rate = 0;
+ }
+
+ error = sysctl_handle_int(oidp, &rate, 0, req);
+ if (error || !req->newptr)
+ return error;
+ return 0;
+}
+
/*
* Add sysctl variables, one per statistic, to the system.
*/
@@ -4421,31 +4926,31 @@ em_add_hw_stats(struct e1000_softc *sc)
/* Driver Statistics */
SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "dropped",
- CTLFLAG_RD, &sc->dropped_pkts,
- "Driver dropped packets");
+ CTLFLAG_RD, &sc->dropped_pkts,
+ "Driver dropped packets");
SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "link_irq",
- CTLFLAG_RD, &sc->link_irq,
- "Link MSI-X IRQ Handled");
+ CTLFLAG_RD, &sc->link_irq,
+ "Link MSI-X IRQ Handled");
SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "rx_overruns",
- CTLFLAG_RD, &sc->rx_overruns,
- "RX overruns");
+ CTLFLAG_RD, &sc->rx_overruns,
+ "RX overruns");
SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_timeouts",
- CTLFLAG_RD, &sc->watchdog_events,
- "Watchdog timeouts");
+ CTLFLAG_RD, &sc->watchdog_events,
+ "Watchdog timeouts");
SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "device_control",
- CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
+ CTLTYPE_UINT | CTLFLAG_RD,
sc, E1000_CTRL, em_sysctl_reg_handler, "IU",
"Device Control Register");
SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_control",
- CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
+ CTLTYPE_UINT | CTLFLAG_RD,
sc, E1000_RCTL, em_sysctl_reg_handler, "IU",
"Receiver Control Register");
SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_high_water",
- CTLFLAG_RD, &sc->hw.fc.high_water, 0,
- "Flow Control High Watermark");
+ CTLFLAG_RD, &sc->hw.fc.high_water, 0,
+ "Flow Control High Watermark");
SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "fc_low_water",
- CTLFLAG_RD, &sc->hw.fc.low_water, 0,
- "Flow Control Low Watermark");
+ CTLFLAG_RD, &sc->hw.fc.low_water, 0,
+ "Flow Control Low Watermark");
for (int i = 0; i < sc->tx_num_queues; i++, tx_que++) {
struct tx_ring *txr = &tx_que->txr;
@@ -4454,17 +4959,22 @@ em_add_hw_stats(struct e1000_softc *sc)
CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX Queue Name");
queue_list = SYSCTL_CHILDREN(queue_node);
+ SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "interrupt_rate",
+ CTLTYPE_UINT | CTLFLAG_RD, tx_que,
+ true, em_sysctl_interrupt_rate_handler,
+ "IU", "Interrupt Rate");
+
SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_head",
- CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
+ CTLTYPE_UINT | CTLFLAG_RD, sc,
E1000_TDH(txr->me), em_sysctl_reg_handler, "IU",
"Transmit Descriptor Head");
SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "txd_tail",
- CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
+ CTLTYPE_UINT | CTLFLAG_RD, sc,
E1000_TDT(txr->me), em_sysctl_reg_handler, "IU",
"Transmit Descriptor Tail");
SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "tx_irq",
- CTLFLAG_RD, &txr->tx_irq,
- "Queue MSI-X Transmit Interrupts");
+ CTLFLAG_RD, &txr->tx_irq,
+ "Queue MSI-X Transmit Interrupts");
}
for (int j = 0; j < sc->rx_num_queues; j++, rx_que++) {
@@ -4474,211 +4984,228 @@ em_add_hw_stats(struct e1000_softc *sc)
CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX Queue Name");
queue_list = SYSCTL_CHILDREN(queue_node);
+ SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "interrupt_rate",
+ CTLTYPE_UINT | CTLFLAG_RD, rx_que,
+ false, em_sysctl_interrupt_rate_handler,
+ "IU", "Interrupt Rate");
+
SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_head",
- CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
+ CTLTYPE_UINT | CTLFLAG_RD, sc,
E1000_RDH(rxr->me), em_sysctl_reg_handler, "IU",
"Receive Descriptor Head");
SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "rxd_tail",
- CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc,
+ CTLTYPE_UINT | CTLFLAG_RD, sc,
E1000_RDT(rxr->me), em_sysctl_reg_handler, "IU",
"Receive Descriptor Tail");
SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO, "rx_irq",
- CTLFLAG_RD, &rxr->rx_irq,
- "Queue MSI-X Receive Interrupts");
+ CTLFLAG_RD, &rxr->rx_irq,
+ "Queue MSI-X Receive Interrupts");
}
/* MAC stats get their own sub node */
-
stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats",
CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics");
stat_list = SYSCTL_CHILDREN(stat_node);
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "excess_coll",
- CTLFLAG_RD, &stats->ecol,
- "Excessive collisions");
+ CTLFLAG_RD, &stats->ecol,
+ "Excessive collisions");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "single_coll",
- CTLFLAG_RD, &stats->scc,
- "Single collisions");
+ CTLFLAG_RD, &stats->scc,
+ "Single collisions");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "multiple_coll",
- CTLFLAG_RD, &stats->mcc,
- "Multiple collisions");
+ CTLFLAG_RD, &stats->mcc,
+ "Multiple collisions");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "late_coll",
- CTLFLAG_RD, &stats->latecol,
- "Late collisions");
+ CTLFLAG_RD, &stats->latecol,
+ "Late collisions");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "collision_count",
- CTLFLAG_RD, &stats->colc,
- "Collision Count");
+ CTLFLAG_RD, &stats->colc,
+ "Collision Count");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "symbol_errors",
- CTLFLAG_RD, &sc->stats.symerrs,
- "Symbol Errors");
+ CTLFLAG_RD, &sc->stats.symerrs,
+ "Symbol Errors");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "sequence_errors",
- CTLFLAG_RD, &sc->stats.sec,
- "Sequence Errors");
+ CTLFLAG_RD, &sc->stats.sec,
+ "Sequence Errors");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "defer_count",
- CTLFLAG_RD, &sc->stats.dc,
- "Defer Count");
+ CTLFLAG_RD, &sc->stats.dc,
+ "Defer Count");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "missed_packets",
- CTLFLAG_RD, &sc->stats.mpc,
- "Missed Packets");
+ CTLFLAG_RD, &sc->stats.mpc,
+ "Missed Packets");
+ SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_length_errors",
+ CTLFLAG_RD, &sc->stats.rlec,
+ "Receive Length Errors");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_no_buff",
- CTLFLAG_RD, &sc->stats.rnbc,
- "Receive No Buffers");
+ CTLFLAG_RD, &sc->stats.rnbc,
+ "Receive No Buffers");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_undersize",
- CTLFLAG_RD, &sc->stats.ruc,
- "Receive Undersize");
+ CTLFLAG_RD, &sc->stats.ruc,
+ "Receive Undersize");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_fragmented",
- CTLFLAG_RD, &sc->stats.rfc,
- "Fragmented Packets Received ");
+ CTLFLAG_RD, &sc->stats.rfc,
+ "Fragmented Packets Received ");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_oversize",
- CTLFLAG_RD, &sc->stats.roc,
- "Oversized Packets Received");
+ CTLFLAG_RD, &sc->stats.roc,
+ "Oversized Packets Received");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_jabber",
- CTLFLAG_RD, &sc->stats.rjc,
- "Recevied Jabber");
+ CTLFLAG_RD, &sc->stats.rjc,
+ "Recevied Jabber");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "recv_errs",
- CTLFLAG_RD, &sc->stats.rxerrc,
- "Receive Errors");
+ CTLFLAG_RD, &sc->stats.rxerrc,
+ "Receive Errors");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "crc_errs",
- CTLFLAG_RD, &sc->stats.crcerrs,
- "CRC errors");
+ CTLFLAG_RD, &sc->stats.crcerrs,
+ "CRC errors");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "alignment_errs",
- CTLFLAG_RD, &sc->stats.algnerrc,
- "Alignment Errors");
+ CTLFLAG_RD, &sc->stats.algnerrc,
+ "Alignment Errors");
/* On 82575 these are collision counts */
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "coll_ext_errs",
- CTLFLAG_RD, &sc->stats.cexterr,
- "Collision/Carrier extension errors");
+ CTLFLAG_RD, &sc->stats.cexterr,
+ "Collision/Carrier extension errors");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_recvd",
- CTLFLAG_RD, &sc->stats.xonrxc,
- "XON Received");
+ CTLFLAG_RD, &sc->stats.xonrxc,
+ "XON Received");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xon_txd",
- CTLFLAG_RD, &sc->stats.xontxc,
- "XON Transmitted");
+ CTLFLAG_RD, &sc->stats.xontxc,
+ "XON Transmitted");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_recvd",
- CTLFLAG_RD, &sc->stats.xoffrxc,
- "XOFF Received");
+ CTLFLAG_RD, &sc->stats.xoffrxc,
+ "XOFF Received");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "xoff_txd",
- CTLFLAG_RD, &sc->stats.xofftxc,
- "XOFF Transmitted");
+ CTLFLAG_RD, &sc->stats.xofftxc,
+ "XOFF Transmitted");
+ SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "unsupported_fc_recvd",
+ CTLFLAG_RD, &sc->stats.fcruc,
+ "Unsupported Flow Control Received");
+ SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_recvd",
+ CTLFLAG_RD, &sc->stats.mgprc,
+ "Management Packets Received");
+ SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_drop",
+ CTLFLAG_RD, &sc->stats.mgpdc,
+ "Management Packets Dropped");
+ SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mgmt_pkts_txd",
+ CTLFLAG_RD, &sc->stats.mgptc,
+ "Management Packets Transmitted");
/* Packet Reception Stats */
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_recvd",
- CTLFLAG_RD, &sc->stats.tpr,
- "Total Packets Received ");
+ CTLFLAG_RD, &sc->stats.tpr,
+ "Total Packets Received ");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_recvd",
- CTLFLAG_RD, &sc->stats.gprc,
- "Good Packets Received");
+ CTLFLAG_RD, &sc->stats.gprc,
+ "Good Packets Received");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_recvd",
- CTLFLAG_RD, &sc->stats.bprc,
- "Broadcast Packets Received");
+ CTLFLAG_RD, &sc->stats.bprc,
+ "Broadcast Packets Received");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_recvd",
- CTLFLAG_RD, &sc->stats.mprc,
- "Multicast Packets Received");
+ CTLFLAG_RD, &sc->stats.mprc,
+ "Multicast Packets Received");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_64",
- CTLFLAG_RD, &sc->stats.prc64,
- "64 byte frames received ");
+ CTLFLAG_RD, &sc->stats.prc64,
+ "64 byte frames received ");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_65_127",
- CTLFLAG_RD, &sc->stats.prc127,
- "65-127 byte frames received");
+ CTLFLAG_RD, &sc->stats.prc127,
+ "65-127 byte frames received");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_128_255",
- CTLFLAG_RD, &sc->stats.prc255,
- "128-255 byte frames received");
+ CTLFLAG_RD, &sc->stats.prc255,
+ "128-255 byte frames received");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_256_511",
- CTLFLAG_RD, &sc->stats.prc511,
- "256-511 byte frames received");
+ CTLFLAG_RD, &sc->stats.prc511,
+ "256-511 byte frames received");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_512_1023",
- CTLFLAG_RD, &sc->stats.prc1023,
- "512-1023 byte frames received");
+ CTLFLAG_RD, &sc->stats.prc1023,
+ "512-1023 byte frames received");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "rx_frames_1024_1522",
- CTLFLAG_RD, &sc->stats.prc1522,
- "1023-1522 byte frames received");
+ CTLFLAG_RD, &sc->stats.prc1522,
+ "1023-1522 byte frames received");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_recvd",
- CTLFLAG_RD, &sc->stats.gorc,
- "Good Octets Received");
+ CTLFLAG_RD, &sc->stats.gorc,
+ "Good Octets Received");
/* Packet Transmission Stats */
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_octets_txd",
- CTLFLAG_RD, &sc->stats.gotc,
- "Good Octets Transmitted");
+ CTLFLAG_RD, &sc->stats.gotc,
+ "Good Octets Transmitted");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "total_pkts_txd",
- CTLFLAG_RD, &sc->stats.tpt,
- "Total Packets Transmitted");
+ CTLFLAG_RD, &sc->stats.tpt,
+ "Total Packets Transmitted");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "good_pkts_txd",
- CTLFLAG_RD, &sc->stats.gptc,
- "Good Packets Transmitted");
+ CTLFLAG_RD, &sc->stats.gptc,
+ "Good Packets Transmitted");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "bcast_pkts_txd",
- CTLFLAG_RD, &sc->stats.bptc,
- "Broadcast Packets Transmitted");
+ CTLFLAG_RD, &sc->stats.bptc,
+ "Broadcast Packets Transmitted");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "mcast_pkts_txd",
- CTLFLAG_RD, &sc->stats.mptc,
- "Multicast Packets Transmitted");
+ CTLFLAG_RD, &sc->stats.mptc,
+ "Multicast Packets Transmitted");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_64",
- CTLFLAG_RD, &sc->stats.ptc64,
- "64 byte frames transmitted ");
+ CTLFLAG_RD, &sc->stats.ptc64,
+ "64 byte frames transmitted ");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_65_127",
- CTLFLAG_RD, &sc->stats.ptc127,
- "65-127 byte frames transmitted");
+ CTLFLAG_RD, &sc->stats.ptc127,
+ "65-127 byte frames transmitted");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_128_255",
- CTLFLAG_RD, &sc->stats.ptc255,
- "128-255 byte frames transmitted");
+ CTLFLAG_RD, &sc->stats.ptc255,
+ "128-255 byte frames transmitted");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_256_511",
- CTLFLAG_RD, &sc->stats.ptc511,
- "256-511 byte frames transmitted");
+ CTLFLAG_RD, &sc->stats.ptc511,
+ "256-511 byte frames transmitted");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_512_1023",
- CTLFLAG_RD, &sc->stats.ptc1023,
- "512-1023 byte frames transmitted");
+ CTLFLAG_RD, &sc->stats.ptc1023,
+ "512-1023 byte frames transmitted");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tx_frames_1024_1522",
- CTLFLAG_RD, &sc->stats.ptc1522,
- "1024-1522 byte frames transmitted");
+ CTLFLAG_RD, &sc->stats.ptc1522,
+ "1024-1522 byte frames transmitted");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_txd",
- CTLFLAG_RD, &sc->stats.tsctc,
- "TSO Contexts Transmitted");
+ CTLFLAG_RD, &sc->stats.tsctc,
+ "TSO Contexts Transmitted");
SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, "tso_ctx_fail",
- CTLFLAG_RD, &sc->stats.tsctfc,
- "TSO Contexts Failed");
-
+ CTLFLAG_RD, &sc->stats.tsctfc,
+ "TSO Contexts Failed");
/* Interrupt Stats */
-
int_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "interrupts",
CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Interrupt Statistics");
int_list = SYSCTL_CHILDREN(int_node);
SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "asserts",
- CTLFLAG_RD, &sc->stats.iac,
- "Interrupt Assertion Count");
+ CTLFLAG_RD, &sc->stats.iac,
+ "Interrupt Assertion Count");
SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_pkt_timer",
- CTLFLAG_RD, &sc->stats.icrxptc,
- "Interrupt Cause Rx Pkt Timer Expire Count");
+ CTLFLAG_RD, &sc->stats.icrxptc,
+ "Interrupt Cause Rx Pkt Timer Expire Count");
SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_abs_timer",
- CTLFLAG_RD, &sc->stats.icrxatc,
- "Interrupt Cause Rx Abs Timer Expire Count");
+ CTLFLAG_RD, &sc->stats.icrxatc,
+ "Interrupt Cause Rx Abs Timer Expire Count");
SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_pkt_timer",
- CTLFLAG_RD, &sc->stats.ictxptc,
- "Interrupt Cause Tx Pkt Timer Expire Count");
+ CTLFLAG_RD, &sc->stats.ictxptc,
+ "Interrupt Cause Tx Pkt Timer Expire Count");
SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_abs_timer",
- CTLFLAG_RD, &sc->stats.ictxatc,
- "Interrupt Cause Tx Abs Timer Expire Count");
+ CTLFLAG_RD, &sc->stats.ictxatc,
+ "Interrupt Cause Tx Abs Timer Expire Count");
SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_empty",
- CTLFLAG_RD, &sc->stats.ictxqec,
- "Interrupt Cause Tx Queue Empty Count");
+ CTLFLAG_RD, &sc->stats.ictxqec,
+ "Interrupt Cause Tx Queue Empty Count");
SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "tx_queue_min_thresh",
- CTLFLAG_RD, &sc->stats.ictxqmtc,
- "Interrupt Cause Tx Queue Min Thresh Count");
+ CTLFLAG_RD, &sc->stats.ictxqmtc,
+ "Interrupt Cause Tx Queue Min Thresh Count");
SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_desc_min_thresh",
- CTLFLAG_RD, &sc->stats.icrxdmtc,
- "Interrupt Cause Rx Desc Min Thresh Count");
+ CTLFLAG_RD, &sc->stats.icrxdmtc,
+ "Interrupt Cause Rx Desc Min Thresh Count");
SYSCTL_ADD_UQUAD(ctx, int_list, OID_AUTO, "rx_overrun",
- CTLFLAG_RD, &sc->stats.icrxoc,
- "Interrupt Cause Receiver Overrun Count");
+ CTLFLAG_RD, &sc->stats.icrxoc,
+ "Interrupt Cause Receiver Overrun Count");
}
static void
@@ -4690,9 +5217,9 @@ em_fw_version_locked(if_ctx_t ctx)
uint16_t eep = 0;
/*
- * em_fw_version_locked() must run under the IFLIB_CTX_LOCK to meet the
- * NVM locking model, so we do it in em_if_attach_pre() and store the
- * info in the softc
+ * em_fw_version_locked() must run under the IFLIB_CTX_LOCK to meet
+ * the NVM locking model, so we do it in em_if_attach_pre() and store
+ * the info in the softc
*/
ASSERT_CTX_LOCK_HELD(hw);
@@ -4705,8 +5232,8 @@ em_fw_version_locked(if_ctx_t ctx)
e1000_get_fw_version(hw, fw_ver);
} else {
/*
- * Otherwise, EEPROM version should be present on (almost?) all
- * devices here
+ * Otherwise, EEPROM version should be present on (almost?)
+ * all devices here
*/
if(e1000_read_nvm(hw, NVM_VERSION, 1, &eep)) {
INIT_DEBUGOUT("can't get EEPROM version");
@@ -4730,17 +5257,18 @@ em_sbuf_fw_version(struct e1000_fw_version *fw_ver, struct sbuf *buf)
space = " ";
}
- if (fw_ver->invm_major || fw_ver->invm_minor || fw_ver->invm_img_type) {
+ if (fw_ver->invm_major || fw_ver->invm_minor ||
+ fw_ver->invm_img_type) {
sbuf_printf(buf, "%sNVM V%d.%d imgtype%d",
- space, fw_ver->invm_major, fw_ver->invm_minor,
- fw_ver->invm_img_type);
+ space, fw_ver->invm_major, fw_ver->invm_minor,
+ fw_ver->invm_img_type);
space = " ";
}
if (fw_ver->or_valid) {
sbuf_printf(buf, "%sOption ROM V%d-b%d-p%d",
- space, fw_ver->or_major, fw_ver->or_build,
- fw_ver->or_patch);
+ space, fw_ver->or_major, fw_ver->or_build,
+ fw_ver->or_patch);
space = " ";
}
@@ -4872,8 +5400,6 @@ em_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
return (EINVAL);
info->value = usecs;
ticks = EM_USECS_TO_TICKS(usecs);
- if (info->offset == E1000_ITR) /* units are 256ns here */
- ticks *= 4;
sc = info->sc;
@@ -4896,10 +5422,47 @@ em_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
return (0);
}
+static int
+em_sysctl_tso_tcp_flags_mask(SYSCTL_HANDLER_ARGS)
+{
+ struct e1000_softc *sc;
+ u32 reg, val, shift;
+ int error, mask;
+
+ sc = oidp->oid_arg1;
+ switch (oidp->oid_arg2) {
+ case 0:
+ reg = E1000_DTXTCPFLGL;
+ shift = 0;
+ break;
+ case 1:
+ reg = E1000_DTXTCPFLGL;
+ shift = 16;
+ break;
+ case 2:
+ reg = E1000_DTXTCPFLGH;
+ shift = 0;
+ break;
+ default:
+ return (EINVAL);
+ break;
+ }
+ val = E1000_READ_REG(&sc->hw, reg);
+ mask = (val >> shift) & 0xfff;
+ error = sysctl_handle_int(oidp, &mask, 0, req);
+ if (error != 0 || req->newptr == NULL)
+ return (error);
+ if (mask < 0 || mask > 0xfff)
+ return (EINVAL);
+ val = (val & ~(0xfff << shift)) | (mask << shift);
+ E1000_WRITE_REG(&sc->hw, reg, val);
+ return (0);
+}
+
static void
em_add_int_delay_sysctl(struct e1000_softc *sc, const char *name,
- const char *description, struct em_int_delay_info *info,
- int offset, int value)
+ const char *description, struct em_int_delay_info *info, int offset,
+ int value)
{
info->sc = sc;
info->offset = offset;
@@ -4923,7 +5486,7 @@ em_set_flowcntl(SYSCTL_HANDLER_ARGS)
{
int error;
static int input = 3; /* default is full */
- struct e1000_softc *sc = (struct e1000_softc *) arg1;
+ struct e1000_softc *sc = (struct e1000_softc *) arg1;
error = sysctl_handle_int(oidp, &input, 0, req);
@@ -4952,6 +5515,55 @@ em_set_flowcntl(SYSCTL_HANDLER_ARGS)
}
/*
+ * Manage DMA Coalesce:
+ * Control values:
+ * 0/1 - off/on
+ * Legal timer values are:
+ * 250,500,1000-10000 in thousands
+ */
+static int
+igb_sysctl_dmac(SYSCTL_HANDLER_ARGS)
+{
+ struct e1000_softc *sc = (struct e1000_softc *) arg1;
+ int error;
+
+ error = sysctl_handle_int(oidp, &sc->dmac, 0, req);
+
+ if ((error) || (req->newptr == NULL))
+ return (error);
+
+ switch (sc->dmac) {
+ case 0:
+ /* Disabling */
+ break;
+ case 1: /* Just enable and use default */
+ sc->dmac = 1000;
+ break;
+ case 250:
+ case 500:
+ case 1000:
+ case 2000:
+ case 3000:
+ case 4000:
+ case 5000:
+ case 6000:
+ case 7000:
+ case 8000:
+ case 9000:
+ case 10000:
+ /* Legal values - allow */
+ break;
+ default:
+ /* Do nothing, illegal value */
+ sc->dmac = 0;
+ return (EINVAL);
+ }
+ /* Reinit the interface */
+ em_if_init(sc->ctx);
+ return (error);
+}
+
+/*
* Manage Energy Efficient Ethernet:
* Control values:
* 0/1 - enabled/disabled
@@ -4962,11 +5574,17 @@ em_sysctl_eee(SYSCTL_HANDLER_ARGS)
struct e1000_softc *sc = (struct e1000_softc *) arg1;
int error, value;
- value = sc->hw.dev_spec.ich8lan.eee_disable;
+ if (sc->hw.mac.type < igb_mac_min)
+ value = sc->hw.dev_spec.ich8lan.eee_disable;
+ else
+ value = sc->hw.dev_spec._82575.eee_disable;
error = sysctl_handle_int(oidp, &value, 0, req);
if (error || req->newptr == NULL)
return (error);
- sc->hw.dev_spec.ich8lan.eee_disable = (value != 0);
+ if (sc->hw.mac.type < igb_mac_min)
+ sc->hw.dev_spec.ich8lan.eee_disable = (value != 0);
+ else
+ sc->hw.dev_spec._82575.eee_disable = (value != 0);
em_if_init(sc->ctx);
return (0);
@@ -5041,15 +5659,15 @@ em_print_debug_info(struct e1000_softc *sc)
for (int i = 0; i < sc->tx_num_queues; i++, txr++) {
device_printf(dev, "TX Queue %d ------\n", i);
device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
- E1000_READ_REG(&sc->hw, E1000_TDH(i)),
- E1000_READ_REG(&sc->hw, E1000_TDT(i)));
+ E1000_READ_REG(&sc->hw, E1000_TDH(i)),
+ E1000_READ_REG(&sc->hw, E1000_TDT(i)));
}
for (int j=0; j < sc->rx_num_queues; j++, rxr++) {
device_printf(dev, "RX Queue %d ------\n", j);
device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
- E1000_READ_REG(&sc->hw, E1000_RDH(j)),
- E1000_READ_REG(&sc->hw, E1000_RDT(j)));
+ E1000_READ_REG(&sc->hw, E1000_RDH(j)),
+ E1000_READ_REG(&sc->hw, E1000_RDT(j)));
}
}
diff --git a/sys/dev/e1000/if_em.h b/sys/dev/e1000/if_em.h
index 244762e8ed0d..52bfed0f9a42 100644
--- a/sys/dev/e1000/if_em.h
+++ b/sys/dev/e1000/if_em.h
@@ -1,8 +1,9 @@
/*-
* SPDX-License-Identifier: BSD-2-Clause
*
+ * Copyright (c) 2001-2024, Intel Corporation
* Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org>
- * All rights reserved.
+ * Copyright (c) 2024 Kevin Bowling <kbowling@FreeBSD.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -243,9 +244,19 @@
/* Support AutoMediaDetect for Marvell M88 PHY in i354 */
#define IGB_MEDIA_RESET (1 << 0)
-/* Define the starting Interrupt rate per Queue */
-#define IGB_INTS_PER_SEC 8000
-#define IGB_DEFAULT_ITR ((1000000/IGB_INTS_PER_SEC) << 2)
+/* Define the interrupt rates and ITR helpers */
+#define EM_INTS_4K 4000
+#define EM_INTS_20K 20000
+#define EM_INTS_70K 70000
+#define EM_INTS_DEFAULT 8000
+#define EM_INTS_MULTIPLIER 256
+#define EM_ITR_DIVIDEND 1000000000
+#define EM_INTS_TO_ITR(i) (EM_ITR_DIVIDEND/(i * EM_INTS_MULTIPLIER))
+#define IGB_EITR_DIVIDEND 1000000
+#define IGB_EITR_SHIFT 2
+#define IGB_QVECTOR_MASK 0x7FFC
+#define IGB_INTS_TO_EITR(i) (((IGB_EITR_DIVIDEND/i) & IGB_QVECTOR_MASK) << \
+ IGB_EITR_SHIFT)
#define IGB_LINK_ITR 2000
#define I210_LINK_DELAY 1000
@@ -383,7 +394,11 @@ struct tx_ring {
/* Interrupt resources */
void *tag;
struct resource *res;
+
+ /* Soft stats */
unsigned long tx_irq;
+ unsigned long tx_packets;
+ unsigned long tx_bytes;
/* Saved csum offloading context information */
int csum_flags;
@@ -419,6 +434,9 @@ struct rx_ring {
unsigned long rx_discarded;
unsigned long rx_packets;
unsigned long rx_bytes;
+
+ /* Next requested ITR latency */
+ u8 rx_nextlatency;
};
struct em_tx_queue {
@@ -434,6 +452,7 @@ struct em_rx_queue {
u32 me;
u32 msix;
u32 eims;
+ u32 itr_setting;
struct rx_ring rxr;
u64 irqs;
struct if_irq que_irq;
@@ -482,6 +501,7 @@ struct e1000_softc {
u32 rx_mbuf_sz;
+ int enable_aim;
/* Management and WOL features */
u32 wol;
bool has_manage;
@@ -505,6 +525,7 @@ struct e1000_softc {
u16 link_duplex;
u32 smartspeed;
u32 dmac;
+ u32 pba;
int link_mask;
int tso_automasked;
diff --git a/sys/dev/e1000/igb_txrx.c b/sys/dev/e1000/igb_txrx.c
index 2819150acba6..568d84807173 100644
--- a/sys/dev/e1000/igb_txrx.c
+++ b/sys/dev/e1000/igb_txrx.c
@@ -42,29 +42,27 @@
/*********************************************************************
* Local Function prototypes
*********************************************************************/
-static int igb_isc_txd_encap(void *arg, if_pkt_info_t pi);
-static void igb_isc_txd_flush(void *arg, uint16_t txqid, qidx_t pidx);
-static int igb_isc_txd_credits_update(void *arg, uint16_t txqid, bool clear);
+static int igb_isc_txd_encap(void *, if_pkt_info_t);
+static void igb_isc_txd_flush(void *, uint16_t, qidx_t);
+static int igb_isc_txd_credits_update(void *, uint16_t, bool);
-static void igb_isc_rxd_refill(void *arg, if_rxd_update_t iru);
+static void igb_isc_rxd_refill(void *, if_rxd_update_t);
-static void igb_isc_rxd_flush(void *arg, uint16_t rxqid, uint8_t flid __unused,
- qidx_t pidx);
-static int igb_isc_rxd_available(void *arg, uint16_t rxqid, qidx_t idx,
- qidx_t budget);
+static void igb_isc_rxd_flush(void *, uint16_t, uint8_t, qidx_t);
+static int igb_isc_rxd_available(void *, uint16_t, qidx_t, qidx_t);
static int igb_isc_rxd_pkt_get(void *arg, if_rxd_info_t ri);
-static int igb_tx_ctx_setup(struct tx_ring *txr, if_pkt_info_t pi,
- uint32_t *cmd_type_len, uint32_t *olinfo_status);
-static int igb_tso_setup(struct tx_ring *txr, if_pkt_info_t pi,
- uint32_t *cmd_type_len, uint32_t *olinfo_status);
+static int igb_tx_ctx_setup(struct tx_ring *, if_pkt_info_t, uint32_t *,
+ uint32_t *);
+static int igb_tso_setup(struct tx_ring *, if_pkt_info_t, uint32_t *,
+ uint32_t *);
-static void igb_rx_checksum(uint32_t staterr, if_rxd_info_t ri, uint32_t ptype);
-static int igb_determine_rsstype(uint16_t pkt_info);
+static void igb_rx_checksum(uint32_t, if_rxd_info_t, uint32_t);
+static int igb_determine_rsstype(uint16_t);
-extern void igb_if_enable_intr(if_ctx_t ctx);
-extern int em_intr(void *arg);
+extern void igb_if_enable_intr(if_ctx_t);
+extern int em_intr(void *);
struct if_txrx igb_txrx = {
.ift_txd_encap = igb_isc_txd_encap,
@@ -104,14 +102,15 @@ igb_tso_setup(struct tx_ring *txr, if_pkt_info_t pi, uint32_t *cmd_type_len,
break;
default:
panic("%s: CSUM_TSO but no supported IP version (0x%04x)",
- __func__, ntohs(pi->ipi_etype));
+ __func__, ntohs(pi->ipi_etype));
break;
}
- TXD = (struct e1000_adv_tx_context_desc *) &txr->tx_base[pi->ipi_pidx];
+ TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[pi->ipi_pidx];
/* This is used in the transmit desc in encap */
- paylen = pi->ipi_len - pi->ipi_ehdrlen - pi->ipi_ip_hlen - pi->ipi_tcp_hlen;
+ paylen = pi->ipi_len - pi->ipi_ehdrlen - pi->ipi_ip_hlen -
+ pi->ipi_tcp_hlen;
/* VLAN MACLEN IPLEN */
if (pi->ipi_mflags & M_VLANTAG) {
@@ -149,8 +148,8 @@ igb_tso_setup(struct tx_ring *txr, if_pkt_info_t pi, uint32_t *cmd_type_len,
*
**********************************************************************/
static int
-igb_tx_ctx_setup(struct tx_ring *txr, if_pkt_info_t pi, uint32_t *cmd_type_len,
- uint32_t *olinfo_status)
+igb_tx_ctx_setup(struct tx_ring *txr, if_pkt_info_t pi,
+ uint32_t *cmd_type_len, uint32_t *olinfo_status)
{
struct e1000_adv_tx_context_desc *TXD;
struct e1000_softc *sc = txr->sc;
@@ -166,7 +165,7 @@ igb_tx_ctx_setup(struct tx_ring *txr, if_pkt_info_t pi, uint32_t *cmd_type_len,
*olinfo_status |= pi->ipi_len << E1000_ADVTXD_PAYLEN_SHIFT;
/* Now ready a context descriptor */
- TXD = (struct e1000_adv_tx_context_desc *) &txr->tx_base[pi->ipi_pidx];
+ TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[pi->ipi_pidx];
/*
** In advanced descriptors the vlan tag must
@@ -248,8 +247,8 @@ igb_isc_txd_encap(void *arg, if_pkt_info_t pi)
pidx_last = olinfo_status = 0;
/* Basic descriptor defines */
- cmd_type_len = (E1000_ADVTXD_DTYP_DATA |
- E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT);
+ cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
+ E1000_ADVTXD_DCMD_DEXT);
if (pi->ipi_mflags & M_VLANTAG)
cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
@@ -292,15 +291,19 @@ igb_isc_txd_encap(void *arg, if_pkt_info_t pi)
txd->read.cmd_type_len |= htole32(E1000_TXD_CMD_EOP | txd_flags);
pi->ipi_new_pidx = i;
+ /* Sent data accounting for AIM */
+ txr->tx_bytes += pi->ipi_len;
+ ++txr->tx_packets;
+
return (0);
}
static void
igb_isc_txd_flush(void *arg, uint16_t txqid, qidx_t pidx)
{
- struct e1000_softc *sc = arg;
- struct em_tx_queue *que = &sc->tx_queues[txqid];
- struct tx_ring *txr = &que->txr;
+ struct e1000_softc *sc = arg;
+ struct em_tx_queue *que = &sc->tx_queues[txqid];
+ struct tx_ring *txr = &que->txr;
E1000_WRITE_REG(&sc->hw, E1000_TDT(txr->me), pidx);
}
@@ -349,7 +352,8 @@ igb_isc_txd_credits_update(void *arg, uint16_t txqid, bool clear)
if (rs_cidx == txr->tx_rs_pidx)
break;
cur = txr->tx_rsq[rs_cidx];
- status = ((union e1000_adv_tx_desc *)&txr->tx_base[cur])->wb.status;
+ status = ((union e1000_adv_tx_desc *)
+ &txr->tx_base[cur])->wb.status;
} while ((status & E1000_TXD_STAT_DD));
txr->tx_rs_cidx = rs_cidx;
@@ -385,7 +389,8 @@ igb_isc_rxd_refill(void *arg, if_rxd_update_t iru)
}
static void
-igb_isc_rxd_flush(void *arg, uint16_t rxqid, uint8_t flid __unused, qidx_t pidx)
+igb_isc_rxd_flush(void *arg, uint16_t rxqid, uint8_t flid __unused,
+ qidx_t pidx)
{
struct e1000_softc *sc = arg;
struct em_rx_queue *que = &sc->rx_queues[rxqid];
@@ -451,7 +456,8 @@ igb_isc_rxd_pkt_get(void *arg, if_rxd_info_t ri)
MPASS ((staterr & E1000_RXD_STAT_DD) != 0);
len = le16toh(rxd->wb.upper.length);
- ptype = le32toh(rxd->wb.lower.lo_dword.data) & IGB_PKTTYPE_MASK;
+ ptype =
+ le32toh(rxd->wb.lower.lo_dword.data) & IGB_PKTTYPE_MASK;
ri->iri_len += len;
rxr->rx_bytes += ri->iri_len;
@@ -460,7 +466,8 @@ igb_isc_rxd_pkt_get(void *arg, if_rxd_info_t ri)
eop = ((staterr & E1000_RXD_STAT_EOP) == E1000_RXD_STAT_EOP);
/* Make sure bad packets are discarded */
- if (eop && ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) != 0)) {
+ if (eop &&
+ ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) != 0)) {
sc->dropped_pkts++;
++rxr->rx_discarded;
return (EBADMSG);
@@ -522,7 +529,8 @@ igb_rx_checksum(uint32_t staterr, if_rxd_info_t ri, uint32_t ptype)
return;
/* If there is a layer 3 or 4 error we are done */
- if (__predict_false(errors & (E1000_RXD_ERR_IPE | E1000_RXD_ERR_TCPE)))
+ if (__predict_false(errors &
+ (E1000_RXD_ERR_IPE | E1000_RXD_ERR_TCPE)))
return;
/* IP Checksum Good */
@@ -533,11 +541,13 @@ igb_rx_checksum(uint32_t staterr, if_rxd_info_t ri, uint32_t ptype)
if (__predict_true(status &
(E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))) {
/* SCTP header present */
- if (__predict_false((ptype & E1000_RXDADV_PKTTYPE_ETQF) == 0 &&
+ if (__predict_false(
+ (ptype & E1000_RXDADV_PKTTYPE_ETQF) == 0 &&
(ptype & E1000_RXDADV_PKTTYPE_SCTP) != 0)) {
ri->iri_csum_flags |= CSUM_SCTP_VALID;
} else {
- ri->iri_csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
+ ri->iri_csum_flags |=
+ CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
ri->iri_csum_data = htons(0xffff);
}
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-07-13 07:55:52 +0000