diff options
Diffstat (limited to 'sys/dev/ice/ice_adminq_cmd.h')
| -rw-r--r-- | sys/dev/ice/ice_adminq_cmd.h | 191 |
1 files changed, 171 insertions, 20 deletions
diff --git a/sys/dev/ice/ice_adminq_cmd.h b/sys/dev/ice/ice_adminq_cmd.h index 70b56144faf2..6225abc0f38b 100644 --- a/sys/dev/ice/ice_adminq_cmd.h +++ b/sys/dev/ice/ice_adminq_cmd.h @@ -187,7 +187,7 @@ struct ice_aqc_list_caps_elem { #define ICE_AQC_CAPS_ROCEV2_LAG 0x0092 #define ICE_AQC_BIT_ROCEV2_LAG 0x01 #define ICE_AQC_BIT_SRIOV_LAG 0x02 - +#define ICE_AQC_CAPS_NEXT_CLUSTER_ID 0x0096 u8 major_ver; u8 minor_ver; /* Number of resources described by this capability */ @@ -320,7 +320,12 @@ struct ice_aqc_set_port_params { (0x3F << ICE_AQC_SET_P_PARAMS_LOGI_PORT_ID_S) #define ICE_AQC_SET_P_PARAMS_IS_LOGI_PORT BIT(14) #define ICE_AQC_SET_P_PARAMS_SWID_VALID BIT(15) - u8 reserved[10]; + u8 lb_mode; +#define ICE_AQC_SET_P_PARAMS_LOOPBACK_MODE_VALID BIT(2) +#define ICE_AQC_SET_P_PARAMS_LOOPBACK_MODE_NORMAL 0x00 +#define ICE_AQC_SET_P_PARAMS_LOOPBACK_MODE_NO 0x01 +#define ICE_AQC_SET_P_PARAMS_LOOPBACK_MODE_HIGH 0x02 + u8 reserved[9]; }; /* These resource type defines are used for all switch resource @@ -1389,7 +1394,18 @@ struct ice_aqc_get_phy_caps { #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2) #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3) #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4) -#define ICE_PHY_TYPE_HIGH_MAX_INDEX 4 +#define ICE_PHY_TYPE_HIGH_200G_CR4_PAM4 BIT_ULL(5) +#define ICE_PHY_TYPE_HIGH_200G_SR4 BIT_ULL(6) +#define ICE_PHY_TYPE_HIGH_200G_FR4 BIT_ULL(7) +#define ICE_PHY_TYPE_HIGH_200G_LR4 BIT_ULL(8) +#define ICE_PHY_TYPE_HIGH_200G_DR4 BIT_ULL(9) +#define ICE_PHY_TYPE_HIGH_200G_KR4_PAM4 BIT_ULL(10) +#define ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC BIT_ULL(11) +#define ICE_PHY_TYPE_HIGH_200G_AUI4 BIT_ULL(12) +#define ICE_PHY_TYPE_HIGH_200G_AUI8_AOC_ACC BIT_ULL(13) +#define ICE_PHY_TYPE_HIGH_200G_AUI8 BIT_ULL(14) +#define ICE_PHY_TYPE_HIGH_400GBASE_FR8 BIT_ULL(15) +#define ICE_PHY_TYPE_HIGH_MAX_INDEX 15 struct ice_aqc_get_phy_caps_data { __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ @@ -1541,11 +1557,14 @@ struct ice_aqc_get_link_status { enum ice_get_link_status_data_version { ICE_GET_LINK_STATUS_DATA_V1 = 1, + ICE_GET_LINK_STATUS_DATA_V2 = 2, }; #define ICE_GET_LINK_STATUS_DATALEN_V1 32 +#define ICE_GET_LINK_STATUS_DATALEN_V2 56 /* Get link status response data structure, also used for Link Status Event */ +#pragma pack(1) struct ice_aqc_get_link_status_data { u8 topo_media_conflict; #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) @@ -1618,7 +1637,7 @@ struct ice_aqc_get_link_status_data { #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 __le16 link_speed; -#define ICE_AQ_LINK_SPEED_M 0x7FF +#define ICE_AQ_LINK_SPEED_M 0xFFF #define ICE_AQ_LINK_SPEED_10MB BIT(0) #define ICE_AQ_LINK_SPEED_100MB BIT(1) #define ICE_AQ_LINK_SPEED_1000MB BIT(2) @@ -1630,12 +1649,37 @@ struct ice_aqc_get_link_status_data { #define ICE_AQ_LINK_SPEED_40GB BIT(8) #define ICE_AQ_LINK_SPEED_50GB BIT(9) #define ICE_AQ_LINK_SPEED_100GB BIT(10) +#define ICE_AQ_LINK_SPEED_200GB BIT(11) #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) - __le32 reserved3; /* Aligns next field to 8-byte boundary */ + __le16 reserved3; /* Aligns next field to 8-byte boundary */ + u8 ext_fec_status; +#define ICE_AQ_LINK_RS_272_FEC_EN BIT(0) /* RS 272 FEC enabled */ + u8 reserved4; __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ + /* Get link status version 2 link partner data */ + __le64 lp_phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ + __le64 lp_phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */ + u8 lp_fec_adv; +#define ICE_AQ_LINK_LP_10G_KR_FEC_CAP BIT(0) +#define ICE_AQ_LINK_LP_25G_KR_FEC_CAP BIT(1) +#define ICE_AQ_LINK_LP_RS_528_FEC_CAP BIT(2) +#define ICE_AQ_LINK_LP_50G_KR_272_FEC_CAP BIT(3) +#define ICE_AQ_LINK_LP_100G_KR_272_FEC_CAP BIT(4) +#define ICE_AQ_LINK_LP_200G_KR_272_FEC_CAP BIT(5) + u8 lp_fec_req; +#define ICE_AQ_LINK_LP_10G_KR_FEC_REQ BIT(0) +#define ICE_AQ_LINK_LP_25G_KR_FEC_REQ BIT(1) +#define ICE_AQ_LINK_LP_RS_528_FEC_REQ BIT(2) +#define ICE_AQ_LINK_LP_KR_272_FEC_REQ BIT(3) + u8 lp_flowcontrol; +#define ICE_AQ_LINK_LP_PAUSE_ADV BIT(0) +#define ICE_AQ_LINK_LP_ASM_DIR_ADV BIT(1) + u8 reserved[5]; }; +#pragma pack() + /* Set event mask command (direct 0x0613) */ struct ice_aqc_set_event_mask { u8 lport_num; @@ -1793,14 +1837,46 @@ struct ice_aqc_dnl_call_command { u8 ctx; /* Used in command, reserved in response */ u8 reserved; __le16 activity_id; +#define ICE_AQC_ACT_ID_DNL 0x1129 __le32 reserved1; __le32 addr_high; __le32 addr_low; }; +struct ice_aqc_dnl_equa_param { + __le16 data_in; +#define ICE_AQC_RX_EQU_SHIFT 8 +#define ICE_AQC_RX_EQU_PRE2 (0x10 << ICE_AQC_RX_EQU_SHIFT) +#define ICE_AQC_RX_EQU_PRE1 (0x11 << ICE_AQC_RX_EQU_SHIFT) +#define ICE_AQC_RX_EQU_POST1 (0x12 << ICE_AQC_RX_EQU_SHIFT) +#define ICE_AQC_RX_EQU_BFLF (0x13 << ICE_AQC_RX_EQU_SHIFT) +#define ICE_AQC_RX_EQU_BFHF (0x14 << ICE_AQC_RX_EQU_SHIFT) +#define ICE_AQC_RX_EQU_DRATE (0x15 << ICE_AQC_RX_EQU_SHIFT) +#define ICE_AQC_TX_EQU_PRE1 0x0 +#define ICE_AQC_TX_EQU_PRE3 0x3 +#define ICE_AQC_TX_EQU_ATTEN 0x4 +#define ICE_AQC_TX_EQU_POST1 0x8 +#define ICE_AQC_TX_EQU_PRE2 0xC + __le16 op_code_serdes_sel; +#define ICE_AQC_OP_CODE_SHIFT 4 +#define ICE_AQC_OP_CODE_RX_EQU (0x9 << ICE_AQC_OP_CODE_SHIFT) +#define ICE_AQC_OP_CODE_TX_EQU (0x10 << ICE_AQC_OP_CODE_SHIFT) + __le32 reserved[3]; +}; + +struct ice_aqc_dnl_equa_resp { + /* Equalization value can be -ve */ + int val; + __le32 reserved[3]; +}; + /* DNL call command/response buffer (indirect 0x0682) */ struct ice_aqc_dnl_call { - __le32 stores[4]; + union { + struct ice_aqc_dnl_equa_param txrx_equa_reqs; + __le32 stores[4]; + struct ice_aqc_dnl_equa_resp txrx_equa_resp; + } sto; }; /* Used for both commands: @@ -1902,8 +1978,8 @@ struct ice_aqc_link_topo_addr { #define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S) /* Used to decode the handle field */ #define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9) -#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9) -#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0 +#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM 0 +#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ BIT(9) #define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0 /* In case of a Mezzanine type */ #define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \ @@ -1919,7 +1995,7 @@ struct ice_aqc_link_topo_addr { struct ice_aqc_get_link_topo { struct ice_aqc_link_topo_addr addr; u8 node_part_num; -#define ICE_ACQ_GET_LINK_TOPO_NODE_NR_PCA9575 0x21 +#define ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575 0x21 u8 rsvd[9]; }; @@ -2054,6 +2130,7 @@ struct ice_aqc_get_port_options_elem { #define ICE_AQC_PORT_OPT_MAX_LANE_25G 5 #define ICE_AQC_PORT_OPT_MAX_LANE_50G 6 #define ICE_AQC_PORT_OPT_MAX_LANE_100G 7 +#define ICE_AQC_PORT_OPT_MAX_LANE_200G 8 u8 global_scid[2]; u8 phy_scid[2]; u8 pf2port_cid[2]; @@ -2201,6 +2278,29 @@ struct ice_aqc_nvm { #define ICE_AQC_NVM_LLDP_STATUS_M_LEN 4 /* In Bits */ #define ICE_AQC_NVM_LLDP_STATUS_RD_LEN 4 /* In Bytes */ +#define ICE_AQC_NVM_SDP_CFG_PTR_OFFSET 0xD8 +#define ICE_AQC_NVM_SDP_CFG_PTR_RD_LEN 2 /* In Bytes */ +#define ICE_AQC_NVM_SDP_CFG_PTR_M MAKEMASK(0x7FFF, 0) +#define ICE_AQC_NVM_SDP_CFG_PTR_TYPE_M BIT(15) +#define ICE_AQC_NVM_SDP_CFG_HEADER_LEN 2 /* In Bytes */ +#define ICE_AQC_NVM_SDP_CFG_SEC_LEN_LEN 2 /* In Bytes */ +#define ICE_AQC_NVM_SDP_CFG_DATA_LEN 14 /* In Bytes */ +#define ICE_AQC_NVM_SDP_CFG_MAX_SECTION_SIZE 7 +#define ICE_AQC_NVM_SDP_CFG_PIN_SIZE 10 +#define ICE_AQC_NVM_SDP_CFG_PIN_OFFSET 6 +#define ICE_AQC_NVM_SDP_CFG_PIN_MASK MAKEMASK(0x3FF, \ + ICE_AQC_NVM_SDP_CFG_PIN_OFFSET) +#define ICE_AQC_NVM_SDP_CFG_CHAN_OFFSET 4 +#define ICE_AQC_NVM_SDP_CFG_CHAN_MASK MAKEMASK(0x3, \ + ICE_AQC_NVM_SDP_CFG_CHAN_OFFSET) +#define ICE_AQC_NVM_SDP_CFG_DIR_OFFSET 3 +#define ICE_AQC_NVM_SDP_CFG_DIR_MASK MAKEMASK(0x1, \ + ICE_AQC_NVM_SDP_CFG_DIR_OFFSET) +#define ICE_AQC_NVM_SDP_CFG_SDP_NUM_OFFSET 0 +#define ICE_AQC_NVM_SDP_CFG_SDP_NUM_MASK MAKEMASK(0x7, \ + ICE_AQC_NVM_SDP_CFG_SDP_NUM_OFFSET) +#define ICE_AQC_NVM_SDP_CFG_NA_PIN_MASK MAKEMASK(0x1, 15) + #define ICE_AQC_NVM_MINSREV_MOD_ID 0x130 #define ICE_AQC_NVM_TX_TOPO_MOD_ID 0x14B #define ICE_AQC_NVM_CMPO_MOD_ID 0x153 @@ -2265,6 +2365,29 @@ struct ice_aqc_nvm_checksum { u8 rsvd2[12]; }; +/* Used for NVM Sanitization command - 0x070C */ +struct ice_aqc_nvm_sanitization { + u8 cmd_flags; +#define ICE_AQ_NVM_SANITIZE_REQ_READ 0 +#define ICE_AQ_NVM_SANITIZE_REQ_OPERATE BIT(0) + +#define ICE_AQ_NVM_SANITIZE_READ_SUBJECT_NVM_BITS 0 +#define ICE_AQ_NVM_SANITIZE_READ_SUBJECT_NVM_STATE BIT(1) +#define ICE_AQ_NVM_SANITIZE_OPERATE_SUBJECT_CLEAR 0 + u8 values; +#define ICE_AQ_NVM_SANITIZE_NVM_BITS_HOST_CLEAN_SUPPORT BIT(0) +#define ICE_AQ_NVM_SANITIZE_NVM_BITS_BMC_CLEAN_SUPPORT BIT(2) +#define ICE_AQ_NVM_SANITIZE_NVM_STATE_HOST_CLEAN_DONE BIT(0) +#define ICE_AQ_NVM_SANITIZE_NVM_STATE_HOST_CLEAN_SUCCESS BIT(1) +#define ICE_AQ_NVM_SANITIZE_NVM_STATE_BMC_CLEAN_DONE BIT(2) +#define ICE_AQ_NVM_SANITIZE_NVM_STATE_BMC_CLEAN_SUCCESS BIT(3) +#define ICE_AQ_NVM_SANITIZE_OPERATE_HOST_CLEAN_DONE BIT(0) +#define ICE_AQ_NVM_SANITIZE_OPERATE_HOST_CLEAN_SUCCESS BIT(1) +#define ICE_AQ_NVM_SANITIZE_OPERATE_BMC_CLEAN_DONE BIT(2) +#define ICE_AQ_NVM_SANITIZE_OPERATE_BMC_CLEAN_SUCCESS BIT(3) + u8 reserved[14]; +}; + /* * Send to PF command (indirect 0x0801) ID is only used by PF * @@ -2560,6 +2683,15 @@ struct ice_aqc_get_set_rss_lut { __le32 addr_low; }; +/* Sideband Control Interface Commands */ +/* Neighbor Device Request (indirect 0x0C00); also used for the response. */ +struct ice_aqc_neigh_dev_req { + __le16 sb_data_len; + u8 reserved[6]; + __le32 addr_high; + __le32 addr_low; +}; + /* Add Tx LAN Queues (indirect 0x0C30) */ struct ice_aqc_add_txqs { u8 num_qgrps; @@ -2812,19 +2944,33 @@ struct ice_aqc_event_lan_overflow { /* Debug Dump Internal Data (indirect 0xFF08) */ struct ice_aqc_debug_dump_internals { __le16 cluster_id; /* Expresses next cluster ID in response */ -#define ICE_AQC_DBG_DUMP_CLUSTER_ID_SW 0 -#define ICE_AQC_DBG_DUMP_CLUSTER_ID_TXSCHED 2 -#define ICE_AQC_DBG_DUMP_CLUSTER_ID_PROFILES 3 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_SW_E810 0 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_ACL_E810 1 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_TXSCHED_E810 2 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_PROFILES_E810 3 /* EMP_DRAM only dumpable in device debug mode */ -#define ICE_AQC_DBG_DUMP_CLUSTER_ID_EMP_DRAM 4 -#define ICE_AQC_DBG_DUMP_CLUSTER_ID_LINK 5 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_EMP_DRAM_E810 4 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_LINK_E810 5 /* AUX_REGS only dumpable in device debug mode */ -#define ICE_AQC_DBG_DUMP_CLUSTER_ID_AUX_REGS 6 -#define ICE_AQC_DBG_DUMP_CLUSTER_ID_DCB 7 -#define ICE_AQC_DBG_DUMP_CLUSTER_ID_L2P 8 -#define ICE_AQC_DBG_DUMP_CLUSTER_ID_QUEUE_MNG 9 -#define ICE_AQC_DBG_DUMP_CLUSTER_ID_FULL_CSR_SPACE 21 -#define ICE_AQC_DBG_DUMP_CLUSTER_ID_MNG_TRANSACTIONS 22 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_AUX_REGS_E810 6 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_DCB_E810 7 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_L2P_E810 8 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_QUEUE_MNG_E810 9 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_FULL_CSR_SPACE_E810 21 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_MNG_TRANSACTIONS_E810 22 + +/* Start cluster to discover first available cluster */ +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_START_ALL 0 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_SW_E830 100 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_ACL_E830 101 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_TXSCHED_E830 102 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_PROFILES_E830 103 +/* EMP_DRAM only dumpable in device debug mode */ +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_LINK_E830 105 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_DCB_E830 107 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_L2P_E830 108 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_QUEUE_MNG_E830 109 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_FULL_CSR_SPACE_E830 121 __le16 table_id; /* Used only for non-memory clusters */ __le32 idx; /* In table entries for tables, in bytes for memory */ __le32 addr_high; @@ -3076,6 +3222,7 @@ struct ice_aq_desc { struct ice_aqc_nvm nvm; struct ice_aqc_nvm_cfg nvm_cfg; struct ice_aqc_nvm_checksum nvm_checksum; + struct ice_aqc_nvm_sanitization sanitization; struct ice_aqc_pf_vf_msg virt; struct ice_aqc_read_write_alt_direct read_write_alt_direct; struct ice_aqc_read_write_alt_indirect read_write_alt_indirect; @@ -3095,6 +3242,7 @@ struct ice_aq_desc { struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl; struct ice_aqc_get_set_rss_lut get_set_rss_lut; struct ice_aqc_get_set_rss_key get_set_rss_key; + struct ice_aqc_neigh_dev_req neigh_dev; struct ice_aqc_add_txqs add_txqs; struct ice_aqc_dis_txqs dis_txqs; struct ice_aqc_move_txqs move_txqs; @@ -3330,6 +3478,7 @@ enum ice_adminq_opc { ice_aqc_opc_nvm_update_empr = 0x0709, ice_aqc_opc_nvm_pkg_data = 0x070A, ice_aqc_opc_nvm_pass_component_tbl = 0x070B, + ice_aqc_opc_nvm_sanitization = 0x070C, /* PF/VF mailbox commands */ ice_mbx_opc_send_msg_to_pf = 0x0801, @@ -3360,6 +3509,8 @@ enum ice_adminq_opc { ice_aqc_opc_set_rss_lut = 0x0B03, ice_aqc_opc_get_rss_key = 0x0B04, ice_aqc_opc_get_rss_lut = 0x0B05, + /* Sideband Control Interface commands */ + ice_aqc_opc_neighbour_device_request = 0x0C00, /* Tx queue handling commands/events */ ice_aqc_opc_add_txqs = 0x0C30, |