diff options
Diffstat (limited to 'sys/dev/mpi3mr')
| -rw-r--r-- | sys/dev/mpi3mr/mpi/mpi30_api.h | 4 | ||||
| -rw-r--r-- | sys/dev/mpi3mr/mpi/mpi30_cnfg.h | 368 | ||||
| -rw-r--r-- | sys/dev/mpi3mr/mpi/mpi30_image.h | 63 | ||||
| -rw-r--r-- | sys/dev/mpi3mr/mpi/mpi30_init.h | 17 | ||||
| -rw-r--r-- | sys/dev/mpi3mr/mpi/mpi30_ioc.h | 108 | ||||
| -rw-r--r-- | sys/dev/mpi3mr/mpi/mpi30_pci.h | 6 | ||||
| -rw-r--r-- | sys/dev/mpi3mr/mpi/mpi30_raid.h | 4 | ||||
| -rw-r--r-- | sys/dev/mpi3mr/mpi/mpi30_sas.h | 5 | ||||
| -rw-r--r-- | sys/dev/mpi3mr/mpi/mpi30_targ.h | 17 | ||||
| -rw-r--r-- | sys/dev/mpi3mr/mpi/mpi30_tool.h | 11 | ||||
| -rw-r--r-- | sys/dev/mpi3mr/mpi/mpi30_transport.h | 104 | ||||
| -rw-r--r-- | sys/dev/mpi3mr/mpi/mpi30_type.h | 4 | ||||
| -rw-r--r-- | sys/dev/mpi3mr/mpi3mr.c | 737 | ||||
| -rw-r--r-- | sys/dev/mpi3mr/mpi3mr.h | 44 | ||||
| -rw-r--r-- | sys/dev/mpi3mr/mpi3mr_app.c | 33 | ||||
| -rw-r--r-- | sys/dev/mpi3mr/mpi3mr_app.h | 2 | ||||
| -rw-r--r-- | sys/dev/mpi3mr/mpi3mr_cam.c | 116 | ||||
| -rw-r--r-- | sys/dev/mpi3mr/mpi3mr_cam.h | 3 | ||||
| -rw-r--r-- | sys/dev/mpi3mr/mpi3mr_pci.c | 45 |
19 files changed, 1302 insertions, 389 deletions
diff --git a/sys/dev/mpi3mr/mpi/mpi30_api.h b/sys/dev/mpi3mr/mpi/mpi30_api.h index aa7b54ec470e..8b05deb7717c 100644 --- a/sys/dev/mpi3mr/mpi/mpi30_api.h +++ b/sys/dev/mpi3mr/mpi/mpi30_api.h @@ -1,7 +1,7 @@ /* - * SPDX-License-Identifier: BSD-2-Clause + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * - * Copyright (c) 2016-2023, Broadcom Inc. All rights reserved. + * Copyright (c) 2016-2025, Broadcom Inc. All rights reserved. * Support: <fbsd-storage-driver.pdl@broadcom.com> * * Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/mpi3mr/mpi/mpi30_cnfg.h b/sys/dev/mpi3mr/mpi/mpi30_cnfg.h index d1ae2ebfa372..d4cec3330a56 100644 --- a/sys/dev/mpi3mr/mpi/mpi30_cnfg.h +++ b/sys/dev/mpi3mr/mpi/mpi30_cnfg.h @@ -1,7 +1,7 @@ /* - * SPDX-License-Identifier: BSD-2-Clause + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * - * Copyright (c) 2016-2023, Broadcom Inc. All rights reserved. + * Copyright (c) 2016-2025, Broadcom Inc. All rights reserved. * Support: <fbsd-storage-driver.pdl@broadcom.com> * * Redistribution and use in source and binary forms, with or without @@ -64,6 +64,7 @@ * Configuration Page Attributes * ****************************************************************************/ #define MPI3_CONFIG_PAGEATTR_MASK (0xF0) +#define MPI3_CONFIG_PAGEATTR_SHIFT (4) #define MPI3_CONFIG_PAGEATTR_READ_ONLY (0x00) #define MPI3_CONFIG_PAGEATTR_CHANGEABLE (0x10) #define MPI3_CONFIG_PAGEATTR_PERSISTENT (0x20) @@ -84,58 +85,79 @@ /**** Device PageAddress Format ****/ #define MPI3_DEVICE_PGAD_FORM_MASK (0xF0000000) +#define MPI3_DEVICE_PGAD_FORM_SHIFT (28) #define MPI3_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) #define MPI3_DEVICE_PGAD_FORM_HANDLE (0x20000000) #define MPI3_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) +#define MPI3_DEVICE_PGAD_HANDLE_SHIFT (0) /**** SAS Expander PageAddress Format ****/ #define MPI3_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) +#define MPI3_SAS_EXPAND_PGAD_FORM_SHIFT (28) #define MPI3_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) #define MPI3_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM (0x10000000) #define MPI3_SAS_EXPAND_PGAD_FORM_HANDLE (0x20000000) #define MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000) #define MPI3_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16) #define MPI3_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF) +#define MPI3_SAS_EXPAND_PGAD_HANDLE_SHIFT (0) /**** SAS Phy PageAddress Format ****/ #define MPI3_SAS_PHY_PGAD_FORM_MASK (0xF0000000) +#define MPI3_SAS_PHY_PGAD_FORM_SHIFT (28) #define MPI3_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000) #define MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) +#define MPI3_SAS_PHY_PGAD_PHY_NUMBER_SHIFT (0) /**** SAS Port PageAddress Format ****/ #define MPI3_SASPORT_PGAD_FORM_MASK (0xF0000000) +#define MPI3_SASPORT_PGAD_FORM_SHIFT (28) #define MPI3_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000) #define MPI3_SASPORT_PGAD_FORM_PORT_NUM (0x10000000) #define MPI3_SASPORT_PGAD_PORT_NUMBER_MASK (0x000000FF) +#define MPI3_SASPORT_PGAD_PORT_NUMBER_SHIFT (0) /**** Enclosure PageAddress Format ****/ #define MPI3_ENCLOS_PGAD_FORM_MASK (0xF0000000) +#define MPI3_ENCLOS_PGAD_FORM_SHIFT (28) #define MPI3_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) #define MPI3_ENCLOS_PGAD_FORM_HANDLE (0x10000000) #define MPI3_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) +#define MPI3_ENCLOS_PGAD_HANDLE_SHIFT (0) /**** PCIe Switch PageAddress Format ****/ #define MPI3_PCIE_SWITCH_PGAD_FORM_MASK (0xF0000000) +#define MPI3_PCIE_SWITCH_PGAD_FORM_SHIFT (28) #define MPI3_PCIE_SWITCH_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) #define MPI3_PCIE_SWITCH_PGAD_FORM_HANDLE_PORT_NUM (0x10000000) #define MPI3_PCIE_SWITCH_PGAD_FORM_HANDLE (0x20000000) #define MPI3_PCIE_SWITCH_PGAD_PORTNUM_MASK (0x00FF0000) #define MPI3_PCIE_SWITCH_PGAD_PORTNUM_SHIFT (16) #define MPI3_PCIE_SWITCH_PGAD_HANDLE_MASK (0x0000FFFF) +#define MPI3_PCIE_SWITCH_PGAD_HANDLE_SHIFT (0) /**** PCIe Link PageAddress Format ****/ #define MPI3_PCIE_LINK_PGAD_FORM_MASK (0xF0000000) +#define MPI3_PCIE_LINK_PGAD_FORM_SHIFT (28) #define MPI3_PCIE_LINK_PGAD_FORM_GET_NEXT_LINK (0x00000000) #define MPI3_PCIE_LINK_PGAD_FORM_LINK_NUM (0x10000000) #define MPI3_PCIE_LINK_PGAD_LINKNUM_MASK (0x000000FF) +#define MPI3_PCIE_LINK_PGAD_LINKNUM_SHIFT (0) /**** Security PageAddress Format ****/ #define MPI3_SECURITY_PGAD_FORM_MASK (0xF0000000) +#define MPI3_SECURITY_PGAD_FORM_SHIFT (28) #define MPI3_SECURITY_PGAD_FORM_GET_NEXT_SLOT (0x00000000) #define MPI3_SECURITY_PGAD_FORM_SLOT_NUM (0x10000000) #define MPI3_SECURITY_PGAD_SLOT_GROUP_MASK (0x0000FF00) #define MPI3_SECURITY_PGAD_SLOT_GROUP_SHIFT (8) #define MPI3_SECURITY_PGAD_SLOT_MASK (0x000000FF) +#define MPI3_SECURITY_PGAD_SLOT_SHIFT (0) + +/**** Instance PageAddress Format ****/ +#define MPI3_INSTANCE_PGAD_INSTANCE_MASK (0x0000FFFF) +#define MPI3_INSTANCE_PGAD_INSTANCE_SHIFT (0) + /***************************************************************************** * Configuration Request Message * @@ -149,7 +171,8 @@ typedef struct _MPI3_CONFIG_REQUEST U8 IOCUseOnly06; /* 0x06 */ U8 MsgFlags; /* 0x07 */ U16 ChangeCount; /* 0x08 */ - U16 Reserved0A; /* 0x0A */ + U8 ProxyIOCNumber; /* 0x0A */ + U8 Reserved0B; /* 0x0B */ U8 PageVersion; /* 0x0C */ U8 PageNumber; /* 0x0D */ U8 PageType; /* 0x0E */ @@ -185,7 +208,7 @@ typedef struct _MPI3_CONFIG_PAGE_HEADER * Common definitions used by Configuration Pages * ****************************************************************************/ -/**** Defines for Negotiated Link Rates ****/ +/**** Defines for NegotiatedLinkRates ****/ #define MPI3_SAS_NEG_LINK_RATE_LOGICAL_MASK (0xF0) #define MPI3_SAS_NEG_LINK_RATE_LOGICAL_SHIFT (4) #define MPI3_SAS_NEG_LINK_RATE_PHYSICAL_MASK (0x0F) @@ -212,6 +235,7 @@ typedef struct _MPI3_CONFIG_PAGE_HEADER #define MPI3_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010) #define MPI3_SAS_APHYINFO_REASON_MASK (0x0000000F) +#define MPI3_SAS_APHYINFO_REASON_SHIFT (0) #define MPI3_SAS_APHYINFO_REASON_UNKNOWN (0x00000000) #define MPI3_SAS_APHYINFO_REASON_POWER_ON (0x00000001) #define MPI3_SAS_APHYINFO_REASON_HARD_RESET (0x00000002) @@ -231,6 +255,7 @@ typedef struct _MPI3_CONFIG_PAGE_HEADER #define MPI3_SAS_PHYINFO_STATUS_VACANT (0x80000000) #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000) +#define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_SHIFT (27) #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_ACTIVE (0x00000000) #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_PARTIAL (0x08000000) #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_SLUMBER (0x10000000) @@ -247,6 +272,7 @@ typedef struct _MPI3_CONFIG_PAGE_HEADER #define MPI3_SAS_PHYINFO_ZONING_ENABLED (0x00100000) #define MPI3_SAS_PHYINFO_REASON_MASK (0x000F0000) +#define MPI3_SAS_PHYINFO_REASON_SHIFT (16) #define MPI3_SAS_PHYINFO_REASON_UNKNOWN (0x00000000) #define MPI3_SAS_PHYINFO_REASON_POWER_ON (0x00010000) #define MPI3_SAS_PHYINFO_REASON_HARD_RESET (0x00020000) @@ -266,12 +292,14 @@ typedef struct _MPI3_CONFIG_PAGE_HEADER #define MPI3_SAS_PHYINFO_PARTIAL_PATHWAY_TIME_SHIFT (8) #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_MASK (0x000000F0) +#define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_SHIFT (4) #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_DIRECT (0x00000000) #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_SUBTRACTIVE (0x00000010) #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_TABLE (0x00000020) /**** Defines for the ProgrammedLinkRate field ****/ #define MPI3_SAS_PRATE_MAX_RATE_MASK (0xF0) +#define MPI3_SAS_PRATE_MAX_RATE_SHIFT (4) #define MPI3_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) #define MPI3_SAS_PRATE_MAX_RATE_1_5 (0x80) #define MPI3_SAS_PRATE_MAX_RATE_3_0 (0x90) @@ -279,6 +307,7 @@ typedef struct _MPI3_CONFIG_PAGE_HEADER #define MPI3_SAS_PRATE_MAX_RATE_12_0 (0xB0) #define MPI3_SAS_PRATE_MAX_RATE_22_5 (0xC0) #define MPI3_SAS_PRATE_MIN_RATE_MASK (0x0F) +#define MPI3_SAS_PRATE_MIN_RATE_SHIFT (0) #define MPI3_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) #define MPI3_SAS_PRATE_MIN_RATE_1_5 (0x08) #define MPI3_SAS_PRATE_MIN_RATE_3_0 (0x09) @@ -288,12 +317,14 @@ typedef struct _MPI3_CONFIG_PAGE_HEADER /**** Defines for the HwLinkRate field ****/ #define MPI3_SAS_HWRATE_MAX_RATE_MASK (0xF0) +#define MPI3_SAS_HWRATE_MAX_RATE_SHIFT (4) #define MPI3_SAS_HWRATE_MAX_RATE_1_5 (0x80) #define MPI3_SAS_HWRATE_MAX_RATE_3_0 (0x90) #define MPI3_SAS_HWRATE_MAX_RATE_6_0 (0xA0) #define MPI3_SAS_HWRATE_MAX_RATE_12_0 (0xB0) #define MPI3_SAS_HWRATE_MAX_RATE_22_5 (0xC0) #define MPI3_SAS_HWRATE_MIN_RATE_MASK (0x0F) +#define MPI3_SAS_HWRATE_MIN_RATE_SHIFT (0) #define MPI3_SAS_HWRATE_MIN_RATE_1_5 (0x08) #define MPI3_SAS_HWRATE_MIN_RATE_3_0 (0x09) #define MPI3_SAS_HWRATE_MIN_RATE_6_0 (0x0A) @@ -331,6 +362,9 @@ typedef struct _MPI3_CONFIG_PAGE_HEADER #define MPI3_MFGPAGE_DEVID_SAS5116_MPI_NS (0x00B5) #define MPI3_MFGPAGE_DEVID_SAS5116_NVME_NS (0x00B6) #define MPI3_MFGPAGE_DEVID_SAS5116_PCIE_SWITCH (0x00B8) +#define MPI3_MFGPAGE_DEVID_SAS5248_MPI (0x00F0) +#define MPI3_MFGPAGE_DEVID_SAS5248_MPI_NS (0x00F1) +#define MPI3_MFGPAGE_DEVID_SAS5248_PCIE_SWITCH (0x00F2) /***************************************************************************** * Manufacturing Page 0 * @@ -478,19 +512,28 @@ typedef struct _MPI3_MAN6_GPIO_ENTRY /**** Defines for FunctionFlags when FunctionCode is ISTWI_RESET ****/ #define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_MASK (0x01) +#define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_SHIFT (0) #define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_ISTWI (0x00) #define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_RECEPTACLEID (0x01) /**** Defines for Param1 (Flags) when FunctionCode is EXT_INTERRUPT ****/ #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_MASK (0xF0) +#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_SHIFT (4) #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_GENERIC (0x00) #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_CABLE_MGMT (0x10) #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_ACTIVE_CABLE_OVERCURRENT (0x20) +#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_ACK_REQUIRED (0x02) #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_MASK (0x01) +#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_SHIFT (0) #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_EDGE (0x00) #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_LEVEL (0x01) +/**** Defines for Param1 (LEVEL) when FunctionCode is OVER_TEMPERATURE ****/ +#define MPI3_MAN6_GPIO_OVER_TEMP_PARAM1_LEVEL_WARNING (0x00) +#define MPI3_MAN6_GPIO_OVER_TEMP_PARAM1_LEVEL_CRITICAL (0x01) +#define MPI3_MAN6_GPIO_OVER_TEMP_PARAM1_LEVEL_FATAL (0x02) + /**** Defines for Param1 (PHY STATE) when FunctionCode is PORT_STATUS_GREEN ****/ #define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ALL_UP (0x00) #define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ONE_OR_MORE_UP (0x01) @@ -506,9 +549,11 @@ typedef struct _MPI3_MAN6_GPIO_ENTRY /**** Defines for the Flags field ****/ #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_MASK (0x0100) +#define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_SHIFT (8) #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_FAST_EDGE (0x0100) #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_SLOW_EDGE (0x0000) #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_MASK (0x00C0) +#define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_SHIFT (6) #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_100OHM (0x0000) #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_66OHM (0x0040) #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_50OHM (0x0080) @@ -518,6 +563,7 @@ typedef struct _MPI3_MAN6_GPIO_ENTRY #define MPI3_MAN6_GPIO_FLAGS_ACTIVE_HIGH (0x0008) #define MPI3_MAN6_GPIO_FLAGS_BI_DIR_ENABLED (0x0004) #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_MASK (0x0003) +#define MPI3_MAN6_GPIO_FLAGS_DIRECTION_SHIFT (0) #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_INPUT (0x0000) #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_OPEN_DRAIN_OUTPUT (0x0001) #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_OPEN_SOURCE_OUTPUT (0x0002) @@ -570,9 +616,11 @@ typedef struct _MPI3_MAN7_RECEPTACLE_INFO /**** Defines for PEDClk field ****/ #define MPI3_MAN7_PEDCLK_ROUTING_MASK (0x10) +#define MPI3_MAN7_PEDCLK_ROUTING_SHIFT (4) #define MPI3_MAN7_PEDCLK_ROUTING_DIRECT (0x00) #define MPI3_MAN7_PEDCLK_ROUTING_CLOCK_BUFFER (0x10) #define MPI3_MAN7_PEDCLK_ID_MASK (0x0F) +#define MPI3_MAN7_PEDCLK_ID_SHIFT (0) #ifndef MPI3_MAN7_RECEPTACLE_INFO_MAX #define MPI3_MAN7_RECEPTACLE_INFO_MAX (1) @@ -594,6 +642,7 @@ typedef struct _MPI3_MAN_PAGE7 /**** Defines for Flags field ****/ #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_MASK (0x01) +#define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_SHIFT (0) #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_0 (0x00) #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_1 (0x01) @@ -965,6 +1014,7 @@ typedef struct _MPI3_MAN11_BOARD_FAN_DEVICE_FORMAT /**** Defines for the Flags field ****/ #define MPI3_MAN11_BOARD_FAN_FLAGS_FAN_CTRLR_TYPE_MASK (0x07) +#define MPI3_MAN11_BOARD_FAN_FLAGS_FAN_CTRLR_TYPE_SHIFT (0) #define MPI3_MAN11_BOARD_FAN_FLAGS_FAN_CTRLR_TYPE_AMC6821 (0x00) typedef union _MPI3_MAN11_DEVICE_SPECIFIC_FORMAT @@ -1067,13 +1117,15 @@ typedef struct _MPI3_MAN_PAGE12 #define MPI3_MAN12_FLAGS_GROUP_ID_DISABLED (0x0100) #define MPI3_MAN12_FLAGS_SIO_CLK_FILTER_ENABLED (0x0004) #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_MASK (0x0002) +#define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_SHIFT (1) #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_PUSH_PULL (0x0000) #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_OPEN_DRAIN (0x0002) #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_MASK (0x0001) +#define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_SHIFT (0) #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_PUSH_PULL (0x0000) #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_OPEN_DRAIN (0x0001) -/**** Defines for the SioClkFreq field ****/ +/**** Defines for the SClockFreq field ****/ #define MPI3_MAN12_SIO_CLK_FREQ_MIN (32) /* 32 Hz min SIO Clk Freq */ #define MPI3_MAN12_SIO_CLK_FREQ_MAX (100000) /* 100 KHz max SIO Clk Freq */ @@ -1089,6 +1141,7 @@ typedef struct _MPI3_MAN_PAGE12 /*** Defines for the Pattern field ****/ #define MPI3_MAN12_PATTERN_RATE_MASK (0xE0000000) +#define MPI3_MAN12_PATTERN_RATE_SHIFT (29) #define MPI3_MAN12_PATTERN_RATE_2_HZ (0x00000000) #define MPI3_MAN12_PATTERN_RATE_4_HZ (0x20000000) #define MPI3_MAN12_PATTERN_RATE_8_HZ (0x40000000) @@ -1300,14 +1353,17 @@ typedef struct _MPI3_MAN_PAGE20 /**** Defines for the AllowedPersonalities field ****/ #define MPI3_MAN20_ALLOWEDPERSON_RAID_MASK (0x02) +#define MPI3_MAN20_ALLOWEDPERSON_RAID_SHIFT (1) #define MPI3_MAN20_ALLOWEDPERSON_RAID_ALLOWED (0x02) #define MPI3_MAN20_ALLOWEDPERSON_RAID_NOT_ALLOWED (0x00) #define MPI3_MAN20_ALLOWEDPERSON_EHBA_MASK (0x01) +#define MPI3_MAN20_ALLOWEDPERSON_EHBA_SHIFT (0) #define MPI3_MAN20_ALLOWEDPERSON_EHBA_ALLOWED (0x01) #define MPI3_MAN20_ALLOWEDPERSON_EHBA_NOT_ALLOWED (0x00) -/**** Defines for the NonpremuimFeatures field ****/ +/**** Defines for the NonpremiumFeatures field ****/ #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_MASK (0x01) +#define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_SHIFT (0) #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_ENABLED (0x00) #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_DISABLED (0x01) @@ -1328,17 +1384,37 @@ typedef struct _MPI3_MAN_PAGE21 /**** Defines for the Flags field ****/ #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_MASK (0x00000060) +#define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_SHIFT (5) #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_BLOCK (0x00000000) #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_ALLOW (0x00000020) #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_WARN (0x00000040) #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_MASK (0x00000008) +#define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_SHIFT (3) #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_ALLOW (0x00000000) #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_PREVENT (0x00000008) #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_MASK (0x00000001) +#define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_SHIFT (0) #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_DEFAULT (0x00000000) #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_OEM_SPECIFIC (0x00000001) /***************************************************************************** + * Manufacturing Page 22 * + ****************************************************************************/ + +typedef struct _MPI3_MAN_PAGE22 +{ + MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ + U32 Reserved08; /* 0x08 */ + U16 NumEUI64; /* 0x0C */ + U16 Reserved0E; /* 0x0E */ + U64 BaseEUI64; /* 0x10 */ +} MPI3_MAN_PAGE22, MPI3_POINTER PTR_MPI3_MAN_PAGE22, + Mpi3ManPage22_t, MPI3_POINTER pMpi3ManPage22_t; + +/**** Defines for the PageVersion field ****/ +#define MPI3_MAN22_PAGEVERSION (0x00) + +/***************************************************************************** * Manufacturing Pages 32-63 (ProductSpecific) * ****************************************************************************/ #ifndef MPI3_MAN_PROD_SPECIFIC_MAX @@ -1390,18 +1466,21 @@ typedef struct _MPI3_IO_UNIT_PAGE1 /**** Defines for the Flags field ****/ #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_MASK (0x00000030) +#define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_SHIFT (4) #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_ENABLE (0x00000000) #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_DISABLE (0x00000010) #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_NO_MODIFY (0x00000020) #define MPI3_IOUNIT1_FLAGS_ATA_SECURITY_FREEZE_LOCK (0x00000008) #define MPI3_IOUNIT1_FLAGS_WRITE_SAME_BUFFER (0x00000004) #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_MASK (0x00000003) +#define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_SHIFT (0) #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_ENABLE (0x00000000) #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_DISABLE (0x00000001) #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_UNCHANGED (0x00000002) /**** Defines for the DMDReport PCIe/SATA/SAS fields ****/ #define MPI3_IOUNIT1_DMD_REPORT_DELAY_TIME_MASK (0x7F) +#define MPI3_IOUNIT1_DMD_REPORT_DELAY_TIME_SHIFT (0) #define MPI3_IOUNIT1_DMD_REPORT_UNIT_16_SEC (0x80) /***************************************************************************** @@ -1427,6 +1506,7 @@ typedef struct _MPI3_IO_UNIT_PAGE2 #define MPI3_IOUNIT2_GPIO_FUNCTION_MASK (0xFFFC) #define MPI3_IOUNIT2_GPIO_FUNCTION_SHIFT (2) #define MPI3_IOUNIT2_GPIO_SETTING_MASK (0x0001) +#define MPI3_IOUNIT2_GPIO_SETTING_SHIFT (0) #define MPI3_IOUNIT2_GPIO_SETTING_OFF (0x0000) #define MPI3_IOUNIT2_GPIO_SETTING_ON (0x0001) @@ -1434,13 +1514,21 @@ typedef struct _MPI3_IO_UNIT_PAGE2 * IO Unit Page 3 * ****************************************************************************/ +typedef enum _MPI3_IOUNIT3_THRESHOLD +{ + MPI3_IOUNIT3_THRESHOLD_WARNING = 0, + MPI3_IOUNIT3_THRESHOLD_CRITICAL = 1, + MPI3_IOUNIT3_THRESHOLD_FATAL = 2, + MPI3_IOUNIT3_THRESHOLD_LOW = 3, + MPI3_IOUNIT3_NUM_THRESHOLDS +} MPI3_IOUNIT3_THRESHOLD; + typedef struct _MPI3_IO_UNIT3_SENSOR { U16 Flags; /* 0x00 */ U8 ThresholdMargin; /* 0x02 */ U8 Reserved03; /* 0x03 */ - U16 Threshold[3]; /* 0x04 */ - U16 Reserved0A; /* 0x0A */ + U16 Threshold[MPI3_IOUNIT3_NUM_THRESHOLDS]; /* 0x04 */ U32 Reserved0C; /* 0x0C */ U32 Reserved10; /* 0x10 */ U32 Reserved14; /* 0x14 */ @@ -1448,6 +1536,7 @@ typedef struct _MPI3_IO_UNIT3_SENSOR Mpi3IOUnit3Sensor_t, MPI3_POINTER pMpi3IOUnit3Sensor_t; /**** Defines for the Flags field ****/ +#define MPI3_IOUNIT3_SENSOR_FLAGS_LOW_THRESHOLD_VALID (0x0020) #define MPI3_IOUNIT3_SENSOR_FLAGS_FATAL_EVENT_ENABLED (0x0010) #define MPI3_IOUNIT3_SENSOR_FLAGS_FATAL_ACTION_ENABLED (0x0008) #define MPI3_IOUNIT3_SENSOR_FLAGS_CRITICAL_EVENT_ENABLED (0x0004) @@ -1591,8 +1680,9 @@ typedef struct _MPI3_IO_UNIT_PAGE5 #define MPI3_IOUNIT5_FLAGS_POWER_CAPABLE_SPINUP (0x02) #define MPI3_IOUNIT5_FLAGS_AUTO_PORT_ENABLE (0x01) -/**** Defines for the PHY field ****/ +/**** Defines for the Phy field ****/ #define MPI3_IOUNIT5_PHY_SPINUP_GROUP_MASK (0x03) +#define MPI3_IOUNIT5_PHY_SPINUP_GROUP_SHIFT (0) /***************************************************************************** * IO Unit Page 6 * @@ -1621,11 +1711,33 @@ typedef struct _MPI3_IO_UNIT_PAGE6 #define MPI3_IOUNIT8_DIGEST_MAX (1) #endif /* MPI3_IOUNIT8_DIGEST_MAX */ -typedef union _MPI3_IOUNIT8_DIGEST +typedef union _MPI3_IOUNIT8_RAW_DIGEST { U32 Dword[16]; U16 Word[32]; U8 Byte[64]; +} MPI3_IOUNIT8_RAW_DIGEST, MPI3_POINTER PTR_MPI3_IOUNIT8_RAW_DIGEST, + Mpi3IOUnit8RawDigest_t, MPI3_POINTER pMpi3IOUnit8RawDigest_t; + +typedef struct _MPI3_IOUNIT8_METADATA_DIGEST +{ + U8 SlotStatus; /* 0x00 */ + U8 Reserved01[3]; /* 0x01 */ + U32 Reserved04[3]; /* 0x04 */ + MPI3_IOUNIT8_RAW_DIGEST DigestData; /* 0x10 */ +} MPI3_IOUNIT8_METADATA_DIGEST, MPI3_POINTER PTR_MPI3_IOUNIT8_METADATA_DIGEST, + Mpi3IOUnit8MetadataDigest_t, MPI3_POINTER pMpi3IOUnit8MetadataDigest_t; + +/**** Defines for the SlotStatus field ****/ +#define MPI3_IOUNIT8_METADATA_DIGEST_SLOTSTATUS_UNUSED (0x00) +#define MPI3_IOUNIT8_METADATA_DIGEST_SLOTSTATUS_UPDATE_PENDING (0x01) +#define MPI3_IOUNIT8_METADATA_DIGEST_SLOTSTATUS_VALID (0x03) +#define MPI3_IOUNIT8_METADATA_DIGEST_SLOTSTATUS_INVALID (0x07) + +typedef union _MPI3_IOUNIT8_DIGEST +{ + MPI3_IOUNIT8_RAW_DIGEST RawDigest[MPI3_IOUNIT8_DIGEST_MAX]; + MPI3_IOUNIT8_METADATA_DIGEST MetadataDigest[MPI3_IOUNIT8_DIGEST_MAX]; } MPI3_IOUNIT8_DIGEST, MPI3_POINTER PTR_MPI3_IOUNIT8_DIGEST, Mpi3IOUnit8Digest_t, MPI3_POINTER pMpi3IOUnit8Digest_t; @@ -1633,8 +1745,9 @@ typedef struct _MPI3_IO_UNIT_PAGE8 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U8 SBMode; /* 0x08 */ - U8 SbState; /* 0x09 */ - U16 Reserved0A; /* 0x0A */ + U8 SBState; /* 0x09 */ + U8 Flags; /* 0x0A */ + U8 Reserved0A; /* 0x0B */ U8 NumSlots; /* 0x0C */ U8 SlotsAvailable; /* 0x0D */ U8 CurrentKeyEncryptionAlgo; /* 0x0E */ @@ -1642,22 +1755,33 @@ typedef struct _MPI3_IO_UNIT_PAGE8 MPI3_VERSION_UNION CurrentSvn; /* 0x10 */ U32 Reserved14; /* 0x14 */ U32 CurrentKey[128]; /* 0x18 */ - MPI3_IOUNIT8_DIGEST Digest[MPI3_IOUNIT8_DIGEST_MAX]; /* 0x218 */ /* variable length */ + MPI3_IOUNIT8_DIGEST Digest; /* 0x218 */ /* variable length */ } MPI3_IO_UNIT_PAGE8, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE8, Mpi3IOUnitPage8_t, MPI3_POINTER pMpi3IOUnitPage8_t; /**** Defines for the PageVersion field ****/ -#define MPI3_IOUNIT8_PAGEVERSION (0x00) +#define MPI3_IOUNIT8_PAGEVERSION (0x00) /**** Defines for the SBMode field ****/ -#define MPI3_IOUNIT8_SBMODE_SECURE_DEBUG (0x04) -#define MPI3_IOUNIT8_SBMODE_HARD_SECURE (0x02) -#define MPI3_IOUNIT8_SBMODE_CONFIG_SECURE (0x01) +#define MPI3_IOUNIT8_SBMODE_HARD_SECURE_RECERTIFIED (0x08) +#define MPI3_IOUNIT8_SBMODE_SECURE_DEBUG (0x04) +#define MPI3_IOUNIT8_SBMODE_HARD_SECURE (0x02) +#define MPI3_IOUNIT8_SBMODE_CONFIG_SECURE (0x01) /**** Defines for the SBState field ****/ -#define MPI3_IOUNIT8_SBSTATE_SVN_UPDATE_PENDING (0x04) -#define MPI3_IOUNIT8_SBSTATE_KEY_UPDATE_PENDING (0x02) -#define MPI3_IOUNIT8_SBSTATE_SECURE_BOOT_ENABLED (0x01) +#define MPI3_IOUNIT8_SBSTATE_SVN_UPDATE_PENDING (0x04) +#define MPI3_IOUNIT8_SBSTATE_KEY_UPDATE_PENDING (0x02) +#define MPI3_IOUNIT8_SBSTATE_SECURE_BOOT_ENABLED (0x01) + +/**** Defines for the Flags field ****/ +#define MPI3_IOUNIT8_FLAGS_CURRENT_KEY_IOUNIT17 (0x08) +#define MPI3_IOUNIT8_FLAGS_DIGESTFORM_MASK (0x07) +#define MPI3_IOUNIT8_FLAGS_DIGESTFORM_SHIFT (0) +#define MPI3_IOUNIT8_FLAGS_DIGESTFORM_RAW (0x00) +#define MPI3_IOUNIT8_FLAGS_DIGESTFORM_DIGEST_WITH_METADATA (0x01) + +/**** Use MPI3_ENCRYPTION_ALGORITHM_ defines (see mpi30_image.h) for the CurrentKeyEncryptionAlgo field ****/ +/**** Use MPI3_HASH_ALGORITHM defines (see mpi30_image.h) for the KeyDigestHashAlgo field ****/ /***************************************************************************** * IO Unit Page 9 * @@ -1685,6 +1809,7 @@ typedef struct _MPI3_IO_UNIT_PAGE9 /**** Defines for the FirstDevice field ****/ #define MPI3_IOUNIT9_FIRSTDEVICE_UNKNOWN (0xFFFF) +#define MPI3_IOUNIT9_FIRSTDEVICE_IN_DRIVER_PAGE_0 (0xFFFE) /***************************************************************************** * IO Unit Page 10 * @@ -1710,6 +1835,7 @@ typedef struct _MPI3_IO_UNIT_PAGE10 /**** Defines for the Flags field ****/ #define MPI3_IOUNIT10_FLAGS_VALID (0x01) #define MPI3_IOUNIT10_FLAGS_ACTIVEID_MASK (0x02) +#define MPI3_IOUNIT10_FLAGS_ACTIVEID_SHIFT (1) #define MPI3_IOUNIT10_FLAGS_ACTIVEID_FIRST_REGION (0x00) #define MPI3_IOUNIT10_FLAGS_ACTIVEID_SECOND_REGION (0x02) #define MPI3_IOUNIT10_FLAGS_PBLP_EXPECTED (0x80) @@ -1791,6 +1917,7 @@ typedef struct _MPI3_IO_UNIT_PAGE12 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_32 (0x00000200) #define MPI3_IOUNIT12_FLAGS_NUMPASSES_64 (0x00000300) #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_MASK (0x00000003) +#define MPI3_IOUNIT12_FLAGS_PASSPERIOD_SHIFT (0) #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_DISABLED (0x00000000) #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_500US (0x00000001) #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_1MS (0x00000002) @@ -1901,6 +2028,7 @@ typedef struct _MPI3_IO_UNIT_PAGE15 /**** Defines for the Flags field ****/ #define MPI3_IOUNIT15_FLAGS_EPRINIT_INITREQUIRED (0x04) #define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_MASK (0x03) +#define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_SHIFT (0) #define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_NOT_SUPPORTED (0x00) #define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_WITHOUT_POWER_BRAKE_GPIO (0x01) #define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_WITH_POWER_BRAKE_GPIO (0x02) @@ -1909,6 +2037,122 @@ typedef struct _MPI3_IO_UNIT_PAGE15 #define MPI3_IOUNIT15_NUMPOWERBUDGETDATA_POWER_BUDGETING_DISABLED (0x00) /***************************************************************************** + * IO Unit Page 16 * + ****************************************************************************/ + +#ifndef MPI3_IOUNIT16_ERROR_MAX +#define MPI3_IOUNIT16_ERROR_MAX (1) +#endif /* MPI3_IOUNIT16_ERROR_MAX */ + +typedef struct _MPI3_IOUNIT16_ERROR +{ + U32 Offset; /* 0x00 */ + U32 Reserved04; /* 0x04 */ + U64 Count; /* 0x08 */ + U64 Timestamp; /* 0x10 */ +} MPI3_IOUNIT16_ERROR, MPI3_POINTER PTR_MPI3_IOUNIT16_ERROR, + Mpi3IOUnit16Error_t, MPI3_POINTER pMpi3IOUnit16Error_t; + +typedef struct _MPI3_IO_UNIT_PAGE16 +{ + MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ + U64 TotalErrorCount; /* 0x08 */ + U32 Reserved10[3]; /* 0x10 */ + U8 NumErrors; /* 0x1C */ + U8 MaxErrorsTracked; /* 0x1D */ + U16 Reserved1E; /* 0x1E */ + MPI3_IOUNIT16_ERROR Error[MPI3_IOUNIT16_ERROR_MAX]; /* 0x20 */ /* variable length */ +} MPI3_IO_UNIT_PAGE16, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE16, + Mpi3IOUnitPage16_t, MPI3_POINTER pMpi3IOUnitPage16_t; + +/**** Defines for the PageVersion field ****/ +#define MPI3_IOUNIT16_PAGEVERSION (0x00) + +/***************************************************************************** + * IO Unit Page 17 * + ****************************************************************************/ + +#ifndef MPI3_IOUNIT17_CURRENTKEY_MAX +#define MPI3_IOUNIT17_CURRENTKEY_MAX (1) +#endif /* MPI3_IOUNIT17_CURRENTKEY_MAX */ + +typedef struct _MPI3_IO_UNIT_PAGE17 +{ + MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ + U8 NumInstances; /* 0x08 */ + U8 Instance; /* 0x09 */ + U16 Reserved0A; /* 0x0A */ + U32 Reserved0C[4]; /* 0x0C */ + U16 KeyLength; /* 0x1C */ + U8 EncryptionAlgorithm; /* 0x1E */ + U8 Reserved1F; /* 0x1F */ + U32 CurrentKey[MPI3_IOUNIT17_CURRENTKEY_MAX]; /* 0x20 */ /* variable length */ +} MPI3_IO_UNIT_PAGE17, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE17, + Mpi3IOUnitPage17_t, MPI3_POINTER pMpi3IOUnitPage17_t; + +/**** Defines for the PageVersion field ****/ +#define MPI3_IOUNIT17_PAGEVERSION (0x00) + +/**** Use MPI3_ENCRYPTION_ALGORITHM_ defines (see mpi30_image.h) for the EncryptionAlgorithm field ****/ + +/***************************************************************************** + * IO Unit Page 18 * + ****************************************************************************/ + +typedef struct _MPI3_IO_UNIT_PAGE18 +{ + MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ + U8 Flags; /* 0x08 */ + U8 PollInterval; /* 0x09 */ + U16 Reserved0A; /* 0x0A */ + U32 Reserved0C; /* 0x0C */ +} MPI3_IO_UNIT_PAGE18, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE18, + Mpi3IOUnitPage18_t, MPI3_POINTER pMpi3IOUnitPage18_t; + +/**** Defines for the PageVersion field ****/ +#define MPI3_IOUNIT18_PAGEVERSION (0x00) + +/**** Defines for the Flags field ****/ +#define MPI3_IOUNIT18_FLAGS_DIRECTATTACHED_ENABLE (0x01) + +/**** Defines for the PollInterval field ****/ +#define MPI3_IOUNIT18_POLLINTERVAL_DISABLE (0x00) + +/***************************************************************************** + * IO Unit Page 19 * + ****************************************************************************/ + +#ifndef MPI3_IOUNIT19_DEVICE_MAX +#define MPI3_IOUNIT19_DEVICE_MAX (1) +#endif /* MPI3_IOUNIT19_DEVICE_MAX */ + +typedef struct _MPI3_IOUNIT19_DEVICE_ +{ + U16 Temperature; /* 0x00 */ + U16 DevHandle; /* 0x02 */ + U16 PersistentID; /* 0x04 */ + U16 Reserved06; /* 0x06 */ +} MPI3_IOUNIT19_DEVICE, MPI3_POINTER PTR_MPI3_IOUNIT19_DEVICE, + Mpi3IOUnit19Device_t, MPI3_POINTER pMpi3IOUnit19Device_t; + +/**** Defines for the Temperature field ****/ +#define MPI3_IOUNIT19_DEVICE_TEMPERATURE_UNAVAILABLE (0x8000) + +typedef struct _MPI3_IO_UNIT_PAGE19 +{ + MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ + U16 NumDevices; /* 0x08 */ + U16 Reserved0A; /* 0x0A */ + U32 Reserved0C; /* 0x0C */ + MPI3_IOUNIT19_DEVICE Device[MPI3_IOUNIT19_DEVICE_MAX]; /* 0x10 */ +} MPI3_IO_UNIT_PAGE19, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE19, + Mpi3IOUnitPage19_t, MPI3_POINTER pMpi3IOUnitPage19_t; + +/**** Defines for the PageVersion field ****/ +#define MPI3_IOUNIT19_PAGEVERSION (0x00) + + +/***************************************************************************** * IOC Configuration Pages * ****************************************************************************/ @@ -1973,7 +2217,8 @@ typedef struct _MPI3_IOC_PAGE2 * Driver Configuration Pages * ****************************************************************************/ -/**** Defines for the Flags field ****/ +/**** Defines for the Flags field in Driver Pages 10, 20, and 30 ****/ +/**** NOT used in Driver Page 1 Flags field ****/ #define MPI3_DRIVER_FLAGS_ADMINRAIDPD_BLOCKED (0x0010) #define MPI3_DRIVER_FLAGS_OOBRAIDPD_BLOCKED (0x0008) #define MPI3_DRIVER_FLAGS_OOBRAIDVD_BLOCKED (0x0004) @@ -2006,11 +2251,13 @@ typedef struct _MPI3_ALLOWED_CMD_NVME } MPI3_ALLOWED_CMD_NVME, MPI3_POINTER PTR_MPI3_ALLOWED_CMD_NVME, Mpi3AllowedCmdNvme_t, MPI3_POINTER pMpi3AllowedCmdNvme_t; -/**** Defines for the CommandFlags field ****/ +/**** Defines for the NVMeCmdFlags field ****/ #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_MASK (0x80) +#define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_SHIFT (7) #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_IO (0x00) #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_ADMIN (0x80) #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_CMDSET_MASK (0x3F) +#define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_CMDSET_SHIFT (0) #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_CMDSET_NVM (0x00) typedef union _MPI3_ALLOWED_CMD @@ -2047,7 +2294,7 @@ typedef struct _MPI3_DRIVER_PAGE0 U8 TURInterval; /* 0x0F */ U8 Reserved10; /* 0x10 */ U8 SecurityKeyTimeout; /* 0x11 */ - U16 Reserved12; /* 0x12 */ + U16 FirstDevice; /* 0x12 */ U32 Reserved14; /* 0x14 */ U32 Reserved18; /* 0x18 */ } MPI3_DRIVER_PAGE0, MPI3_POINTER PTR_MPI3_DRIVER_PAGE0, @@ -2057,13 +2304,20 @@ typedef struct _MPI3_DRIVER_PAGE0 #define MPI3_DRIVER0_PAGEVERSION (0x00) /**** Defines for the BSDOptions field ****/ +#define MPI3_DRIVER0_BSDOPTS_DEVICEEXPOSURE_DISABLE (0x00000020) +#define MPI3_DRIVER0_BSDOPTS_WRITECACHE_DISABLE (0x00000010) #define MPI3_DRIVER0_BSDOPTS_HEADLESS_MODE_ENABLE (0x00000008) #define MPI3_DRIVER0_BSDOPTS_DIS_HII_CONFIG_UTIL (0x00000004) #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_MASK (0x00000003) +#define MPI3_DRIVER0_BSDOPTS_REGISTRATION_SHIFT (0) #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_AND_DEVS (0x00000000) #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_ONLY (0x00000001) #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_AND_INTERNAL_DEVS (0x00000002) +/**** Defines for the FirstDevice field ****/ +#define MPI3_DRIVER0_FIRSTDEVICE_IGNORE1 (0x0000) +#define MPI3_DRIVER0_FIRSTDEVICE_IGNORE2 (0xFFFF) + /***************************************************************************** * Driver Page 1 * ****************************************************************************/ @@ -2071,7 +2325,8 @@ typedef struct _MPI3_DRIVER_PAGE1 { MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ U32 Flags; /* 0x08 */ - U32 Reserved0C; /* 0x0C */ + U8 TimeStampUpdate; /* 0x0C */ + U8 Reserved0D[3]; /* 0x0D */ U16 HostDiagTraceMaxSize; /* 0x10 */ U16 HostDiagTraceMinSize; /* 0x12 */ U16 HostDiagTraceDecrementSize; /* 0x14 */ @@ -2263,14 +2518,6 @@ typedef union _MPI3_SECURITY_NONCE } MPI3_SECURITY_NONCE, MPI3_POINTER PTR_MPI3_SECURITY_NONCE, Mpi3SecurityNonce_t, MPI3_POINTER pMpi3SecurityNonce_t; -typedef union _MPI3_SECURITY_ROOT_DIGEST -{ - U32 Dword[16]; - U16 Word[32]; - U8 Byte[64]; -} MPI3_SECURITY_ROOT_DIGEST, MPI3_POINTER PTR_MPI3_SECURITY_ROOT_DIGEST, - Mpi3SecurityRootDigest_t, MPI3_POINTER pMpi3SecurityRootDigest_t; - /***************************************************************************** * Security Page 0 * ****************************************************************************/ @@ -2305,6 +2552,7 @@ typedef struct _MPI3_SECURITY_PAGE0 /**** Defines for the CertChainFlags field ****/ #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_MASK (0x0E) +#define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_SHIFT (1) #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_UNUSED (0x00) #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_CERBERUS (0x02) #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_SPDM (0x04) @@ -2343,6 +2591,7 @@ typedef struct _MPI3_SECURITY1_KEY_RECORD /**** Defines for the Flags field ****/ #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_MASK (0x1F) +#define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_SHIFT (0) #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_NOT_VALID (0x00) #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_HMAC (0x01) #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_AES (0x02) @@ -2382,17 +2631,25 @@ typedef struct _MPI3_SECURITY_PAGE1 #define MPI3_SECURITY2_TRUSTED_ROOT_MAX 1 #endif /* MPI3_SECURITY2_TRUSTED_ROOT_MAX */ +#ifndef MPI3_SECURITY2_ROOT_LEN +#define MPI3_SECURITY2_ROOT_LEN 4 +#endif /* MPI3_SECURITY2_ROOT_LEN */ + typedef struct _MPI3_SECURITY2_TRUSTED_ROOT { U8 Level; /* 0x00 */ U8 HashAlgorithm; /* 0x01 */ U16 TrustedRootFlags; /* 0x02 */ U32 Reserved04[3]; /* 0x04 */ - MPI3_SECURITY_ROOT_DIGEST RootDigest; /* 0x10 */ + U8 Root[MPI3_SECURITY2_ROOT_LEN]; /* 0x10 */ /* variable length */ } MPI3_SECURITY2_TRUSTED_ROOT, MPI3_POINTER PTR_MPI3_SECURITY2_TRUSTED_ROOT, Mpi3Security2TrustedRoot_t, MPI3_POINTER pMpi3Security2TrustedRoot_t; /**** Defines for the TrustedRootFlags field ****/ +#define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_ROOTFORM_MASK (0xF000) +#define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_ROOTFORM_SHIFT (12) +#define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_ROOTFORM_DIGEST (0x0000) +#define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_ROOTFORM_DERCERT (0x1000) #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_MASK (0x0006) #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_SHIFT (1) #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_HA_FIELD (0x0000) @@ -2407,7 +2664,8 @@ typedef struct _MPI3_SECURITY_PAGE2 MPI3_SECURITY_NONCE Nonce; /* 0x50 */ U32 Reserved90[3]; /* 0x90 */ U8 NumRoots; /* 0x9C */ - U8 Reserved9D[3]; /* 0x9D */ + U8 Reserved9D; /* 0x9D */ + U16 RootElementSize; /* 0x9E */ MPI3_SECURITY2_TRUSTED_ROOT TrustedRoot[MPI3_SECURITY2_TRUSTED_ROOT_MAX]; /* 0xA0 */ /* variable length */ } MPI3_SECURITY_PAGE2, MPI3_POINTER PTR_MPI3_SECURITY_PAGE2, Mpi3SecurityPage2_t, MPI3_POINTER pMpi3SecurityPage2_t; @@ -2469,6 +2727,7 @@ typedef struct _MPI3_SAS_IO_UNIT_PAGE0 /**** Defines for the PortFlags field ****/ #define MPI3_SASIOUNIT0_PORTFLAGS_DISC_IN_PROGRESS (0x08) #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_MASK (0x03) +#define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_SHIFT (0) #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_IOUNIT1 (0x00) #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_DYNAMIC (0x01) #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_BACKPLANE (0x02) @@ -2533,6 +2792,7 @@ typedef struct _MPI3_SAS_IO_UNIT_PAGE1 #define MPI3_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) #define MPI3_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_MASK (0x0001) +#define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_SHIFT (0) #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_DEVICE_NAME (0x0000) #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_SAS_ADDRESS (0x0001) @@ -2562,6 +2822,7 @@ typedef struct _MPI3_SAS_IO_UNIT_PAGE1 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_12_0 (0xB0) #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_22_5 (0xC0) #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_MASK (0x0F) +#define MPI3_SASIOUNIT1_MMLR_MIN_RATE_SHIFT (0) #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_6_0 (0x0A) #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_12_0 (0x0B) #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_22_5 (0x0C) @@ -3052,10 +3313,11 @@ typedef struct _MPI3_SAS_PHY_PAGE4 * Common definitions used by PCIe Configuration Pages * ****************************************************************************/ -/**** Defines for Negotiated Link Rates ****/ +/**** Defines for NegotiatedLinkRates ****/ #define MPI3_PCIE_LINK_RETIMERS_MASK (0x30) #define MPI3_PCIE_LINK_RETIMERS_SHIFT (4) #define MPI3_PCIE_NEG_LINK_RATE_MASK (0x0F) +#define MPI3_PCIE_NEG_LINK_RATE_SHIFT (0) #define MPI3_PCIE_NEG_LINK_RATE_UNKNOWN (0x00) #define MPI3_PCIE_NEG_LINK_RATE_PHY_DISABLED (0x01) #define MPI3_PCIE_NEG_LINK_RATE_2_5 (0x02) @@ -3099,6 +3361,7 @@ typedef struct _MPI3_PCIE_IO_UNIT0_PHY_DATA /**** Defines for the LinkFlags field ****/ #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_MASK (0x10) +#define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_SHIFT (4) #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_IOUNIT1 (0x00) #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_BKPLANE (0x10) #define MPI3_PCIEIOUNIT0_LINKFLAGS_ENUM_IN_PROGRESS (0x08) @@ -3175,6 +3438,7 @@ typedef struct _MPI3_PCIE_IO_UNIT1_PHY_DATA /**** Defines for the LinkFlags field ****/ #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_MASK (0x03) +#define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_SHIFT (0) #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_DIS_SEPARATE_REFCLK (0x00) #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_EN_SRIS (0x01) #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_EN_SRNS (0x02) @@ -3213,14 +3477,16 @@ typedef struct _MPI3_PCIE_IO_UNIT_PAGE1 /**** Defines for the ControlFlags field ****/ #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_MASK (0xE0000000) +#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_SHIFT (29) #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_NONE (0x00000000) #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_DEASSERT (0x20000000) #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_ASSERT (0x40000000) #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_BACKPLANE_ERROR (0x60000000) #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_MASK (0x1C000000) +#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_SHIFT (26) #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_NONE (0x00000000) -#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_DEASSERT (0x04000000) -#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_ASSERT (0x08000000) +#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_ENABLE (0x04000000) +#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_DISABLE (0x08000000) #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_BACKPLANE_ERROR (0x0C000000) #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PARTIAL_CAPACITY_ENABLE (0x00000100) #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_OVERRIDE_DISABLE (0x00000080) @@ -3231,6 +3497,7 @@ typedef struct _MPI3_PCIE_IO_UNIT_PAGE1 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRIS_ENABLED (0x00000010) #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRNS_ENABLED (0x00000020) #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MASK (0x0000000F) +#define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_SHIFT (0) #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_USE_BACKPLANE (0x00000000) #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_2_5 (0x00000002) #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_5_0 (0x00000003) @@ -3362,12 +3629,14 @@ typedef struct _MPI3_PCIE_SWITCH_PAGE1 /**** Defines for the PageVersion field ****/ #define MPI3_PCIESWITCH1_PAGEVERSION (0x00) -/**** Defines for the FLAGS field ****/ +/**** Defines for the Flags field ****/ #define MPI3_PCIESWITCH1_FLAGS_ASPMSTATE_MASK (0x0C) #define MPI3_PCIESWITCH1_FLAGS_ASPMSTATE_SHIFT (2) + /*** use MPI3_PCIE_ASPM_ENABLE_ defines for ASPMState field values ***/ #define MPI3_PCIESWITCH1_FLAGS_ASPMSUPPORT_MASK (0x03) #define MPI3_PCIESWITCH1_FLAGS_ASPMSUPPORT_SHIFT (0) + /*** use MPI3_PCIE_ASPM_SUPPORT_ defines for ASPMSupport field values ***/ /**** Defines for the NegotiatedLinkRate field - use MPI3_PCIE_NEG_LINK_RATE_ defines ****/ @@ -3454,6 +3723,8 @@ typedef struct _MPI3_ENCLOSURE_PAGE0 U16 SEPDevHandle; /* 0x1A */ U8 ChassisSlot; /* 0x1C */ U8 Reserved1D[3]; /* 0x1D */ + U32 ReceptacleIDs; /* 0x20 */ + U32 Reserved24; /* 0x24 */ } MPI3_ENCLOSURE_PAGE0, MPI3_POINTER PTR_MPI3_ENCLOSURE_PAGE0, Mpi3EnclosurePage0_t, MPI3_POINTER pMpi3EnclosurePage0_t; @@ -3462,19 +3733,23 @@ typedef struct _MPI3_ENCLOSURE_PAGE0 /**** Defines for the Flags field ****/ #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_MASK (0xC000) +#define MPI3_ENCLS0_FLAGS_ENCL_TYPE_SHIFT (0xC000) #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_VIRTUAL (0x0000) #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_SAS (0x4000) #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_PCIE (0x8000) #define MPI3_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020) #define MPI3_ENCLS0_FLAGS_ENCL_DEV_PRESENT_MASK (0x0010) +#define MPI3_ENCLS0_FLAGS_ENCL_DEV_PRESENT_SHIFT (4) #define MPI3_ENCLS0_FLAGS_ENCL_DEV_NOT_FOUND (0x0000) #define MPI3_ENCLS0_FLAGS_ENCL_DEV_PRESENT (0x0010) #define MPI3_ENCLS0_FLAGS_MNG_MASK (0x000F) +#define MPI3_ENCLS0_FLAGS_MNG_SHIFT (0) #define MPI3_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) #define MPI3_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) #define MPI3_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0002) -/**** Defines for the PhysicalPort field - use MPI3_DEVICE0_PHYPORT_ defines ****/ +/**** Defines for the ReceptacleIDs field ****/ +#define MPI3_ENCLS0_RECEPTACLEIDS_NOT_REPORTED (0x00000000) /***************************************************************************** * Device Configuration Pages * @@ -3550,6 +3825,7 @@ typedef struct _MPI3_DEVICE0_PCIE_FORMAT /**** Defines for DeviceInfo bitfield ****/ #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_MASK (0x0007) +#define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_SHIFT (0) #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NO_DEVICE (0x0000) #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NVME_DEVICE (0x0001) #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_SWITCH_DEVICE (0x0002) @@ -3577,11 +3853,13 @@ typedef struct _MPI3_DEVICE0_PCIE_FORMAT #define MPI3_DEVICE0_PCIE_CAP_ASPM_SHIFT (6) /*** use MPI3_PCIE_ASPM_SUPPORT_ defines for ASPM field values ***/ -/**** Defines for the RecoverMethod field ****/ +/**** Defines for the RecoveryInfo field ****/ #define MPI3_DEVICE0_PCIE_RECOVER_METHOD_MASK (0xE0) +#define MPI3_DEVICE0_PCIE_RECOVER_METHOD_SHIFT (5) #define MPI3_DEVICE0_PCIE_RECOVER_METHOD_NS_MGMT (0x00) #define MPI3_DEVICE0_PCIE_RECOVER_METHOD_FORMAT (0x20) #define MPI3_DEVICE0_PCIE_RECOVER_REASON_MASK (0x1F) +#define MPI3_DEVICE0_PCIE_RECOVER_REASON_SHIFT (0) #define MPI3_DEVICE0_PCIE_RECOVER_REASON_NO_NS (0x00) #define MPI3_DEVICE0_PCIE_RECOVER_REASON_NO_NSID_1 (0x01) #define MPI3_DEVICE0_PCIE_RECOVER_REASON_TOO_MANY_NS (0x02) @@ -3628,6 +3906,11 @@ typedef struct _MPI3_DEVICE0_VD_FORMAT /**** Defines for the Flags field ****/ #define MPI3_DEVICE0_VD_FLAGS_IO_THROTTLE_GROUP_QD_MASK (0xF000) #define MPI3_DEVICE0_VD_FLAGS_IO_THROTTLE_GROUP_QD_SHIFT (12) +#define MPI3_DEVICE0_VD_FLAGS_OSEXPOSURE_MASK (0x0003) +#define MPI3_DEVICE0_VD_FLAGS_OSEXPOSURE_SHIFT (0) +#define MPI3_DEVICE0_VD_FLAGS_OSEXPOSURE_HDD (0x0000) +#define MPI3_DEVICE0_VD_FLAGS_OSEXPOSURE_SSD (0x0001) +#define MPI3_DEVICE0_VD_FLAGS_OSEXPOSURE_NO_GUIDANCE (0x0002) typedef union _MPI3_DEVICE0_DEV_SPEC_FORMAT { @@ -3705,6 +3988,7 @@ typedef struct _MPI3_DEVICE_PAGE0 #define MPI3_DEVICE0_ASTATUS_SIF_UDMA_SN (0x27) #define MPI3_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x28) #define MPI3_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x29) +#define MPI3_DEVICE0_ASTATUS_SIF_DEVICE_FAULT (0x2A) #define MPI3_DEVICE0_ASTATUS_SIF_MAX (0x2F) /* PCIe Access Status Codes */ #define MPI3_DEVICE0_ASTATUS_PCIE_UNKNOWN (0x30) @@ -3740,6 +4024,7 @@ typedef struct _MPI3_DEVICE_PAGE0 /**** Defines for the Flags field ****/ #define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_MASK (0xE000) +#define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_SHIFT (13) #define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_NO_LIMIT (0x0000) #define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_256_LB (0x2000) #define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_2048_LB (0x4000) @@ -3773,7 +4058,8 @@ typedef struct _MPI3_DEVICE1_PCIE_FORMAT U16 DeviceID; /* 0x02 */ U16 SubsystemVendorID; /* 0x04 */ U16 SubsystemID; /* 0x06 */ - U32 Reserved08; /* 0x08 */ + U16 ReadyTimeout; /* 0x08 */ + U16 Reserved0A; /* 0x0A */ U8 RevisionID; /* 0x0C */ U8 Reserved0D; /* 0x0D */ U16 PCIParameters; /* 0x0E */ diff --git a/sys/dev/mpi3mr/mpi/mpi30_image.h b/sys/dev/mpi3mr/mpi/mpi30_image.h index 7b953cb3b1a6..73451d80fe58 100644 --- a/sys/dev/mpi3mr/mpi/mpi30_image.h +++ b/sys/dev/mpi3mr/mpi/mpi30_image.h @@ -1,7 +1,7 @@ /* - * SPDX-License-Identifier: BSD-2-Clause + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * - * Copyright (c) 2016-2023, Broadcom Inc. All rights reserved. + * Copyright (c) 2016-2025, Broadcom Inc. All rights reserved. * Support: <fbsd-storage-driver.pdl@broadcom.com> * * Redistribution and use in source and binary forms, with or without @@ -119,13 +119,23 @@ typedef struct _MPI3_COMPONENT_IMAGE_HEADER #define MPI3_IMAGE_HEADER_SIGNATURE1_RMC (0x20434D52) /* string "RMC " */ #define MPI3_IMAGE_HEADER_SIGNATURE1_SMM (0x204D4D53) /* string "SMM " */ #define MPI3_IMAGE_HEADER_SIGNATURE1_PSW (0x20575350) /* string "PSW " */ - +#define MPI3_IMAGE_HEADER_SIGNATURE1_CSW (0x20575343) /* string "CSW " */ /**** Definitions for Signature2 field ****/ #define MPI3_IMAGE_HEADER_SIGNATURE2_VALUE (0x50584546) /**** Definitions for Flags field ****/ +#define MPI3_IMAGE_HEADER_FLAGS_SIGNED_UEFI_MASK (0x00000300) +#define MPI3_IMAGE_HEADER_FLAGS_SIGNED_UEFI_SHIFT (8) +#define MPI3_IMAGE_HEADER_FLAGS_SIGNED_UEFI_UNSPECIFIED (0x00000000) +#define MPI3_IMAGE_HEADER_FLAGS_SIGNED_UEFI_NOT_SIGNED (0x00000100) +#define MPI3_IMAGE_HEADER_FLAGS_SIGNED_UEFI_MICROSOFT_SIGNED (0x00000200) +#define MPI3_IMAGE_HEADER_FLAGS_CERT_CHAIN_FORMAT_MASK (0x000000C0) +#define MPI3_IMAGE_HEADER_FLAGS_CERT_CHAIN_FORMAT_SHIFT (6) +#define MPI3_IMAGE_HEADER_FLAGS_CERT_CHAIN_FORMAT_DEVICE_CERT (0x00000000) +#define MPI3_IMAGE_HEADER_FLAGS_CERT_CHAIN_FORMAT_ALIAS_CERT (0x00000040) #define MPI3_IMAGE_HEADER_FLAGS_DEVICE_KEY_BASIS_MASK (0x00000030) +#define MPI3_IMAGE_HEADER_FLAGS_DEVICE_KEY_BASIS_SHIFT (4) #define MPI3_IMAGE_HEADER_FLAGS_DEVICE_KEY_BASIS_CDI (0x00000000) #define MPI3_IMAGE_HEADER_FLAGS_DEVICE_KEY_BASIS_DI (0x00000010) #define MPI3_IMAGE_HEADER_FLAGS_SIGNED_NVDATA (0x00000008) @@ -216,12 +226,14 @@ typedef struct _MPI3_CI_MANIFEST_MPI /* defines for the ReleaseLevel field */ #define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_DEV (0x00) +#define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_PRE_PRODUCTION (0x08) #define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_PREALPHA (0x10) #define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_ALPHA (0x20) #define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_BETA (0x30) #define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_RC (0x40) #define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_GCA (0x50) #define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_POINT (0x60) +#define MPI3_CI_MANIFEST_MPI_RELEASE_LEVEL_DIAG (0xF0) /* defines for the Flags field */ #define MPI3_CI_MANIFEST_MPI_FLAGS_DIAG_AUTHORIZATION (0x01) @@ -314,9 +326,9 @@ typedef struct _MPI3_SUPPORTED_DEVICES_DATA } MPI3_SUPPORTED_DEVICES_DATA, MPI3_POINTER PTR_MPI3_SUPPORTED_DEVICES_DATA, Mpi3SupportedDevicesData_t, MPI3_POINTER pMpi3SupportedDevicesData_t; -#ifndef MPI3_ENCRYPTED_HASH_MAX -#define MPI3_ENCRYPTED_HASH_MAX (1) -#endif /* MPI3_ENCRYPTED_HASH_MAX */ +#ifndef MPI3_PUBLIC_KEY_MAX +#define MPI3_PUBLIC_KEY_MAX (1) +#endif /* MPI3_PUBLIC_KEY_MAX */ /* Encrypted Hash Entry Format */ typedef struct _MPI3_ENCRYPTED_HASH_ENTRY @@ -324,24 +336,30 @@ typedef struct _MPI3_ENCRYPTED_HASH_ENTRY U8 HashImageType; /* 0x00 */ U8 HashAlgorithm; /* 0x01 */ U8 EncryptionAlgorithm; /* 0x02 */ - U8 Reserved03; /* 0x03 */ - U32 Reserved04; /* 0x04 */ - U32 EncryptedHash[MPI3_ENCRYPTED_HASH_MAX]; /* 0x08 */ /* variable length */ + U8 Flags; /* 0x03 */ + U16 PublicKeySize; /* 0x04 */ + U16 SignatureSize; /* 0x06 */ + U32 PublicKey[MPI3_PUBLIC_KEY_MAX]; /* 0x08 */ /* variable length */ + /* Signature - offset of this field must be calculated */ /* variable length */ } MPI3_ENCRYPTED_HASH_ENTRY, MPI3_POINTER PTR_MPI3_ENCRYPTED_HASH_ENTRY, Mpi3EncryptedHashEntry_t, MPI3_POINTER pMpi3EncryptedHashEntry_t; /* defines for the HashImageType field */ -#define MPI3_HASH_IMAGE_TYPE_KEY_WITH_SIGNATURE (0x03) +#define MPI3_HASH_IMAGE_TYPE_KEY_WITH_HASH (0x03) +#define MPI3_HASH_IMAGE_TYPE_KEY_WITH_HASH_1_OF_2 (0x04) +#define MPI3_HASH_IMAGE_TYPE_KEY_WITH_HASH_2_OF_2 (0x05) /* defines for the HashAlgorithm field */ #define MPI3_HASH_ALGORITHM_VERSION_MASK (0xE0) +#define MPI3_HASH_ALGORITHM_VERSION_SHIFT (5) #define MPI3_HASH_ALGORITHM_VERSION_NONE (0x00) #define MPI3_HASH_ALGORITHM_VERSION_SHA1 (0x20) /* Obsolete */ #define MPI3_HASH_ALGORITHM_VERSION_SHA2 (0x40) #define MPI3_HASH_ALGORITHM_VERSION_SHA3 (0x60) #define MPI3_HASH_ALGORITHM_SIZE_MASK (0x1F) +#define MPI3_HASH_ALGORITHM_SIZE_SHIFT (0) #define MPI3_HASH_ALGORITHM_SIZE_UNUSED (0x00) #define MPI3_HASH_ALGORITHM_SIZE_SHA256 (0x01) #define MPI3_HASH_ALGORITHM_SIZE_SHA512 (0x02) @@ -358,24 +376,15 @@ typedef struct _MPI3_ENCRYPTED_HASH_ENTRY #define MPI3_ENCRYPTION_ALGORITHM_ECDSA_P256 (0x07) /* NIST secp256r1 curve */ #define MPI3_ENCRYPTION_ALGORITHM_ECDSA_P384 (0x08) /* NIST secp384r1 curve */ #define MPI3_ENCRYPTION_ALGORITHM_ECDSA_P521 (0x09) /* NIST secp521r1 curve */ +#define MPI3_ENCRYPTION_ALGORITHM_LMS_HSS (0x0A) /* Leighton-Micali Signature (LMS) */ + /* Hierarchical Signature System (HSS) */ +#define MPI3_ENCRYPTION_ALGORITHM_ML_DSA_87 (0x0B) /* Module-Lattice-Based Sig Algo - Category 5 */ +#define MPI3_ENCRYPTION_ALGORITHM_ML_DSA_65 (0x0C) /* Module-Lattice-Based Sig Algo - Category 3 */ +#define MPI3_ENCRYPTION_ALGORITHM_ML_DSA_44 (0x0D) /* Module-Lattice-Based Sig Algo - Category 2 */ - -#ifndef MPI3_PUBLIC_KEY_MAX -#define MPI3_PUBLIC_KEY_MAX (1) -#endif /* MPI3_PUBLIC_KEY_MAX */ - -/* Encrypted Key with Hash Entry Format */ -typedef struct _MPI3_ENCRYPTED_KEY_WITH_HASH_ENTRY -{ - U8 HashImageType; /* 0x00 */ - U8 HashAlgorithm; /* 0x01 */ - U8 EncryptionAlgorithm; /* 0x02 */ - U8 Reserved03; /* 0x03 */ - U32 Reserved04; /* 0x04 */ - U32 PublicKey[MPI3_PUBLIC_KEY_MAX]; /* 0x08 */ /* variable length */ - /* EncryptedHash - offset of this field must be calculated */ /* variable length */ -} MPI3_ENCRYPTED_KEY_WITH_HASH_ENTRY, MPI3_POINTER PTR_MPI3_ENCRYPTED_KEY_WITH_HASH_ENTRY, - Mpi3EncryptedKeyWithHashEntry_t, MPI3_POINTER pMpi3EncryptedKeyWithHashEntry_t; +/* defines for the Flags field */ +#define MPI3_ENCRYPTED_HASH_ENTRY_FLAGS_PAIRED_KEY_MASK (0x0F) +#define MPI3_ENCRYPTED_HASH_ENTRY_FLAGS_PAIRED_KEY_SHIFT (0) #ifndef MPI3_ENCRYPTED_HASH_ENTRY_MAX #define MPI3_ENCRYPTED_HASH_ENTRY_MAX (1) diff --git a/sys/dev/mpi3mr/mpi/mpi30_init.h b/sys/dev/mpi3mr/mpi/mpi30_init.h index c0ba14909ac1..c24725972162 100644 --- a/sys/dev/mpi3mr/mpi/mpi30_init.h +++ b/sys/dev/mpi3mr/mpi/mpi30_init.h @@ -1,7 +1,7 @@ /* - * SPDX-License-Identifier: BSD-2-Clause + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * - * Copyright (c) 2016-2023, Broadcom Inc. All rights reserved. + * Copyright (c) 2016-2025, Broadcom Inc. All rights reserved. * Support: <fbsd-storage-driver.pdl@broadcom.com> * * Redistribution and use in source and binary forms, with or without @@ -78,7 +78,7 @@ typedef struct _MPI3_SCSI_IO_REQUEST U16 ChangeCount; /* 0x08 */ U16 DevHandle; /* 0x0A */ U32 Flags; /* 0x0C */ - U32 SkipCount; /* 0x10 */ + U32 IOCUseOnly10; /* 0x10 */ U32 DataLength; /* 0x14 */ U8 LUN[8]; /* 0x18 */ MPI3_SCSI_IO_CDB_UNION CDB; /* 0x20 */ @@ -91,11 +91,16 @@ typedef struct _MPI3_SCSI_IO_REQUEST #define MPI3_SCSIIO_MSGFLAGS_DIVERT_TO_FIRMWARE (0x40) /**** Defines for the Flags field ****/ -#define MPI3_SCSIIO_FLAGS_LARGE_CDB (0x60000000) +#define MPI3_SCSIIO_FLAGS_LARGE_CDB_MASK (0x60000000) +#define MPI3_SCSIIO_FLAGS_LARGE_CDB_SHIFT (29) #define MPI3_SCSIIO_FLAGS_CDB_16_OR_LESS (0x00000000) #define MPI3_SCSIIO_FLAGS_CDB_GREATER_THAN_16 (0x20000000) #define MPI3_SCSIIO_FLAGS_CDB_IN_SEPARATE_BUFFER (0x40000000) +#define MPI3_SCSIIO_FLAGS_CDB_PRODUCT_SPECIFIC (0x60000000) +#define MPI3_SCSIIO_FLAGS_IOC_USE_ONLY_27_MASK (0x18000000) +#define MPI3_SCSIIO_FLAGS_IOC_USE_ONLY_27_SHIFT (27) #define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_MASK (0x07000000) +#define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_SHIFT (24) #define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_SIMPLEQ (0x00000000) #define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_HEADOFQ (0x01000000) #define MPI3_SCSIIO_FLAGS_TASKATTRIBUTE_ORDEREDQ (0x02000000) @@ -103,12 +108,15 @@ typedef struct _MPI3_SCSI_IO_REQUEST #define MPI3_SCSIIO_FLAGS_CMDPRI_MASK (0x00F00000) #define MPI3_SCSIIO_FLAGS_CMDPRI_SHIFT (20) #define MPI3_SCSIIO_FLAGS_DATADIRECTION_MASK (0x000C0000) +#define MPI3_SCSIIO_FLAGS_DATADIRECTION_SHIFT (18) #define MPI3_SCSIIO_FLAGS_DATADIRECTION_NO_DATA_TRANSFER (0x00000000) #define MPI3_SCSIIO_FLAGS_DATADIRECTION_WRITE (0x00040000) #define MPI3_SCSIIO_FLAGS_DATADIRECTION_READ (0x00080000) #define MPI3_SCSIIO_FLAGS_DMAOPERATION_MASK (0x00030000) +#define MPI3_SCSIIO_FLAGS_DMAOPERATION_SHIFT (16) #define MPI3_SCSIIO_FLAGS_DMAOPERATION_HOST_PI (0x00010000) #define MPI3_SCSIIO_FLAGS_DIVERT_REASON_MASK (0x000000F0) +#define MPI3_SCSIIO_FLAGS_DIVERT_REASON_SHIFT (4) #define MPI3_SCSIIO_FLAGS_DIVERT_REASON_IO_THROTTLING (0x00000010) #define MPI3_SCSIIO_FLAGS_DIVERT_REASON_WRITE_SAME_TOO_LARGE (0x00000020) #define MPI3_SCSIIO_FLAGS_DIVERT_REASON_PROD_SPECIFIC (0x00000080) @@ -166,6 +174,7 @@ typedef struct _MPI3_SCSI_IO_REPLY /**** Defines for the SCSIState field ****/ #define MPI3_SCSI_STATE_SENSE_MASK (0x03) +#define MPI3_SCSI_STATE_SENSE_SHIFT (0) #define MPI3_SCSI_STATE_SENSE_VALID (0x00) #define MPI3_SCSI_STATE_SENSE_FAILED (0x01) #define MPI3_SCSI_STATE_SENSE_BUFF_Q_EMPTY (0x02) diff --git a/sys/dev/mpi3mr/mpi/mpi30_ioc.h b/sys/dev/mpi3mr/mpi/mpi30_ioc.h index 77f6be5b2694..dc7b478536c3 100644 --- a/sys/dev/mpi3mr/mpi/mpi30_ioc.h +++ b/sys/dev/mpi3mr/mpi/mpi30_ioc.h @@ -1,7 +1,7 @@ /* - * SPDX-License-Identifier: BSD-2-Clause + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * - * Copyright (c) 2016-2023, Broadcom Inc. All rights reserved. + * Copyright (c) 2016-2025, Broadcom Inc. All rights reserved. * Support: <fbsd-storage-driver.pdl@broadcom.com> * * Redistribution and use in source and binary forms, with or without @@ -76,17 +76,20 @@ typedef struct _MPI3_IOC_INIT_REQUEST Mpi3IOCInitRequest_t, MPI3_POINTER pMpi3IOCInitRequest_t; /**** Defines for the MsgFlags field ****/ -#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_MASK (0x03) -#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_NOT_USED (0x00) -#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_SEPARATED (0x01) -#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_INLINE (0x02) -#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_BOTH (0x03) +#define MPI3_IOCINIT_MSGFLAGS_WRITESAMEDIVERT_SUPPORTED (0x08) +#define MPI3_IOCINIT_MSGFLAGS_SCSIIOSTATUSREPLY_SUPPORTED (0x04) +#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_MASK (0x03) +#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_SHIFT (0) +#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_NOT_USED (0x00) +#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_SEPARATED (0x01) +#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_INLINE (0x02) +#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_BOTH (0x03) /**** Defines for the WhoInit field ****/ -#define MPI3_WHOINIT_NOT_INITIALIZED (0x00) -#define MPI3_WHOINIT_ROM_BIOS (0x02) -#define MPI3_WHOINIT_HOST_DRIVER (0x03) -#define MPI3_WHOINIT_MANUFACTURER (0x04) +#define MPI3_WHOINIT_NOT_INITIALIZED (0x00) +#define MPI3_WHOINIT_ROM_BIOS (0x02) +#define MPI3_WHOINIT_HOST_DRIVER (0x03) +#define MPI3_WHOINIT_MANUFACTURER (0x04) /**** Defines for the DriverInformationAddress field */ typedef struct _MPI3_DRIVER_INFO_LAYOUT @@ -102,6 +105,13 @@ typedef struct _MPI3_DRIVER_INFO_LAYOUT } MPI3_DRIVER_INFO_LAYOUT, MPI3_POINTER PTR_MPI3_DRIVER_INFO_LAYOUT, Mpi3DriverInfoLayout_t, MPI3_POINTER pMpi3DriverInfoLayout_t; +#define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_MASK (0x00000003) +#define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_SHIFT (0) +#define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_NO_GUIDANCE (0x00000000) +#define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_NO_SPECIAL (0x00000001) +#define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_REPORT_AS_HDD (0x00000002) +#define MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_REPORT_AS_SSD (0x00000003) + /***************************************************************************** * IOCFacts Request Message * ****************************************************************************/ @@ -173,23 +183,27 @@ typedef struct _MPI3_IOC_FACTS_DATA U16 MaxIOThrottleGroup; /* 0x62 */ U16 IOThrottleLow; /* 0x64 */ U16 IOThrottleHigh; /* 0x66 */ + U32 DiagFdlSize; /* 0x68 */ + U32 DiagTtySize; /* 0x6C */ } MPI3_IOC_FACTS_DATA, MPI3_POINTER PTR_MPI3_IOC_FACTS_DATA, Mpi3IOCFactsData_t, MPI3_POINTER pMpi3IOCFactsData_t; /**** Defines for the IOCCapabilities field ****/ #define MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_MASK (0x80000000) +#define MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_SHIFT (31) #define MPI3_IOCFACTS_CAPABILITY_SUPERVISOR_IOC (0x00000000) #define MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_IOC (0x80000000) #define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_MASK (0x00000600) +#define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_SHIFT (9) #define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_FIXED_THRESHOLD (0x00000000) #define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_OUTSTANDING_IO (0x00000200) -#define MPI3_IOCFACTS_CAPABILITY_COMPLETE_RESET_CAPABLE (0x00000100) -#define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_TRACE_ENABLED (0x00000080) -#define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_FW_ENABLED (0x00000040) -#define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_DRIVER_ENABLED (0x00000020) -#define MPI3_IOCFACTS_CAPABILITY_ADVANCED_HOST_PD_ENABLED (0x00000010) -#define MPI3_IOCFACTS_CAPABILITY_RAID_CAPABLE (0x00000008) -#define MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED (0x00000002) +#define MPI3_IOCFACTS_CAPABILITY_COMPLETE_RESET_SUPPORTED (0x00000100) +#define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_TRACE_SUPPORTED (0x00000080) +#define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_FW_SUPPORTED (0x00000040) +#define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_DRIVER_SUPPORTED (0x00000020) +#define MPI3_IOCFACTS_CAPABILITY_ADVANCED_HOST_PD_SUPPORTED (0x00000010) +#define MPI3_IOCFACTS_CAPABILITY_RAID_SUPPORTED (0x00000008) +#define MPI3_IOCFACTS_CAPABILITY_MULTIPATH_SUPPORTED (0x00000002) #define MPI3_IOCFACTS_CAPABILITY_COALESCE_CTRL_SUPPORTED (0x00000001) /**** WhoInit values are defined under IOCInit Request Message definition ****/ @@ -207,6 +221,7 @@ typedef struct _MPI3_IOC_FACTS_DATA #define MPI3_IOCFACTS_EXCEPT_SAS_DISABLED (0x1000) #define MPI3_IOCFACTS_EXCEPT_SAFE_MODE (0x0800) #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_MASK (0x0700) +#define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_SHIFT (8) #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_NONE (0x0000) #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_LOCAL_VIA_MGMT (0x0100) #define MPI3_IOCFACTS_EXCEPT_SECURITY_KEY_EXT_VIA_MGMT (0x0200) @@ -219,7 +234,10 @@ typedef struct _MPI3_IOC_FACTS_DATA #define MPI3_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0020) #define MPI3_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0010) #define MPI3_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0008) +#define MPI3_IOCFACTS_EXCEPT_BLOCKING_BOOT_EVENT (0x0004) +#define MPI3_IOCFACTS_EXCEPT_SECURITY_SELFTEST_FAILURE (0x0002) #define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x0001) +#define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_SHIFT (0) #define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_PRIMARY (0x0000) #define MPI3_IOCFACTS_EXCEPT_BOOTSTAT_SECONDARY (0x0001) @@ -234,22 +252,31 @@ typedef struct _MPI3_IOC_FACTS_DATA #define MPI3_IOCFACTS_MAX_DATA_LENGTH_NOT_REPORTED (0x0000) /**** Defines for the Flags field ****/ -#define MPI3_IOCFACTS_FLAGS_SIGNED_NVDATA_REQUIRED (0x00010000) -#define MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK (0x0000FF00) -#define MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT (8) -#define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_MASK (0x00000030) -#define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_NOT_STARTED (0x00000000) -#define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_IN_PROGRESS (0x00000010) -#define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_COMPLETE (0x00000020) -#define MPI3_IOCFACTS_FLAGS_PERSONALITY_MASK (0x0000000F) -#define MPI3_IOCFACTS_FLAGS_PERSONALITY_EHBA (0x00000000) -#define MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR (0x00000002) +#define MPI3_IOCFACTS_FLAGS_SIGNED_NVDATA_REQUIRED (0x00010000) +#define MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK (0x0000FF00) +#define MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT (8) +#define MPI3_IOCFACTS_FLAGS_MAX_REQ_PER_REPLY_QUEUE_LIMIT (0x00000040) +#define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_MASK (0x00000030) +#define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_SHIFT (4) +#define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_NOT_STARTED (0x00000000) +#define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_IN_PROGRESS (0x00000010) +#define MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_COMPLETE (0x00000020) +#define MPI3_IOCFACTS_FLAGS_PERSONALITY_MASK (0x0000000F) +#define MPI3_IOCFACTS_FLAGS_PERSONALITY_SHIFT (0) +#define MPI3_IOCFACTS_FLAGS_PERSONALITY_EHBA (0x00000000) +#define MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR (0x00000002) /**** Defines for the IOThrottleDataLength field ****/ -#define MPI3_IOCFACTS_IO_THROTTLE_DATA_LENGTH_NOT_REQUIRED (0x0000) +#define MPI3_IOCFACTS_IO_THROTTLE_DATA_LENGTH_NOT_REQUIRED (0x0000) -/**** Defines for the IOThrottleDataLength field ****/ -#define MPI3_IOCFACTS_MAX_IO_THROTTLE_GROUP_NOT_REQUIRED (0x0000) +/**** Defines for the MaxIOThrottleGroup field ****/ +#define MPI3_IOCFACTS_MAX_IO_THROTTLE_GROUP_NOT_REQUIRED (0x0000) + +/**** Defines for the DiagFdlSize field ****/ +#define MPI3_IOCFACTS_DIAGFDLSIZE_NOT_SUPPORTED (0x00000000) + +/**** Defines for the DiagTtySize field ****/ +#define MPI3_IOCFACTS_DIAGTTYSIZE_NOT_SUPPORTED (0x00000000) /***************************************************************************** * Management Passthrough Request Message * @@ -295,6 +322,7 @@ typedef struct _MPI3_CREATE_REQUEST_QUEUE_REQUEST /**** Defines for the Flags field ****/ #define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_MASK (0x80) +#define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SHIFT (7) #define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED (0x80) #define MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_CONTIGUOUS (0x00) @@ -343,10 +371,12 @@ typedef struct _MPI3_CREATE_REPLY_QUEUE_REQUEST /**** Defines for the Flags field ****/ #define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_MASK (0x80) +#define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_SHIFT (7) #define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_SEGMENTED (0x80) #define MPI3_CREATE_REPLY_QUEUE_FLAGS_SEGMENTED_CONTIGUOUS (0x00) #define MPI3_CREATE_REPLY_QUEUE_FLAGS_COALESCE_DISABLE (0x02) #define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_MASK (0x01) +#define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_SHIFT (0) #define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_DISABLE (0x00) #define MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE (0x01) @@ -440,9 +470,9 @@ typedef struct _MPI3_EVENT_NOTIFICATION_REQUEST } MPI3_EVENT_NOTIFICATION_REQUEST, MPI3_POINTER PTR_MPI3_EVENT_NOTIFICATION_REQUEST, Mpi3EventNotificationRequest_t, MPI3_POINTER pMpi3EventNotificationRequest_t; -/**** Defines for the SASBroadcastPrimitiveMasks field - use MPI3_EVENT_PRIMITIVE_ values ****/ +/**** Defines for the SASBroadcastPrimitiveMasks field - use MPI3_EVENT_BROADCAST_PRIMITIVE_ values ****/ -/**** Defines for the SASNotifyPrimitiveMasks field - use MPI3_EVENT_NOTIFY_ values ****/ +/**** Defines for the SASNotifyPrimitiveMasks field - use MPI3_EVENT_NOTIFY_PRIMITIVE_ values ****/ /**** Defines for the EventMasks field - use MPI3_EVENT_ values ****/ @@ -470,9 +500,11 @@ typedef struct _MPI3_EVENT_NOTIFICATION_REPLY /**** Defines for the MsgFlags field ****/ #define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_MASK (0x01) +#define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_SHIFT (0) #define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_REQUIRED (0x01) #define MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_NOT_REQUIRED (0x00) #define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_MASK (0x02) +#define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_SHIFT (1) #define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_ORIGINAL (0x00) #define MPI3_EVENT_NOTIFY_MSGFLAGS_EVENT_ORIGINALITY_REPLAY (0x02) @@ -716,7 +748,7 @@ typedef struct _MPI3_EVENT_SAS_TOPO_PHY_ENTRY { U16 AttachedDevHandle; /* 0x00 */ U8 LinkRate; /* 0x02 */ - U8 Status; /* 0x03 */ + U8 PhyStatus; /* 0x03 */ } MPI3_EVENT_SAS_TOPO_PHY_ENTRY, MPI3_POINTER PTR_MPI3_EVENT_SAS_TOPO_PHY_ENTRY, Mpi3EventSasTopoPhyEntry_t, MPI3_POINTER pMpi3EventSasTopoPhyEntry_t; @@ -743,6 +775,7 @@ typedef struct _MPI3_EVENT_SAS_TOPO_PHY_ENTRY #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_NO_EXIST (0x40) #define MPI3_EVENT_SAS_TOPO_PHY_STATUS_VACANT (0x80) #define MPI3_EVENT_SAS_TOPO_PHY_RC_MASK (0x0F) +#define MPI3_EVENT_SAS_TOPO_PHY_RC_SHIFT (0) #define MPI3_EVENT_SAS_TOPO_PHY_RC_TARG_NOT_RESPONDING (0x02) #define MPI3_EVENT_SAS_TOPO_PHY_RC_PHY_CHANGED (0x03) #define MPI3_EVENT_SAS_TOPO_PHY_RC_NO_CHANGE (0x04) @@ -873,6 +906,7 @@ typedef struct _MPI3_EVENT_PCIE_TOPO_PORT_ENTRY /**** Defines for the CurrentPortInfo and PreviousPortInfo field ****/ #define MPI3_EVENT_PCIE_TOPO_PI_LANES_MASK (0xF0) +#define MPI3_EVENT_PCIE_TOPO_PI_LANES_SHIFT (4) #define MPI3_EVENT_PCIE_TOPO_PI_LANES_UNKNOWN (0x00) #define MPI3_EVENT_PCIE_TOPO_PI_LANES_1 (0x10) #define MPI3_EVENT_PCIE_TOPO_PI_LANES_2 (0x20) @@ -881,6 +915,7 @@ typedef struct _MPI3_EVENT_PCIE_TOPO_PORT_ENTRY #define MPI3_EVENT_PCIE_TOPO_PI_LANES_16 (0x50) #define MPI3_EVENT_PCIE_TOPO_PI_RATE_MASK (0x0F) +#define MPI3_EVENT_PCIE_TOPO_PI_RATE_SHIFT (0) #define MPI3_EVENT_PCIE_TOPO_PI_RATE_UNKNOWN (0x00) #define MPI3_EVENT_PCIE_TOPO_PI_RATE_DISABLED (0x01) #define MPI3_EVENT_PCIE_TOPO_PI_RATE_2_5 (0x02) @@ -1369,6 +1404,7 @@ typedef struct _MPI3_PEL_REQ_ACTION_ACKNOWLEDGE /**** Definitions for the MsgFlags field ****/ #define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_MASK (0x03) +#define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_SHIFT (0) #define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_NO_GUIDANCE (0x00) #define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_CONTINUE_OP (0x01) #define MPI3_PELACKNOWLEDGE_MSGFLAGS_SAFE_MODE_EXIT_TRANSITION_TO_FAULT (0x02) @@ -1425,6 +1461,7 @@ typedef struct _MPI3_CI_DOWNLOAD_REQUEST #define MPI3_CI_DOWNLOAD_MSGFLAGS_FORCE_FMC_ENABLE (0x40) #define MPI3_CI_DOWNLOAD_MSGFLAGS_SIGNED_NVDATA (0x20) #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_MASK (0x03) +#define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_SHIFT (0) #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_FAST (0x00) #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_MEDIUM (0x01) #define MPI3_CI_DOWNLOAD_MSGFLAGS_WRITE_CACHE_FLUSH_SLOW (0x02) @@ -1460,6 +1497,7 @@ typedef struct _MPI3_CI_DOWNLOAD_REPLY #define MPI3_CI_DOWNLOAD_FLAGS_OFFLINE_ACTIVATION_REQUIRED (0x20) #define MPI3_CI_DOWNLOAD_FLAGS_KEY_UPDATE_PENDING (0x10) #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_MASK (0x0E) +#define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_SHIFT (1) #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_NOT_NEEDED (0x00) #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_AWAITING (0x02) #define MPI3_CI_DOWNLOAD_FLAGS_ACTIVATION_STATUS_ONLINE_PENDING (0x04) @@ -1490,9 +1528,11 @@ typedef struct _MPI3_CI_UPLOAD_REQUEST /**** Defines for the MsgFlags field ****/ #define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_MASK (0x01) +#define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_SHIFT (0) #define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_PRIMARY (0x00) #define MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_SECONDARY (0x01) #define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_MASK (0x02) +#define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_SHIFT (1) #define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_FLASH (0x00) #define MPI3_CI_UPLOAD_MSGFLAGS_FORMAT_EXECUTABLE (0x02) diff --git a/sys/dev/mpi3mr/mpi/mpi30_pci.h b/sys/dev/mpi3mr/mpi/mpi30_pci.h index f15dab2a5a9c..12d7000882cb 100644 --- a/sys/dev/mpi3mr/mpi/mpi30_pci.h +++ b/sys/dev/mpi3mr/mpi/mpi30_pci.h @@ -1,7 +1,7 @@ /* - * SPDX-License-Identifier: BSD-2-Clause + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * - * Copyright (c) 2016-2023, Broadcom Inc. All rights reserved. + * Copyright (c) 2016-2025, Broadcom Inc. All rights reserved. * Support: <fbsd-storage-driver.pdl@broadcom.com> * * Redistribution and use in source and binary forms, with or without @@ -69,9 +69,11 @@ typedef struct _MPI3_NVME_ENCAPSULATED_REQUEST /**** Defines for the Flags field ****/ #define MPI3_NVME_FLAGS_FORCE_ADMIN_ERR_REPLY_MASK (0x0002) +#define MPI3_NVME_FLAGS_FORCE_ADMIN_ERR_REPLY_SHIFT (1) #define MPI3_NVME_FLAGS_FORCE_ADMIN_ERR_REPLY_FAIL_ONLY (0x0000) #define MPI3_NVME_FLAGS_FORCE_ADMIN_ERR_REPLY_ALL (0x0002) #define MPI3_NVME_FLAGS_SUBMISSIONQ_MASK (0x0001) +#define MPI3_NVME_FLAGS_SUBMISSIONQ_SHIFT (0) #define MPI3_NVME_FLAGS_SUBMISSIONQ_IO (0x0000) #define MPI3_NVME_FLAGS_SUBMISSIONQ_ADMIN (0x0001) diff --git a/sys/dev/mpi3mr/mpi/mpi30_raid.h b/sys/dev/mpi3mr/mpi/mpi30_raid.h index fe2c4baffd3c..6fe557f843f3 100644 --- a/sys/dev/mpi3mr/mpi/mpi30_raid.h +++ b/sys/dev/mpi3mr/mpi/mpi30_raid.h @@ -1,7 +1,7 @@ /* - * SPDX-License-Identifier: BSD-2-Clause + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * - * Copyright (c) 2016-2023, Broadcom Inc. All rights reserved. + * Copyright (c) 2016-2025, Broadcom Inc. All rights reserved. * Support: <fbsd-storage-driver.pdl@broadcom.com> * * Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/mpi3mr/mpi/mpi30_sas.h b/sys/dev/mpi3mr/mpi/mpi30_sas.h index c28de07c9fdd..e50bcde0ade4 100644 --- a/sys/dev/mpi3mr/mpi/mpi30_sas.h +++ b/sys/dev/mpi3mr/mpi/mpi30_sas.h @@ -1,7 +1,7 @@ /* - * SPDX-License-Identifier: BSD-2-Clause + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * - * Copyright (c) 2016-2023, Broadcom Inc. All rights reserved. + * Copyright (c) 2016-2025, Broadcom Inc. All rights reserved. * Support: <fbsd-storage-driver.pdl@broadcom.com> * * Redistribution and use in source and binary forms, with or without @@ -52,6 +52,7 @@ #define MPI3_SAS_DEVICE_INFO_STP_INITIATOR (0x00000010) #define MPI3_SAS_DEVICE_INFO_SMP_INITIATOR (0x00000008) #define MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_MASK (0x00000007) +#define MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_SHIFT (0) #define MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_NO_DEVICE (0x00000000) #define MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_END_DEVICE (0x00000001) #define MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_EXPANDER (0x00000002) diff --git a/sys/dev/mpi3mr/mpi/mpi30_targ.h b/sys/dev/mpi3mr/mpi/mpi30_targ.h index d9aee48a6437..8ae654410165 100644 --- a/sys/dev/mpi3mr/mpi/mpi30_targ.h +++ b/sys/dev/mpi3mr/mpi/mpi30_targ.h @@ -1,7 +1,7 @@ /* - * SPDX-License-Identifier: BSD-2-Clause + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * - * Copyright (c) 2016-2023, Broadcom Inc. All rights reserved. + * Copyright (c) 2016-2025, Broadcom Inc. All rights reserved. * Support: <fbsd-storage-driver.pdl@broadcom.com> * * Redistribution and use in source and binary forms, with or without @@ -123,6 +123,7 @@ typedef struct _MPI3_TARGET_CMD_BUF_POST_BASE_REQUEST /**** Defines for the BufferPostFlags field ****/ #define MPI3_CMD_BUF_POST_BASE_FLAGS_DLAS_MASK (0x0C) +#define MPI3_CMD_BUF_POST_BASE_FLAGS_DLAS_SHIFT (2) #define MPI3_CMD_BUF_POST_BASE_FLAGS_DLAS_SYSTEM (0x00) #define MPI3_CMD_BUF_POST_BASE_FLAGS_DLAS_IOCUDP (0x04) #define MPI3_CMD_BUF_POST_BASE_FLAGS_DLAS_IOCCTL (0x08) @@ -191,7 +192,7 @@ typedef struct _MPI3_TARGET_ASSIST_REQUEST U16 QueueTag; /* 0x12 */ U16 IoIndex; /* 0x14 */ U16 InitiatorConnectionTag; /* 0x16 */ - U32 SkipCount; /* 0x18 */ + U32 IOCUseOnly18; /* 0x18 */ U32 DataLength; /* 0x1C */ U32 PortTransferLength; /* 0x20 */ U32 PrimaryReferenceTag; /* 0x24 */ @@ -206,12 +207,18 @@ typedef struct _MPI3_TARGET_ASSIST_REQUEST #define MPI3_TARGET_ASSIST_MSGFLAGS_METASGL_VALID (0x80) /**** Defines for the Flags field ****/ +#define MPI3_TARGET_ASSIST_FLAGS_IOC_USE_ONLY_23_MASK (0x00800000) +#define MPI3_TARGET_ASSIST_FLAGS_IOC_USE_ONLY_23_SHIFT (23) +#define MPI3_TARGET_ASSIST_FLAGS_IOC_USE_ONLY_22_MASK (0x00400000) +#define MPI3_TARGET_ASSIST_FLAGS_IOC_USE_ONLY_22_SHIFT (22) #define MPI3_TARGET_ASSIST_FLAGS_REPOST_CMD_BUFFER (0x00200000) #define MPI3_TARGET_ASSIST_FLAGS_AUTO_STATUS (0x00100000) #define MPI3_TARGET_ASSIST_FLAGS_DATADIRECTION_MASK (0x000C0000) +#define MPI3_TARGET_ASSIST_FLAGS_DATADIRECTION_SHIFT (18) #define MPI3_TARGET_ASSIST_FLAGS_DATADIRECTION_WRITE (0x00040000) #define MPI3_TARGET_ASSIST_FLAGS_DATADIRECTION_READ (0x00080000) #define MPI3_TARGET_ASSIST_FLAGS_DMAOPERATION_MASK (0x00030000) +#define MPI3_TARGET_ASSIST_FLAGS_DMAOPERATION_SHIFT (16) #define MPI3_TARGET_ASSIST_FLAGS_DMAOPERATION_HOST_PI (0x00010000) /**** Defines for the SGL field ****/ @@ -243,6 +250,8 @@ typedef struct _MPI3_TARGET_STATUS_SEND_REQUEST Mpi3TargetStatusSendRequest_t, MPI3_POINTER pMpi3TargetStatusSendRequest_t; /**** Defines for the Flags field ****/ +#define MPI3_TSS_FLAGS_IOC_USE_ONLY_6_MASK (0x0040) +#define MPI3_TSS_FLAGS_IOC_USE_ONLY_6_SHIFT (6) #define MPI3_TSS_FLAGS_REPOST_CMD_BUFFER (0x0020) #define MPI3_TSS_FLAGS_AUTO_SEND_GOOD_STATUS (0x0010) @@ -292,7 +301,7 @@ typedef struct _MPI3_TARGET_MODE_ABORT_REQUEST #define MPI3_TARGET_MODE_ABORT_ALL_CMD_BUFFERS (0x00) #define MPI3_TARGET_MODE_ABORT_EXACT_IO_REQUEST (0x01) #define MPI3_TARGET_MODE_ABORT_ALL_COMMANDS (0x02) - +#define MPI3_TARGET_MODE_ABORT_ALL_COMMANDS_DEVHANDLE (0x03) /***************************************************************************** * Target Mode Abort Reply Message * diff --git a/sys/dev/mpi3mr/mpi/mpi30_tool.h b/sys/dev/mpi3mr/mpi/mpi30_tool.h index 55fb53601863..7f43d5d45465 100644 --- a/sys/dev/mpi3mr/mpi/mpi30_tool.h +++ b/sys/dev/mpi3mr/mpi/mpi30_tool.h @@ -1,7 +1,7 @@ /* - * SPDX-License-Identifier: BSD-2-Clause + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * - * Copyright (c) 2016-2023, Broadcom Inc. All rights reserved. + * Copyright (c) 2016-2025, Broadcom Inc. All rights reserved. * Support: <fbsd-storage-driver.pdl@broadcom.com> * * Redistribution and use in source and binary forms, with or without @@ -106,9 +106,11 @@ typedef struct _MPI3_TOOL_ISTWI_READ_WRITE_REQUEST /**** Bitfield definitions for Flags field ****/ #define MPI3_TOOLBOX_ISTWI_FLAGS_AUTO_RESERVE_RELEASE (0x80) #define MPI3_TOOLBOX_ISTWI_FLAGS_ADDRESS_MODE_MASK (0x04) +#define MPI3_TOOLBOX_ISTWI_FLAGS_ADDRESS_MODE_SHIFT (2) #define MPI3_TOOLBOX_ISTWI_FLAGS_ADDRESS_MODE_DEVINDEX (0x00) #define MPI3_TOOLBOX_ISTWI_FLAGS_ADDRESS_MODE_DEVICE_FIELD (0x04) #define MPI3_TOOLBOX_ISTWI_FLAGS_PAGE_ADDRESS_MASK (0x03) +#define MPI3_TOOLBOX_ISTWI_FLAGS_PAGE_ADDRESS_SHIFT (0) /**** Definitions for the Action field ****/ #define MPI3_TOOLBOX_ISTWI_ACTION_RESERVE_BUS (0x00) @@ -366,6 +368,7 @@ typedef struct _MPI3_DIAG_BUFFER_POST_REQUEST #define MPI3_DIAG_BUFFER_TYPE_FW (0x02) #define MPI3_DIAG_BUFFER_TYPE_DRIVER (0x10) #define MPI3_DIAG_BUFFER_TYPE_FDL (0x20) +#define MPI3_DIAG_BUFFER_TYPE_TTY (0x30) #define MPI3_DIAG_BUFFER_MIN_PRODUCT_SPECIFIC (0xF0) #define MPI3_DIAG_BUFFER_MAX_PRODUCT_SPECIFIC (0xFF) @@ -388,11 +391,12 @@ typedef struct _MPI3_DRIVER_BUFFER_HEADER } MPI3_DRIVER_BUFFER_HEADER, MPI3_POINTER PTR_MPI3_DRIVER_BUFFER_HEADER, Mpi3DriverBufferHeader_t, MPI3_POINTER pMpi3DriverBufferHeader_t; -/**** Defines for the Type field ****/ +/**** Defines for the Signature field ****/ #define MPI3_DRIVER_DIAG_BUFFER_HEADER_SIGNATURE_CIRCULAR (0x43495243) /**** Defines for the Flags field ****/ #define MPI3_DRIVER_DIAG_BUFFER_HEADER_FLAGS_CIRCULAR_BUF_FORMAT_MASK (0x00000003) +#define MPI3_DRIVER_DIAG_BUFFER_HEADER_FLAGS_CIRCULAR_BUF_FORMAT_SHIFT (0) #define MPI3_DRIVER_DIAG_BUFFER_HEADER_FLAGS_CIRCULAR_BUF_FORMAT_ASCII (0x00000000) #define MPI3_DRIVER_DIAG_BUFFER_HEADER_FLAGS_CIRCULAR_BUF_FORMAT_RTTRACE (0x00000001) @@ -449,6 +453,7 @@ typedef struct _MPI3_DIAG_BUFFER_UPLOAD_REQUEST /**** Defined for the Flags field ****/ #define MPI3_DIAG_BUFFER_UPLOAD_FLAGS_FORMAT_MASK (0x01) +#define MPI3_DIAG_BUFFER_UPLOAD_FLAGS_FORMAT_SHIFT (0) #define MPI3_DIAG_BUFFER_UPLOAD_FLAGS_FORMAT_DECODED (0x00) #define MPI3_DIAG_BUFFER_UPLOAD_FLAGS_FORMAT_ENCODED (0x01) diff --git a/sys/dev/mpi3mr/mpi/mpi30_transport.h b/sys/dev/mpi3mr/mpi/mpi30_transport.h index 436496411309..d9ebbfa0b5d8 100644 --- a/sys/dev/mpi3mr/mpi/mpi30_transport.h +++ b/sys/dev/mpi3mr/mpi/mpi30_transport.h @@ -1,7 +1,7 @@ /* - * SPDX-License-Identifier: BSD-2-Clause + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * - * Copyright (c) 2016-2023, Broadcom Inc. All rights reserved. + * Copyright (c) 2016-2025, Broadcom Inc. All rights reserved. * Support: <fbsd-storage-driver.pdl@broadcom.com> * * Redistribution and use in source and binary forms, with or without @@ -37,10 +37,9 @@ * * Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD * - */ - -/* - * Version History + * + * + * Version History * --------------- * * Date Version Description @@ -72,8 +71,20 @@ * 09-02-22 03.00.27.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 27. * 10-20-22 03.00.27.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 27 - Interim Release 1. * 12-02-22 03.00.28.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 28. - * 02-24-22 03.00.29.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 29. + * 02-24-23 03.00.29.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 29. + * 05-19-23 03.00.30.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 30. + * 08-18-23 03.00.30.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 30 - Interim Release 1. + * 11-17-23 03.00.31.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 31 + * 02-16-24 03.00.32.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 32 + * 02-23-24 03.00.32.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 32 - Interim Release 1. + * 04-19-24 03.00.32.02 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 32 - Interim Release 2. + * 05-10-24 03.00.33.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 33 + * 06-14-24 03.00.33.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 33 - Interim Release 1. + * 07-26-24 03.00.34.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 34 + * 11-08-24 03.00.35.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 35 + * 02-14-25 03.00.36.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 36 */ + #ifndef MPI30_TRANSPORT_H #define MPI30_TRANSPORT_H 1 @@ -101,7 +112,7 @@ typedef union _MPI3_VERSION_UNION /****** Version constants for this revision ****/ #define MPI3_VERSION_MAJOR (3) #define MPI3_VERSION_MINOR (0) -#define MPI3_VERSION_UNIT (29) +#define MPI3_VERSION_UNIT (36) #define MPI3_VERSION_DEV (0) /****** DevHandle definitions *****/ @@ -176,6 +187,7 @@ typedef volatile struct _MPI3_SYSIF_REGISTERS #define MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ (0x000F0000) #define MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ_SHIFT (16) #define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_MASK (0x0000C000) +#define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_SHIFT (14) #define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NO (0x00000000) #define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL (0x00004000) #define MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN_SEND_REQ (0x00002000) @@ -196,6 +208,7 @@ typedef volatile struct _MPI3_SYSIF_REGISTERS /**** Defines for the AdminQueueNumEntries register ****/ #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_OFFSET (0x00000024) #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REQ_MASK (0x0FFF) +#define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REQ_SHIFT (0) #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REPLY_OFFSET (0x00000026) #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REPLY_MASK (0x0FFF0000) #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REPLY_SHIFT (16) @@ -211,6 +224,7 @@ typedef volatile struct _MPI3_SYSIF_REGISTERS /**** Defines for the CoalesceControl register ****/ #define MPI3_SYSIF_COALESCE_CONTROL_OFFSET (0x00000040) #define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_MASK (0xC0000000) +#define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_SHIFT (30) #define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_NO_CHANGE (0x00000000) #define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_DISABLE (0x40000000) #define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_ENABLE (0xC0000000) @@ -239,6 +253,7 @@ typedef volatile struct _MPI3_SYSIF_REGISTERS /**** Defines for the WriteSequence register *****/ #define MPI3_SYSIF_WRITE_SEQUENCE_OFFSET (0x00001C04) #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_MASK (0x0000000F) +#define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_SHIFT (0) #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_FLUSH (0x0) #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_1ST (0xF) #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND (0x4) @@ -250,6 +265,7 @@ typedef volatile struct _MPI3_SYSIF_REGISTERS /**** Defines for the HostDiagnostic register *****/ #define MPI3_SYSIF_HOST_DIAG_OFFSET (0x00001C08) #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_MASK (0x00000700) +#define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SHIFT (8) #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_NO_RESET (0x00000000) #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET (0x00000100) #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_HOST_CONTROL_BOOT_RESET (0x00000200) @@ -267,6 +283,7 @@ typedef volatile struct _MPI3_SYSIF_REGISTERS /**** Defines for the Fault register ****/ #define MPI3_SYSIF_FAULT_OFFSET (0x00001C10) #define MPI3_SYSIF_FAULT_CODE_MASK (0x0000FFFF) +#define MPI3_SYSIF_FAULT_CODE_SHIFT (0) #define MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET (0x0000F000) #define MPI3_SYSIF_FAULT_CODE_CI_ACTIVATION_RESET (0x0000F001) #define MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS (0x0000F002) @@ -274,6 +291,7 @@ typedef volatile struct _MPI3_SYSIF_REGISTERS #define MPI3_SYSIF_FAULT_CODE_SOFT_RESET_NEEDED (0x0000F004) #define MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED (0x0000F005) #define MPI3_SYSIF_FAULT_CODE_TEMP_THRESHOLD_EXCEEDED (0x0000F006) +#define MPI3_SYSIF_FAULT_CODE_INSUFFICIENT_PCI_SLOT_POWER (0x0000F007) /**** Defines for FaultCodeAdditionalInfo registers ****/ #define MPI3_SYSIF_FAULT_INFO0_OFFSET (0x00001C14) @@ -307,12 +325,14 @@ typedef volatile struct _MPI3_SYSIF_REGISTERS /**** Defines for DiagRWControl register ****/ #define MPI3_SYSIF_DIAG_RW_CONTROL_OFFSET (0x00001C60) #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_MASK (0x00000030) +#define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_SHIFT (4) #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_1BYTE (0x00000000) #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_2BYTES (0x00000010) #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_4BYTES (0x00000020) #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_8BYTES (0x00000030) #define MPI3_SYSIF_DIAG_RW_CONTROL_RESET (0x00000004) #define MPI3_SYSIF_DIAG_RW_CONTROL_DIR_MASK (0x00000002) +#define MPI3_SYSIF_DIAG_RW_CONTROL_DIR_SHIFT (1) #define MPI3_SYSIF_DIAG_RW_CONTROL_DIR_READ (0x00000000) #define MPI3_SYSIF_DIAG_RW_CONTROL_DIR_WRITE (0x00000002) #define MPI3_SYSIF_DIAG_RW_CONTROL_START (0x00000001) @@ -320,6 +340,7 @@ typedef volatile struct _MPI3_SYSIF_REGISTERS /**** Defines for DiagRWStatus register ****/ #define MPI3_SYSIF_DIAG_RW_STATUS_OFFSET (0x00001C62) #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_MASK (0x0000000E) +#define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_SHIFT (1) #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_SUCCESS (0x00000000) #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_INV_ADDR (0x00000002) #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_ACC_ERR (0x00000004) @@ -357,7 +378,9 @@ typedef struct _MPI3_DEFAULT_REPLY_DESCRIPTOR /**** Defines for the ReplyFlags field ****/ #define MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK (0x0001) +#define MPI3_REPLY_DESCRIPT_FLAGS_PHASE_SHIFT (0) #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_MASK (0xF000) +#define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SHIFT (12) #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_ADDRESS_REPLY (0x0000) #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SUCCESS (0x1000) #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_TARGET_COMMAND_BUFFER (0x2000) @@ -425,15 +448,9 @@ typedef struct _MPI3_STATUS_REPLY_DESCRIPTOR } MPI3_STATUS_REPLY_DESCRIPTOR, MPI3_POINTER PTR_MPI3_STATUS_REPLY_DESCRIPTOR, Mpi3StatusReplyDescriptor_t, MPI3_POINTER pMpi3StatusReplyDescriptor_t; -/**** Defines for the IOCStatus field ****/ -#define MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL (0x8000) -#define MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK (0x7FFF) +/**** Use MPI3_IOCSTATUS_ defines for the IOCStatus field ****/ -/**** Defines for the IOCLogInfo field ****/ -#define MPI3_REPLY_DESCRIPT_STATUS_IOCLOGINFO_TYPE_MASK (0xF0000000) -#define MPI3_REPLY_DESCRIPT_STATUS_IOCLOGINFO_TYPE_NO_INFO (0x00000000) -#define MPI3_REPLY_DESCRIPT_STATUS_IOCLOGINFO_TYPE_SAS (0x30000000) -#define MPI3_REPLY_DESCRIPT_STATUS_IOCLOGINFO_DATA_MASK (0x0FFFFFFF) +/**** Use MPI3_IOCLOGINFO_ defines for the IOCLogInfo field ****/ /***************************************************************************** * Union of Reply Descriptors * @@ -516,6 +533,7 @@ typedef union _MPI3_SGE_UNION /**** Definitions for the Flags field ****/ #define MPI3_SGE_FLAGS_ELEMENT_TYPE_MASK (0xF0) +#define MPI3_SGE_FLAGS_ELEMENT_TYPE_SHIFT (4) #define MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE (0x00) #define MPI3_SGE_FLAGS_ELEMENT_TYPE_BIT_BUCKET (0x10) #define MPI3_SGE_FLAGS_ELEMENT_TYPE_CHAIN (0x20) @@ -524,6 +542,7 @@ typedef union _MPI3_SGE_UNION #define MPI3_SGE_FLAGS_END_OF_LIST (0x08) #define MPI3_SGE_FLAGS_END_OF_BUFFER (0x04) #define MPI3_SGE_FLAGS_DLAS_MASK (0x03) +#define MPI3_SGE_FLAGS_DLAS_SHIFT (0) #define MPI3_SGE_FLAGS_DLAS_SYSTEM (0x00) #define MPI3_SGE_FLAGS_DLAS_IOC_UDP (0x01) #define MPI3_SGE_FLAGS_DLAS_IOC_CTL (0x02) @@ -532,30 +551,33 @@ typedef union _MPI3_SGE_UNION #define MPI3_SGE_EXT_OPER_EEDP (0x00) /**** Definitions for the EEDPFlags field of Extended EEDP element ****/ -#define MPI3_EEDPFLAGS_INCR_PRI_REF_TAG (0x8000) -#define MPI3_EEDPFLAGS_INCR_SEC_REF_TAG (0x4000) -#define MPI3_EEDPFLAGS_INCR_PRI_APP_TAG (0x2000) -#define MPI3_EEDPFLAGS_INCR_SEC_APP_TAG (0x1000) -#define MPI3_EEDPFLAGS_ESC_PASSTHROUGH (0x0800) -#define MPI3_EEDPFLAGS_CHK_REF_TAG (0x0400) -#define MPI3_EEDPFLAGS_CHK_APP_TAG (0x0200) -#define MPI3_EEDPFLAGS_CHK_GUARD (0x0100) -#define MPI3_EEDPFLAGS_ESC_MODE_MASK (0x00C0) -#define MPI3_EEDPFLAGS_ESC_MODE_DO_NOT_DISABLE (0x0040) -#define MPI3_EEDPFLAGS_ESC_MODE_APPTAG_DISABLE (0x0080) +#define MPI3_EEDPFLAGS_INCR_PRI_REF_TAG (0x8000) +#define MPI3_EEDPFLAGS_INCR_SEC_REF_TAG (0x4000) +#define MPI3_EEDPFLAGS_INCR_PRI_APP_TAG (0x2000) +#define MPI3_EEDPFLAGS_INCR_SEC_APP_TAG (0x1000) +#define MPI3_EEDPFLAGS_ESC_PASSTHROUGH (0x0800) +#define MPI3_EEDPFLAGS_CHK_REF_TAG (0x0400) +#define MPI3_EEDPFLAGS_CHK_APP_TAG (0x0200) +#define MPI3_EEDPFLAGS_CHK_GUARD (0x0100) +#define MPI3_EEDPFLAGS_ESC_MODE_MASK (0x00C0) +#define MPI3_EEDPFLAGS_ESC_MODE_SHIFT (6) +#define MPI3_EEDPFLAGS_ESC_MODE_DO_NOT_DISABLE (0x0040) +#define MPI3_EEDPFLAGS_ESC_MODE_APPTAG_DISABLE (0x0080) #define MPI3_EEDPFLAGS_ESC_MODE_APPTAG_REFTAG_DISABLE (0x00C0) -#define MPI3_EEDPFLAGS_HOST_GUARD_MASK (0x0030) -#define MPI3_EEDPFLAGS_HOST_GUARD_T10_CRC (0x0000) -#define MPI3_EEDPFLAGS_HOST_GUARD_IP_CHKSUM (0x0010) -#define MPI3_EEDPFLAGS_HOST_GUARD_OEM_SPECIFIC (0x0020) -#define MPI3_EEDPFLAGS_PT_REF_TAG (0x0008) -#define MPI3_EEDPFLAGS_EEDP_OP_MASK (0x0007) -#define MPI3_EEDPFLAGS_EEDP_OP_CHECK (0x0001) -#define MPI3_EEDPFLAGS_EEDP_OP_STRIP (0x0002) -#define MPI3_EEDPFLAGS_EEDP_OP_CHECK_REMOVE (0x0003) -#define MPI3_EEDPFLAGS_EEDP_OP_INSERT (0x0004) -#define MPI3_EEDPFLAGS_EEDP_OP_REPLACE (0x0006) -#define MPI3_EEDPFLAGS_EEDP_OP_CHECK_REGEN (0x0007) +#define MPI3_EEDPFLAGS_HOST_GUARD_MASK (0x0030) +#define MPI3_EEDPFLAGS_HOST_GUARD_SHIFT (4) +#define MPI3_EEDPFLAGS_HOST_GUARD_T10_CRC (0x0000) +#define MPI3_EEDPFLAGS_HOST_GUARD_IP_CHKSUM (0x0010) +#define MPI3_EEDPFLAGS_HOST_GUARD_OEM_SPECIFIC (0x0020) +#define MPI3_EEDPFLAGS_PT_REF_TAG (0x0008) +#define MPI3_EEDPFLAGS_EEDP_OP_MASK (0x0007) +#define MPI3_EEDPFLAGS_EEDP_OP_SHIFT (0) +#define MPI3_EEDPFLAGS_EEDP_OP_CHECK (0x0001) +#define MPI3_EEDPFLAGS_EEDP_OP_STRIP (0x0002) +#define MPI3_EEDPFLAGS_EEDP_OP_CHECK_REMOVE (0x0003) +#define MPI3_EEDPFLAGS_EEDP_OP_INSERT (0x0004) +#define MPI3_EEDPFLAGS_EEDP_OP_REPLACE (0x0006) +#define MPI3_EEDPFLAGS_EEDP_OP_CHECK_REGEN (0x0007) /**** Definitions for the UserDataSize field of Extended EEDP element ****/ #define MPI3_EEDP_UDS_512 (0x01) @@ -652,9 +674,9 @@ typedef struct _MPI3_DEFAULT_REPLY #define MPI3_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* End of the product-specific range of function codes */ /**** Defines for IOCStatus ****/ -#define MPI3_IOCSTATUS_LOG_INFO_AVAIL_MASK (0x8000) #define MPI3_IOCSTATUS_LOG_INFO_AVAILABLE (0x8000) #define MPI3_IOCSTATUS_STATUS_MASK (0x7FFF) +#define MPI3_IOCSTATUS_STATUS_SHIFT (0) /* Common IOCStatus values for all replies */ #define MPI3_IOCSTATUS_SUCCESS (0x0000) @@ -665,6 +687,7 @@ typedef struct _MPI3_DEFAULT_REPLY #define MPI3_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) #define MPI3_IOCSTATUS_INVALID_FIELD (0x0007) #define MPI3_IOCSTATUS_INVALID_STATE (0x0008) +#define MPI3_IOCSTATUS_SHUTDOWN_ACTIVE (0x0009) #define MPI3_IOCSTATUS_INSUFFICIENT_POWER (0x000A) #define MPI3_IOCSTATUS_INVALID_CHANGE_COUNT (0x000B) #define MPI3_IOCSTATUS_ALLOWED_CMD_BLOCK (0x000C) @@ -742,6 +765,7 @@ typedef struct _MPI3_DEFAULT_REPLY #define MPI3_IOCLOGINFO_TYPE_NONE (0x0) #define MPI3_IOCLOGINFO_TYPE_SAS (0x3) #define MPI3_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF) +#define MPI3_IOCLOGINFO_LOG_DATA_SHIFT (0) #endif /* MPI30_TRANSPORT_H */ diff --git a/sys/dev/mpi3mr/mpi/mpi30_type.h b/sys/dev/mpi3mr/mpi/mpi30_type.h index 267ede701762..a6ec8c395c35 100644 --- a/sys/dev/mpi3mr/mpi/mpi30_type.h +++ b/sys/dev/mpi3mr/mpi/mpi30_type.h @@ -1,7 +1,7 @@ /* - * SPDX-License-Identifier: BSD-2-Clause + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * - * Copyright (c) 2016-2023, Broadcom Inc. All rights reserved. + * Copyright (c) 2016-2025, Broadcom Inc. All rights reserved. * Support: <fbsd-storage-driver.pdl@broadcom.com> * * Redistribution and use in source and binary forms, with or without diff --git a/sys/dev/mpi3mr/mpi3mr.c b/sys/dev/mpi3mr/mpi3mr.c index 932d174a6b50..99edd3542619 100644 --- a/sys/dev/mpi3mr/mpi3mr.c +++ b/sys/dev/mpi3mr/mpi3mr.c @@ -1,7 +1,7 @@ /* * SPDX-License-Identifier: BSD-2-Clause * - * Copyright (c) 2016-2023, Broadcom Inc. All rights reserved. + * Copyright (c) 2016-2025, Broadcom Inc. All rights reserved. * Support: <fbsd-storage-driver.pdl@broadcom.com> * * Authors: Sumit Saxena <sumit.saxena@broadcom.com> @@ -83,7 +83,7 @@ static void mpi3mr_port_enable_complete(struct mpi3mr_softc *sc, struct mpi3mr_drvr_cmd *drvrcmd); static void mpi3mr_flush_io(struct mpi3mr_softc *sc); static int mpi3mr_issue_reset(struct mpi3mr_softc *sc, U16 reset_type, - U32 reset_reason); + U16 reset_reason); static void mpi3mr_dev_rmhs_send_tm(struct mpi3mr_softc *sc, U16 handle, struct mpi3mr_drvr_cmd *cmdparam, U8 iou_rc); static void mpi3mr_dev_rmhs_complete_iou(struct mpi3mr_softc *sc, @@ -186,7 +186,7 @@ poll_for_command_completion(struct mpi3mr_softc *sc, * Return: None. */ static void -mpi3mr_trigger_snapdump(struct mpi3mr_softc *sc, U32 reason_code) +mpi3mr_trigger_snapdump(struct mpi3mr_softc *sc, U16 reason_code) { U32 host_diagnostic, timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10; @@ -221,7 +221,7 @@ mpi3mr_trigger_snapdump(struct mpi3mr_softc *sc, U32 reason_code) * * Return: None. */ -static void mpi3mr_check_rh_fault_ioc(struct mpi3mr_softc *sc, U32 reason_code) +static void mpi3mr_check_rh_fault_ioc(struct mpi3mr_softc *sc, U16 reason_code) { U32 ioc_status; @@ -1147,7 +1147,7 @@ enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_softc *sc) return MRIOC_STATE_RESET_REQUESTED; } -static inline void mpi3mr_clear_resethistory(struct mpi3mr_softc *sc) +static inline void mpi3mr_clear_reset_history(struct mpi3mr_softc *sc) { U32 ioc_status; @@ -1167,9 +1167,9 @@ static inline void mpi3mr_clear_resethistory(struct mpi3mr_softc *sc) * * Return: 0 on success, -1 on failure. */ -static int mpi3mr_mur_ioc(struct mpi3mr_softc *sc, U32 reset_reason) +static int mpi3mr_mur_ioc(struct mpi3mr_softc *sc, U16 reset_reason) { - U32 ioc_config, timeout, ioc_status; + U32 ioc_config, timeout, ioc_status, scratch_pad0; int retval = -1; mpi3mr_dprint(sc, MPI3MR_INFO, "Issuing Message Unit Reset(MUR)\n"); @@ -1177,8 +1177,13 @@ static int mpi3mr_mur_ioc(struct mpi3mr_softc *sc, U32 reset_reason) mpi3mr_dprint(sc, MPI3MR_ERROR, "IOC is unrecoverable MUR not issued\n"); return retval; } - mpi3mr_clear_resethistory(sc); - mpi3mr_regwrite(sc, MPI3_SYSIF_SCRATCHPAD0_OFFSET, reset_reason); + mpi3mr_clear_reset_history(sc); + + scratch_pad0 = ((MPI3MR_RESET_REASON_OSTYPE_FREEBSD << + MPI3MR_RESET_REASON_OSTYPE_SHIFT) | + (sc->facts.ioc_num << + MPI3MR_RESET_REASON_IOCNUM_SHIFT) | reset_reason); + mpi3mr_regwrite(sc, MPI3_SYSIF_SCRATCHPAD0_OFFSET, scratch_pad0); ioc_config = mpi3mr_regread(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET); ioc_config &= ~MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC; mpi3mr_regwrite(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET, ioc_config); @@ -1187,7 +1192,7 @@ static int mpi3mr_mur_ioc(struct mpi3mr_softc *sc, U32 reset_reason) do { ioc_status = mpi3mr_regread(sc, MPI3_SYSIF_IOC_STATUS_OFFSET); if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)) { - mpi3mr_clear_resethistory(sc); + mpi3mr_clear_reset_history(sc); ioc_config = mpi3mr_regread(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET); if (!((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) || @@ -1217,24 +1222,44 @@ static int mpi3mr_mur_ioc(struct mpi3mr_softc *sc, U32 reset_reason) * * Return: 0 on success, appropriate error on failure. */ -static int mpi3mr_bring_ioc_ready(struct mpi3mr_softc *sc) +static int mpi3mr_bring_ioc_ready(struct mpi3mr_softc *sc, + U64 *start_time) { - U32 ioc_config, timeout; - enum mpi3mr_iocstate current_state; + enum mpi3mr_iocstate current_state; + U32 ioc_status; + int retval; - ioc_config = mpi3mr_regread(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET); - ioc_config |= MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC; + U32 ioc_config = mpi3mr_regread(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET); + ioc_config |= MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC; mpi3mr_regwrite(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET, ioc_config); - timeout = sc->ready_timeout * 10; - do { - current_state = mpi3mr_get_iocstate(sc); - if (current_state == MRIOC_STATE_READY) - return 0; - DELAY(100 * 1000); - } while (--timeout); + if (*start_time == 0) + *start_time = ticks; - return -1; + do { + ioc_status = mpi3mr_regread(sc, MPI3_SYSIF_IOC_STATUS_OFFSET); + if (ioc_status & (MPI3_SYSIF_IOC_STATUS_FAULT | MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)) { + if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) { + mpi3mr_print_fault_info(sc); + retval = mpi3mr_issue_reset(sc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, MPI3MR_RESET_FROM_BRINGUP); + if (retval) { + mpi3mr_dprint(sc, MPI3MR_ERROR, "%s: Failed to soft reset the IOC, error 0x%d\n", __func__, retval); + return -1; + } + } + mpi3mr_clear_reset_history(sc); + return EAGAIN; + } + + current_state = mpi3mr_get_iocstate(sc); + if (current_state == MRIOC_STATE_READY) + return 0; + + DELAY(100 * 1000); + + } while (((ticks - *start_time) / hz) < sc->ready_timeout); + + return -1; } static const struct { @@ -1313,6 +1338,7 @@ static const struct { "diagnostic buffer post timeout" }, { MPI3MR_RESET_FROM_FIRMWARE, "firmware asynchronus reset" }, + { MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT, "configuration request timeout" }, { MPI3MR_RESET_REASON_COUNT, "Reset reason count" }, }; @@ -1403,14 +1429,10 @@ mpi3mr_soft_reset_success(U32 ioc_status, U32 ioc_config) static inline bool mpi3mr_diagfault_success(struct mpi3mr_softc *sc, U32 ioc_status) { - U32 fault; - if (!(ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) return false; - fault = mpi3mr_regread(sc, MPI3_SYSIF_FAULT_OFFSET) & MPI3_SYSIF_FAULT_CODE_MASK; - if (fault == MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET) - return true; - return false; + mpi3mr_print_fault_info(sc); + return true; } /** @@ -1616,6 +1638,7 @@ static int mpi3mr_process_factsdata(struct mpi3mr_softc *sc, (facts_data->MaxPCIeSwitches); sc->facts.max_sasexpanders = (facts_data->MaxSASExpanders); + sc->facts.max_data_length = facts_data->MaxDataLength; sc->facts.max_sasinitiators = (facts_data->MaxSASInitiators); sc->facts.max_enclosures = (facts_data->MaxEnclosures); @@ -1650,6 +1673,10 @@ static int mpi3mr_process_factsdata(struct mpi3mr_softc *sc, sc->facts.io_throttle_low = facts_data->IOThrottleLow; sc->facts.io_throttle_high = facts_data->IOThrottleHigh; + if (sc->facts.max_data_length == MPI3_IOCFACTS_MAX_DATA_LENGTH_NOT_REPORTED) + sc->facts.max_data_length = MPI3MR_DEFAULT_MAX_IO_SIZE; + else + sc->facts.max_data_length *= MPI3MR_PAGE_SIZE_4K; /*Store in 512b block count*/ if (sc->facts.io_throttle_data_length) sc->io_throttle_data_length = @@ -1889,6 +1916,15 @@ static int mpi3mr_reply_alloc(struct mpi3mr_softc *sc) goto out_failed; } + sc->cfg_cmds.reply = malloc(sc->reply_sz, + M_MPI3MR, M_NOWAIT | M_ZERO); + + if (!sc->cfg_cmds.reply) { + printf(IOCNAME "Cannot allocate memory for cfg_cmds.reply\n", + sc->name); + goto out_failed; + } + sc->ioctl_cmds.reply = malloc(sc->reply_sz, M_MPI3MR, M_NOWAIT | M_ZERO); if (!sc->ioctl_cmds.reply) { printf(IOCNAME "Cannot allocate memory for ioctl_cmds.reply\n", @@ -2139,7 +2175,7 @@ static int mpi3mr_issue_iocinit(struct mpi3mr_softc *sc) strcpy(drvr_info->DriverName, MPI3MR_DRIVER_NAME); strcpy(drvr_info->DriverVersion, MPI3MR_DRIVER_VERSION); strcpy(drvr_info->DriverReleaseDate, MPI3MR_DRIVER_RELDATE); - drvr_info->DriverCapabilities = 0; + drvr_info->DriverCapabilities = MPI3_IOCINIT_DRIVERCAP_OSEXPOSURE_NO_SPECIAL; memcpy((U8 *)&sc->driver_info, (U8 *)drvr_info, sizeof(sc->driver_info)); memset(&iocinit_req, 0, sizeof(iocinit_req)); @@ -2175,6 +2211,8 @@ static int mpi3mr_issue_iocinit(struct mpi3mr_softc *sc) time_in_msec = (now.tv_sec * 1000 + now.tv_usec/1000); iocinit_req.TimeStamp = htole64(time_in_msec); + iocinit_req.MsgFlags |= MPI3_IOCINIT_MSGFLAGS_WRITESAMEDIVERT_SUPPORTED; + init_completion(&sc->init_cmds.completion); retval = mpi3mr_submit_admin_cmd(sc, &iocinit_req, sizeof(iocinit_req)); @@ -2267,7 +2305,7 @@ mpi3mr_display_ioc_info(struct mpi3mr_softc *sc) printf("Capabilities=("); if (sc->facts.ioc_capabilities & - MPI3_IOCFACTS_CAPABILITY_RAID_CAPABLE) { + MPI3_IOCFACTS_CAPABILITY_RAID_SUPPORTED) { printf("RAID"); i++; } @@ -2508,7 +2546,9 @@ static int mpi3mr_alloc_chain_bufs(struct mpi3mr_softc *sc) goto out_failed; } - sz = MPI3MR_CHAINSGE_SIZE; + if (sc->max_sgl_entries > sc->facts.max_data_length / PAGE_SIZE) + sc->max_sgl_entries = sc->facts.max_data_length / PAGE_SIZE; + sz = sc->max_sgl_entries * sizeof(Mpi3SGESimple_t); if (bus_dma_tag_create(sc->mpi3mr_parent_dmat, /* parent */ 4096, 0, /* algnmnt, boundary */ @@ -2707,14 +2747,16 @@ int mpi3mr_initialize_ioc(struct mpi3mr_softc *sc, U8 init_type) { int retval = 0; enum mpi3mr_iocstate ioc_state; - U64 ioc_info; + U64 ioc_info, start_ticks = 0; U32 ioc_status, ioc_control, i, timeout; Mpi3IOCFactsData_t facts_data; char str[32]; U32 size; + U8 retry = 0; sc->cpu_count = mp_ncpus; +retry_init: ioc_status = mpi3mr_regread(sc, MPI3_SYSIF_IOC_STATUS_OFFSET); ioc_control = mpi3mr_regread(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET); ioc_info = mpi3mr_regread64(sc, MPI3_SYSIF_IOC_INFO_LOW_OFFSET); @@ -2722,28 +2764,25 @@ int mpi3mr_initialize_ioc(struct mpi3mr_softc *sc, U8 init_type) mpi3mr_dprint(sc, MPI3MR_INFO, "SOD ioc_status: 0x%x ioc_control: 0x%x " "ioc_info: 0x%lx\n", ioc_status, ioc_control, ioc_info); - /*The timeout value is in 2sec unit, changing it to seconds*/ + /*The timeout value is in 2sec unit, changing it to seconds*/ sc->ready_timeout = ((ioc_info & MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK) >> MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_SHIFT) * 2; ioc_state = mpi3mr_get_iocstate(sc); - mpi3mr_dprint(sc, MPI3MR_INFO, "IOC state: %s IOC ready timeout: %d\n", mpi3mr_iocstate_name(ioc_state), sc->ready_timeout); - if (ioc_state == MRIOC_STATE_BECOMING_READY || - ioc_state == MRIOC_STATE_RESET_REQUESTED) { - timeout = sc->ready_timeout * 10; - do { - DELAY(1000 * 100); - } while (--timeout); - + timeout = sc->ready_timeout * 10; + do { ioc_state = mpi3mr_get_iocstate(sc); - mpi3mr_dprint(sc, MPI3MR_INFO, - "IOC in %s state after waiting for reset time\n", - mpi3mr_iocstate_name(ioc_state)); - } + + if (ioc_state != MRIOC_STATE_BECOMING_READY && + ioc_state != MRIOC_STATE_RESET_REQUESTED) + break; + + DELAY(1000 * 100); + } while (--timeout); if (ioc_state == MRIOC_STATE_READY) { retval = mpi3mr_mur_ioc(sc, MPI3MR_RESET_FROM_BRINGUP); @@ -2755,53 +2794,75 @@ int mpi3mr_initialize_ioc(struct mpi3mr_softc *sc, U8 init_type) } if (ioc_state != MRIOC_STATE_RESET) { - mpi3mr_print_fault_info(sc); - mpi3mr_dprint(sc, MPI3MR_ERROR, "issuing soft reset to bring to reset state\n"); - retval = mpi3mr_issue_reset(sc, - MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, - MPI3MR_RESET_FROM_BRINGUP); - if (retval) { - mpi3mr_dprint(sc, MPI3MR_ERROR, - "%s :Failed to soft reset IOC, error 0x%d\n", - __func__, retval); - goto out_failed; - } - } - + if (ioc_state == MRIOC_STATE_FAULT) { + mpi3mr_print_fault_info(sc); + + U32 fault = mpi3mr_regread(sc, MPI3_SYSIF_FAULT_OFFSET) & + MPI3_SYSIF_FAULT_CODE_MASK; + if (fault == MPI3_SYSIF_FAULT_CODE_INSUFFICIENT_PCI_SLOT_POWER) + mpi3mr_dprint(sc, MPI3MR_INFO, + "controller faulted due to insufficient power, try by connecting it in a different slot\n"); + goto err; + + U32 host_diagnostic; + timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10; + do { + host_diagnostic = mpi3mr_regread(sc, MPI3_SYSIF_HOST_DIAG_OFFSET); + if (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS)) + break; + DELAY(100 * 1000); + } while (--timeout); + } + mpi3mr_dprint(sc, MPI3MR_ERROR, "issuing soft reset to bring to reset state\n"); + retval = mpi3mr_issue_reset(sc, + MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, + MPI3MR_RESET_FROM_BRINGUP); + if (retval) { + mpi3mr_dprint(sc, MPI3MR_ERROR, + "%s :Failed to soft reset IOC, error 0x%d\n", + __func__, retval); + goto err_retry; + } + } + ioc_state = mpi3mr_get_iocstate(sc); if (ioc_state != MRIOC_STATE_RESET) { mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot bring IOC to reset state\n"); - goto out_failed; + goto err_retry; } retval = mpi3mr_setup_admin_qpair(sc); if (retval) { mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to setup Admin queues, error 0x%x\n", retval); - goto out_failed; + if (retval == ENOMEM) + goto err; + goto err_retry; } - - retval = mpi3mr_bring_ioc_ready(sc); + + retval = mpi3mr_bring_ioc_ready(sc, &start_ticks); if (retval) { - mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to bring IOC ready, error 0x%x\n", - retval); - goto out_failed; + mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to bring IOC ready, error 0x%x\n", retval); + if (retval == EAGAIN) + goto err_retry; + goto err; } + if (init_type == MPI3MR_INIT_TYPE_INIT) { retval = mpi3mr_alloc_interrupts(sc, 1); if (retval) { mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to allocate interrupts, error 0x%x\n", retval); - goto out_failed; + goto err; } - + retval = mpi3mr_setup_irqs(sc); if (retval) { mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to setup ISR, error 0x%x\n", retval); - goto out_failed; + goto err; } } @@ -2825,6 +2886,12 @@ int mpi3mr_initialize_ioc(struct mpi3mr_softc *sc, U8 init_type) sc->init_cmds.dev_handle = MPI3MR_INVALID_DEV_HANDLE; sc->init_cmds.host_tag = MPI3MR_HOSTTAG_INITCMDS; + mtx_init(&sc->cfg_cmds.completion.lock, "CFG commands lock", NULL, MTX_DEF); + sc->cfg_cmds.reply = NULL; + sc->cfg_cmds.state = MPI3MR_CMD_NOTUSED; + sc->cfg_cmds.dev_handle = MPI3MR_INVALID_DEV_HANDLE; + sc->cfg_cmds.host_tag = MPI3MR_HOSTTAG_CFGCMDS; + mtx_init(&sc->ioctl_cmds.completion.lock, "IOCTL commands lock", NULL, MTX_DEF); sc->ioctl_cmds.reply = NULL; sc->ioctl_cmds.state = MPI3MR_CMD_NOTUSED; @@ -2861,25 +2928,30 @@ int mpi3mr_initialize_ioc(struct mpi3mr_softc *sc, U8 init_type) retval = mpi3mr_issue_iocfacts(sc, &facts_data); if (retval) { - mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to Issue IOC Facts, retval: 0x%x\n", + mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to Issue IOC Facts, error: 0x%x\n", retval); - goto out_failed; + if (retval == ENOMEM) + goto err; + goto err_retry; } retval = mpi3mr_process_factsdata(sc, &facts_data); if (retval) { - mpi3mr_dprint(sc, MPI3MR_ERROR, "IOC Facts data processing failedi, retval: 0x%x\n", + mpi3mr_dprint(sc, MPI3MR_ERROR, "IOC Facts data processing failed, error: 0x%x\n", retval); - goto out_failed; + goto err_retry; } sc->num_io_throttle_group = sc->facts.max_io_throttle_group; mpi3mr_atomic_set(&sc->pend_large_data_sz, 0); - + if (init_type == MPI3MR_INIT_TYPE_RESET) { retval = mpi3mr_validate_fw_update(sc); - if (retval) - goto out_failed; + if (retval) { + if (retval == ENOMEM) + goto err; + goto err_retry; + } } else { sc->reply_sz = sc->facts.reply_sz; } @@ -2888,25 +2960,27 @@ int mpi3mr_initialize_ioc(struct mpi3mr_softc *sc, U8 init_type) retval = mpi3mr_reply_alloc(sc); if (retval) { - mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to allocated reply and sense buffers, retval: 0x%x\n", + mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to allocated reply and sense buffers, error: 0x%x\n", retval); - goto out_failed; + goto err; } - + if (init_type == MPI3MR_INIT_TYPE_INIT) { retval = mpi3mr_alloc_chain_bufs(sc); if (retval) { - mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to allocated chain buffers, retval: 0x%x\n", - retval); - goto out_failed; + mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to allocated chain buffers, error: 0x%x\n", + retval); + goto err; } } - + retval = mpi3mr_issue_iocinit(sc); if (retval) { - mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to Issue IOC Init, retval: 0x%x\n", - retval); - goto out_failed; + mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to Issue IOC Init, error: 0x%x\n", + retval); + if (retval == ENOMEM) + goto err; + goto err_retry; } mpi3mr_print_fw_pkg_ver(sc); @@ -2914,77 +2988,87 @@ int mpi3mr_initialize_ioc(struct mpi3mr_softc *sc, U8 init_type) sc->reply_free_q_host_index = sc->num_reply_bufs; mpi3mr_regwrite(sc, MPI3_SYSIF_REPLY_FREE_HOST_INDEX_OFFSET, sc->reply_free_q_host_index); - + sc->sense_buf_q_host_index = sc->num_sense_bufs; - + mpi3mr_regwrite(sc, MPI3_SYSIF_SENSE_BUF_FREE_HOST_INDEX_OFFSET, sc->sense_buf_q_host_index); if (init_type == MPI3MR_INIT_TYPE_INIT) { retval = mpi3mr_alloc_interrupts(sc, 0); if (retval) { - mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to allocate interrupts, retval: 0x%x\n", + mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to allocate interrupts, error: 0x%x\n", retval); - goto out_failed; + goto err; } retval = mpi3mr_setup_irqs(sc); if (retval) { - printf(IOCNAME "Failed to setup ISR, error: 0x%x\n", - sc->name, retval); - goto out_failed; + mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to setup ISR, error: 0x%x\n", retval); + goto err; } mpi3mr_enable_interrupts(sc); } else mpi3mr_enable_interrupts(sc); - - retval = mpi3mr_create_op_queues(sc); + retval = mpi3mr_create_op_queues(sc); if (retval) { mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to create operational queues, error: %d\n", retval); - goto out_failed; + if (retval == ENOMEM) + goto err; + goto err_retry; } if (!sc->throttle_groups && sc->num_io_throttle_group) { - mpi3mr_dprint(sc, MPI3MR_ERROR, "allocating memory for throttle groups\n"); size = sizeof(struct mpi3mr_throttle_group_info); sc->throttle_groups = (struct mpi3mr_throttle_group_info *) malloc(sc->num_io_throttle_group * size, M_MPI3MR, M_NOWAIT | M_ZERO); - if (!sc->throttle_groups) - goto out_failed; + if (!sc->throttle_groups) { + mpi3mr_dprint(sc, MPI3MR_ERROR, "throttle groups memory allocation failed\n"); + goto err; + } } if (init_type == MPI3MR_INIT_TYPE_RESET) { - mpi3mr_dprint(sc, MPI3MR_INFO, "Re-register events\n"); + mpi3mr_dprint(sc, MPI3MR_XINFO, "Re-register events\n"); retval = mpi3mr_register_events(sc); if (retval) { - mpi3mr_dprint(sc, MPI3MR_INFO, "Failed to re-register events, retval: 0x%x\n", + mpi3mr_dprint(sc, MPI3MR_INFO, "Failed to re-register events, error: 0x%x\n", retval); - goto out_failed; + goto err_retry; } mpi3mr_dprint(sc, MPI3MR_INFO, "Issuing Port Enable\n"); retval = mpi3mr_issue_port_enable(sc, 0); if (retval) { - mpi3mr_dprint(sc, MPI3MR_INFO, "Failed to issue port enable, retval: 0x%x\n", + mpi3mr_dprint(sc, MPI3MR_INFO, "Failed to issue port enable, error: 0x%x\n", retval); - goto out_failed; + goto err_retry; } } retval = mpi3mr_pel_alloc(sc); if (retval) { - mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to allocate memory for PEL, retval: 0x%x\n", + mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to allocate memory for PEL, error: 0x%x\n", retval); - goto out_failed; + goto err; } - + + if (mpi3mr_cfg_get_driver_pg1(sc) != 0) + mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to get the cfg driver page1\n"); + return retval; -out_failed: +err_retry: + if ((retry++ < 2) && (((ticks - start_ticks) / hz) < (sc->ready_timeout - 60))) { + mpi3mr_dprint(sc, MPI3MR_ERROR, "Retrying controller initialization," + "retry_count: %d\n", retry); + goto retry_init; + } +err: retval = -1; return retval; } @@ -3053,6 +3137,115 @@ out: return retval; } +static int mpi3mr_timestamp_sync(struct mpi3mr_softc *sc) +{ + int retval = 0; + struct timeval current_time; + int64_t time_in_msec; + Mpi3IoUnitControlRequest_t iou_ctrl = {0}; + + mtx_lock(&sc->init_cmds.completion.lock); + if (sc->init_cmds.state & MPI3MR_CMD_PENDING) { + mpi3mr_dprint(sc, MPI3MR_ERROR, "Issue timestamp sync: command is in use\n"); + mtx_unlock(&sc->init_cmds.completion.lock); + return -1; + } + + sc->init_cmds.state = MPI3MR_CMD_PENDING; + sc->init_cmds.is_waiting = 1; + sc->init_cmds.callback = NULL; + iou_ctrl.HostTag = htole64(MPI3MR_HOSTTAG_INITCMDS); + iou_ctrl.Function = MPI3_FUNCTION_IO_UNIT_CONTROL; + iou_ctrl.Operation = MPI3_CTRL_OP_UPDATE_TIMESTAMP; + getmicrotime(¤t_time); + time_in_msec = (int64_t)current_time.tv_sec * 1000 + current_time.tv_usec/1000; + iou_ctrl.Param64[0] = htole64(time_in_msec); + + init_completion(&sc->init_cmds.completion); + + retval = mpi3mr_submit_admin_cmd(sc, &iou_ctrl, sizeof(iou_ctrl)); + if (retval) { + mpi3mr_dprint(sc, MPI3MR_ERROR, "timestamp sync: Admin Post failed\n"); + goto out_unlock; + } + + wait_for_completion_timeout(&sc->init_cmds.completion, + (MPI3MR_INTADMCMD_TIMEOUT)); + + if (!(sc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { + mpi3mr_dprint(sc, MPI3MR_ERROR, "Issue timestamp sync: command timed out\n"); + sc->init_cmds.is_waiting = 0; + + if (!(sc->init_cmds.state & MPI3MR_CMD_RESET)) + mpi3mr_check_rh_fault_ioc(sc, MPI3MR_RESET_FROM_TSU_TIMEOUT); + + retval = -1; + goto out_unlock; + } + + if (((sc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) != MPI3_IOCSTATUS_SUCCESS) && + (sc->init_cmds.ioc_status != MPI3_IOCSTATUS_SUPERVISOR_ONLY)) { + mpi3mr_dprint(sc, MPI3MR_ERROR, "Issue timestamp sync: Failed IOCStatus(0x%04x) Loginfo(0x%08x)\n", + (sc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), sc->init_cmds.ioc_loginfo); + retval = -1; + } + +out_unlock: + sc->init_cmds.state = MPI3MR_CMD_NOTUSED; + mtx_unlock(&sc->init_cmds.completion.lock); + + return retval; +} + +void +mpi3mr_timestamp_thread(void *arg) +{ + struct mpi3mr_softc *sc = (struct mpi3mr_softc *)arg; + U64 elapsed_time = 0; + + sc->timestamp_thread_active = 1; + mtx_lock(&sc->reset_mutex); + while (1) { + + if (sc->mpi3mr_flags & MPI3MR_FLAGS_SHUTDOWN || + (sc->unrecoverable == 1)) { + mpi3mr_dprint(sc, MPI3MR_INFO, + "Exit due to %s from %s\n", + sc->mpi3mr_flags & MPI3MR_FLAGS_SHUTDOWN ? "Shutdown" : + "Hardware critical error", __func__); + break; + } + mtx_unlock(&sc->reset_mutex); + + while (sc->reset_in_progress) { + if (elapsed_time) + elapsed_time = 0; + if (sc->unrecoverable) + break; + pause("mpi3mr_timestamp_thread", hz / 5); + } + + if (elapsed_time++ >= sc->ts_update_interval * 60) { + mpi3mr_timestamp_sync(sc); + elapsed_time = 0; + } + + /* + * Sleep for 1 second if we're not exiting, then loop to top + * to poll exit status and hardware health. + */ + mtx_lock(&sc->reset_mutex); + if (((sc->mpi3mr_flags & MPI3MR_FLAGS_SHUTDOWN) == 0) && + (!sc->unrecoverable) && (!sc->reset_in_progress)) { + msleep(&sc->timestamp_chan, &sc->reset_mutex, PRIBIO, + "mpi3mr_timestamp", 1 * hz); + } + } + mtx_unlock(&sc->reset_mutex); + sc->timestamp_thread_active = 0; + kproc_exit(0); +} + void mpi3mr_watchdog_thread(void *arg) { @@ -3118,6 +3311,14 @@ mpi3mr_watchdog_thread(void *arg) sc->unrecoverable = 1; break; } + + if (fault == MPI3_SYSIF_FAULT_CODE_INSUFFICIENT_PCI_SLOT_POWER) { + mpi3mr_dprint(sc, MPI3MR_INFO, + "controller faulted due to insufficient power, marking controller as unrecoverable\n"); + sc->unrecoverable = 1; + break; + } + if ((fault == MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET) || (fault == MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS) || (sc->reset_in_progress)) @@ -3338,6 +3539,19 @@ void mpi3mr_update_device(struct mpi3mr_softc *sc, break; } + switch (flags & MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_MASK) { + case MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_256_LB: + tgtdev->ws_len = 256; + break; + case MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_2048_LB: + tgtdev->ws_len = 2048; + break; + case MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_NO_LIMIT: + default: + tgtdev->ws_len = 0; + break; + } + switch (tgtdev->dev_type) { case MPI3_DEVICE_DEVFORM_SAS_SATA: { @@ -3477,6 +3691,7 @@ static void mpi3mr_dev_rmhs_complete_iou(struct mpi3mr_softc *sc, { U16 cmd_idx = drv_cmd->host_tag - MPI3MR_HOSTTAG_DEVRMCMD_MIN; struct delayed_dev_rmhs_node *delayed_dev_rmhs = NULL; + struct mpi3mr_target *tgtdev = NULL; mpi3mr_dprint(sc, MPI3MR_EVENT, "%s :dev_rmhs_iouctrl_complete:handle(0x%04x), ioc_status(0x%04x), loginfo(0x%08x)\n", @@ -3497,6 +3712,13 @@ static void mpi3mr_dev_rmhs_complete_iou(struct mpi3mr_softc *sc, "%s :dev removal handshake failed after all retries: handle(0x%04x)\n", __func__, drv_cmd->dev_handle); } else { + mtx_lock_spin(&sc->target_lock); + TAILQ_FOREACH(tgtdev, &sc->cam_sc->tgt_list, tgt_next) { + if (tgtdev->dev_handle == drv_cmd->dev_handle) + tgtdev->state = MPI3MR_DEV_REMOVE_HS_COMPLETED; + } + mtx_unlock_spin(&sc->target_lock); + mpi3mr_dprint(sc, MPI3MR_INFO, "%s :dev removal handshake completed successfully: handle(0x%04x)\n", __func__, drv_cmd->dev_handle); @@ -3604,18 +3826,7 @@ static void mpi3mr_dev_rmhs_send_tm(struct mpi3mr_softc *sc, U16 handle, U8 retrycount = 5; struct mpi3mr_drvr_cmd *drv_cmd = cmdparam; struct delayed_dev_rmhs_node *delayed_dev_rmhs = NULL; - struct mpi3mr_target *tgtdev = NULL; - mtx_lock_spin(&sc->target_lock); - TAILQ_FOREACH(tgtdev, &sc->cam_sc->tgt_list, tgt_next) { - if ((tgtdev->dev_handle == handle) && - (iou_rc == MPI3_CTRL_OP_REMOVE_DEVICE)) { - tgtdev->state = MPI3MR_DEV_REMOVE_HS_STARTED; - break; - } - } - mtx_unlock_spin(&sc->target_lock); - if (drv_cmd) goto issue_cmd; do { @@ -3890,7 +4101,7 @@ static void mpi3mr_sastopochg_evt_th(struct mpi3mr_softc *sc, handle = le16toh(topo_evt->PhyEntry[i].AttachedDevHandle); if (!handle) continue; - reason_code = topo_evt->PhyEntry[i].Status & + reason_code = topo_evt->PhyEntry[i].PhyStatus & MPI3_EVENT_SAS_TOPO_PHY_RC_MASK; tgtdev = mpi3mr_find_target_by_dev_handle(sc->cam_sc, handle); switch (reason_code) { @@ -4170,11 +4381,16 @@ static void mpi3mr_process_events(struct mpi3mr_softc *sc, break; } case MPI3_EVENT_DEVICE_INFO_CHANGED: - case MPI3_EVENT_LOG_DATA: { process_evt_bh = 1; break; } + case MPI3_EVENT_LOG_DATA: + { + mpi3mr_app_save_logdata(sc, (char*)event_reply->EventData, + le16toh(event_reply->EventDataLength) * 4); + break; + } case MPI3_EVENT_ENERGY_PACK_CHANGE: { mpi3mr_energypackchg_evt_th(sc, event_reply); @@ -4281,10 +4497,9 @@ static void mpi3mr_process_admin_reply_desc(struct mpi3mr_softc *sc, status_desc = (Mpi3StatusReplyDescriptor_t *)reply_desc; host_tag = status_desc->HostTag; ioc_status = status_desc->IOCStatus; - if (ioc_status & - MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL) + if (ioc_status & MPI3_IOCSTATUS_STATUS_MASK) ioc_loginfo = status_desc->IOCLogInfo; - ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK; + ioc_status &= MPI3_IOCSTATUS_STATUS_MASK; break; case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_ADDRESS_REPLY: addr_desc = (Mpi3AddressReplyDescriptor_t *)reply_desc; @@ -4294,10 +4509,9 @@ static void mpi3mr_process_admin_reply_desc(struct mpi3mr_softc *sc, goto out; host_tag = def_reply->HostTag; ioc_status = def_reply->IOCStatus; - if (ioc_status & - MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL) + if (ioc_status & MPI3_IOCSTATUS_STATUS_MASK) ioc_loginfo = def_reply->IOCLogInfo; - ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK; + ioc_status &= MPI3_IOCSTATUS_STATUS_MASK; if (def_reply->Function == MPI3_FUNCTION_SCSI_IO) { scsi_reply = (Mpi3SCSIIOReply_t *)def_reply; sense_buf = mpi3mr_get_sensebuf_virt_addr(sc, @@ -4315,6 +4529,9 @@ static void mpi3mr_process_admin_reply_desc(struct mpi3mr_softc *sc, case MPI3MR_HOSTTAG_INITCMDS: cmdptr = &sc->init_cmds; break; + case MPI3MR_HOSTTAG_CFGCMDS: + cmdptr = &sc->cfg_cmds; + break; case MPI3MR_HOSTTAG_IOCTLCMDS: cmdptr = &sc->ioctl_cmds; break; @@ -4391,6 +4608,7 @@ static int mpi3mr_complete_admin_cmd(struct mpi3mr_softc *sc) U32 num_adm_reply = 0; U64 reply_dma = 0; Mpi3DefaultReplyDescriptor_t *reply_desc; + U16 threshold_comps = 0; mtx_lock_spin(&sc->admin_reply_lock); if (sc->admin_in_use == false) { @@ -4428,6 +4646,11 @@ static int mpi3mr_complete_admin_cmd(struct mpi3mr_softc *sc) if ((reply_desc->ReplyFlags & MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) break; + + if (++threshold_comps == MPI3MR_THRESHOLD_REPLY_COUNT) { + mpi3mr_regwrite(sc, MPI3_SYSIF_ADMIN_REPLY_Q_CI_OFFSET, adm_reply_ci); + threshold_comps = 0; + } } while (1); mpi3mr_regwrite(sc, MPI3_SYSIF_ADMIN_REPLY_Q_CI_OFFSET, adm_reply_ci); @@ -4492,10 +4715,9 @@ void mpi3mr_process_op_reply_desc(struct mpi3mr_softc *sc, status_desc = (Mpi3StatusReplyDescriptor_t *)reply_desc; host_tag = status_desc->HostTag; ioc_status = status_desc->IOCStatus; - if (ioc_status & - MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL) + if (ioc_status & MPI3_IOCSTATUS_STATUS_MASK) ioc_loginfo = status_desc->IOCLogInfo; - ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK; + ioc_status &= MPI3_IOCSTATUS_STATUS_MASK; break; case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_ADDRESS_REPLY: addr_desc = (Mpi3AddressReplyDescriptor_t *)reply_desc; @@ -4519,10 +4741,9 @@ void mpi3mr_process_op_reply_desc(struct mpi3mr_softc *sc, resp_data = scsi_reply->ResponseData; sense_buf = mpi3mr_get_sensebuf_virt_addr(sc, scsi_reply->SenseDataBufferAddress); - if (ioc_status & - MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL) + if (ioc_status & MPI3_IOCSTATUS_STATUS_MASK) ioc_loginfo = scsi_reply->IOCLogInfo; - ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK; + ioc_status &= MPI3_IOCSTATUS_STATUS_MASK; if (sense_state == MPI3_SCSI_STATE_SENSE_BUFF_Q_EMPTY) mpi3mr_dprint(sc, MPI3MR_ERROR, "Ran out of sense buffers\n"); @@ -4724,7 +4945,7 @@ void mpi3mr_process_op_reply_desc(struct mpi3mr_softc *sc, csio->resid = cm->length - le32toh(xfer_count); case MPI3_IOCSTATUS_SCSI_RECOVERED_ERROR: case MPI3_IOCSTATUS_SUCCESS: - if ((scsi_reply->IOCStatus & MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK) == + if ((scsi_reply->IOCStatus & MPI3_IOCSTATUS_STATUS_MASK) == MPI3_IOCSTATUS_SCSI_RECOVERED_ERROR) mpi3mr_dprint(sc, MPI3MR_XINFO, "func: %s line: %d recovered error\n", __func__, __LINE__); @@ -4840,7 +5061,7 @@ int mpi3mr_complete_io_cmd(struct mpi3mr_softc *sc, U32 num_op_replies = 0; U64 reply_dma = 0; Mpi3DefaultReplyDescriptor_t *reply_desc; - U16 req_qid = 0; + U16 req_qid = 0, threshold_comps = 0; mtx_lock_spin(&op_reply_q->q_lock); if (op_reply_q->in_use == false) { @@ -4885,6 +5106,12 @@ int mpi3mr_complete_io_cmd(struct mpi3mr_softc *sc, if ((reply_desc->ReplyFlags & MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) break; + + if (++threshold_comps == MPI3MR_THRESHOLD_REPLY_COUNT) { + mpi3mr_regwrite(sc, MPI3_SYSIF_OPER_REPLY_Q_N_CI_OFFSET(op_reply_q->qid), reply_ci); + threshold_comps = 0; + } + } while (1); @@ -4940,7 +5167,7 @@ mpi3mr_alloc_requests(struct mpi3mr_softc *sc) struct mpi3mr_cmd *cmd; int i, j, nsegs, ret; - nsegs = MPI3MR_SG_DEPTH; + nsegs = sc->max_sgl_entries; ret = bus_dma_tag_create( sc->mpi3mr_parent_dmat, /* parent */ 1, 0, /* algnmnt, boundary */ sc->dma_loaddr, /* lowaddr */ @@ -5210,6 +5437,184 @@ out_failed: mpi3mr_free_ioctl_dma_memory(sc); } +static void inline +mpi3mr_free_dma_mem(struct mpi3mr_softc *sc, + struct dma_memory_desc *mem_desc) +{ + if (mem_desc->dma_addr) + bus_dmamap_unload(mem_desc->tag, mem_desc->dmamap); + + if (mem_desc->addr != NULL) { + bus_dmamem_free(mem_desc->tag, mem_desc->addr, mem_desc->dmamap); + mem_desc->addr = NULL; + } + + if (mem_desc->tag != NULL) + bus_dma_tag_destroy(mem_desc->tag); +} + +static int +mpi3mr_alloc_dma_mem(struct mpi3mr_softc *sc, + struct dma_memory_desc *mem_desc) +{ + int retval; + + if (bus_dma_tag_create(sc->mpi3mr_parent_dmat, /* parent */ + 4, 0, /* algnmnt, boundary */ + sc->dma_loaddr, /* lowaddr */ + sc->dma_hiaddr, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + mem_desc->size, /* maxsize */ + 1, /* nsegments */ + mem_desc->size, /* maxsize */ + 0, /* flags */ + NULL, NULL, /* lockfunc, lockarg */ + &mem_desc->tag)) { + mpi3mr_dprint(sc, MPI3MR_ERROR, "%s: Cannot allocate DMA tag\n", __func__); + return ENOMEM; + } + + if (bus_dmamem_alloc(mem_desc->tag, (void **)&mem_desc->addr, + BUS_DMA_NOWAIT, &mem_desc->dmamap)) { + mpi3mr_dprint(sc, MPI3MR_ERROR, "%s: Cannot allocate DMA memory\n", __func__); + retval = ENOMEM; + goto out; + } + + bzero(mem_desc->addr, mem_desc->size); + + bus_dmamap_load(mem_desc->tag, mem_desc->dmamap, mem_desc->addr, mem_desc->size, + mpi3mr_memaddr_cb, &mem_desc->dma_addr, BUS_DMA_NOWAIT); + + if (!mem_desc->addr) { + mpi3mr_dprint(sc, MPI3MR_ERROR, "%s: Cannot load DMA map\n", __func__); + retval = ENOMEM; + goto out; + } + return 0; +out: + mpi3mr_free_dma_mem(sc, mem_desc); + return retval; +} + +static int +mpi3mr_post_cfg_req(struct mpi3mr_softc *sc, Mpi3ConfigRequest_t *cfg_req) +{ + int retval; + + mtx_lock(&sc->cfg_cmds.completion.lock); + if (sc->cfg_cmds.state & MPI3MR_CMD_PENDING) { + mpi3mr_dprint(sc, MPI3MR_ERROR, "Issue cfg request: cfg command is in use\n"); + mtx_unlock(&sc->cfg_cmds.completion.lock); + return -1; + } + + sc->cfg_cmds.state = MPI3MR_CMD_PENDING; + sc->cfg_cmds.is_waiting = 1; + sc->cfg_cmds.callback = NULL; + sc->cfg_cmds.ioc_status = 0; + sc->cfg_cmds.ioc_loginfo = 0; + + cfg_req->HostTag = htole16(MPI3MR_HOSTTAG_CFGCMDS); + cfg_req->Function = MPI3_FUNCTION_CONFIG; + cfg_req->PageType = MPI3_CONFIG_PAGETYPE_DRIVER; + cfg_req->PageNumber = 1; + cfg_req->PageAddress = 0; + + init_completion(&sc->cfg_cmds.completion); + + retval = mpi3mr_submit_admin_cmd(sc, cfg_req, sizeof(*cfg_req)); + if (retval) { + mpi3mr_dprint(sc, MPI3MR_ERROR, "Issue cfg request: Admin Post failed\n"); + goto out; + } + + wait_for_completion_timeout(&sc->cfg_cmds.completion, + (MPI3MR_INTADMCMD_TIMEOUT)); + + if (!(sc->cfg_cmds.state & MPI3MR_CMD_COMPLETE)) { + if (!(sc->cfg_cmds.state & MPI3MR_CMD_RESET)) { + mpi3mr_dprint(sc, MPI3MR_ERROR, "config request command timed out\n"); + mpi3mr_check_rh_fault_ioc(sc, MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT); + } + retval = -1; + sc->cfg_cmds.is_waiting = 0; + goto out; + } + + if ((sc->cfg_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) != + MPI3_IOCSTATUS_SUCCESS ) { + mpi3mr_dprint(sc, MPI3MR_ERROR, "config request failed, IOCStatus(0x%04x) " + " Loginfo(0x%08x) \n",(sc->cfg_cmds.ioc_status & + MPI3_IOCSTATUS_STATUS_MASK), sc->cfg_cmds.ioc_loginfo); + retval = -1; + } + +out: + sc->cfg_cmds.state = MPI3MR_CMD_NOTUSED; + mtx_unlock(&sc->cfg_cmds.completion.lock); + return retval; +} + +static int mpi3mr_process_cfg_req(struct mpi3mr_softc *sc, + Mpi3ConfigRequest_t *cfg_req, + Mpi3ConfigPageHeader_t *cfg_hdr, + void *cfg_buf, U32 cfg_buf_sz) +{ + int retval; + struct dma_memory_desc mem_desc = {0}; + + if (cfg_req->Action == MPI3_CONFIG_ACTION_PAGE_HEADER) + mem_desc.size = sizeof(Mpi3ConfigPageHeader_t); + else { + mem_desc.size = le16toh(cfg_hdr->PageLength) * 4; + cfg_req->PageLength = cfg_hdr->PageLength; + cfg_req->PageVersion = cfg_hdr->PageVersion; + } + + retval = mpi3mr_alloc_dma_mem(sc, &mem_desc); + if (retval) { + mpi3mr_dprint(sc, MPI3MR_ERROR, "%s: Failed to allocate DMA memory\n", __func__); + return retval; + } + + mpi3mr_add_sg_single(&cfg_req->SGL, MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST, + mem_desc.size, mem_desc.dma_addr); + + retval = mpi3mr_post_cfg_req(sc, cfg_req); + if (retval) + mpi3mr_dprint(sc, MPI3MR_ERROR, "%s: Failed to post config request\n", __func__); + else + memcpy(cfg_buf, mem_desc.addr, min(mem_desc.size, cfg_buf_sz)); + + mpi3mr_free_dma_mem(sc, &mem_desc); + return retval; +} + +int mpi3mr_cfg_get_driver_pg1(struct mpi3mr_softc *sc) +{ + int retval; + Mpi3DriverPage1_t driver_pg1 = {0}; + Mpi3ConfigPageHeader_t cfg_hdr = {0}; + Mpi3ConfigRequest_t cfg_req = {0}; + + cfg_req.Action = MPI3_CONFIG_ACTION_PAGE_HEADER; + retval = mpi3mr_process_cfg_req(sc, &cfg_req, NULL, &cfg_hdr, sizeof(cfg_hdr)); + if (retval) + goto error; + + cfg_req.Action = MPI3_CONFIG_ACTION_READ_CURRENT; + retval = mpi3mr_process_cfg_req(sc, &cfg_req, &cfg_hdr, &driver_pg1, sizeof(driver_pg1)); + +error: + if (!retval && driver_pg1.TimeStampUpdate) + sc->ts_update_interval = driver_pg1.TimeStampUpdate; + else + sc->ts_update_interval = MPI3MR_TSUPDATE_INTERVAL; + + return retval; +} + void mpi3mr_destory_mtx(struct mpi3mr_softc *sc) { @@ -5241,6 +5646,9 @@ mpi3mr_destory_mtx(struct mpi3mr_softc *sc) if (mtx_initialized(&sc->init_cmds.completion.lock)) mtx_destroy(&sc->init_cmds.completion.lock); + if (mtx_initialized(&sc->cfg_cmds.completion.lock)) + mtx_destroy(&sc->cfg_cmds.completion.lock); + if (mtx_initialized(&sc->ioctl_cmds.completion.lock)) mtx_destroy(&sc->ioctl_cmds.completion.lock); @@ -5419,6 +5827,11 @@ mpi3mr_free_mem(struct mpi3mr_softc *sc) sc->init_cmds.reply = NULL; } + if (sc->cfg_cmds.reply) { + free(sc->cfg_cmds.reply, M_MPI3MR); + sc->cfg_cmds.reply = NULL; + } + if (sc->ioctl_cmds.reply) { free(sc->ioctl_cmds.reply, M_MPI3MR); sc->ioctl_cmds.reply = NULL; @@ -5536,6 +5949,9 @@ static void mpi3mr_flush_drv_cmds(struct mpi3mr_softc *sc) cmdptr = &sc->init_cmds; mpi3mr_drv_cmd_comp_reset(sc, cmdptr); + cmdptr = &sc->cfg_cmds; + mpi3mr_drv_cmd_comp_reset(sc, cmdptr); + cmdptr = &sc->ioctl_cmds; mpi3mr_drv_cmd_comp_reset(sc, cmdptr); @@ -5579,6 +5995,7 @@ static void mpi3mr_memset_buffers(struct mpi3mr_softc *sc) memset(sc->admin_reply, 0, sc->admin_reply_q_sz); memset(sc->init_cmds.reply, 0, sc->reply_sz); + memset(sc->cfg_cmds.reply, 0, sc->reply_sz); memset(sc->ioctl_cmds.reply, 0, sc->reply_sz); memset(sc->host_tm_cmds.reply, 0, sc->reply_sz); memset(sc->pel_cmds.reply, 0, sc->reply_sz); @@ -5642,6 +6059,7 @@ static void mpi3mr_invalidate_devhandles(struct mpi3mr_softc *sc) target->io_throttle_enabled = 0; target->io_divert = 0; target->throttle_group = NULL; + target->ws_len = 0; } } mtx_unlock_spin(&sc->target_lock); @@ -5668,6 +6086,8 @@ static void mpi3mr_rfresh_tgtdevs(struct mpi3mr_softc *sc) if (target->exposed_to_os) mpi3mr_remove_device_from_os(sc, target->dev_handle); mpi3mr_remove_device_from_list(sc, target, true); + } else if (target->is_hidden && target->exposed_to_os) { + mpi3mr_remove_device_from_os(sc, target->dev_handle); } } @@ -5693,6 +6113,8 @@ static void mpi3mr_flush_io(struct mpi3mr_softc *sc) if (cmd->callout_owner) { ccb = (union ccb *)(cmd->ccb); ccb->ccb_h.status = CAM_SCSI_BUS_RESET; + mpi3mr_atomic_dec(&sc->fw_outstanding); + mpi3mr_atomic_dec(&cmd->targ->outstanding); mpi3mr_cmd_done(sc, cmd); } else { cmd->ccb = NULL; @@ -5701,23 +6123,6 @@ static void mpi3mr_flush_io(struct mpi3mr_softc *sc) } } } -/** - * mpi3mr_clear_reset_history - Clear reset history - * @sc: Adapter instance reference - * - * Write the reset history bit in IOC Status to clear the bit, - * if it is already set. - * - * Return: Nothing. - */ -static inline void mpi3mr_clear_reset_history(struct mpi3mr_softc *sc) -{ - U32 ioc_status; - - ioc_status = mpi3mr_regread(sc, MPI3_SYSIF_IOC_STATUS_OFFSET); - if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) - mpi3mr_regwrite(sc, MPI3_SYSIF_IOC_STATUS_OFFSET, ioc_status); -} /** * mpi3mr_set_diagsave - Set diag save bit for snapdump @@ -5752,11 +6157,11 @@ static inline void mpi3mr_set_diagsave(struct mpi3mr_softc *sc) * Return: 0 on success, non-zero on failure. */ static int mpi3mr_issue_reset(struct mpi3mr_softc *sc, U16 reset_type, - U32 reset_reason) + U16 reset_reason) { int retval = -1; U8 unlock_retry_count = 0; - U32 host_diagnostic, ioc_status, ioc_config; + U32 host_diagnostic, ioc_status, ioc_config, scratch_pad0; U32 timeout = MPI3MR_RESET_ACK_TIMEOUT * 10; if ((reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET) && @@ -5810,7 +6215,14 @@ static int mpi3mr_issue_reset(struct mpi3mr_softc *sc, U16 reset_type, unlock_retry_count, host_diagnostic); } while (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_DIAG_WRITE_ENABLE)); - mpi3mr_regwrite(sc, MPI3_SYSIF_SCRATCHPAD0_OFFSET, reset_reason); + if (reset_type == MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT) + mpi3mr_set_diagsave(sc); + + scratch_pad0 = ((MPI3MR_RESET_REASON_OSTYPE_FREEBSD << + MPI3MR_RESET_REASON_OSTYPE_SHIFT) | + (sc->facts.ioc_num << + MPI3MR_RESET_REASON_IOCNUM_SHIFT) | reset_reason); + mpi3mr_regwrite(sc, MPI3_SYSIF_SCRATCHPAD0_OFFSET, scratch_pad0); mpi3mr_regwrite(sc, MPI3_SYSIF_HOST_DIAG_OFFSET, host_diagnostic | reset_type); if (reset_type == MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET) { @@ -5889,7 +6301,7 @@ inline void mpi3mr_cleanup_event_taskq(struct mpi3mr_softc *sc) * Return: 0 on success, non-zero on failure. */ int mpi3mr_soft_reset_handler(struct mpi3mr_softc *sc, - U32 reset_reason, bool snapdump) + U16 reset_reason, bool snapdump) { int retval = 0, i = 0; enum mpi3mr_iocstate ioc_state; @@ -5929,6 +6341,9 @@ int mpi3mr_soft_reset_handler(struct mpi3mr_softc *sc, sc->reset_in_progress = 1; sc->block_ioctls = 1; + if (sc->timestamp_thread_active) + wakeup(&sc->timestamp_chan); + while (mpi3mr_atomic_read(&sc->pend_ioctls) && (i < PEND_IOCTLS_COMP_WAIT_TIME)) { ioc_state = mpi3mr_get_iocstate(sc); if (ioc_state == MRIOC_STATE_FAULT) @@ -5996,10 +6411,14 @@ out: mpi3mr_app_send_aen(sc); } } else { - mpi3mr_issue_reset(sc, - MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason); + ioc_state = mpi3mr_get_iocstate(sc); + if (ioc_state != MRIOC_STATE_FAULT) + mpi3mr_issue_reset(sc, + MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason); + sc->unrecoverable = 1; sc->reset_in_progress = 0; + sc->block_ioctls = 0; } mpi3mr_dprint(sc, MPI3MR_INFO, "Soft Reset: %s\n", ((retval == 0) ? "SUCCESS" : "FAILED")); diff --git a/sys/dev/mpi3mr/mpi3mr.h b/sys/dev/mpi3mr/mpi3mr.h index d93c53b286cb..e2f2bfc47fbf 100644 --- a/sys/dev/mpi3mr/mpi3mr.h +++ b/sys/dev/mpi3mr/mpi3mr.h @@ -1,7 +1,7 @@ /* * SPDX-License-Identifier: BSD-2-Clause * - * Copyright (c) 2020-2023, Broadcom Inc. All rights reserved. + * Copyright (c) 2020-2025, Broadcom Inc. All rights reserved. * Support: <fbsd-storage-driver.pdl@broadcom.com> * * Authors: Sumit Saxena <sumit.saxena@broadcom.com> @@ -87,18 +87,19 @@ #include <sys/kthread.h> #include "mpi/mpi30_api.h" -#define MPI3MR_DRIVER_VERSION "8.6.0.2.0" -#define MPI3MR_DRIVER_RELDATE "17th May 2023" +#define MPI3MR_DRIVER_VERSION "8.14.0.2.0" +#define MPI3MR_DRIVER_RELDATE "9th Apr 2025" #define MPI3MR_DRIVER_NAME "mpi3mr" #define MPI3MR_NAME_LENGTH 32 #define IOCNAME "%s: " +#define MPI3MR_DEFAULT_MAX_IO_SIZE (1 * 1024 * 1024) + #define SAS4116_CHIP_REV_A0 0 #define SAS4116_CHIP_REV_B0 1 -#define MPI3MR_SG_DEPTH (MPI3MR_4K_PGSZ/sizeof(Mpi3SGESimple_t)) #define MPI3MR_MAX_SECTORS 2048 #define MPI3MR_MAX_CMDS_LUN 7 #define MPI3MR_MAX_CDB_LENGTH 16 @@ -109,7 +110,12 @@ #define MPI3MR_RAID_QDEPTH 128 #define MPI3MR_NVME_QDEPTH 128 +/* Definitions for internal SGL and Chain SGL buffers */ #define MPI3MR_4K_PGSZ 4096 +#define MPI3MR_PAGE_SIZE_4K 4096 +#define MPI3MR_DEFAULT_SGL_ENTRIES 256 +#define MPI3MR_MAX_SGL_ENTRIES 2048 + #define MPI3MR_AREQQ_SIZE (2 * MPI3MR_4K_PGSZ) #define MPI3MR_AREPQ_SIZE (4 * MPI3MR_4K_PGSZ) #define MPI3MR_AREQ_FRAME_SZ 128 @@ -123,7 +129,7 @@ #define MPI3MR_OP_REP_Q_QD 1024 #define MPI3MR_OP_REP_Q_QD_A0 4096 -#define MPI3MR_CHAINSGE_SIZE MPI3MR_4K_PGSZ +#define MPI3MR_THRESHOLD_REPLY_COUNT 100 #define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \ (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \ @@ -135,10 +141,14 @@ #define MPI3MR_HOSTTAG_PELABORT 3 #define MPI3MR_HOSTTAG_PELWAIT 4 #define MPI3MR_HOSTTAG_TMS 5 +#define MPI3MR_HOSTTAG_CFGCMDS 6 #define MAX_MGMT_ADAPTERS 8 #define MPI3MR_WAIT_BEFORE_CTRL_RESET 5 +#define MPI3MR_RESET_REASON_OSTYPE_FREEBSD 0x4 +#define MPI3MR_RESET_REASON_OSTYPE_SHIFT 28 +#define MPI3MR_RESET_REASON_IOCNUM_SHIFT 20 struct mpi3mr_mgmt_info { uint16_t count; @@ -154,7 +164,7 @@ extern char fmt_os_ver[16]; raw_os_ver[3], raw_os_ver[4], raw_os_ver[5],\ raw_os_ver[6]); #define MPI3MR_NUM_DEVRMCMD 1 -#define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_TMS + 1) +#define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_CFGCMDS + 1) #define MPI3MR_HOSTTAG_DEVRMCMD_MAX (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \ MPI3MR_NUM_DEVRMCMD - 1) #define MPI3MR_INTERNALCMDS_RESVD MPI3MR_HOSTTAG_DEVRMCMD_MAX @@ -226,6 +236,10 @@ extern char fmt_os_ver[16]; #define MPI3MR_PERIODIC_DELAY 1 /* 1 second heartbeat/watchdog check */ +#define WRITE_SAME_32 0x0d + +#define MPI3MR_TSUPDATE_INTERVAL 900 + struct completion { unsigned int done; struct mtx lock; @@ -302,6 +316,7 @@ enum mpi3mr_reset_reason { MPI3MR_RESET_FROM_SCSIIO_TIMEOUT = 26, MPI3MR_RESET_FROM_FIRMWARE = 27, MPI3MR_DEFAULT_RESET_REASON = 28, + MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT = 29, MPI3MR_RESET_REASON_COUNT, }; @@ -328,6 +343,7 @@ struct mpi3mr_ioc_facts U16 max_perids; U16 max_pds; U16 max_sasexpanders; + U32 max_data_length; U16 max_sasinitiators; U16 max_enclosures; U16 max_pcieswitches; @@ -446,8 +462,7 @@ enum mpi3mr_cmd_state { enum mpi3mr_target_state { MPI3MR_DEV_CREATED = 1, - MPI3MR_DEV_REMOVE_HS_STARTED = 2, - MPI3MR_DEV_DELETED = 3, + MPI3MR_DEV_REMOVE_HS_COMPLETED = 2, }; struct mpi3mr_cmd { @@ -544,6 +559,7 @@ struct mpi3mr_softc { char driver_name[MPI3MR_NAME_LENGTH]; int bars; bus_addr_t dma_loaddr; + bus_addr_t dma_hiaddr; u_int mpi3mr_debug; struct mpi3mr_reset reset; int max_msix_vectors; @@ -665,6 +681,7 @@ struct mpi3mr_softc { struct mtx target_lock; U16 max_host_ios; + U32 max_sgl_entries; bus_dma_tag_t chain_sgl_list_tag; struct mpi3mr_chain *chain_sgl_list; U16 chain_bitmap_sz; @@ -676,6 +693,7 @@ struct mpi3mr_softc { struct mpi3mr_drvr_cmd host_tm_cmds; struct mpi3mr_drvr_cmd dev_rmhs_cmds[MPI3MR_NUM_DEVRMCMD]; struct mpi3mr_drvr_cmd evtack_cmds[MPI3MR_NUM_EVTACKCMD]; + struct mpi3mr_drvr_cmd cfg_cmds; U16 devrem_bitmap_sz; void *devrem_bitmap; @@ -753,6 +771,10 @@ struct mpi3mr_softc { struct dma_memory_desc ioctl_chain_sge; struct dma_memory_desc ioctl_resp_sge; bool ioctl_sges_allocated; + struct proc *timestamp_thread_proc; + void *timestamp_chan; + u_int8_t timestamp_thread_active; + U32 ts_update_interval; }; static __inline uint64_t @@ -960,11 +982,12 @@ void mpi3mr_cleanup_event_taskq(struct mpi3mr_softc *sc); void mpi3mr_hexdump(void *buf, int sz, int format); int mpi3mr_soft_reset_handler(struct mpi3mr_softc *sc, - U32 reset_reason, bool snapdump); + U16 reset_reason, bool snapdump); void mpi3mrsas_release_simq_reinit(struct mpi3mr_cam_softc *cam_sc); void mpi3mr_watchdog_thread(void *arg); +void mpi3mr_timestamp_thread(void *arg); void mpi3mr_add_device(struct mpi3mr_softc *sc, U16 per_id); int mpi3mr_remove_device(struct mpi3mr_softc *sc, U16 handle); int @@ -982,6 +1005,7 @@ void mpi3mr_set_io_divert_for_all_vd_in_tg(struct mpi3mr_softc *sc, enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_softc *sc); void mpi3mr_poll_pend_io_completions(struct mpi3mr_softc *sc); void int_to_lun(unsigned int lun, U8 *req_lun); -void trigger_reset_from_watchdog(struct mpi3mr_softc *sc, U8 reset_type, U32 reset_reason); +void trigger_reset_from_watchdog(struct mpi3mr_softc *sc, U8 reset_type, U16 reset_reason); void mpi3mr_alloc_ioctl_dma_memory(struct mpi3mr_softc *sc); +int mpi3mr_cfg_get_driver_pg1(struct mpi3mr_softc *sc); #endif /*MPI3MR_H_INCLUDED*/ diff --git a/sys/dev/mpi3mr/mpi3mr_app.c b/sys/dev/mpi3mr/mpi3mr_app.c index 7bd926269018..7e439bf7ed72 100644 --- a/sys/dev/mpi3mr/mpi3mr_app.c +++ b/sys/dev/mpi3mr/mpi3mr_app.c @@ -1,7 +1,7 @@ /* * SPDX-License-Identifier: BSD-2-Clause * - * Copyright (c) 2020-2023, Broadcom Inc. All rights reserved. + * Copyright (c) 2020-2025, Broadcom Inc. All rights reserved. * Support: <fbsd-storage-driver.pdl@broadcom.com> * * Authors: Sumit Saxena <sumit.saxena@broadcom.com> @@ -797,6 +797,8 @@ mpi3mr_app_mptcmds(struct cdev *dev, u_long cmd, void *uarg, struct mpi3mr_ioctl_mpt_dma_buffer *dma_buffers = NULL, *dma_buff = NULL; struct mpi3mr_ioctl_mpirepbuf *mpirepbuf = NULL; struct mpi3mr_ioctl_mptcmd *karg = (struct mpi3mr_ioctl_mptcmd *)uarg; + struct mpi3mr_target *tgtdev = NULL; + Mpi3SCSITaskMgmtRequest_t *tm_req = NULL; sc = mpi3mr_app_get_adp_instance(karg->mrioc_id); @@ -1060,6 +1062,18 @@ mpi3mr_app_mptcmds(struct cdev *dev, u_long cmd, void *uarg, } } + if (mpi_header->Function == MPI3_FUNCTION_SCSI_TASK_MGMT) { + tm_req = (Mpi3SCSITaskMgmtRequest_t *)mpi_request; + if (tm_req->TaskType != MPI3_SCSITASKMGMT_TASKTYPE_ABORT_TASK) { + tgtdev = mpi3mr_find_target_by_dev_handle(sc->cam_sc, tm_req->DevHandle); + if (!tgtdev) { + rval = ENODEV; + goto out; + } + mpi3mr_atomic_inc(&tgtdev->block_io); + } + } + sc->ioctl_cmds.state = MPI3MR_CMD_PENDING; sc->ioctl_cmds.is_waiting = 1; sc->ioctl_cmds.callback = NULL; @@ -1178,6 +1192,9 @@ mpi3mr_app_mptcmds(struct cdev *dev, u_long cmd, void *uarg, sc->mpi3mr_aen_triggered = 0; out_failed: + if (tgtdev) + mpi3mr_atomic_dec(&tgtdev->block_io); + sc->ioctl_cmds.is_senseprst = 0; sc->ioctl_cmds.sensebuf = NULL; sc->ioctl_cmds.state = MPI3MR_CMD_NOTUSED; @@ -1641,6 +1658,18 @@ mpi3mr_pel_enable(struct mpi3mr_softc *sc, struct mpi3mr_ioctl_pel_enable pel_enable; mpi3mr_dprint(sc, MPI3MR_TRACE, "%s() line: %d\n", __func__, __LINE__); + if (sc->unrecoverable) { + device_printf(sc->mpi3mr_dev, "Issue IOCTL: controller is in unrecoverable state\n"); + return EFAULT; + } + if (sc->reset_in_progress) { + device_printf(sc->mpi3mr_dev, "Issue IOCTL: reset in progress\n"); + return EAGAIN; + } + if (sc->block_ioctls) { + device_printf(sc->mpi3mr_dev, "Issue IOCTL: IOCTLs are blocked\n"); + return EAGAIN; + } if ((data_out_sz != sizeof(pel_enable) || (pel_enable.pel_class > MPI3_PEL_CLASS_FAULT))) { @@ -2067,7 +2096,7 @@ mpi3mr_get_adpinfo(struct mpi3mr_softc *sc, adpinfo.pci_dev_hw_rev = pci_read_config(sc->mpi3mr_dev, PCIR_REVID, 1); adpinfo.pci_subsys_dev_id = pci_get_subdevice(sc->mpi3mr_dev); adpinfo.pci_subsys_ven_id = pci_get_subvendor(sc->mpi3mr_dev); - adpinfo.pci_bus = pci_get_bus(sc->mpi3mr_dev);; + adpinfo.pci_bus = pci_get_bus(sc->mpi3mr_dev); adpinfo.pci_dev = pci_get_slot(sc->mpi3mr_dev); adpinfo.pci_func = pci_get_function(sc->mpi3mr_dev); adpinfo.pci_seg_id = pci_get_domain(sc->mpi3mr_dev); diff --git a/sys/dev/mpi3mr/mpi3mr_app.h b/sys/dev/mpi3mr/mpi3mr_app.h index 733aeb0ae53d..a02c83ad32fe 100644 --- a/sys/dev/mpi3mr/mpi3mr_app.h +++ b/sys/dev/mpi3mr/mpi3mr_app.h @@ -1,7 +1,7 @@ /* * SPDX-License-Identifier: BSD-2-Clause * - * Copyright (c) 2020-2023, Broadcom Inc. All rights reserved. + * Copyright (c) 2020-2025, Broadcom Inc. All rights reserved. * Support: <fbsd-storage-driver.pdl@broadcom.com> * * Authors: Sumit Saxena <sumit.saxena@broadcom.com> diff --git a/sys/dev/mpi3mr/mpi3mr_cam.c b/sys/dev/mpi3mr/mpi3mr_cam.c index b842e2a05bda..77e25339a1a9 100644 --- a/sys/dev/mpi3mr/mpi3mr_cam.c +++ b/sys/dev/mpi3mr/mpi3mr_cam.c @@ -1,7 +1,7 @@ /* * SPDX-License-Identifier: BSD-2-Clause * - * Copyright (c) 2020-2023, Broadcom Inc. All rights reserved. + * Copyright (c) 2020-2025, Broadcom Inc. All rights reserved. * Support: <fbsd-storage-driver.pdl@broadcom.com> * * Authors: Sumit Saxena <sumit.saxena@broadcom.com> @@ -58,13 +58,12 @@ #include <sys/kthread.h> #include <sys/taskqueue.h> #include <sys/sbuf.h> +#include <sys/stdarg.h> #include <machine/bus.h> #include <machine/resource.h> #include <sys/rman.h> -#include <machine/stdarg.h> - #include <cam/cam.h> #include <cam/cam_ccb.h> #include <cam/cam_debug.h> @@ -82,6 +81,7 @@ #include "mpi3mr.h" #include <sys/time.h> /* XXX for pcpu.h */ #include <sys/pcpu.h> /* XXX for PCPU_GET */ +#include <asm/unaligned.h> #define smp_processor_id() PCPU_GET(cpuid) @@ -101,6 +101,37 @@ extern void mpi3mr_add_sg_single(void *paddr, U8 flags, U32 length, static U32 event_count; +static +inline void mpi3mr_divert_ws(Mpi3SCSIIORequest_t *req, + struct ccb_scsiio *csio, + U16 ws_len) +{ + U8 unmap = 0, ndob = 0; + U32 num_blocks = 0; + U8 opcode = scsiio_cdb_ptr(csio)[0]; + U16 service_action = ((scsiio_cdb_ptr(csio)[8] << 8) | scsiio_cdb_ptr(csio)[9]); + + + if (opcode == WRITE_SAME_16 || + (opcode == VARIABLE_LEN_CDB && + service_action == WRITE_SAME_32)) { + + int unmap_ndob_index = (opcode == WRITE_SAME_16) ? 1 : 10; + + unmap = scsiio_cdb_ptr(csio)[unmap_ndob_index] & 0x08; + ndob = scsiio_cdb_ptr(csio)[unmap_ndob_index] & 0x01; + num_blocks = get_unaligned_be32(scsiio_cdb_ptr(csio) + + ((opcode == WRITE_SAME_16) ? 10 : 28)); + + /* Check conditions for diversion to firmware */ + if (unmap && ndob && num_blocks > ws_len) { + req->MsgFlags |= MPI3_SCSIIO_MSGFLAGS_DIVERT_TO_FIRMWARE; + req->Flags = htole32(le32toh(req->Flags) | + MPI3_SCSIIO_FLAGS_DIVERT_REASON_WRITE_SAME_TOO_LARGE); + } + } +} + static void mpi3mr_prepare_sgls(void *arg, bus_dma_segment_t *segs, int nsegs, int error) { @@ -144,7 +175,7 @@ static void mpi3mr_prepare_sgls(void *arg, bus_dmamap_sync(sc->buffer_dmat, cm->dmamap, BUS_DMASYNC_PREWRITE); - KASSERT(nsegs <= MPI3MR_SG_DEPTH && nsegs > 0, + KASSERT(nsegs <= sc->max_sgl_entries && nsegs > 0, ("%s: bad SGE count: %d\n", device_get_nameunit(sc->mpi3mr_dev), nsegs)); KASSERT(scsiio_req->DataLength != 0, ("%s: Data segments (%d), but DataLength == 0\n", @@ -186,7 +217,7 @@ static void mpi3mr_prepare_sgls(void *arg, chain = chain_req->buf; chain_dma = chain_req->buf_phys; - memset(chain_req->buf, 0, PAGE_SIZE); + memset(chain_req->buf, 0, sc->max_sgl_entries * sizeof(Mpi3SGESimple_t)); sges_in_segment = sges_left; chain_length = sges_in_segment * sizeof(Mpi3SGESimple_t); @@ -454,7 +485,7 @@ void mpi3mr_poll_pend_io_completions(struct mpi3mr_softc *sc) } void -trigger_reset_from_watchdog(struct mpi3mr_softc *sc, U8 reset_type, U32 reset_reason) +trigger_reset_from_watchdog(struct mpi3mr_softc *sc, U8 reset_type, U16 reset_reason) { if (sc->reset_in_progress) { mpi3mr_dprint(sc, MPI3MR_INFO, "Another reset is in progress, no need to trigger the reset\n"); @@ -1079,6 +1110,9 @@ mpi3mr_action_scsiio(struct mpi3mr_cam_softc *cam_sc, union ccb *ccb) break; } + if (targ->ws_len) + mpi3mr_divert_ws(req, csio, targ->ws_len); + req->Flags = htole32(mpi_control); if (csio->ccb_h.flags & CAM_CDB_POINTER) @@ -1119,7 +1153,7 @@ mpi3mr_action_scsiio(struct mpi3mr_cam_softc *cam_sc, union ccb *ccb) return; case CAM_DATA_VADDR: case CAM_DATA_BIO: - if (csio->dxfer_len > (MPI3MR_SG_DEPTH * MPI3MR_4K_PGSZ)) { + if (csio->dxfer_len > (sc->max_sgl_entries * PAGE_SIZE)) { mpi3mr_set_ccbstatus(ccb, CAM_REQ_TOO_BIG); mpi3mr_release_command(cm); xpt_done(ccb); @@ -1270,8 +1304,10 @@ mpi3mr_cam_action(struct cam_sim *sim, union ccb *ccb) { struct mpi3mr_cam_softc *cam_sc; struct mpi3mr_target *targ; + struct mpi3mr_softc *sc; cam_sc = cam_sim_softc(sim); + sc = cam_sc->sc; mpi3mr_dprint(cam_sc->sc, MPI3MR_TRACE, "ccb func_code 0x%x target id: 0x%x\n", ccb->ccb_h.func_code, ccb->ccb_h.target_id); @@ -1322,7 +1358,7 @@ mpi3mr_cam_action(struct cam_sim *sim, union ccb *ccb) "PCI device target_id: %u max io size: %u\n", ccb->ccb_h.target_id, cpi->maxio); } else { - cpi->maxio = PAGE_SIZE * (MPI3MR_SG_DEPTH - 1); + cpi->maxio = PAGE_SIZE * (sc->max_sgl_entries - 1); } mpi3mr_set_ccbstatus(ccb, CAM_REQ_CMP); break; @@ -1560,7 +1596,7 @@ mpi3mr_sastopochg_evt_debug(struct mpi3mr_softc *sc, if (!handle) continue; phy_number = event_data->StartPhyNum + i; - reason_code = event_data->PhyEntry[i].Status & + reason_code = event_data->PhyEntry[i].PhyStatus & MPI3_EVENT_SAS_TOPO_PHY_RC_MASK; switch (reason_code) { case MPI3_EVENT_SAS_TOPO_PHY_RC_TARG_NOT_RESPONDING: @@ -1613,7 +1649,7 @@ mpi3mr_process_sastopochg_evt(struct mpi3mr_softc *sc, struct mpi3mr_fw_event_wo continue; target->link_rate = link_rate; - reason_code = event_data->PhyEntry[i].Status & + reason_code = event_data->PhyEntry[i].PhyStatus & MPI3_EVENT_SAS_TOPO_PHY_RC_MASK; switch (reason_code) { @@ -1638,14 +1674,6 @@ mpi3mr_process_sastopochg_evt(struct mpi3mr_softc *sc, struct mpi3mr_fw_event_wo return; } -static inline void -mpi3mr_logdata_evt_bh(struct mpi3mr_softc *sc, - struct mpi3mr_fw_event_work *fwevt) -{ - mpi3mr_app_save_logdata(sc, fwevt->event_data, - fwevt->event_data_size); -} - static void mpi3mr_pcietopochg_evt_debug(struct mpi3mr_softc *sc, Mpi3EventDataPcieTopologyChangeList_t *event_data) @@ -1802,9 +1830,9 @@ out: int mpi3mr_remove_device_from_os(struct mpi3mr_softc *sc, U16 handle) { - U32 i = 0; int retval = 0; struct mpi3mr_target *target; + unsigned int target_outstanding; mpi3mr_dprint(sc, MPI3MR_EVENT, "Removing Device (dev_handle: %d)\n", handle); @@ -1822,17 +1850,18 @@ int mpi3mr_remove_device_from_os(struct mpi3mr_softc *sc, U16 handle) target->flags |= MPI3MRSAS_TARGET_INREMOVAL; - while (mpi3mr_atomic_read(&target->outstanding) && (i < 30)) { - i++; - if (!(i % 2)) { - mpi3mr_dprint(sc, MPI3MR_INFO, - "[%2d]waiting for " - "waiting for outstanding commands to complete on target: %d\n", - i, target->per_id); - } - DELAY(1000 * 1000); - } - + target_outstanding = mpi3mr_atomic_read(&target->outstanding); + if (target_outstanding) { + mpi3mr_dprint(sc, MPI3MR_ERROR, "there are [%2d] outstanding IOs on target: %d " + "Poll reply queue once\n", target_outstanding, target->per_id); + mpi3mr_poll_pend_io_completions(sc); + target_outstanding = mpi3mr_atomic_read(&target->outstanding); + if (target_outstanding) + target_outstanding = mpi3mr_atomic_read(&target->outstanding); + mpi3mr_dprint(sc, MPI3MR_ERROR, "[%2d] outstanding IOs present on target: %d " + "despite poll\n", target_outstanding, target->per_id); + } + if (target->exposed_to_os && !sc->reset_in_progress) { mpi3mr_rescan_target(sc, target); mpi3mr_dprint(sc, MPI3MR_INFO, @@ -1848,18 +1877,16 @@ out: void mpi3mr_remove_device_from_list(struct mpi3mr_softc *sc, struct mpi3mr_target *target, bool must_delete) { + if ((must_delete == false) && + (target->state != MPI3MR_DEV_REMOVE_HS_COMPLETED)) + return; + mtx_lock_spin(&sc->target_lock); - if ((target->state == MPI3MR_DEV_REMOVE_HS_STARTED) || - (must_delete == true)) { - TAILQ_REMOVE(&sc->cam_sc->tgt_list, target, tgt_next); - target->state = MPI3MR_DEV_DELETED; - } + TAILQ_REMOVE(&sc->cam_sc->tgt_list, target, tgt_next); mtx_unlock_spin(&sc->target_lock); - if (target->state == MPI3MR_DEV_DELETED) { - free(target, M_MPI3MR); - target = NULL; - } + free(target, M_MPI3MR); + target = NULL; return; } @@ -1999,11 +2026,6 @@ mpi3mr_fw_work(struct mpi3mr_softc *sc, struct mpi3mr_fw_event_work *fw_event) mpi3mr_process_pcietopochg_evt(sc, fw_event); break; } - case MPI3_EVENT_LOG_DATA: - { - mpi3mr_logdata_evt_bh(sc, fw_event); - break; - } default: mpi3mr_dprint(sc, MPI3MR_TRACE,"Unhandled event 0x%0X\n", fw_event->event); @@ -2064,12 +2086,6 @@ mpi3mr_cam_attach(struct mpi3mr_softc *sc) mpi3mr_dprint(sc, MPI3MR_XINFO, "Starting CAM Attach\n"); cam_sc = malloc(sizeof(struct mpi3mr_cam_softc), M_MPI3MR, M_WAITOK|M_ZERO); - if (!cam_sc) { - mpi3mr_dprint(sc, MPI3MR_ERROR, - "Failed to allocate memory for controller CAM instance\n"); - return (ENOMEM); - } - cam_sc->maxtargets = sc->facts.max_perids + 1; TAILQ_INIT(&cam_sc->tgt_list); diff --git a/sys/dev/mpi3mr/mpi3mr_cam.h b/sys/dev/mpi3mr/mpi3mr_cam.h index 4f3ce47751e9..a6c41226b2e5 100644 --- a/sys/dev/mpi3mr/mpi3mr_cam.h +++ b/sys/dev/mpi3mr/mpi3mr_cam.h @@ -1,7 +1,7 @@ /* * SPDX-License-Identifier: BSD-2-Clause * - * Copyright (c) 2020-2023, Broadcom Inc. All rights reserved. + * Copyright (c) 2020-2025, Broadcom Inc. All rights reserved. * Support: <fbsd-storage-driver.pdl@broadcom.com> * * Authors: Sumit Saxena <sumit.saxena@broadcom.com> @@ -121,6 +121,7 @@ struct mpi3mr_target { struct mpi3mr_throttle_group_info *throttle_group; uint64_t q_depth; enum mpi3mr_target_state state; + uint16_t ws_len; }; struct mpi3mr_cam_softc { diff --git a/sys/dev/mpi3mr/mpi3mr_pci.c b/sys/dev/mpi3mr/mpi3mr_pci.c index 1548d577a726..b436541b26c0 100644 --- a/sys/dev/mpi3mr/mpi3mr_pci.c +++ b/sys/dev/mpi3mr/mpi3mr_pci.c @@ -1,7 +1,7 @@ /* * SPDX-License-Identifier: BSD-2-Clause * - * Copyright (c) 2020-2023, Broadcom Inc. All rights reserved. + * Copyright (c) 2020-2025, Broadcom Inc. All rights reserved. * Support: <fbsd-storage-driver.pdl@broadcom.com> * * Authors: Sumit Saxena <sumit.saxena@broadcom.com> @@ -178,12 +178,15 @@ mpi3mr_get_tunables(struct mpi3mr_softc *sc) sc->reset_in_progress = 0; sc->reset.type = 0; sc->iot_enable = 1; + sc->max_sgl_entries = maxphys / PAGE_SIZE; + /* * Grab the global variables. */ TUNABLE_INT_FETCH("hw.mpi3mr.debug_level", &sc->mpi3mr_debug); TUNABLE_INT_FETCH("hw.mpi3mr.ctrl_reset", &sc->reset.type); TUNABLE_INT_FETCH("hw.mpi3mr.iot_enable", &sc->iot_enable); + TUNABLE_INT_FETCH("hw.mpi3mr.max_sgl_entries", &sc->max_sgl_entries); /* Grab the unit-instance variables */ snprintf(tmpstr, sizeof(tmpstr), "dev.mpi3mr.%d.debug_level", @@ -197,6 +200,10 @@ mpi3mr_get_tunables(struct mpi3mr_softc *sc) snprintf(tmpstr, sizeof(tmpstr), "dev.mpi3mr.%d.iot_enable", device_get_unit(sc->mpi3mr_dev)); TUNABLE_INT_FETCH(tmpstr, &sc->iot_enable); + + snprintf(tmpstr, sizeof(tmpstr), "dev.mpi3mr.%d.max_sgl_entries", + device_get_unit(sc->mpi3mr_dev)); + TUNABLE_INT_FETCH(tmpstr, &sc->max_sgl_entries); } static struct mpi3mr_ident * @@ -325,6 +332,13 @@ mpi3mr_ich_startup(void *arg) mtx_unlock(&sc->mpi3mr_mtx); + error = mpi3mr_kproc_create(mpi3mr_timestamp_thread, sc, + &sc->timestamp_thread_proc, 0, 0, + "mpi3mr_timestamp_thread%d", + device_get_unit(sc->mpi3mr_dev)); + if (error) + device_printf(sc->mpi3mr_dev, "Error %d starting timestamp thread\n", error); + error = mpi3mr_kproc_create(mpi3mr_watchdog_thread, sc, &sc->watchdog_thread, 0, 0, "mpi3mr_watchdog%d", device_get_unit(sc->mpi3mr_dev)); @@ -443,7 +457,16 @@ mpi3mr_pci_attach(device_t dev) sc->mpi3mr_dev = dev; mpi3mr_get_tunables(sc); - + + if (sc->max_sgl_entries > MPI3MR_MAX_SGL_ENTRIES) + sc->max_sgl_entries = MPI3MR_MAX_SGL_ENTRIES; + else if (sc->max_sgl_entries < MPI3MR_DEFAULT_SGL_ENTRIES) + sc->max_sgl_entries = MPI3MR_DEFAULT_SGL_ENTRIES; + else { + sc->max_sgl_entries /= MPI3MR_DEFAULT_SGL_ENTRIES; + sc->max_sgl_entries *= MPI3MR_DEFAULT_SGL_ENTRIES; + } + if ((error = mpi3mr_initialize_ioc(sc, MPI3MR_INIT_TYPE_INIT)) != 0) { mpi3mr_dprint(sc, MPI3MR_ERROR, "FW initialization failed\n"); goto load_failed; @@ -458,7 +481,7 @@ mpi3mr_pci_attach(device_t dev) mpi3mr_dprint(sc, MPI3MR_ERROR, "CAM attach failed\n"); goto load_failed; } - + sc->mpi3mr_ich.ich_func = mpi3mr_ich_startup; sc->mpi3mr_ich.ich_arg = sc; if (config_intrhook_establish(&sc->mpi3mr_ich) != 0) { @@ -648,10 +671,26 @@ mpi3mr_pci_detach(device_t dev) mtx_lock(&sc->reset_mutex); sc->mpi3mr_flags |= MPI3MR_FLAGS_SHUTDOWN; + if (sc->timestamp_thread_active) + wakeup(&sc->timestamp_chan); + if (sc->watchdog_thread_active) wakeup(&sc->watchdog_chan); mtx_unlock(&sc->reset_mutex); + i = 0; + while (sc->timestamp_thread_active && (i < 180)) { + i++; + if (!(i % 5)) { + mpi3mr_dprint(sc, MPI3MR_INFO, + "[%2d]waiting for " + "timestamp thread to quit reset %d\n", i, + sc->timestamp_thread_active); + } + pause("mpi3mr_shutdown", hz); + } + + i = 0; while (sc->reset_in_progress && (i < PEND_IOCTLS_COMP_WAIT_TIME)) { i++; if (!(i % 5)) { |