diff options
Diffstat (limited to 'sys/dev')
101 files changed, 3578 insertions, 1850 deletions
diff --git a/sys/dev/acpi_support/acpi_ibm.c b/sys/dev/acpi_support/acpi_ibm.c index 1221384e7d8a..a5c44b1f81b9 100644 --- a/sys/dev/acpi_support/acpi_ibm.c +++ b/sys/dev/acpi_support/acpi_ibm.c @@ -1449,11 +1449,11 @@ acpi_ibm_eventhandler(struct acpi_ibm_softc *sc, int arg) switch (arg) { /* * XXX "Suspend-to-RAM" here is as opposed to suspend-to-disk, but it is - * fine if our suspend sleep state transition request puts us in s2idle - * instead of suspend-to-RAM. + * fine if our suspend sleep state transition request puts us in + * suspend-to-idle instead of actual suspend-to-RAM. */ case IBM_EVENT_SUSPEND_TO_RAM: - power_pm_suspend(POWER_SSTATE_TRANSITION_SUSPEND); + (void)power_pm_suspend(POWER_TRANSITION_SUSPEND); break; case IBM_EVENT_BLUETOOTH: diff --git a/sys/dev/acpi_support/acpi_panasonic.c b/sys/dev/acpi_support/acpi_panasonic.c index 8fea47ee45e8..5f54ca07c5a6 100644 --- a/sys/dev/acpi_support/acpi_panasonic.c +++ b/sys/dev/acpi_support/acpi_panasonic.c @@ -233,7 +233,9 @@ acpi_panasonic_shutdown(device_t dev) /* Mute the main audio during reboot to prevent static burst to speaker. */ sc = device_get_softc(dev); mute = 1; + ACPI_SERIAL_BEGIN(panasonic); hkey_sound_mute(sc->handle, HKEY_SET, &mute); + ACPI_SERIAL_END(panasonic); return (0); } diff --git a/sys/dev/acpica/acpi.c b/sys/dev/acpica/acpi.c index bdc197a4fb59..5cb0afa581ca 100644 --- a/sys/dev/acpica/acpi.c +++ b/sys/dev/acpica/acpi.c @@ -666,18 +666,19 @@ acpi_attach(device_t dev) /* * Pick the first valid sleep type for the sleep button default. If that - * type was hibernate and we support s2idle, set it to that. The sleep - * button prefers s2mem instead of s2idle at the moment as s2idle may not - * yet work reliably on all machines. In the future, we should set this to - * s2idle when ACPI_FADT_LOW_POWER_S0 is set. + * type was hibernate and we support suspend_to_idle , set it to that. The + * sleep button prefers fw_suspend instead of suspend_to_idle at the moment + * as suspend_to_idle may not yet work reliably on all machines. In the + * future, we should set this to suspend_to_idle when + * ACPI_FADT_LOW_POWER_S0 is set. */ sc->acpi_sleep_button_stype = POWER_STYPE_UNKNOWN; - for (stype = POWER_STYPE_STANDBY; stype <= POWER_STYPE_HIBERNATE; stype++) + for (stype = POWER_STYPE_STANDBY; stype <= POWER_STYPE_FW_HIBERNATE; stype++) if (acpi_supported_stypes[stype]) { sc->acpi_sleep_button_stype = stype; break; } - if (sc->acpi_sleep_button_stype == POWER_STYPE_HIBERNATE || + if (sc->acpi_sleep_button_stype == POWER_STYPE_FW_HIBERNATE || sc->acpi_sleep_button_stype == POWER_STYPE_UNKNOWN) { if (acpi_supported_stypes[POWER_STYPE_SUSPEND_TO_IDLE]) sc->acpi_sleep_button_stype = POWER_STYPE_SUSPEND_TO_IDLE; @@ -743,7 +744,7 @@ acpi_attach(device_t dev) OID_AUTO, "lid_switch_state", CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, &sc->acpi_lid_switch_stype, 0, acpi_stype_sysctl, "A", - "Lid ACPI sleep state. Set to s2idle or s2mem if you want to suspend " + "Lid ACPI sleep state. Set to suspend_to_idle or fw_suspend if you want to suspend " "your laptop when you close the lid."); SYSCTL_ADD_PROC(&sc->acpi_sysctl_ctx, SYSCTL_CHILDREN(sc->acpi_sysctl_tree), OID_AUTO, "suspend_state", CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, @@ -816,9 +817,9 @@ acpi_stype_to_sstate(struct acpi_softc *sc, enum power_stype stype) return (ACPI_STATE_S0); case POWER_STYPE_STANDBY: return (sc->acpi_standby_sx); - case POWER_STYPE_SUSPEND_TO_MEM: + case POWER_STYPE_FW_SUSPEND: return (ACPI_STATE_S3); - case POWER_STYPE_HIBERNATE: + case POWER_STYPE_FW_HIBERNATE: return (ACPI_STATE_S4); case POWER_STYPE_POWEROFF: return (ACPI_STATE_S5); @@ -851,9 +852,9 @@ acpi_sstate_to_stype(int sstate) case ACPI_STATE_S2: return (POWER_STYPE_STANDBY); case ACPI_STATE_S3: - return (POWER_STYPE_SUSPEND_TO_MEM); + return (POWER_STYPE_FW_SUSPEND); case ACPI_STATE_S4: - return (POWER_STYPE_HIBERNATE); + return (POWER_STYPE_FW_HIBERNATE); case ACPI_STATE_S5: return (POWER_STYPE_POWEROFF); } @@ -2154,9 +2155,9 @@ acpi_device_pwr_for_sleep_sxd(device_t dev, ACPI_HANDLE handle, int state, * we are currently entering (sc->acpi_stype is set in acpi_EnterSleepState * before the ACPI bus gets suspended, and thus before this function is called). * - * If entering s2idle, we will try to enter whichever D-state we would've been - * transitioning to in S3. If we are entering an ACPI S-state, we evaluate the - * relevant _SxD state instead (ACPI 7.3.16 - 7.3.19). + * If entering suspend_to_idle, we will try to enter whichever D-state we + * would've been transitioning to in S3. If we are entering an ACPI S-state, we + * evaluate the relevant _SxD state instead (ACPI 7.3.16 - 7.3.19). */ int acpi_device_pwr_for_sleep(device_t bus, device_t dev, int *dstate) @@ -3723,8 +3724,8 @@ acpi_EnterSleepState(struct acpi_softc *sc, enum power_stype stype) case POWER_STYPE_STANDBY: do_standby(sc, &slp_state, intr); break; - case POWER_STYPE_SUSPEND_TO_MEM: - case POWER_STYPE_HIBERNATE: + case POWER_STYPE_FW_SUSPEND: + case POWER_STYPE_FW_HIBERNATE: do_sleep(sc, &slp_state, intr, acpi_sstate); break; case POWER_STYPE_SUSPEND_TO_IDLE: @@ -4609,7 +4610,7 @@ acpi_sleep_state_sysctl(SYSCTL_HANDLER_ARGS) static int acpi_stype_sysctl(SYSCTL_HANDLER_ARGS) { - char name[10]; + char name[POWER_STYPE_NAME_LEN]; int err; int sstate; enum power_stype new_stype, old_stype; @@ -5064,7 +5065,7 @@ acpi_pm_func(u_long cmd, void *arg, enum power_stype stype) error = EINVAL; goto out; } - if (ACPI_FAILURE(acpi_EnterSleepState(sc, stype))) + if (ACPI_FAILURE(acpi_ReqSleepState(sc, stype))) error = ENXIO; break; default: diff --git a/sys/dev/acpica/acpi_spmc.c b/sys/dev/acpica/acpi_spmc.c index 03944800327d..611a9a09a6eb 100644 --- a/sys/dev/acpica/acpi_spmc.c +++ b/sys/dev/acpica/acpi_spmc.c @@ -5,6 +5,10 @@ * * This software was developed by Aymeric Wibo <obiwac@freebsd.org> * under sponsorship from the FreeBSD Foundation. + * + * Portions of this software were developed by Olivier Certner + * <olce@FreeBSD.org> at Kumacom SARL under sponsorship from the FreeBSD + * Foundation. */ #include <sys/param.h> @@ -22,126 +26,199 @@ #include <dev/acpica/acpivar.h> + /* Hooks for the ACPI CA debugging infrastructure */ #define _COMPONENT ACPI_SPMC ACPI_MODULE_NAME("SPMC") -static SYSCTL_NODE(_debug_acpi, OID_AUTO, spmc, CTLFLAG_RD | CTLFLAG_MPSAFE, - NULL, "SPMC debugging"); - static char *spmc_ids[] = { "PNP0D80", NULL }; -enum intel_dsm_index { - DSM_ENUM_FUNCTIONS = 0, - DSM_GET_DEVICE_CONSTRAINTS = 1, - DSM_GET_CRASH_DUMP_DEVICE = 2, - DSM_DISPLAY_OFF_NOTIF = 3, - DSM_DISPLAY_ON_NOTIF = 4, - DSM_ENTRY_NOTIF = 5, - DSM_EXIT_NOTIF = 6, - /* Only for Microsoft DSM set. */ - DSM_MODERN_ENTRY_NOTIF = 7, - DSM_MODERN_EXIT_NOTIF = 8, - DSM_MODERN_TURN_ON_DISPLAY = 9, -}; +/* sysctl(8) knobs */ +static SYSCTL_NODE(_debug_acpi, OID_AUTO, spmc, CTLFLAG_RD | CTLFLAG_MPSAFE, + NULL, "SPMC debugging"); -enum amd_dsm_index { - AMD_DSM_ENUM_FUNCTIONS = 0, - AMD_DSM_GET_DEVICE_CONSTRAINTS = 1, - AMD_DSM_ENTRY_NOTIF = 2, - AMD_DSM_EXIT_NOTIF = 3, - AMD_DSM_DISPLAY_OFF_NOTIF = 4, - AMD_DSM_DISPLAY_ON_NOTIF = 5, -}; +int8_t dsm_intel_revision = -15; +SYSCTL_S8(_debug_acpi_spmc, OID_AUTO, intel_dsm_revision, CTLFLAG_RW, + &dsm_intel_revision, 0, + "Revision to use with the Intel DSM " + "(negative: auto, try from 0 to minus the value)"); -enum dsm_set_flags { - DSM_SET_INTEL = 1 << 0, - DSM_SET_MS = 1 << 1, - DSM_SET_AMD = 1 << 2, -}; +int8_t dsm_amd_revision = -15; +SYSCTL_S8(_debug_acpi_spmc, OID_AUTO, amd_dsm_revision, CTLFLAG_RW, + &dsm_amd_revision, 0, + "Revision to use with the AMD DSM " + "(negative: auto, try from 0 to minus the value)"); + +int8_t dsm_ms_revision = -15; +SYSCTL_S8(_debug_acpi_spmc, OID_AUTO, ms_dsm_revision, CTLFLAG_RW, + &dsm_ms_revision, 0, + "Revision to use with the Microsoft DSM " + "(negative: auto, try from 0 to minus the value)"); + +static int verbose; +SYSCTL_INT(_debug_acpi_spmc, OID_AUTO, verbose, CTLFLAG_RW, + &verbose, 0, "acpi_spmc(4) verbosity"); + +#define VERBOSE() (verbose || bootverbose) -struct dsm_set { - enum dsm_set_flags flag; +static bool force_call_expected_functions; +SYSCTL_BOOL(_debug_acpi_spmc, OID_AUTO, always_call_expected_functions, + CTLFLAG_RW, &force_call_expected_functions, 0, + "Call all expected functions on a present DSM, even those not enumerated."); + +/* Conversion of an index to a mask. */ +#define IDX_TO_BIT(idx) (1ull << (idx)) + +/* List of supported DSMs. */ +#define DSM_INTEL 0 +#define DSM_MS 1 +#define DSM_AMD 2 + +/* List of DSM function indices. */ +#define DSM_ENUM_FUNCTIONS 0 /* Common to all DSMs */ +#define DSM_GET_DEVICE_CONSTRAINTS 1 /* AMD and Intel, MS N/A */ + +#define DSM_GET_CRASH_DUMP_DEVICE 2 /* Intel, MS N/A */ +#define DSM_INTEL_MS_DISPLAY_OFF_NOTIF 3 +#define DSM_INTEL_MS_DISPLAY_ON_NOTIF 4 +#define DSM_INTEL_MS_LPI_ENTRY_NOTIF 5 +#define DSM_INTEL_MS_LPI_EXIT_NOTIF 6 + +#define DSM_MS_SLEEP_ENTRY_NOTIF 7 +#define DSM_MS_SLEEP_EXIT_NOTIF 8 +#define DSM_MS_TURN_ON_DISPLAY 9 + +#define DSM_AMD_LPI_ENTRY_NOTIF 2 +#define DSM_AMD_LPI_EXIT_NOTIF 3 +#define DSM_AMD_DISPLAY_OFF_NOTIF 4 +#define DSM_AMD_DISPLAY_ON_NOTIF 5 + + +/* Descriptors for the DSMs we support. */ + +struct dsm_desc { const char *name; - int revision; - struct uuid uuid; - uint64_t dsms_supported; - uint64_t dsms_expected; - uint64_t extra_dsms; + struct uuid uuid; + /* + * Points to an integer which, if negative, indicates to auto-detect the + * revision by trying all revisions between 0 and minus the value, else + * is the sole revision to try. + */ + const int8_t *revision_spec; + uint64_t expected_functions; + uint64_t extra_functions; + /* Human-friendly names of known functions. */ + const char *const *function_names; + int function_names_nb; + /* Index in the dsms[] array below. */ + int index; }; -static struct dsm_set intel_dsm_set = { - .flag = DSM_SET_INTEL, +static const char *const dsm_intel_function_names[] = { + [DSM_GET_DEVICE_CONSTRAINTS] = "DEVICE_CONSTRAINTS", + [DSM_GET_CRASH_DUMP_DEVICE] = "CRASH_DUMP_DEVICE", + [DSM_INTEL_MS_DISPLAY_OFF_NOTIF] = "DISPLAY_OFF", + [DSM_INTEL_MS_DISPLAY_ON_NOTIF] = "DISPLAY_ON", + [DSM_INTEL_MS_LPI_ENTRY_NOTIF] = "LPI_ENTRY", + [DSM_INTEL_MS_LPI_EXIT_NOTIF] = "LPI_EXIT", +}; + +static const struct dsm_desc dsm_intel = { + .index = DSM_INTEL, .name = "Intel", - /* - * XXX Linux uses 1 for the revision on Intel DSMs, but doesn't explain - * why. The commit that introduces this links to a document mentioning - * revision 0, so default this to 0. - * - * The debug.acpi.spmc.intel_dsm_revision sysctl may be used to configure - * this just in case. - */ - .revision = 0, .uuid = { /* c4eb40a0-6cd2-11e2-bcfd-0800200c9a66 */ 0xc4eb40a0, 0x6cd2, 0x11e2, 0xbc, 0xfd, - {0x08, 0x00, 0x20, 0x0c, 0x9a, 0x66}, + {0x08, 0x00, 0x20, 0x0c, 0x9a, 0x66} }, - .dsms_expected = (1 << DSM_GET_DEVICE_CONSTRAINTS) | - (1 << DSM_DISPLAY_OFF_NOTIF) | (1 << DSM_DISPLAY_ON_NOTIF) | - (1 << DSM_ENTRY_NOTIF) | (1 << DSM_EXIT_NOTIF), + .revision_spec = &dsm_intel_revision, + .expected_functions = + IDX_TO_BIT(DSM_GET_DEVICE_CONSTRAINTS) | + IDX_TO_BIT(DSM_INTEL_MS_DISPLAY_OFF_NOTIF) | + IDX_TO_BIT(DSM_INTEL_MS_DISPLAY_ON_NOTIF) | + IDX_TO_BIT(DSM_INTEL_MS_LPI_ENTRY_NOTIF) | + IDX_TO_BIT(DSM_INTEL_MS_LPI_EXIT_NOTIF), + .extra_functions = + IDX_TO_BIT(DSM_GET_CRASH_DUMP_DEVICE), /* Not used. */ + .function_names = dsm_intel_function_names, + .function_names_nb = nitems(dsm_intel_function_names), }; -SYSCTL_INT(_debug_acpi_spmc, OID_AUTO, intel_dsm_revision, CTLFLAG_RW, - &intel_dsm_set.revision, 0, - "Revision to use when evaluating Intel SPMC DSMs"); +static const char *const dsm_ms_function_names[] = { + [DSM_INTEL_MS_DISPLAY_OFF_NOTIF] = "DISPLAY_OFF", + [DSM_INTEL_MS_DISPLAY_ON_NOTIF] = "DISPLAY_ON", + [DSM_INTEL_MS_LPI_ENTRY_NOTIF] = "LPI_ENTRY", + [DSM_INTEL_MS_LPI_EXIT_NOTIF] = "LPI_EXIT", + [DSM_MS_SLEEP_ENTRY_NOTIF] = "SLEEP_ENTRY", + [DSM_MS_SLEEP_EXIT_NOTIF] = "SLEEP_EXIT", + [DSM_MS_TURN_ON_DISPLAY] = "TURN_ON", +}; -static struct dsm_set ms_dsm_set = { - .flag = DSM_SET_MS, +static const struct dsm_desc dsm_ms = { + .index = DSM_MS, .name = "Microsoft", - .revision = 0, .uuid = { /* 11e00d56-ce64-47ce-837b-1f898f9aa461 */ 0x11e00d56, 0xce64, 0x47ce, 0x83, 0x7b, - {0x1f, 0x89, 0x8f, 0x9a, 0xa4, 0x61}, + {0x1f, 0x89, 0x8f, 0x9a, 0xa4, 0x61} }, - .dsms_expected = (1 << DSM_DISPLAY_OFF_NOTIF) | - (1 << DSM_DISPLAY_ON_NOTIF) | (1 << DSM_ENTRY_NOTIF) | - (1 << DSM_EXIT_NOTIF) | (1 << DSM_MODERN_ENTRY_NOTIF) | - (1 << DSM_MODERN_EXIT_NOTIF), - .extra_dsms = (1 << DSM_MODERN_TURN_ON_DISPLAY), + .revision_spec = &dsm_ms_revision, + .expected_functions = + IDX_TO_BIT(DSM_INTEL_MS_DISPLAY_OFF_NOTIF) | + IDX_TO_BIT(DSM_INTEL_MS_DISPLAY_ON_NOTIF) | + IDX_TO_BIT(DSM_INTEL_MS_LPI_ENTRY_NOTIF) | + IDX_TO_BIT(DSM_INTEL_MS_LPI_EXIT_NOTIF) | + IDX_TO_BIT(DSM_MS_SLEEP_ENTRY_NOTIF) | + IDX_TO_BIT(DSM_MS_SLEEP_EXIT_NOTIF), + .extra_functions = + IDX_TO_BIT(DSM_MS_TURN_ON_DISPLAY), + .function_names = dsm_ms_function_names, + .function_names_nb = nitems(dsm_ms_function_names), +}; + +static const char *const dsm_amd_function_names[] = { + [DSM_GET_DEVICE_CONSTRAINTS] = "DEVICE_CONSTRAINTS", + [DSM_AMD_DISPLAY_OFF_NOTIF] = "DISPLAY_OFF", + [DSM_AMD_DISPLAY_ON_NOTIF] = "DISPLAY_ON", + [DSM_AMD_LPI_ENTRY_NOTIF] = "LPI_ENTRY", + [DSM_AMD_LPI_EXIT_NOTIF] = "LPI_EXIT", }; -static struct dsm_set amd_dsm_set = { - .flag = DSM_SET_AMD, +static const struct dsm_desc dsm_amd = { + .index = DSM_AMD, .name = "AMD", - /* - * XXX Linux uses 0 for the revision on AMD DSMs, but at least on the - * Framework 13 AMD 7040 series, the enum functions DSM only returns a - * function mask that covers all the DSMs we need to call when called - * with revision 2. - * - * The debug.acpi.spmc.amd_dsm_revision sysctl may be used to configure - * this just in case. - */ - .revision = 2, .uuid = { /* e3f32452-febc-43ce-9039-932122d37721 */ 0xe3f32452, 0xfebc, 0x43ce, 0x90, 0x39, - {0x93, 0x21, 0x22, 0xd3, 0x77, 0x21}, + {0x93, 0x21, 0x22, 0xd3, 0x77, 0x21} }, - .dsms_expected = (1 << AMD_DSM_GET_DEVICE_CONSTRAINTS) | - (1 << AMD_DSM_ENTRY_NOTIF) | (1 << AMD_DSM_EXIT_NOTIF) | - (1 << AMD_DSM_DISPLAY_OFF_NOTIF) | (1 << AMD_DSM_DISPLAY_ON_NOTIF), + .revision_spec = &dsm_amd_revision, + .expected_functions = + IDX_TO_BIT(DSM_GET_DEVICE_CONSTRAINTS) | + IDX_TO_BIT(DSM_AMD_DISPLAY_OFF_NOTIF) | + IDX_TO_BIT(DSM_AMD_DISPLAY_ON_NOTIF) | + IDX_TO_BIT(DSM_AMD_LPI_ENTRY_NOTIF) | + IDX_TO_BIT(DSM_AMD_LPI_EXIT_NOTIF), + .function_names = dsm_amd_function_names, + .function_names_nb = nitems(dsm_amd_function_names), }; -SYSCTL_INT(_debug_acpi_spmc, OID_AUTO, amd_dsm_revision, CTLFLAG_RW, - &amd_dsm_set.revision, 0, "Revision to use when evaluating AMD SPMC DSMs"); +static const struct dsm_desc *const dsms[] = { + [DSM_INTEL] = &dsm_intel, + [DSM_MS] = &dsm_ms, + [DSM_AMD] = &dsm_amd, +}; -union dsm_index { - int i; - enum intel_dsm_index regular; - enum amd_dsm_index amd; +/* Per DSM probed information. */ +struct dsm_info { + uint64_t supported_functions; + /* + * Revisions are zero or a positive number. Strictly speaking, next + * field should be a 'uint64_t' as per the ACPI spec, but our ACPI DSM + * interface takes an 'int' and anyway actual revision numbers never + * even exceed the limits of a 'uint8_t'. + */ + uint8_t revision; }; struct acpi_spmc_constraint { @@ -150,32 +227,179 @@ struct acpi_spmc_constraint { int min_d_state; ACPI_HANDLE handle; - /* Unused, spec only. */ + /* Intel only. Currently filled but unused. */ uint64_t lpi_uid; uint64_t min_dev_specific_state; - /* Unused, AMD only. */ + /* AMD only. Currently filled but unused. */ uint64_t function_states; }; struct acpi_spmc_softc { device_t dev; ACPI_HANDLE handle; - ACPI_OBJECT *obj; - enum dsm_set_flags dsm_sets; + struct dsm_info dsms_info[nitems(dsms)]; struct eventhandler_entry *eh_suspend; struct eventhandler_entry *eh_resume; - bool constraints_populated; +#ifdef INVARIANTS + bool get_constraints_succeeded; +#endif size_t constraint_count; struct acpi_spmc_constraint *constraints; }; -static void acpi_spmc_check_dsm_set(struct acpi_spmc_softc *sc, - ACPI_HANDLE handle, struct dsm_set *dsm_set); -static int acpi_spmc_get_constraints(device_t dev); -static void acpi_spmc_free_constraints(struct acpi_spmc_softc *sc); + +static const struct dsm_desc * +resolve_dsm(int dsm_index) +{ + MPASS(0 <= dsm_index && dsm_index < nitems(dsms)); + return (dsms[dsm_index]); +} + +static struct dsm_info * +get_dsm_info(struct acpi_spmc_softc *const sc, const int dsm_index) +{ + MPASS(0 <= dsm_index && dsm_index < nitems(dsms)); + return (&sc->dsms_info[dsm_index]); +} + +static const struct dsm_info * +get_const_dsm_info(const struct acpi_spmc_softc *const sc, const int dsm_index) +{ + MPASS(0 <= dsm_index && dsm_index < nitems(dsms)); + return (&sc->dsms_info[dsm_index]); +} + +static const uint64_t +get_supported_functions(const struct acpi_spmc_softc *const sc, + const int dsm_index) +{ + return (get_const_dsm_info(sc, dsm_index)->supported_functions); +} + +static const uint8_t +get_revision(const struct acpi_spmc_softc *const sc, const int dsm_index) +{ + return (get_const_dsm_info(sc, dsm_index)->revision); +} + +static bool +supports_function_bitset(const uint64_t supported_functions, + const int function_index) +{ + return ((supported_functions & IDX_TO_BIT(function_index)) != 0); +} + +static bool +supports_function(const struct acpi_spmc_softc *const sc, const int dsm_index, + const int function_index) +{ + return (supports_function_bitset(get_supported_functions(sc, dsm_index), + function_index)); +} + +static bool +has_dsm_bitset(const uint64_t supported_functions) +{ + /* DSM is supported if bit DSM_ENUM_FUNCTIONS (0) is set. */ + return (supports_function_bitset(supported_functions, + DSM_ENUM_FUNCTIONS)); +} + +static bool +has_dsm(const struct acpi_spmc_softc *const sc, const int dsm_index) +{ + return (has_dsm_bitset(get_supported_functions(sc, dsm_index))); +} + +typedef const char *pbf_get_name_t(const int, const void *const); + +static const char * +pbf_dsm_name(const int dsm_index, const void *const opaque __unused) +{ + return (resolve_dsm(dsm_index)->name); +} + +static const char * +dsm_function_name(const struct dsm_desc *const dsm, const int function_index) +{ + MPASS(function_index >= 0); + if (function_index >= dsm->function_names_nb) + return (NULL); + /* May be NULL. */ + return (dsm->function_names[function_index]); +} + +static const char * +pbf_function_name(const int function_index, const void *const opaque) +{ + return (dsm_function_name(opaque, function_index)); +} + +static int +print_bit_field(char *const buf, const size_t buf_size, + const uint64_t bit_field, const char *const fallback_prefix, + pbf_get_name_t get_name, const void *const opaque) +{ + uint64_t bf = bit_field; + char *const buf_end = buf + buf_size; + char *p = buf; + int ret = 0; + bool one_set = false; + +#define PBF_PRINT(...) \ + do { \ + const __ptrdiff_t rem = MAX(buf_end - p, 0); \ + const int lret = snprintf(p, rem, __VA_ARGS__); \ + \ + MPASS(lret >= 0); \ + p += MIN(lret, rem); \ + ret += lret; \ + } while (0) + + if (bf == 0) { + PBF_PRINT(""); + return (ret); + } + + do { + const int b_idx = ffsll(bf) - 1; + const char *const name = get_name(b_idx, opaque); + + PBF_PRINT(one_set ? "," : "<"); + one_set = true; + if (name != NULL) + PBF_PRINT("%s", name); + else + PBF_PRINT("%s_%d", fallback_prefix, b_idx); + + bf &= ~IDX_TO_BIT(b_idx); + } while (bf != 0); + PBF_PRINT(">"); +#undef PBF_PRINT + + return (ret); +} + +static void +failed_to_call_dsm(const struct acpi_spmc_softc *const sc, + const struct dsm_desc *const dsm, const int function_index) +{ + (void)device_printf(sc->dev, + "Failed to call DSM %s (rev %u) function %s\n", + dsm->name, get_revision(sc, dsm->index), + dsm_function_name(dsm, function_index)); +} + +static void acpi_spmc_probe_dsm(struct acpi_spmc_softc *const sc, + const struct dsm_desc *const dsm); +static void acpi_spmc_dsm_print( + const struct acpi_spmc_softc *const sc, + const struct dsm_desc *const dsm); +static int acpi_spmc_get_constraints(struct acpi_spmc_softc *const sc); +static void acpi_spmc_free_constraints(struct acpi_spmc_softc *const sc); static void acpi_spmc_suspend(device_t dev, enum power_stype stype); static void acpi_spmc_resume(device_t dev, enum power_stype stype); @@ -183,9 +407,7 @@ static void acpi_spmc_resume(device_t dev, enum power_stype stype); static int acpi_spmc_probe(device_t dev) { - char *name; - ACPI_HANDLE handle; - struct acpi_spmc_softc *sc; + char *name; /* Check that this is an enabled device. */ if (acpi_get_type(dev) != ACPI_TYPE_DEVICE || acpi_disabled("spmc")) @@ -194,49 +416,61 @@ acpi_spmc_probe(device_t dev) if (ACPI_ID_PROBE(device_get_parent(dev), dev, spmc_ids, &name) > 0) return (ENXIO); - if (device_get_unit(dev) > 0) { - device_printf(dev, "shouldn't have more than one SPMC"); - return (ENXIO); - } + device_set_desc(dev, "System Power Management Controller"); + + return (BUS_PROBE_DEFAULT); +} - handle = acpi_get_handle(dev); - /* ACPI_ID_PROBE() above cannot succeed without a handle. */ +static int +acpi_spmc_attach(device_t dev) +{ + struct acpi_spmc_softc *const sc = device_get_softc(dev); + const ACPI_HANDLE handle = acpi_get_handle(dev); + int supported_dsms; + char buf[32]; + int error; + + /* + * ACPI_ID_PROBE() in acpi_spmc_probe() cannot succeed without a handle. + */ MPASS(handle != NULL); - sc = device_get_softc(dev); sc->dev = dev; + sc->handle = handle; - /* Check which sets of DSMs are supported. */ - sc->dsm_sets = 0; + supported_dsms = 0; + for (int i = 0; i < nitems(dsms); ++i) { + KASSERT(dsms[i] != NULL, ("%s: Sparse dsms[]!", __func__)); + KASSERT(dsms[i]->index == i, + ("%s: Inconsistent indices for DSM %s", __func__, + dsms[i]->name)); - acpi_spmc_check_dsm_set(sc, handle, &intel_dsm_set); - acpi_spmc_check_dsm_set(sc, handle, &ms_dsm_set); - acpi_spmc_check_dsm_set(sc, handle, &amd_dsm_set); + acpi_spmc_probe_dsm(sc, dsms[i]); + if (has_dsm(sc, i)) + supported_dsms |= IDX_TO_BIT(i); + } - if (sc->dsm_sets == 0) + if (supported_dsms == 0) { + device_printf(dev, "No DSM supported!"); return (ENXIO); + } - device_set_descf(dev, "System Power Management Controller " - "(DSM sets 0x%x)", sc->dsm_sets); - - return (0); -} - -static int -acpi_spmc_attach(device_t dev) -{ - struct acpi_spmc_softc *sc = device_get_softc(dev); - - sc->handle = acpi_get_handle(dev); - if (sc->handle == NULL) - return (ENXIO); + print_bit_field(buf, sizeof(buf), supported_dsms, "DSM", + pbf_dsm_name, NULL); + device_printf(dev, "DSMs supported: %s\n", buf); - sc->constraints_populated = false; - sc->constraint_count = 0; - sc->constraints = NULL; + /* Print supported functions of usable DSMs. */ + for (int i = 0; i < nitems(dsms); ++i) + if (has_dsm(sc, i)) + acpi_spmc_dsm_print(sc, dsms[i]); /* Get device constraints. We can only call this once so do this now. */ - acpi_spmc_get_constraints(dev); + error = acpi_spmc_get_constraints(sc); + if (error != 0) + /* acpi_spmc_get_constraints() takes care of cleaning up. */ + device_printf(dev, + "Could not parse power state constraints (%d), " + "will not check for them before suspend\n", error); sc->eh_suspend = EVENTHANDLER_REGISTER(acpi_post_dev_suspend, acpi_spmc_suspend, dev, 0); @@ -253,44 +487,123 @@ acpi_spmc_detach(device_t dev) EVENTHANDLER_DEREGISTER(acpi_post_dev_suspend, sc->eh_suspend); EVENTHANDLER_DEREGISTER(acpi_pre_dev_resume, sc->eh_resume); - - acpi_spmc_free_constraints(device_get_softc(dev)); + acpi_spmc_free_constraints(sc); return (0); } -static void -acpi_spmc_check_dsm_set(struct acpi_spmc_softc *sc, ACPI_HANDLE handle, - struct dsm_set *dsm_set) +static uint64_t +dsm_missing_functions(const struct dsm_desc *const dsm, + uint64_t supported_functions) { - uint64_t dsms_supported = acpi_DSMQuery(handle, - (uint8_t *)&dsm_set->uuid, dsm_set->revision); - const uint64_t min_dsms = dsm_set->dsms_expected; - const uint64_t max_dsms = min_dsms | dsm_set->extra_dsms; + return (dsm->expected_functions & ~supported_functions); +} +static void +acpi_spmc_dsm_print(const struct acpi_spmc_softc *const sc, + const struct dsm_desc *const dsm) +{ /* - * Check if DSM set supported at all. We do this by checking the - * existence of "enum functions". + * Remove the enumeration function bit, which we do not care about when + * printing which functions are supported and which we do not want to + * report as unknown. */ - if ((dsms_supported & 1) == 0) + const uint64_t supported_functions = ~IDX_TO_BIT(DSM_ENUM_FUNCTIONS) & + get_supported_functions(sc, dsm->index); + const uint64_t missing = dsm_missing_functions(dsm, supported_functions); + const uint64_t unknown = supported_functions & + ~(dsm->expected_functions | dsm->extra_functions); + char buf[128]; + + print_bit_field(buf, sizeof(buf), supported_functions, + "FUNC", pbf_function_name, dsm); + device_printf(sc->dev, + "DSM %s, revision %d: Supported functions: %#" PRIx64 "%s\n", + dsm->name, get_revision(sc, dsm->index), supported_functions, buf); + + if (VERBOSE() && missing != 0) { + print_bit_field(buf, sizeof(buf), missing, "FUNC", + pbf_function_name, dsm); + device_printf(sc->dev, "DSM %s: Does not enumerate expected " + "functions %#" PRIx64 "%s. Will skip calling them.\n", + dsm->name, missing, buf); + } + + if (VERBOSE() && unknown != 0) { + print_bit_field(buf, sizeof(buf), unknown, "FUNC", + pbf_function_name, dsm); + device_printf(sc->dev, "DSM %s: Supports more functions than " + "used (%#" PRIx64 "%s), driver might need an upgrade.\n", + dsm->name, unknown, buf); + } +} + +/* Returns whether the DSM is supported (enumeration succeeds). */ +static bool +probe_dsm_revision(const struct acpi_spmc_softc *const sc, + const struct dsm_desc *const dsm, const uint8_t revision, + uint64_t *const supported_functions) +{ + *supported_functions = acpi_DSMQuery(sc->handle, + (const uint8_t *)&dsm->uuid, revision); + return (has_dsm_bitset(*supported_functions)); +} + +static void +set_dsm_revision(struct acpi_spmc_softc *const sc, + const struct dsm_desc *const dsm, const uint8_t revision, + uint64_t supported_functions) +{ + struct dsm_info *const dsm_info = get_dsm_info(sc, dsm->index); + + MPASS(has_dsm_bitset(supported_functions)); + dsm_info->supported_functions = supported_functions; + dsm_info->revision = revision; +} + +static void +acpi_spmc_probe_dsm(struct acpi_spmc_softc *const sc, + const struct dsm_desc *const dsm) +{ + const int8_t revision_spec = *dsm->revision_spec; + uint64_t supported_functions; + + if (revision_spec >= 0) { + /* Specific revision specified. */ + if (probe_dsm_revision(sc, dsm, revision_spec, + &supported_functions)) + set_dsm_revision(sc, dsm, revision_spec, + supported_functions); return; - dsms_supported &= ~1; - dsm_set->dsms_supported = dsms_supported; - sc->dsm_sets |= dsm_set->flag; + } + + /* + * Auto-detect. We try revisions in ascending order, selecting the + * first that has all the functions we expect in the hope to avoid potential + * backwards-compatibility problems, else continuing with higher ones + * but adopting them only if they actually add new functions (it seems + * common that firmwares do not care about the revision, or will return + * the same supported functions after a revision limit). + */ + for (uint8_t revision = 0; revision <= -revision_spec; ++revision) { + if (!probe_dsm_revision(sc, dsm, revision, + &supported_functions)) + continue; + if ((~get_supported_functions(sc, dsm->index) & + supported_functions) == 0) + /* This revision adds no new function, skip it. */ + continue; - if ((dsms_supported & min_dsms) != min_dsms) - device_printf(sc->dev, "DSM set %s does not support expected " - "DSMs (%#" PRIx64 " vs %#" PRIx64 "). " - "Some methods may fail.\n", - dsm_set->name, dsms_supported, min_dsms); + set_dsm_revision(sc, dsm, revision, supported_functions); - if ((dsms_supported & ~max_dsms) != 0) - device_printf(sc->dev, "DSM set %s supports more DSMs than " - "expected (%#" PRIx64 " vs %#" PRIx64 ").\n", dsm_set->name, - dsms_supported, max_dsms); + if (dsm_missing_functions(dsm, ~IDX_TO_BIT(DSM_ENUM_FUNCTIONS) & + supported_functions) == 0) + /* We have all expected functions, bail out. */ + break; + } } static void -acpi_spmc_free_constraints(struct acpi_spmc_softc *sc) +acpi_spmc_free_constraints(struct acpi_spmc_softc *const sc) { for (size_t i = 0; i < sc->constraint_count; i++) free(sc->constraints[i].name, M_TEMP); @@ -301,7 +614,7 @@ acpi_spmc_free_constraints(struct acpi_spmc_softc *sc) } static int -acpi_spmc_get_constraints_spec(struct acpi_spmc_softc *sc, ACPI_OBJECT *object) +acpi_spmc_parse_constraints_intel(struct acpi_spmc_softc *sc, ACPI_OBJECT *object) { struct acpi_spmc_constraint *constraint; int revision; @@ -310,9 +623,6 @@ acpi_spmc_get_constraints_spec(struct acpi_spmc_softc *sc, ACPI_OBJECT *object) ACPI_OBJECT *detail; ACPI_OBJECT *constraint_package; - KASSERT(sc->constraints_populated == false, - ("constraints already populated")); - sc->constraint_count = object->Package.Count; sc->constraints = malloc(sc->constraint_count * sizeof *sc->constraints, M_TEMP, M_WAITOK | M_ZERO); @@ -331,10 +641,6 @@ acpi_spmc_get_constraints_spec(struct acpi_spmc_softc *sc, ACPI_OBJECT *object) name_obj = &constraint_obj->Package.Elements[0]; constraint->name = strdup(name_obj->String.Pointer, M_TEMP); - if (constraint->name == NULL) { - acpi_spmc_free_constraints(sc); - return (ENOMEM); - } detail = &constraint_obj->Package.Elements[2]; /* @@ -343,8 +649,13 @@ acpi_spmc_get_constraints_spec(struct acpi_spmc_softc *sc, ACPI_OBJECT *object) */ revision = detail->Package.Elements[0].Integer.Value; if (revision != 0) { - device_printf(sc->dev, "Unknown revision %d for " - "device constraint detail package\n", revision); + /* Only print this error message once if not verbose. */ + if (VERBOSE() || sc->constraint_count == + object->Package.Count) + device_printf(sc->dev, + "Intel: Unknown revision %d for " + "constraint %zu's detail package\n", + revision, i); sc->constraint_count--; continue; } @@ -359,12 +670,11 @@ acpi_spmc_get_constraints_spec(struct acpi_spmc_softc *sc, ACPI_OBJECT *object) constraint_package->Package.Elements[2].Integer.Value; } - sc->constraints_populated = true; return (0); } static int -acpi_spmc_get_constraints_amd(struct acpi_spmc_softc *sc, ACPI_OBJECT *object) +acpi_spmc_parse_constraints_amd(struct acpi_spmc_softc *sc, ACPI_OBJECT *object) { size_t constraint_count; ACPI_OBJECT *constraint_obj; @@ -372,9 +682,6 @@ acpi_spmc_get_constraints_amd(struct acpi_spmc_softc *sc, ACPI_OBJECT *object) struct acpi_spmc_constraint *constraint; ACPI_OBJECT *name_obj; - KASSERT(sc->constraints_populated == false, - ("constraints already populated")); - /* * First element in the package is unknown. * Second element is the number of device constraints. @@ -384,7 +691,8 @@ acpi_spmc_get_constraints_amd(struct acpi_spmc_softc *sc, ACPI_OBJECT *object) constraints = &object->Package.Elements[2]; if (constraints->Package.Count != constraint_count) { - device_printf(sc->dev, "constraint count mismatch (%d to %zu)\n", + device_printf(sc->dev, + "AMD: Constraints: Count mismatch (%d to %zu)\n", constraints->Package.Count, constraint_count); return (ENXIO); } @@ -397,7 +705,8 @@ acpi_spmc_get_constraints_amd(struct acpi_spmc_softc *sc, ACPI_OBJECT *object) /* Parse the constraint package. */ constraint_obj = &constraints->Package.Elements[i]; if (constraint_obj->Package.Count != 4) { - device_printf(sc->dev, "constraint %zu has %d elements\n", + device_printf(sc->dev, + "AMD: Constraint %zu has %d elements, not 4\n", i, constraint_obj->Package.Count); acpi_spmc_free_constraints(sc); return (ENXIO); @@ -409,10 +718,6 @@ acpi_spmc_get_constraints_amd(struct acpi_spmc_softc *sc, ACPI_OBJECT *object) name_obj = &constraint_obj->Package.Elements[1]; constraint->name = strdup(name_obj->String.Pointer, M_TEMP); - if (constraint->name == NULL) { - acpi_spmc_free_constraints(sc); - return (ENOMEM); - } constraint->function_states = constraint_obj->Package.Elements[2].Integer.Value; @@ -420,52 +725,58 @@ acpi_spmc_get_constraints_amd(struct acpi_spmc_softc *sc, ACPI_OBJECT *object) constraint_obj->Package.Elements[3].Integer.Value; } - sc->constraints_populated = true; return (0); } static int -acpi_spmc_get_constraints(device_t dev) +acpi_spmc_get_constraints(struct acpi_spmc_softc *const sc) { - struct acpi_spmc_softc *sc; - union dsm_index dsm_index; - struct dsm_set *dsm_set; - ACPI_STATUS status; - ACPI_BUFFER result; - ACPI_OBJECT *object; - bool is_amd; - int rv; + const struct dsm_desc *dsm; + ACPI_STATUS status; + ACPI_BUFFER result; + ACPI_OBJECT *object; + int rv; struct acpi_spmc_constraint *constraint; - sc = device_get_softc(dev); - if (sc->constraints_populated) - return (0); - /* The Microsoft DSM set doesn't have this DSM. */ - is_amd = (sc->dsm_sets & DSM_SET_AMD) != 0; - if (is_amd) { - dsm_set = &amd_dsm_set; - dsm_index.amd = AMD_DSM_GET_DEVICE_CONSTRAINTS; - } else { - dsm_set = &intel_dsm_set; - dsm_index.regular = DSM_GET_DEVICE_CONSTRAINTS; - } + MPASS(!sc->get_constraints_succeeded); + /* + * Constraints are not supported by the Microsoft DSM. Since we do not + * expect both Intel and AMD DSMs to be present at once, we only have + * a single storage for common information ('min_d_state'). In case + * some day both happen to be present, warn the user so that he can + * report that condition to us, and somewhat arbitrarily favor the Intel + * one because it at least has a written specification. + */ + if (supports_function(sc, DSM_INTEL, DSM_GET_DEVICE_CONSTRAINTS)) { + dsm = &dsm_intel; + + if (supports_function(sc, DSM_AMD, DSM_GET_DEVICE_CONSTRAINTS)) + device_printf(sc->dev, "Constraints: Both Intel and " + "AMD DSMs support getting them!\n" + "Using constraints from Intel.\nPlease report.\n"); + } else if (supports_function(sc, DSM_AMD, DSM_GET_DEVICE_CONSTRAINTS)) + dsm = &dsm_amd; + else + return (0); - /* XXX It seems like this DSM fails if called more than once. */ - status = acpi_EvaluateDSMTyped(sc->handle, (uint8_t *)&dsm_set->uuid, - dsm_set->revision, dsm_index.i, NULL, &result, - ACPI_TYPE_PACKAGE); + /* It seems like this DSM can fail if called more than once. */ + status = acpi_EvaluateDSMTyped(sc->handle, (const uint8_t *)&dsm->uuid, + get_revision(sc, dsm->index), DSM_GET_DEVICE_CONSTRAINTS, NULL, + &result, ACPI_TYPE_PACKAGE); if (ACPI_FAILURE(status)) { - device_printf(dev, "%s failed to call %s DSM %d (rev %d)\n", - __func__, dsm_set->name, dsm_index.i, dsm_set->revision); + failed_to_call_dsm(sc, dsm, DSM_GET_DEVICE_CONSTRAINTS); return (ENXIO); - } + } else if (VERBOSE()) + device_printf(sc->dev, "Constraints: Retrieved successfully\n"); object = (ACPI_OBJECT *)result.Pointer; - if (is_amd) - rv = acpi_spmc_get_constraints_amd(sc, object); - else - rv = acpi_spmc_get_constraints_spec(sc, object); + if (dsm == &dsm_intel) + rv = acpi_spmc_parse_constraints_intel(sc, object); + else { + MPASS(dsm == &dsm_amd); + rv = acpi_spmc_parse_constraints_amd(sc, object); + } AcpiOsFree(object); if (rv != 0) return (rv); @@ -474,149 +785,151 @@ acpi_spmc_get_constraints(device_t dev) for (size_t i = 0; i < sc->constraint_count; i++) { constraint = &sc->constraints[i]; - status = acpi_GetHandleInScope(sc->handle, - __DECONST(char *, constraint->name), &constraint->handle); + status = acpi_GetHandleInScope(sc->handle, constraint->name, + &constraint->handle); if (ACPI_FAILURE(status)) { - device_printf(dev, "failed to get handle for %s\n", - constraint->name); + if (VERBOSE()) + device_printf(sc->dev, + "Constraints: Cannot get handle for %s, " + "ignoring\n", + constraint->name); constraint->handle = NULL; } } + +#ifdef INVARIANTS + sc->get_constraints_succeeded = true; +#endif return (0); } static void -acpi_spmc_check_constraints(struct acpi_spmc_softc *sc) +acpi_spmc_check_constraints(device_t dev) { + const struct acpi_spmc_softc *const sc = device_get_softc(dev); +#ifdef notyet bool violation = false; +#endif - KASSERT(sc->constraints_populated, ("constraints not populated")); + /* + * Avoid printing that constraints are respected when there are no + * constraints at all. + */ + if (sc->constraint_count == 0) + return; for (size_t i = 0; i < sc->constraint_count; i++) { - struct acpi_spmc_constraint *constraint = &sc->constraints[i]; + const struct acpi_spmc_constraint *constraint = + &sc->constraints[i]; if (!constraint->enabled) continue; if (constraint->handle == NULL) continue; - ACPI_STATUS status = acpi_GetHandleInScope(sc->handle, - __DECONST(char *, constraint->name), &constraint->handle); - if (ACPI_FAILURE(status)) { - device_printf(sc->dev, "failed to get handle for %s\n", - constraint->name); - constraint->handle = NULL; - } - if (constraint->handle == NULL) - continue; - #ifdef notyet int d_state; if (ACPI_FAILURE(acpi_pwr_get_state(constraint->handle, &d_state))) continue; if (d_state < constraint->min_d_state) { - device_printf(sc->dev, "constraint for device %s" - " violated (minimum D-state required was %s, actual" - " D-state is %s), might fail to enter LPI state\n", + device_printf(sc->dev, "Constraint for device %s" + " violated (current D-state: %s, " + "required minimum D-state: %s).\n" constraint->name, - acpi_d_state_to_str(constraint->min_d_state), - acpi_d_state_to_str(d_state)); + acpi_d_state_to_str(d_state), + acpi_d_state_to_str(constraint->min_d_state)); violation = true; } #endif } - if (!violation) +#ifdef notyet + if (violation) + device_printf(sc->dev, "Some constraints violated, " + "might fail to enter a Low-Power Idle state\n"); + else device_printf(sc->dev, - "all device power constraints respected!\n"); + "All device power constraints respected!\n"); +#endif } +/* + * Run a single DSM function. + * + * Only runs the function if it was reported present during enumeration. + * Discards the result, but prints a message on error. + */ static void -acpi_spmc_run_dsm(device_t dev, struct dsm_set *dsm_set, int index) +acpi_spmc_run(device_t dev, const struct dsm_desc *const dsm, + const int function_index) { - struct acpi_spmc_softc *sc; - ACPI_STATUS status; - ACPI_BUFFER result; + const struct acpi_spmc_softc *const sc = device_get_softc(dev); + ACPI_STATUS status; + ACPI_BUFFER result; - sc = device_get_softc(dev); + if (!(supports_function(sc, dsm->index, function_index) || + (force_call_expected_functions && has_dsm(sc, dsm->index)))) + return; - status = acpi_EvaluateDSMTyped(sc->handle, (uint8_t *)&dsm_set->uuid, - dsm_set->revision, index, NULL, &result, ACPI_TYPE_ANY); + if (VERBOSE()) + device_printf(dev, "DSM %s: Calling function %s\n", + dsm->name, dsm_function_name(dsm, function_index)); + status = acpi_EvaluateDSMTyped(sc->handle, (const uint8_t *)&dsm->uuid, + get_revision(sc, dsm->index), function_index, NULL, + &result, ACPI_TYPE_ANY); - if (ACPI_FAILURE(status)) { - device_printf(dev, "%s failed to call %s DSM %d (rev %d)\n", - __func__, dsm_set->name, index, dsm_set->revision); - return; + if (ACPI_FAILURE(status)) + failed_to_call_dsm(sc, dsm, function_index); + else { + if (VERBOSE()) + device_printf(dev, "DSM %s: Function %s successful\n", + dsm->name, dsm_function_name(dsm, function_index)); + AcpiOsFree(result.Pointer); } - - AcpiOsFree(result.Pointer); } /* - * Try running the DSMs from all the DSM sets we have, as them failing costs us + * Try running the functions from all the DSMs we have, as them failing costs us * nothing, and it seems like on AMD platforms, both the AMD entry and Microsoft - * "modern" DSM's are required for it to enter modern standby. + * "modern" functions are required for it to enter modern standby. * * This is what Linux does too. */ static void acpi_spmc_display_off_notif(device_t dev) { - struct acpi_spmc_softc *sc = device_get_softc(dev); - - if ((sc->dsm_sets & DSM_SET_INTEL) != 0) - acpi_spmc_run_dsm(dev, &intel_dsm_set, DSM_DISPLAY_OFF_NOTIF); - if ((sc->dsm_sets & DSM_SET_MS) != 0) - acpi_spmc_run_dsm(dev, &ms_dsm_set, DSM_DISPLAY_OFF_NOTIF); - if ((sc->dsm_sets & DSM_SET_AMD) != 0) - acpi_spmc_run_dsm(dev, &amd_dsm_set, AMD_DSM_DISPLAY_OFF_NOTIF); + acpi_spmc_run(dev, &dsm_intel, DSM_INTEL_MS_DISPLAY_OFF_NOTIF); + acpi_spmc_run(dev, &dsm_ms, DSM_INTEL_MS_DISPLAY_OFF_NOTIF); + acpi_spmc_run(dev, &dsm_amd, DSM_AMD_DISPLAY_OFF_NOTIF); } static void acpi_spmc_display_on_notif(device_t dev) { - struct acpi_spmc_softc *sc = device_get_softc(dev); - - if ((sc->dsm_sets & DSM_SET_INTEL) != 0) - acpi_spmc_run_dsm(dev, &intel_dsm_set, DSM_DISPLAY_ON_NOTIF); - if ((sc->dsm_sets & DSM_SET_MS) != 0) - acpi_spmc_run_dsm(dev, &ms_dsm_set, DSM_DISPLAY_ON_NOTIF); - if ((sc->dsm_sets & DSM_SET_AMD) != 0) - acpi_spmc_run_dsm(dev, &amd_dsm_set, AMD_DSM_DISPLAY_ON_NOTIF); + acpi_spmc_run(dev, &dsm_intel, DSM_INTEL_MS_DISPLAY_ON_NOTIF); + acpi_spmc_run(dev, &dsm_ms, DSM_INTEL_MS_DISPLAY_ON_NOTIF); + acpi_spmc_run(dev, &dsm_amd, DSM_AMD_DISPLAY_ON_NOTIF); } static void acpi_spmc_entry_notif(device_t dev) { - struct acpi_spmc_softc *sc = device_get_softc(dev); - - acpi_spmc_check_constraints(sc); + /* XXX - No real check currently. Check return code when it does. */ + acpi_spmc_check_constraints(dev); - if ((sc->dsm_sets & DSM_SET_AMD) != 0) - acpi_spmc_run_dsm(dev, &amd_dsm_set, AMD_DSM_ENTRY_NOTIF); - if ((sc->dsm_sets & DSM_SET_MS) != 0) { - acpi_spmc_run_dsm(dev, &ms_dsm_set, DSM_MODERN_ENTRY_NOTIF); - acpi_spmc_run_dsm(dev, &ms_dsm_set, DSM_ENTRY_NOTIF); - } - if ((sc->dsm_sets & DSM_SET_INTEL) != 0) - acpi_spmc_run_dsm(dev, &intel_dsm_set, DSM_ENTRY_NOTIF); + acpi_spmc_run(dev, &dsm_amd, DSM_AMD_LPI_ENTRY_NOTIF); + acpi_spmc_run(dev, &dsm_ms, DSM_MS_SLEEP_ENTRY_NOTIF); + acpi_spmc_run(dev, &dsm_ms, DSM_INTEL_MS_LPI_ENTRY_NOTIF); + acpi_spmc_run(dev, &dsm_intel, DSM_INTEL_MS_LPI_ENTRY_NOTIF); } static void acpi_spmc_exit_notif(device_t dev) { - struct acpi_spmc_softc *sc = device_get_softc(dev); - - if ((sc->dsm_sets & DSM_SET_INTEL) != 0) - acpi_spmc_run_dsm(dev, &intel_dsm_set, DSM_EXIT_NOTIF); - if ((sc->dsm_sets & DSM_SET_AMD) != 0) - acpi_spmc_run_dsm(dev, &amd_dsm_set, AMD_DSM_EXIT_NOTIF); - if ((sc->dsm_sets & DSM_SET_MS) != 0) { - acpi_spmc_run_dsm(dev, &ms_dsm_set, DSM_EXIT_NOTIF); - if (ms_dsm_set.dsms_supported & - (1 << DSM_MODERN_TURN_ON_DISPLAY)) - acpi_spmc_run_dsm(dev, &ms_dsm_set, - DSM_MODERN_TURN_ON_DISPLAY); - acpi_spmc_run_dsm(dev, &ms_dsm_set, DSM_MODERN_EXIT_NOTIF); - } + acpi_spmc_run(dev, &dsm_intel, DSM_INTEL_MS_LPI_EXIT_NOTIF); + acpi_spmc_run(dev, &dsm_amd, DSM_AMD_LPI_EXIT_NOTIF); + acpi_spmc_run(dev, &dsm_ms, DSM_INTEL_MS_LPI_EXIT_NOTIF); + /* Hint to the platform we are soon going to turn on the display. */ + acpi_spmc_run(dev, &dsm_ms, DSM_MS_TURN_ON_DISPLAY); + acpi_spmc_run(dev, &dsm_ms, DSM_MS_SLEEP_EXIT_NOTIF); } static void diff --git a/sys/dev/ata/ata-all.c b/sys/dev/ata/ata-all.c index 2e77c0f6478e..85fe40aa4584 100644 --- a/sys/dev/ata/ata-all.c +++ b/sys/dev/ata/ata-all.c @@ -1176,8 +1176,7 @@ ataaction(struct cam_sim *sim, union ccb *ccb) cpi->protocol = PROTO_ATA; cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; cpi->maxio = ch->dma.max_iosize ? ch->dma.max_iosize : DFLTPHYS; - if (device_get_devclass(device_get_parent(parent)) == - devclass_find("pci")) { + if (is_pci_device(parent)) { cpi->hba_vendor = pci_get_vendor(parent); cpi->hba_device = pci_get_device(parent); cpi->hba_subvendor = pci_get_subvendor(parent); diff --git a/sys/dev/ath/if_ath.c b/sys/dev/ath/if_ath.c index 1304b597c545..2d52afcf62aa 100644 --- a/sys/dev/ath/if_ath.c +++ b/sys/dev/ath/if_ath.c @@ -179,7 +179,7 @@ static struct ieee80211_node *ath_node_alloc(struct ieee80211vap *, static void ath_node_cleanup(struct ieee80211_node *); static void ath_node_free(struct ieee80211_node *); static void ath_node_getsignal(const struct ieee80211_node *, - int8_t *, int8_t *); + net80211_rssi_t *, int8_t *); static void ath_txq_init(struct ath_softc *sc, struct ath_txq *, int); static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); static int ath_tx_setup(struct ath_softc *, int, int); @@ -3957,7 +3957,7 @@ ath_node_free(struct ieee80211_node *ni) } static void -ath_node_getsignal(const struct ieee80211_node *ni, int8_t *rssi, int8_t *noise) +ath_node_getsignal(const struct ieee80211_node *ni, net80211_rssi_t *rssi, int8_t *noise) { struct ieee80211com *ic = ni->ni_ic; struct ath_softc *sc = ic->ic_softc; diff --git a/sys/dev/ath/if_ath_tx.c b/sys/dev/ath/if_ath_tx.c index 9ac591c14943..d37210723680 100644 --- a/sys/dev/ath/if_ath_tx.c +++ b/sys/dev/ath/if_ath_tx.c @@ -6225,7 +6225,8 @@ ath_bar_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap, * Also, don't call it if bar_tx/bar_wait are 0; something * has beaten us to the punch? (XXX figure out what?) */ - if (status == 0 || attempts == 50) { + if (status == 0 || + ieee80211_ht_check_bar_exceed_retry_count(ni, attempts)) { ATH_TX_LOCK(sc); if (atid->bar_tx == 0 || atid->bar_wait == 0) DPRINTF(sc, ATH_DEBUG_SW_TX_BAR, diff --git a/sys/dev/bge/if_bge.c b/sys/dev/bge/if_bge.c index 2feb19bff677..3551f10b2ae3 100644 --- a/sys/dev/bge/if_bge.c +++ b/sys/dev/bge/if_bge.c @@ -3202,20 +3202,13 @@ bge_mbox_reorder(struct bge_softc *sc) } mbox_reorder_lists[] = { { 0x1022, 0x7450, "AMD-8131 PCI-X Bridge" }, }; - devclass_t pci, pcib; - device_t bus, dev; + device_t dev; int i; - pci = devclass_find("pci"); - pcib = devclass_find("pcib"); dev = sc->bge_dev; - bus = device_get_parent(dev); for (;;) { - dev = device_get_parent(bus); - bus = device_get_parent(dev); - if (device_get_devclass(dev) != pcib) - break; - if (device_get_devclass(bus) != pci) + dev = device_get_parent(device_get_parent(dev)); + if (!is_pci_device(dev)) break; for (i = 0; i < nitems(mbox_reorder_lists); i++) { if (pci_get_vendor(dev) == diff --git a/sys/dev/bnxt/bnxt_en/bnxt_sriov.c b/sys/dev/bnxt/bnxt_en/bnxt_sriov.c index 270c18165fb7..071feffbadfd 100644 --- a/sys/dev/bnxt/bnxt_en/bnxt_sriov.c +++ b/sys/dev/bnxt/bnxt_en/bnxt_sriov.c @@ -7,6 +7,8 @@ #include "bnxt_hwrm.h" #include "bnxt_sriov.h" +#ifdef PCI_IOV + static int bnxt_set_vf_admin_mac(struct bnxt_softc *softc, struct bnxt_vf_info *vf, const uint8_t *mac) @@ -973,6 +975,43 @@ void bnxt_sriov_attach(struct bnxt_softc *softc) device_printf(dev, "Failed to initialize SR-IOV (error=%d)\n", rc); } +#else + +void +bnxt_sriov_attach(struct bnxt_softc *softc __unused) +{ +} + +int +bnxt_cfg_hw_sriov(struct bnxt_softc *softc __unused, + uint16_t *num_vfs __unused, bool reset __unused) +{ + return (0); +} + +int +bnxt_approve_mac(struct bnxt_softc *sc __unused) +{ + return (0); +} + +void +bnxt_hwrm_exec_fwd_req(struct bnxt_softc *softc __unused) +{ +} + +bool +bnxt_promisc_ok(struct bnxt_softc *softc __unused) +{ + return (true); +} + +void +bnxt_update_vf_mac(struct bnxt_softc *sc __unused) +{ +} +#endif + void bnxt_reenable_sriov(struct bnxt_softc *bp) { if (BNXT_PF(bp)) { diff --git a/sys/dev/bnxt/bnxt_en/bnxt_sriov.h b/sys/dev/bnxt/bnxt_en/bnxt_sriov.h index 176f54af0aa8..24ea11f29b83 100644 --- a/sys/dev/bnxt/bnxt_en/bnxt_sriov.h +++ b/sys/dev/bnxt/bnxt_en/bnxt_sriov.h @@ -8,10 +8,6 @@ #include "opt_global.h" #include "bnxt.h" -#ifndef PCI_IOV -#define PCI_IOV 1 -#endif - /* macro definations */ #define BNXT_MAX_VFS 4 diff --git a/sys/dev/bnxt/bnxt_en/if_bnxt.c b/sys/dev/bnxt/bnxt_en/if_bnxt.c index 6618016f3932..6d82302615e1 100644 --- a/sys/dev/bnxt/bnxt_en/if_bnxt.c +++ b/sys/dev/bnxt/bnxt_en/if_bnxt.c @@ -2875,11 +2875,9 @@ bnxt_attach_post(if_ctx_t ctx) bnxt_dcb_init(softc); bnxt_rdma_aux_device_init(softc); -#if PCI_IOV /* SR-IOV attach */ if (BNXT_PF(softc) && BNXT_CHIP_P5_PLUS(softc)) bnxt_sriov_attach(softc); -#endif failed: return rc; diff --git a/sys/dev/cxgbe/adapter.h b/sys/dev/cxgbe/adapter.h index 24a482b74dfb..8c5cf052b689 100644 --- a/sys/dev/cxgbe/adapter.h +++ b/sys/dev/cxgbe/adapter.h @@ -194,6 +194,7 @@ enum { IHF_CLR_ALL_SET = (1 << 5), /* Clear all set bits */ IHF_CLR_ALL_UNIGNORED = (1 << 6), /* Clear all unignored bits */ IHF_RUN_ALL_ACTIONS = (1 << 7), /* As if all cause are set */ + IHF_CLR_DELAYED = (1 << 9), /* Cleared in a delayed call */ }; #define IS_DETACHING(vi) ((vi)->flags & VI_DETACHING) diff --git a/sys/dev/cxgbe/common/common.h b/sys/dev/cxgbe/common/common.h index 2033967ffb94..fcc728a8bf31 100644 --- a/sys/dev/cxgbe/common/common.h +++ b/sys/dev/cxgbe/common/common.h @@ -457,6 +457,10 @@ struct adapter_params { unsigned int max_ordird_qp; /* Max read depth per RDMA QP */ unsigned int max_ird_adapter; /* Max read depth per adapter */ + unsigned int nipsec_tunnel; + unsigned int nipsec_transport; + unsigned int nofld_ipsec_tunnel; + /* These values are for all ports (8b/port, upto 4 ports) */ uint32_t mps_bg_map; /* MPS rx buffer group map */ uint32_t tp_ch_map; /* TPCHMAP from firmware */ diff --git a/sys/dev/cxgbe/common/t4_hw.c b/sys/dev/cxgbe/common/t4_hw.c index f4eef54e5c6b..41606201ad39 100644 --- a/sys/dev/cxgbe/common/t4_hw.c +++ b/sys/dev/cxgbe/common/t4_hw.c @@ -4794,6 +4794,27 @@ struct intr_info { const struct intr_action *actions; }; +/* Helper to clear interrupts that have IHF_CLR_DELAYED. */ +static void +clear_int_cause_reg(struct adapter *sc, const struct intr_info *ii, int flags) +{ + u32 cause, ucause; + + cause = ucause = t4_read_reg(sc, ii->cause_reg); + if (cause == 0) + return; + flags |= ii->flags; + if (flags & IHF_IGNORE_IF_DISABLED) + ucause &= t4_read_reg(sc, ii->enable_reg); + if (flags & IHF_CLR_ALL_SET) { + t4_write_reg(sc, ii->cause_reg, cause); + (void)t4_read_reg(sc, ii->cause_reg); + } else if (ucause != 0 && flags & IHF_CLR_ALL_UNIGNORED) { + t4_write_reg(sc, ii->cause_reg, ucause); + (void)t4_read_reg(sc, ii->cause_reg); + } +} + static inline char intr_alert_char(u32 cause, u32 enable, u32 fatal) { @@ -4869,8 +4890,8 @@ t4_handle_intr(struct adapter *sc, const struct intr_info *ii, uint32_t acause, } } - /* clear */ - if (cause != 0) { + /* Clear here unless delayed clear is requested. */ + if (cause != 0 && (flags & IHF_CLR_DELAYED) == 0) { if (flags & IHF_CLR_ALL_SET) { t4_write_reg(sc, ii->cause_reg, cause); (void)t4_read_reg(sc, ii->cause_reg); @@ -5003,22 +5024,63 @@ static bool pcie_intr_handler(struct adapter *adap, int arg, int flags) .details = NULL, .actions = NULL, }; + static const struct intr_details pcie_intr_cause_ext_details[] = { + { F_IPFORMQPERR, "PCIe IP FormQ Buffer PERR" }, + { F_IPFORMQCERR, "PCIe IP FormQ Buffer CERR" }, + { F_TRGT1GRPCERR, "TRGT1 Group FIFOs CERR" }, + { F_IPSOTCERR, "PCIe IP SOT Buffer SRAM CERR" }, + { F_IPRETRYCERR, "PCIe IP Replay Buffer CERR" }, + { F_IPRXDATAGRPCERR, "PCIe IP Rx Data Group SRAMs CERR" }, + { F_IPRXHDRGRPCERR, "PCIe IP Rx Header Group SRAMs CERR" }, + { F_A0ARBRSPORDFIFOPERR, "A0 Arbiter Response Order FIFO Parity Error" }, + { F_HRSPCERR, "Master HMA Channel Response Data SRAM CERR" }, + { F_HREQRDCERR, "Master HMA Channel Read Request SRAM CERR" }, + { F_HREQWRCERR, "Master HMA Channel Write Request SRAM CERR" }, + { F_DRSPCERR, "Master DMA Channel Response Data SRAM CERR" }, + { F_DREQRDCERR, "Master DMA Channel Read Request SRAM CERR" }, + { F_DREQWRCERR, "Master DMA Channel Write Request SRAM CERR" }, + { F_CRSPCERR, "Master CMD Channel Response Data SRAM CERR" }, + { F_ARSPPERR, "Master ARM Channel Response Data SRAM PERR" }, + { F_AREQRDPERR, "Master ARM Channel Read Request SRAM PERR" }, + { F_AREQWRPERR, "Master ARM Channel Write Request SRAM PERR" }, + { F_PIOREQGRPCERR, "PIO Request Group FIFOs CERR" }, + { F_ARSPCERR, "Master ARM Channel Response Data SRAM CERR" }, + { F_AREQRDCERR, "Master ARM Channel Read Request SRAM CERR" }, + { F_AREQWRCERR, "Master ARM Channel Write Request SRAM CERR" }, + { F_MARSPPERR, "INIC MA Ctrl and Data Rsp Perr" }, + { F_INICMAWDATAORDPERR, "INIC Ma Arb Write Ord Data Fifo Perr" }, + { F_EMUPERR, "CFG EMU SRAM PERR" }, + { F_ERRSPPERR, "CFG EMU SRAM CERR" }, + { F_MSTGRPCERR, "Master Data Path and Response Read Queue SRAM CERR" }, + { 0 } + }; struct intr_info pcie_int_cause_ext = { .name = "PCIE_INT_CAUSE_EXT", .cause_reg = A_PCIE_INT_CAUSE_EXT, .enable_reg = A_PCIE_INT_ENABLE_EXT, .fatal = 0, .flags = 0, - .details = NULL, + .details = pcie_intr_cause_ext_details, .actions = NULL, }; + static const struct intr_details pcie_intr_cause_x8_details[] = { + { F_X8TGTGRPPERR, "x8 TGT Group FIFOs parity error" }, + { F_X8IPSOTPERR, "PCIe x8 IP SOT Buffer SRAM PERR" }, + { F_X8IPRETRYPERR, "PCIe x8 IP Replay Buffer PERR" }, + { F_X8IPRXDATAGRPPERR, "PCIe x8 IP Rx Data Group SRAMs PERR" }, + { F_X8IPRXHDRGRPPERR, "PCIe x8 IP Rx Header Group SRAMs PERR" }, + { F_X8IPCORECERR, "x8 IP SOT, Retry, RxData, RxHdr SRAM CERR" }, + { F_X8MSTGRPPERR, "x8 Master Data Path and Response Read Queue SRAM PERR" }, + { F_X8MSTGRPCERR, "x8 Master Data Path and Response Read Queue SRAM CERR" }, + { 0 } + }; struct intr_info pcie_int_cause_x8 = { .name = "PCIE_INT_CAUSE_X8", .cause_reg = A_PCIE_INT_CAUSE_X8, .enable_reg = A_PCIE_INT_ENABLE_X8, .fatal = 0, .flags = 0, - .details = NULL, + .details = pcie_intr_cause_x8_details, .actions = NULL, }; bool fatal = false; @@ -5050,80 +5112,247 @@ static bool tp_intr_handler(struct adapter *adap, int arg, int flags) { F_FLMTXFLSTEMPTY, "TP out of Tx pages" }, { 0 } }; - static const struct intr_info tp_intr_info = { + static const struct intr_details t7_tp_intr_details[] = { + { F_FLMTXFLSTEMPTY, "Offload memory manager Tx free list empty" }, + { F_TPCERR, "TP modules flagged Correctable Error" }, + { F_OTHERPERR, "TP Other modules (Core, TM, FLM, MMGR, DB) Parity Error" }, + { F_TPEING1PERR, "TP-ESide Ingress1 Parity Error" }, + { F_TPEING0PERR, "TP-ESide Ingress0 Parity Error" }, + { F_TPEEGPERR, "TP-ESide Egress Parity Error" }, + { F_TPCPERR, "TP-CSide Parity Error" }, + { 0 } + }; + struct intr_info tp_intr_info = { .name = "TP_INT_CAUSE", .cause_reg = A_TP_INT_CAUSE, .enable_reg = A_TP_INT_ENABLE, .fatal = 0x7fffffff, - .flags = IHF_FATAL_IFF_ENABLED, - .details = tp_intr_details, + .flags = IHF_FATAL_IFF_ENABLED | IHF_CLR_DELAYED, + .details = NULL, .actions = NULL, }; - static const struct intr_info tp_inic_perr_cause = { - .name = "TP_INIC_PERR_CAUSE", - .cause_reg = A_TP_INIC_PERR_CAUSE, - .enable_reg = A_TP_INIC_PERR_ENABLE, + static const struct intr_details tp_cerr_cause_details[] = { + { F_TPCEGDATAFIFO, "TPCSide Egress Data FIFO" }, + { F_TPCLBKDATAFIFO, "TPCSide Loopback Data FIFO" }, + { F_RSSLKPSRAM, "RSS Lookup SRAM" }, + { F_SRQSRAM, "SRQ SRAM" }, + { F_ARPDASRAM, "ARP DA SRAM" }, + { F_ARPSASRAM, "ARP SA SRAM" }, + { F_ARPGRESRAM, "ARP GRE SRAM" }, + { F_ARPIPSECSRAM1, "ARP IPSec SRAM0" }, + { F_ARPIPSECSRAM0, "ARP IPSec SRAM1" }, + { 0 } + }; + static const struct intr_info tp_cerr_cause = { + .name = "TP_CERR_CAUSE", + .cause_reg = A_TP_CERR_CAUSE, + .enable_reg = A_TP_CERR_ENABLE, .fatal = 0xffffffff, .flags = IHF_FATAL_IFF_ENABLED, - .details = NULL, + .details = tp_cerr_cause_details, .actions = NULL, }; + static const struct intr_details tp_c_perr_details[] = { + { F_DMXFIFOOVFL, "Demux FIFO Overflow" }, + { F_URX2TPCDDPINTF, "ULPRX to TPC DDP Interface and FIFO" }, + { F_TPCDISPTOKENFIFO, "TPC Dispatch Token FIFO" }, + { F_TPCDISPCPLFIFO3, "TPC Dispatch CPL FIFO Ch3" }, + { F_TPCDISPCPLFIFO2, "TPC Dispatch CPL FIFO Ch2" }, + { F_TPCDISPCPLFIFO1, "TPC Dispatch CPL FIFO Ch1" }, + { F_TPCDISPCPLFIFO0, "TPC Dispatch CPL FIFO Ch0" }, + { F_URXPLDINTFCRC3, "ULPRX to TPC Payload Interface CRC Error Ch3" }, + { F_URXPLDINTFCRC2, "ULPRX to TPC Payload Interface CRC Error Ch2" }, + { F_URXPLDINTFCRC1, "ULPRX to TPC Payload Interface CRC Error Ch1" }, + { F_URXPLDINTFCRC0, "ULPRX to TPC Payload Interface CRC Error Ch0" }, + { F_DMXDBFIFO, "Demux DB FIFO" }, + { F_DMXDBSRAM, "Demux DB SRAM" }, + { F_DMXCPLFIFO, "Demux CPL FIFO" }, + { F_DMXCPLSRAM, "Demux CPL SRAM" }, + { F_DMXCSUMFIFO, "Demux Checksum FIFO" }, + { F_DMXLENFIFO, "Demux Length FIFO" }, + { F_DMXCHECKFIFO, "Demux Check CRC16 FIFO" }, + { F_DMXWINFIFO, "Demux Winner FIFO" }, + { F_EGTOKENFIFO, "Egress Token FIFO Parity Error" }, + { F_EGDATAFIFO, "Egress FIFO Parity Error" }, + { F_UTX2TPCINTF3, "ULPTX to TPC Interface Parity Error Ch3" }, + { F_UTX2TPCINTF2, "ULPTX to TPC Interface Parity Error Ch2" }, + { F_UTX2TPCINTF1, "ULPTX to TPC Interface Parity Error Ch1" }, + { F_UTX2TPCINTF0, "ULPTX to TPC Interface Parity Error Ch0" }, + { F_LBKTOKENFIFO, "Loopback Token FIFO Parity Error" }, + { F_LBKDATAFIFO, "Loopback FIFO Parity Error" }, + { 0 } + }; static const struct intr_info tp_c_perr_cause = { .name = "TP_C_PERR_CAUSE", .cause_reg = A_TP_C_PERR_CAUSE, .enable_reg = A_TP_C_PERR_ENABLE, .fatal = 0xffffffff, .flags = IHF_FATAL_IFF_ENABLED, - .details = NULL, + .details = tp_c_perr_details, .actions = NULL, }; + static const struct intr_details tp_e_eg_perr_details[] = { + { F_MPSLPBKTOKENFIFO, "MPS Loopback Token FIFO parity error" }, + { F_MPSMACTOKENFIFO, "MPS MAC Token FIFO parity error" }, + { F_DISPIPSECFIFO3, "Ch3 Dispatch IPSec FIFO parity error" }, + { F_DISPTCPFIFO3, "Ch3 Dispatch TCP FIFO parity error" }, + { F_DISPIPFIFO3, "Ch3 Dispatch IP FIFO parity error" }, + { F_DISPETHFIFO3, "Ch3 Dispatch ETH FIFO parity error" }, + { F_DISPGREFIFO3, "Ch3 Dispatch GRE FIFO parity error" }, + { F_DISPCPL5FIFO3, "Ch3 Dispatch CPL5 FIFO parity error" }, + { F_DISPIPSECFIFO2, "Ch2 Dispatch IPSec FIFO parity error" }, + { F_DISPTCPFIFO2, "Ch2 Dispatch TCP FIFO parity error" }, + { F_DISPIPFIFO2, "Ch2 Dispatch IP FIFO parity error" }, + { F_DISPETHFIFO2, "Ch2 Dispatch ETH FIFO parity error" }, + { F_DISPGREFIFO2, "Ch2 Dispatch GRE FIFO parity error" }, + { F_DISPCPL5FIFO2, "Ch2 Dispatch CPL5 FIFO parity error" }, + { F_DISPIPSECFIFO1, "Ch1 Dispatch IPSec FIFO parity error" }, + { F_DISPTCPFIFO1, "Ch1 Dispatch TCP FIFO parity error" }, + { F_DISPIPFIFO1, "Ch1 Dispatch IP FIFO parity error" }, + { F_DISPETHFIFO1, "Ch1 Dispatch ETH FIFO parity error" }, + { F_DISPGREFIFO1, "Ch1 Dispatch GRE FIFO parity error" }, + { F_DISPCPL5FIFO1, "Ch1 Dispatch CPL5 FIFO parity error" }, + { F_DISPIPSECFIFO0, "Ch0 Dispatch IPSec FIFO parity error" }, + { F_DISPTCPFIFO0, "Ch0 Dispatch TCP FIFO parity error" }, + { F_DISPIPFIFO0, "Ch0 Dispatch IP FIFO parity error" }, + { F_DISPETHFIFO0, "Ch0 Dispatch ETH FIFO parity error" }, + { F_DISPGREFIFO0, "Ch0 Dispatch GRE FIFO parity error" }, + { F_DISPCPL5FIFO0, "Ch0 Dispatch CPL5 FIFO parity error" }, + { 0 } + }; static const struct intr_info tp_e_eg_perr_cause = { .name = "TP_E_EG_PERR_CAUSE", .cause_reg = A_TP_E_EG_PERR_CAUSE, .enable_reg = A_TP_E_EG_PERR_ENABLE, .fatal = 0xffffffff, .flags = IHF_FATAL_IFF_ENABLED, - .details = NULL, + .details = tp_e_eg_perr_details, .actions = NULL, }; + static const struct intr_details tp_e_in0_perr_details[] = { + { F_DMXISSFIFO, "Demux ISS FIFO parity error" }, + { F_DMXERRFIFO, "Demux Error FIFO parity error" }, + { F_DMXATTFIFO, "Demux Attributes FIFO parity error" }, + { F_DMXTCPFIFO, "Demux TCP Fields FIFO parity error" }, + { F_DMXMPAFIFO, "Demux MPA FIFO parity error" }, + { F_DMXOPTFIFO, "Demux TCP Options FIFO parity error" }, + { F_INGTOKENFIFO, "Demux Ingress Token FIFO parity error" }, + { F_DMXPLDCHKOVFL1, "Ch1 PLD TxCheck FIFO Overflow" }, + { F_DMXPLDCHKFIFO1, "Ch1 PLD TxCheck FIFO parity error" }, + { F_DMXOPTFIFO1, "Ch1 Options buffer parity error" }, + { F_DMXMPAFIFO1, "Ch1 MPA FIFO parity error" }, + { F_DMXDBFIFO1, "Ch1 DB FIFO parity error" }, + { F_DMXATTFIFO1, "Ch1 Attribute FIFO parity error" }, + { F_DMXISSFIFO1, "Ch1 ISS FIFO parity error" }, + { F_DMXTCPFIFO1, "Ch1 TCP Fields FIFO parity error" }, + { F_DMXERRFIFO1, "Ch1 Error FIFO parity error" }, + { F_MPS2TPINTF1, "Ch1 MPS2TP Interface parity error" }, + { F_DMXPLDCHKOVFL0, "Ch0 PLD TxCheck FIFO Overflow" }, + { F_DMXPLDCHKFIFO0, "Ch0 PLD TxCheck FIFO parity error" }, + { F_DMXOPTFIFO0, "Ch0 Options buffer parity error" }, + { F_DMXMPAFIFO0, "Ch0 MPA FIFO parity error" }, + { F_DMXDBFIFO0, "Ch0 DB FIFO parity error" }, + { F_DMXATTFIFO0, "Ch0 Attribute FIFO parity error" }, + { F_DMXISSFIFO0, "Ch0 ISS FIFO parity error" }, + { F_DMXTCPFIFO0, "Ch0 TCP Fields FIFO parity error" }, + { F_DMXERRFIFO0, "Ch0 Error FIFO parity error" }, + { F_MPS2TPINTF0, "Ch0 MPS2TP Interface parity error" }, + { 0 } + }; static const struct intr_info tp_e_in0_perr_cause = { .name = "TP_E_IN0_PERR_CAUSE", .cause_reg = A_TP_E_IN0_PERR_CAUSE, .enable_reg = A_TP_E_IN0_PERR_ENABLE, .fatal = 0xffffffff, .flags = IHF_FATAL_IFF_ENABLED, - .details = NULL, + .details = tp_e_in0_perr_details, .actions = NULL, }; + static const struct intr_details tp_e_in1_perr_details[] = { + { F_DMXPLDCHKOVFL3, "Ch3 PLD TxCheck FIFO Overflow" }, + { F_DMXPLDCHKFIFO3, "Ch3 PLD TxCheck FIFO parity error" }, + { F_DMXOPTFIFO3, "Ch3 Options buffer parity error" }, + { F_DMXMPAFIFO3, "Ch3 MPA FIFO parity error" }, + { F_DMXDBFIFO3, "Ch3 DB FIFO parity error" }, + { F_DMXATTFIFO3, "Ch3 Attribute FIFO parity error" }, + { F_DMXISSFIFO3, "Ch3 ISS FIFO parity error" }, + { F_DMXTCPFIFO3, "Ch3 TCP Fields FIFO parity error" }, + { F_DMXERRFIFO3, "Ch3 Error FIFO parity error" }, + { F_MPS2TPINTF3, "Ch3 MPS2TP Interface parity error" }, + { F_DMXPLDCHKOVFL2, "Ch2 PLD TxCheck FIFO Overflow" }, + { F_DMXPLDCHKFIFO2, "Ch2 PLD TxCheck FIFO parity error" }, + { F_DMXOPTFIFO2, "Ch2 Options buffer parity error" }, + { F_DMXMPAFIFO2, "Ch2 MPA FIFO parity error" }, + { F_DMXDBFIFO2, "Ch2 DB FIFO parity error" }, + { F_DMXATTFIFO2, "Ch2 Attribute FIFO parity error" }, + { F_DMXISSFIFO2, "Ch2 ISS FIFO parity error" }, + { F_DMXTCPFIFO2, "Ch2 TCP Fields FIFO parity error" }, + { F_DMXERRFIFO2, "Ch2 Error FIFO parity error" }, + { F_MPS2TPINTF2, "Ch2 MPS2TP Interface parity error" }, + { 0 } + }; static const struct intr_info tp_e_in1_perr_cause = { .name = "TP_E_IN1_PERR_CAUSE", .cause_reg = A_TP_E_IN1_PERR_CAUSE, .enable_reg = A_TP_E_IN1_PERR_ENABLE, .fatal = 0xffffffff, .flags = IHF_FATAL_IFF_ENABLED, - .details = NULL, + .details = tp_e_in1_perr_details, .actions = NULL, }; + static const struct intr_details tp_other_perr_details[] = { + { F_DMARBTPERR, "DMARBT MA Rsp Interface parity Error" }, + { F_MMGRCACHEDATASRAM, "TP MMGR Cache Data SRAM" }, + { F_MMGRCACHETAGFIFO, "TP MMGR Cache Tag FIFO" }, + { F_DBL2TLUTPERR, "TP DB Lookup Table" }, + { F_DBTXTIDPERR, "TP DB FIFOs" }, + { F_DBEXTPERR, "TP DB Extended Opcode FIFO" }, + { F_DBOPPERR, "TP DB Opcode FIFO" }, + { F_TMCACHEPERR, "TP TM Cache SRAM" }, + { F_TPPROTOSRAM, "TP Protocol SRAM" }, + { F_HSPSRAM, "HighSpeed SRAM" }, + { F_RATEGRPSRAM, "Rate Group SRAM" }, + { F_TXFBSEQFIFO, "Tx Feedback Sequence Number FIFO" }, + { F_CMDATASRAM, "Cache Data SRAM" }, + { F_CMTAGFIFO, "Cache Tag FIFO" }, + { F_RFCOPFIFO, "RCF Opcode FIFO" }, + { F_DELINVFIFO, "Delete Invalid FIFO" }, + { F_RSSCFGSRAM, "RSS Config or Round-Robin SRAM" }, + { F_RSSKEYSRAM, "RSS Key SRAM" }, + { F_RSSLKPSRAM, "RSS Lookup SRAM" }, + { F_SRQSRAM, "SRQ SRAM" }, + { F_ARPDASRAM, "ARP DA SRAM" }, + { F_ARPSASRAM, "ARP SA SRAM" }, + { F_ARPGRESRAM, "ARP GRE SRAM" }, + { F_ARPIPSECSRAM1, "ARP IPSec SRAM0" }, + { F_ARPIPSECSRAM0, "ARP IPSec SRAM1" }, + { 0 } + }; static const struct intr_info tp_o_perr_cause = { .name = "TP_O_PERR_CAUSE", .cause_reg = A_TP_O_PERR_CAUSE, .enable_reg = A_TP_O_PERR_ENABLE, .fatal = 0xffffffff, .flags = IHF_FATAL_IFF_ENABLED, - .details = NULL, + .details = tp_other_perr_details, .actions = NULL, }; bool fatal; - fatal = t4_handle_intr(adap, &tp_intr_info, 0, flags); if (chip_id(adap) > CHELSIO_T6) { - fatal |= t4_handle_intr(adap, &tp_inic_perr_cause, 0, flags); + tp_intr_info.details = t7_tp_intr_details; + fatal = t4_handle_intr(adap, &tp_intr_info, 0, flags); + fatal |= t4_handle_intr(adap, &tp_cerr_cause, 0, flags); fatal |= t4_handle_intr(adap, &tp_c_perr_cause, 0, flags); fatal |= t4_handle_intr(adap, &tp_e_eg_perr_cause, 0, flags); fatal |= t4_handle_intr(adap, &tp_e_in0_perr_cause, 0, flags); fatal |= t4_handle_intr(adap, &tp_e_in1_perr_cause, 0, flags); fatal |= t4_handle_intr(adap, &tp_o_perr_cause, 0, flags); + } else { + tp_intr_info.details = tp_intr_details; + fatal = t4_handle_intr(adap, &tp_intr_info, 0, flags); } + clear_int_cause_reg(adap, &tp_intr_info, flags); return (fatal); } @@ -5133,16 +5362,86 @@ static bool tp_intr_handler(struct adapter *adap, int arg, int flags) */ static bool sge_intr_handler(struct adapter *adap, int arg, int flags) { + static const struct intr_details sge_int1_details[] = { + { F_PERR_FLM_CREDITFIFO, "SGE FLM credit FIFO parity error" }, + { F_PERR_IMSG_HINT_FIFO, "SGE IMSG hint FIFO parity error" }, + { F_PERR_HEADERSPLIT_FIFO3 | F_PERR_HEADERSPLIT_FIFO2, + "SGE header split FIFO parity error" }, + { F_PERR_PAYLOAD_FIFO3 | F_PERR_PAYLOAD_FIFO2, + "SGE payload FIFO parity error" }, + { F_PERR_PC_RSP, "SGE PC response parity error" }, + { F_PERR_PC_REQ, "SGE PC request parity error" }, + { 0x003c0000, "SGE DBP PC response FIFO parity error" }, + { F_PERR_DMARBT, "SGE DMA RBT parity error" }, + { F_PERR_FLM_DBPFIFO, "SGE FLM DBP FIFO parity error" }, + { F_PERR_FLM_MCREQ_FIFO, "SGE FLM MC request FIFO parity error" }, + { F_PERR_FLM_HINTFIFO, "SGE FLM hint FIFO parity error" }, + { 0x00003c00, "SGE align control FIFO parity error" }, + { 0x000003c0, "SGE EDMA FIFO parity error" }, + { 0x0000003c, "SGE PD FIFO parity error" }, + { F_PERR_ING_CTXT_MIFRSP, "SGE Ingress context MIF response parity error" }, + { F_PERR_EGR_CTXT_MIFRSP, "SGE Egress context MIF response parity error" }, + { 0 } + }; static const struct intr_info sge_int1_info = { .name = "SGE_INT_CAUSE1", .cause_reg = A_SGE_INT_CAUSE1, .enable_reg = A_SGE_INT_ENABLE1, .fatal = 0xffffffff, .flags = IHF_FATAL_IFF_ENABLED, - .details = NULL, + .details = sge_int1_details, .actions = NULL, }; - static const struct intr_info sge_int2_info = { + static const struct intr_details t7_sge_int2_details[] = { + { F_TF_FIFO_PERR, "SGE TF FIFO parity error" }, + { F_PERR_EGR_DBP_TX_COAL, "SGE egress DBP TX coal parity error" }, + { F_PERR_DBP_FL_FIFO, "SGE DBP FL FIFO parity error" }, + { F_DEQ_LL_PERR, "SGE linked list SRAM parity error" }, + { F_ENQ_PERR, "SGE enq tag SRAM parity error" }, + { F_DEQ_OUT_PERR, "SGE tbuf deq output FIFO parity error" }, + { F_BUF_PERR, "SGE tbuf main buffer parity error" }, + { F_PERR_CONM_SRAM, "SGE CONM SRAM parity error" }, + { F_PERR_ISW_IDMA3_FIFO | F_PERR_ISW_IDMA2_FIFO | + F_PERR_ISW_IDMA1_FIFO | F_PERR_ISW_IDMA0_FIFO, + "SGE ISW IDMA FIFO parity error" }, + { F_PERR_ISW_DBP_FIFO, "SGE ISW DBP FIFO parity error" }, + { F_PERR_ISW_GTS_FIFO, "SGE ISW GTS FIFO parity error" }, + { F_PERR_ITP_EVR, "SGE ITP EVR parity error" }, + { F_PERR_FLM_CNTXMEM, "SGE FLM context memory parity error" }, + { F_PERR_FLM_L1CACHE, "SGE FLM L1 cache parity error" }, + { F_SGE_IPP_FIFO_PERR, "SGE IPP FIFO parity error" }, + { F_PERR_DBP_HP_FIFO, "SGE DBP HP FIFO parity error" }, + { F_PERR_DB_FIFO, "SGE doorbell FIFO parity error" }, + { F_PERR_ING_CTXT_CACHE | F_PERR_EGR_CTXT_CACHE, + "SGE context cache parity error" }, + { F_PERR_BASE_SIZE, "SGE base size parity error" }, + { 0 } + }; + static const struct intr_details t6_sge_int2_details[] = { + { F_PERR_DBP_HINT_FL_FIFO, "SGE DBP hint FL FIFO parity error" }, + { F_PERR_EGR_DBP_TX_COAL, "SGE egress DBP TX coal parity error" }, + { F_PERR_DBP_FL_FIFO, "SGE DBP FL FIFO parity error" }, + { F_DEQ_LL_PERR, "SGE tbuf dequeue linked list SRAM parity error" }, + { F_ENQ_PERR, "SGE tbuf enqueue tag SRAM parity error" }, + { F_DEQ_OUT_PERR, "SGE tbuf dequeue output FIFO parity error" }, + { F_BUF_PERR, "SGE tbuf main buffer parity error" }, + { F_PERR_CONM_SRAM, "SGE CONM SRAM parity error" }, + { F_PERR_ISW_IDMA1_FIFO, "SGE ISW IDMA FIFO parity error" }, + { F_PERR_ISW_IDMA0_FIFO, "SGE ISW IDMA FIFO parity error" }, + { F_PERR_ISW_DBP_FIFO, "SGE ISW DBP FIFO parity error" }, + { F_PERR_ISW_GTS_FIFO, "SGE ISW GTS FIFO parity error" }, + { F_PERR_ITP_EVR, "SGE ITP EVR parity error" }, + { F_PERR_FLM_CNTXMEM, "SGE FLM context memory parity error" }, + { F_PERR_FLM_L1CACHE, "SGE FLM L1 cache parity error" }, + { F_PERR_DBP_HINT_FIFO, "SGE DBP hint FIFO parity error" }, + { F_PERR_DBP_HP_FIFO, "SGE DBP high priority FIFO parity error" }, + { F_PERR_DB_FIFO, "SGE DBP merge DB FIFO parity error" }, + { F_PERR_ING_CTXT_CACHE, "SGE ingress context cache parity error" }, + { F_PERR_EGR_CTXT_CACHE, "SGE egress context cache parity error" }, + { F_PERR_BASE_SIZE, "SGE base size parity error" }, + { 0 } + }; + struct intr_info sge_int2_info = { .name = "SGE_INT_CAUSE2", .cause_reg = A_SGE_INT_CAUSE2, .enable_reg = A_SGE_INT_ENABLE2, @@ -5231,16 +5530,105 @@ static bool sge_intr_handler(struct adapter *adap, int arg, int flags) .details = NULL, .actions = NULL, }; + static const struct intr_details sge_int4_details[] = { + { F_ERR_ISHIFT_UR1 | F_ERR_ISHIFT_UR0, "SGE ishift underrun" }, + { F_BAR2_EGRESS_LEN_OR_ADDR_ERR, "SGE BAR2 PL access length or alignment error" }, + { F_ERR_CPL_EXCEED_MAX_IQE_SIZE1 | F_ERR_CPL_EXCEED_MAX_IQE_SIZE0, + "SGE CPL exceeds max IQE size" }, + { F_ERR_WR_LEN_TOO_LARGE3 | F_ERR_WR_LEN_TOO_LARGE2 | + F_ERR_WR_LEN_TOO_LARGE1 | F_ERR_WR_LEN_TOO_LARGE0, + "SGE WR length too large" }, + { F_ERR_LARGE_MINFETCH_WITH_TXCOAL3 | F_ERR_LARGE_MINFETCH_WITH_TXCOAL2 | + F_ERR_LARGE_MINFETCH_WITH_TXCOAL1 | F_ERR_LARGE_MINFETCH_WITH_TXCOAL0, + "SGE invalid MinFetchBurst with TxCoalesce" }, + { F_COAL_WITH_HP_DISABLE_ERR, "SGE coalesce with HP disable error" }, + { F_BAR2_EGRESS_COAL0_ERR, "SGE BAR2 PL access addr offset 0" }, + { F_BAR2_EGRESS_SIZE_ERR, "SGE BAR2 illegal egress QID access" }, + { F_FLM_PC_RSP_ERR, "SGE FLM PC response error" }, + { F_ERR_TH3_MAX_FETCH | F_ERR_TH2_MAX_FETCH | + F_ERR_TH1_MAX_FETCH | F_ERR_TH0_MAX_FETCH, + "SGE max fetch violation" }, + { F_ERR_RX_CPL_PACKET_SIZE1 | F_ERR_RX_CPL_PACKET_SIZE0, + "SGE CPL length mismatch error" }, + { F_ERR_BAD_UPFL_INC_CREDIT3 | F_ERR_BAD_UPFL_INC_CREDIT2 | + F_ERR_BAD_UPFL_INC_CREDIT1 | F_ERR_BAD_UPFL_INC_CREDIT0, + "SGE upfl credit wrap error" }, + { F_ERR_PHYSADDR_LEN0_IDMA1 | F_ERR_PHYSADDR_LEN0_IDMA0, + "SGE CPL_RX_PHYS_ADDR length 0 error" }, + { F_ERR_FLM_INVALID_PKT_DROP1 | F_ERR_FLM_INVALID_PKT_DROP0, + "SGE IDMA packet drop due to invalid FLM context" }, + { F_ERR_UNEXPECTED_TIMER, "SGE unexpected timer error" }, + { 0 } + }; static const struct intr_info sge_int4_info = { .name = "SGE_INT_CAUSE4", .cause_reg = A_SGE_INT_CAUSE4, .enable_reg = A_SGE_INT_ENABLE4, .fatal = 0, .flags = 0, - .details = NULL, + .details = sge_int4_details, .actions = NULL, }; - static const struct intr_info sge_int5_info = { + static const struct intr_details t7_sge_int5_details[] = { + { F_ERR_T_RXCRC, "SGE RxCRC error" }, + { F_PERR_MC_RSPDATA, "SGE MC response data parity error" }, + { F_PERR_PC_RSPDATA, "SGE PC response data parity error" }, + { F_PERR_PD_RDRSPDATA, "SGE PD read response data parity error" }, + { F_PERR_U_RXDATA, "SGE U Rx data parity error" }, + { F_PERR_UD_RXDATA, "SGE UD Rx data parity error" }, + { F_PERR_UP_DATA, "SGE uP data parity error" }, + { F_PERR_CIM2SGE_RXDATA, "SGE CIM2SGE Rx data parity error" }, + { F_PERR_IMSG_PD_FIFO, "SGE IMSG PD FIFO parity error" }, + { F_PERR_ULPTX_FIFO1 | F_PERR_ULPTX_FIFO0, "SGE ULPTX FIFO parity error" }, + { F_PERR_IDMA2IMSG_FIFO3 | F_PERR_IDMA2IMSG_FIFO2 | + F_PERR_IDMA2IMSG_FIFO1 | F_PERR_IDMA2IMSG_FIFO0, + "SGE IDMA2IMSG FIFO parity error" }, + { F_PERR_POINTER_DATA_FIFO3 | F_PERR_POINTER_DATA_FIFO2 | + F_PERR_POINTER_DATA_FIFO1 | F_PERR_POINTER_DATA_FIFO0, + "SGE pointer data FIFO parity error" }, + { F_PERR_POINTER_HDR_FIFO3 | F_PERR_POINTER_HDR_FIFO2 | + F_PERR_POINTER_HDR_FIFO1 | F_PERR_POINTER_HDR_FIFO0, + "SGE pointer header FIFO parity error" }, + { F_PERR_PAYLOAD_FIFO1 | F_PERR_PAYLOAD_FIFO0, + "SGE payload FIFO parity error" }, + { F_PERR_MGT_BAR2_FIFO, "SGE MGT BAR2 FIFO parity error" }, + { F_PERR_HEADERSPLIT_FIFO1 | F_PERR_HEADERSPLIT_FIFO0, + "SGE header split FIFO parity error" }, + { F_PERR_HINT_DELAY_FIFO, "SGE hint delay FIFO parity error" }, + { 0 } + }; + static const struct intr_details t6_sge_int5_details[] = { + { F_ERR_T_RXCRC, "SGE T RxCRC parity error" }, + { F_PERR_MC_RSPDATA, "SGE MC response data parity error" }, + { F_PERR_PC_RSPDATA, "SGE PC response data parity error" }, + { F_PERR_U_RXDATA | F_PERR_UD_RXDATA, "SGE ULP Rx data parity error" }, + { F_PERR_UP_DATA, "SGE uP data parity error" }, + { F_PERR_CIM2SGE_RXDATA, "SGE CIM2SGE Rx data parity error" }, + { F_PERR_HINT_DELAY_FIFO1 | F_PERR_HINT_DELAY_FIFO0, + "SGE hint delay FIFO parity error" }, + { F_PERR_IMSG_PD_FIFO, "SGE IMSG PD FIFO parity error" }, + { F_PERR_ULPTX_FIFO1 | F_PERR_ULPTX_FIFO0, + "SGE ULPTX FIFO parity error" }, + { F_PERR_IDMA2IMSG_FIFO1 | F_PERR_IDMA2IMSG_FIFO0, + "SGE IDMA2IMSG FIFO parity error" }, + { F_PERR_POINTER_DATA_FIFO1 | F_PERR_POINTER_DATA_FIFO0, + "SGE pointer data FIFO parity error" }, + { F_PERR_POINTER_HDR_FIFO1 | F_PERR_POINTER_HDR_FIFO0, + "SGE pointer header FIFO parity error" }, + { F_PERR_PAYLOAD_FIFO1 | F_PERR_PAYLOAD_FIFO0, + "SGE payload FIFO parity error" }, + { F_PERR_EDMA_INPUT_FIFO3 | F_PERR_EDMA_INPUT_FIFO2 | + F_PERR_EDMA_INPUT_FIFO1 | F_PERR_EDMA_INPUT_FIFO0, + "SGE EDMA input FIFO parity error" }, + { F_PERR_MGT_BAR2_FIFO, "SGE MGT BAR2 FIFO parity error" }, + { F_PERR_HEADERSPLIT_FIFO1 | F_PERR_HEADERSPLIT_FIFO0, + "SGE header split FIFO parity error" }, + { F_PERR_CIM_FIFO1 | F_PERR_CIM_FIFO0, "SGE CIM FIFO parity error" }, + { F_PERR_IDMA_SWITCH_OUTPUT_FIFO1 | F_PERR_IDMA_SWITCH_OUTPUT_FIFO0, + "SGE IDMA switch output FIFO parity error" }, + { 0 } + }; + struct intr_info sge_int5_info = { .name = "SGE_INT_CAUSE5", .cause_reg = A_SGE_INT_CAUSE5, .enable_reg = A_SGE_INT_ENABLE5, @@ -5249,31 +5637,94 @@ static bool sge_intr_handler(struct adapter *adap, int arg, int flags) .details = NULL, .actions = NULL, }; + static const struct intr_details sge_int6_details[] = { + /* T7+ */ + { 0xe0000000, "SGE fatal DEQ0 DRDY error" }, + { 0x1c000000, "SGE fatal OUT0 DRDY error" }, + { F_IMSG_DBG3_STUCK | F_IMSG_DBG2_STUCK | + F_IMSG_DBG1_STUCK | F_IMSG_DBG0_STUCK, + "SGE IMSG stuck due to insufficient credits" }, + /* T6 + */ + { F_ERR_DB_SYNC, "SGE doorbell sync failed" }, + { F_ERR_GTS_SYNC, "SGE GTS sync failed" }, + { F_FATAL_LARGE_COAL, "SGE BAR2 payload too large" }, + { F_PL_BAR2_FRM_ERR, "SGE BAR2 framing error" }, + { F_SILENT_DROP_TX_COAL, "SGE silent drop of Tx coal WR" }, + { F_ERR_INV_CTXT4, "SGE context access for invalid queue thread 4" }, + { F_ERR_BAD_DB_PIDX4, "SGE doorbell pidx too large thread 4" }, + { F_ERR_BAD_UPFL_INC_CREDIT4, "SGE upfl credit wrap thread 4" }, + { F_FATAL_TAG_MISMATCH, "SGE doorbell tag mismatch" }, + { F_FATAL_ENQ_CTL_RDY, "SGE enq_ctl_fifo overflow" }, + { F_ERR_PC_RSP_LEN3 | F_ERR_PC_RSP_LEN2 | + F_ERR_PC_RSP_LEN1 | F_ERR_PC_RSP_LEN0, + "SGE PCIe response error for DBP threads" }, + { F_FATAL_ENQ2LL_VLD, "SGE tbuf fatal_enq2ll_vld" }, + { F_FATAL_LL_EMPTY, "SGE tbuf fatal_ll_empty" }, + { F_FATAL_OFF_WDENQ, "SGE tbuf fatal_off_wdenq" }, + { 0x00000018, "SGE tbuf fatal_deq1_drdy" }, + { 0x00000006, "SGE tbuf fatal_out1_drdy" }, + { F_FATAL_DEQ, "SGE tbuf fatal_deq" }, + { 0 } + }; static const struct intr_info sge_int6_info = { .name = "SGE_INT_CAUSE6", .cause_reg = A_SGE_INT_CAUSE6, .enable_reg = A_SGE_INT_ENABLE6, .fatal = 0, .flags = 0, - .details = NULL, + .details = sge_int6_details, .actions = NULL, }; + static const struct intr_details sge_int7_details[] = { + { F_HINT_FIFO_FULL, "SGE hint FIFO full" }, + { F_CERR_HINT_DELAY_FIFO, "SGE hint delay FIFO ECC error" }, + { F_COAL_TIMER_FIFO_PERR, "SGE coalescing timer FIFO parity error" }, + { F_CMP_FIFO_PERR, "SGE CMP FIFO parity error" }, + { F_SGE_IPP_FIFO_CERR, "SGE IPP FIFO ECC error" }, + { F_CERR_ING_CTXT_CACHE | F_CERR_EGR_CTXT_CACHE, + "SGE context cache ECC error" }, + { F_IMSG_CNTX_PERR, "SGE IMSG context parity error" }, + { F_PD_FIFO_PERR, "SGE PD FIFO parity error" }, + { F_IMSG_512_FIFO_PERR, "SGE IMSG 512 FIFO parity error" }, + { F_CPLSW_FIFO_PERR, "SGE CPLSW FIFO parity error" }, + { F_IMSG_FIFO_PERR, "SGE IMSG FIFO parity error" }, + { F_CERR_ITP_EVR, "SGE ITP EVR ECC error" }, + { F_CERR_CONM_SRAM, "SGE CONM SRAM ECC error" }, + { F_CERR_FLM_CNTXMEM, "SGE FLM context memory ECC error" }, + { F_CERR_FUNC_QBASE, "SGE function queue base ECC error" }, + { F_IMSG_CNTX_CERR, "SGE IMSG context ECC error" }, + { F_PD_FIFO_CERR, "SGE PD FIFO ECC error" }, + { F_IMSG_512_FIFO_CERR, "SGE IMSG 512 FIFO ECC error" }, + { F_CPLSW_FIFO_CERR, "SGE CPLSW FIFO ECC error" }, + { F_IMSG_FIFO_CERR, "SGE IMSG FIFO ECC error" }, + { 0x0000001e, "SGE header split FIFO ECC error" }, // Bits 4:1 + { F_CERR_FLM_L1CACHE, "SGE FLM L1 cache ECC error" }, + { 0 } + }; static const struct intr_info sge_int7_info = { .name = "SGE_INT_CAUSE7", .cause_reg = A_SGE_INT_CAUSE7, .enable_reg = A_SGE_INT_ENABLE7, .fatal = 0, .flags = 0, - .details = NULL, + .details = sge_int7_details, .actions = NULL, }; + static const struct intr_details sge_int8_details[] = { + { F_TRACE_RXPERR, "SGE trace packet parity error" }, + { F_U3_RXPERR | F_U2_RXPERR | F_U1_RXPERR | F_U0_RXPERR, + "SGE ULP interface parity error" }, + { F_T3_RXPERR | F_T2_RXPERR | F_T1_RXPERR | F_T0_RXPERR, + "SGE TP interface parity error" }, + { 0 } + }; static const struct intr_info sge_int8_info = { .name = "SGE_INT_CAUSE8", .cause_reg = A_SGE_INT_CAUSE8, .enable_reg = A_SGE_INT_ENABLE8, .fatal = 0, .flags = 0, - .details = NULL, + .details = sge_int8_details, .actions = NULL, }; bool fatal; @@ -5281,8 +5732,14 @@ static bool sge_intr_handler(struct adapter *adap, int arg, int flags) if (chip_id(adap) <= CHELSIO_T5) { sge_int3_info.details = sge_int3_details; + } else if (chip_id(adap) == CHELSIO_T6) { + sge_int3_info.details = t6_sge_int3_details; + sge_int2_info.details = t6_sge_int2_details; + sge_int5_info.details = t6_sge_int5_details; } else { sge_int3_info.details = t6_sge_int3_details; + sge_int2_info.details = t7_sge_int2_details; + sge_int5_info.details = t7_sge_int5_details; } fatal = false; @@ -5316,6 +5773,19 @@ static bool sge_intr_handler(struct adapter *adap, int arg, int flags) */ static bool cim_intr_handler(struct adapter *adap, int arg, int flags) { + static const struct intr_details cim_host_t7_intr_details[] = { + { F_CORE7ACCINT, "CIM slave core 7 access interrupt "}, + { F_CORE6ACCINT, "CIM slave core 6 access interrupt "}, + { F_CORE5ACCINT, "CIM slave core 5 access interrupt "}, + { F_CORE4ACCINT, "CIM slave core 4 access interrupt "}, + { F_CORE3ACCINT, "CIM slave core 3 access interrupt "}, + { F_CORE2ACCINT, "CIM slave core 2 access interrupt "}, + { F_CORE1ACCINT, "CIM slave core 1 access interrupt "}, + { F_TIMER1INT, "CIM TIMER0 interrupt" }, + { F_TIMER0INT, "CIM TIMER0 interrupt" }, + { F_PREFDROPINT, "CIM control register prefetch drop" }, + { 0} + }; static const struct intr_details cim_host_intr_details[] = { /* T6+ */ { F_PCIE2CIMINTFPARERR, "CIM IBQ PCIe interface parity error" }, @@ -5328,8 +5798,8 @@ static bool cim_intr_handler(struct adapter *adap, int arg, int flags) { F_SGE2CIMINTFPARERR, "CIM IBQ SGE interface parity error" }, { F_ULP2CIMINTFPARERR, "CIM IBQ ULP_TX interface parity error" }, { F_TP2CIMINTFPARERR, "CIM IBQ TP interface parity error" }, - { F_OBQSGERX1PARERR, "CIM OBQ SGE1_RX parity error" }, - { F_OBQSGERX0PARERR, "CIM OBQ SGE0_RX parity error" }, + { F_OBQSGERX1PARERR, "CIM OBQ PCIE_RX parity error" }, + { F_OBQSGERX0PARERR, "CIM OBQ SGE_RX parity error" }, /* T4+ */ { F_TIEQOUTPARERRINT, "CIM TIEQ outgoing FIFO parity error" }, @@ -5354,16 +5824,17 @@ static bool cim_intr_handler(struct adapter *adap, int arg, int flags) { F_PREFDROPINT, "CIM control register prefetch drop" }, { 0} }; - static const struct intr_info cim_host_intr_info = { + struct intr_info cim_host_intr_info = { .name = "CIM_HOST_INT_CAUSE", .cause_reg = A_CIM_HOST_INT_CAUSE, .enable_reg = A_CIM_HOST_INT_ENABLE, .fatal = 0x007fffe6, .flags = IHF_FATAL_IFF_ENABLED, - .details = cim_host_intr_details, + .details = NULL, .actions = NULL, }; static const struct intr_details cim_host_upacc_intr_details[] = { + { F_CONWRERRINT, "CIM condition write error "}, { F_EEPROMWRINT, "CIM EEPROM came out of busy state" }, { F_TIMEOUTMAINT, "CIM PIF MA timeout" }, { F_TIMEOUTINT, "CIM PIF timeout" }, @@ -5423,18 +5894,54 @@ static bool cim_intr_handler(struct adapter *adap, int arg, int flags) .details = NULL, .actions = NULL, }; + static const struct intr_details cim_perr_cause_details[] = { + { F_T7_MA_CIM_INTFPERR, "MA2CIM interface parity error" }, + { F_T7_MBHOSTPARERR, "Mailbox Host Read parity error" }, + { F_MAARBINVRSPTAG, "MA Arbiter Invalid Response Tag (Fatal)" }, + { F_MAARBFIFOPARERR, "MA Arbiter FIFO Parity Error" }, + { F_SEMSRAMPARERR, "Semaphore logic SRAM Parity Error" }, + { F_RSACPARERR, "RSA Code SRAM Parity Error" }, + { F_RSADPARERR, "RSA Data SRAM Parity Error" }, + { F_T7_PLCIM_MSTRSPDATAPARERR, "PL2CIM Master response data parity error" }, + { F_T7_PCIE2CIMINTFPARERR, "IBQ PCIE intf parity error" }, + { F_T7_NCSI2CIMINTFPARERR, "IBQ NCSI intf parity error" }, + { F_T7_SGE2CIMINTFPARERR, "IBQ SGE Intf Parity error" }, + { F_T7_ULP2CIMINTFPARERR, "IBQ ULP_TX intf parity error" }, + { F_T7_TP2CIMINTFPARERR, "IBQ TP intf parity error" }, + { F_CORE7PARERR, "Slave Core7 parity error" }, + { F_CORE6PARERR, "Slave Core6 parity error" }, + { F_CORE5PARERR, "Slave Core5 parity error" }, + { F_CORE4PARERR, "Slave Core4 parity error" }, + { F_CORE3PARERR, "Slave Core3 parity error" }, + { F_CORE2PARERR, "Slave Core2 parity error" }, + { F_CORE1PARERR, "Slave Core1 parity error" }, + { F_GFTPARERR, "GFT block Memory parity error" }, + { F_MPSRSPDATAPARERR, "MPS lookup interface Response parity error" }, + { F_ER_RSPDATAPARERR, "Expansion ROM/Flash Interface Response Parity Error" }, + { F_FLOWFIFOPARERR, "SGE FlowID Prefetch FIFO Parity Error" }, + { F_OBQSRAMPARERR, "OBQ SRAM Parity Error" }, + { F_TIEQOUTPARERR, "TIE Queue Outgoing FIFO parity error" }, + { F_TIEQINPARERR, "TIE Queue Incoming FIFO parity error" }, + { F_PIFRSPPARERR, "PIF Response interface FIFO Parity error" }, + { F_PIFREQPARERR, "PIF Request interface FIFO Parity error" }, + { 0 } + }; static const struct intr_info cim_perr_cause = { .name = "CIM_PERR_CAUSE", .cause_reg = A_CIM_PERR_CAUSE, .enable_reg = A_CIM_PERR_ENABLE, .fatal = 0xffffffff, .flags = IHF_FATAL_IFF_ENABLED, - .details = NULL, + .details = cim_perr_cause_details, .actions = NULL, }; u32 val, fw_err; bool fatal; + if (chip_id(adap) >= CHELSIO_T7) + cim_host_intr_info.details = cim_host_t7_intr_details; + else + cim_host_intr_info.details = cim_host_intr_details; /* * When the Firmware detects an internal error which normally wouldn't * raise a Host Interrupt, it forces a CIM Timer0 interrupt in order @@ -5477,62 +5984,237 @@ static bool ulprx_intr_handler(struct adapter *adap, int arg, int flags) { 0x007fffff, "ULPRX parity error" }, { 0 } }; - static const struct intr_info ulprx_intr_info = { + static const struct intr_details t6_ulprx_int_cause_details[] = { + { F_SE_CNT_MISMATCH_1, "SE count mismatch in channel1" }, + { F_SE_CNT_MISMATCH_0, "SE count mismatch in channel 0" }, + { F_CAUSE_CTX_1, "Context access error on channel 1" }, + { F_CAUSE_CTX_0, "Context access error on channel 0" }, + { F_CAUSE_FF, "filp-flop based fifos" }, + { F_CAUSE_APF_1, "Arb prefetch memory, channel 1" }, + { F_CAUSE_APF_0, "Arb prefetch memory, channel 0" }, + { F_CAUSE_AF_1, "Arb fetch memory, channel 1" }, + { F_CAUSE_AF_0, "Arb fetch memory, channel 0" }, + { F_CAUSE_DDPDF_1, "ddp_data_fifo Fifo, channel 1" }, + { F_CAUSE_DDPMF_1, "ddp_msg_fifo Fifo, channel 1" }, + { F_CAUSE_MEMRF_1, "mem_req_fifo_d Fifo, channel 1" }, + { F_CAUSE_PRSDF_1, "prsr_data_fifo Fifo, channel 1" }, + { F_CAUSE_DDPDF_0, "ddp_data_fifo Fifo, channel 0" }, + { F_CAUSE_DDPMF_0, "ddp_msg_fifo Fifo, channel 0" }, + { F_CAUSE_MEMRF_0, "mem_req_fifo_d Fifo, channel 0" }, + { F_CAUSE_PRSDF_0, "prsr_data_fifo Fifo, channel 0" }, + { F_CAUSE_PCMDF_1, "Pcmd Fifo, channel 1" }, + { F_CAUSE_TPTCF_1, "tpt_ctl_fifo Fifo, channel 1" }, + { F_CAUSE_DDPCF_1, "ddp_ctl_fifo Fifo, channel 1" }, + { F_CAUSE_MPARF_1, "mpar_ctl_fifo Fifo, channel 1" }, + { F_CAUSE_MPARC_1, "mpac_ctl_fifo Fifo, channel 1" }, + { F_CAUSE_PCMDF_0, "Pcmd Fifo, channel 0" }, + { F_CAUSE_TPTCF_0, "tpt_ctl_fifo Fifo, channel 0" }, + { F_CAUSE_DDPCF_0, "ddp_ctl_fifo Fifo, channel 0" }, + { F_CAUSE_MPARF_0, "mpar_ctl_fifo Fifo, channel 0" }, + { F_CAUSE_MPARC_0, "mpac_ctl_fifo Fifo, channel 0" }, + { 0 } + }; + static const struct intr_details t7_ulprx_int_cause_details[] = { + { F_CERR_PCMD_FIFO_3, "PCMD FIFO correctable Error3" }, + { F_CERR_PCMD_FIFO_2, "PCMD FIFO correctable Error2" }, + { F_CERR_PCMD_FIFO_1, "PCMD FIFO correctable Error1" }, + { F_CERR_PCMD_FIFO_0, "PCMD FIFO correctable Error0" }, + { F_CERR_DATA_FIFO_3, "DDP Data FIFO correctable Error3" }, + { F_CERR_DATA_FIFO_2, "DDP Data FIFO correctable Error2" }, + { F_CERR_DATA_FIFO_1, "DDP Data FIFO correctable Error1" }, + { F_CERR_DATA_FIFO_0, "DDP Data FIFO correctable Error0" }, + { F_SE_CNT_MISMATCH_3, "SE count mismatch in channel3" }, + { F_SE_CNT_MISMATCH_2, "SE count mismatch in channel2" }, + { F_T7_SE_CNT_MISMATCH_1, "SE count mismatch in channel1" }, + { F_T7_SE_CNT_MISMATCH_0, "SE count mismatch in channel 0" }, + { F_T7_ENABLE_CTX_3, "Context access error on channel 3" }, + { F_T7_ENABLE_CTX_2, "Context access error on channel 2" }, + { F_T7_ENABLE_CTX_1, "Context access error on channel 1" }, + { F_T7_ENABLE_CTX_0, "Context access error on channel 0" }, + { F_T7_ENABLE_ALN_SDC_ERR_3, "SDC error reported by aligner in channel3" }, + { F_T7_ENABLE_ALN_SDC_ERR_2, "SDC error reported by aligner in channel2" }, + { F_T7_ENABLE_ALN_SDC_ERR_1, "SDC error reported by aligner in channel1" }, + { F_T7_ENABLE_ALN_SDC_ERR_0, "SDC error reported by aligner in channel0" }, + { 0 } + }; + struct intr_info ulprx_intr_info = { .name = "ULP_RX_INT_CAUSE", .cause_reg = A_ULP_RX_INT_CAUSE, .enable_reg = A_ULP_RX_INT_ENABLE, .fatal = 0x07ffffff, .flags = IHF_FATAL_IFF_ENABLED, - .details = ulprx_intr_details, + .details = NULL, .actions = NULL, }; + static const struct intr_details ulprx_int_cause_2_details[] = { + { F_ULPRX2MA_INTFPERR, "SDC error reported by ULPRX2MA interface parity checker" }, + { F_ALN_SDC_ERR_1, "SDC error reported by aligner in channel 1" }, + { F_ALN_SDC_ERR_0, "SDC error reported by aligner in channel 0" }, + { F_PF_UNTAGGED_TPT_1, "Parity error from Untagged TPT prefetch fifo channel 1" }, + { F_PF_UNTAGGED_TPT_0, "Parity error from Untagged TPT prefetch fifo channel 0" }, + { F_PF_PBL_1, "Parity error from PBL prefetch fifo channel 1" }, + { F_PF_PBL_0, "Parity error from PBL prefetch fifo channel 0" }, + { F_DDP_HINT_1, "DDP hint fifo Perr in channel 1" }, + { F_DDP_HINT_0, "DDP hint fifo Perr in channel 0" }, + { 0 } + }; static const struct intr_info ulprx_intr2_info = { .name = "ULP_RX_INT_CAUSE_2", .cause_reg = A_ULP_RX_INT_CAUSE_2, .enable_reg = A_ULP_RX_INT_ENABLE_2, .fatal = 0, .flags = 0, - .details = NULL, + .details = ulprx_int_cause_2_details, .actions = NULL, }; + static const struct intr_details ulprx_int_cause_pcmd_details[] = { + { F_CAUSE_PCMD_SFIFO_3, "Small FIFOs, channel 3" }, + { F_CAUSE_PCMD_FIFO_3, "pcmd_ctl_fifo, channel 3" }, + { F_CAUSE_PCMD_DDP_HINT_3, "ddp_hint_ctl_fifo FIFO, channel 3" }, + { F_CAUSE_PCMD_TPT_3, "tpt_ctl_fifo FIFO, channel 3" }, + { F_CAUSE_PCMD_DDP_3, "ddp_ctl_fifo FIFO, channel 3" }, + { F_CAUSE_PCMD_MPAR_3, "mpar_ctl_fifo FIFO, channel 3" }, + { F_CAUSE_PCMD_MPAC_3, "mpac_ctl_fifo FIFO, channel 3" }, + { F_CAUSE_PCMD_SFIFO_2, "Small FIFOs, channel 2" }, + { F_CAUSE_PCMD_FIFO_2, "pcmd_ctl_fifo, channel 2" }, + { F_CAUSE_PCMD_DDP_HINT_2, "ddp_hint_ctl_fifo FIFO, channel 2" }, + { F_CAUSE_PCMD_TPT_2, "tpt_ctl_fifo FIFO, channel 2" }, + { F_CAUSE_PCMD_DDP_2, "ddp_ctl_fifo FIFO, channel 2" }, + { F_CAUSE_PCMD_MPAR_2, "mpar_ctl_fifo FIFO, channel 2" }, + { F_CAUSE_PCMD_MPAC_2, "mpac_ctl_fifo FIFO, channel 2" }, + { F_CAUSE_PCMD_SFIFO_1, "Small FIFOs, channel 1" }, + { F_CAUSE_PCMD_FIFO_1, "pcmd_ctl_fifo, channel 1" }, + { F_CAUSE_PCMD_DDP_HINT_1, "ddp_hint_ctl_fifo FIFO, channel 1" }, + { F_CAUSE_PCMD_TPT_1, "tpt_ctl_fifo FIFO, channel 1" }, + { F_CAUSE_PCMD_DDP_1, "ddp_ctl_fifo FIFO, channel 1" }, + { F_CAUSE_PCMD_MPAR_1, "mpar_ctl_fifo FIFO, channel 1" }, + { F_CAUSE_PCMD_MPAC_1, "mpac_ctl_fifo FIFO, channel 1" }, + { F_CAUSE_PCMD_SFIFO_0, "Small FIFOs, channel 0" }, + { F_CAUSE_PCMD_FIFO_0, "pcmd_ctl_fifo, channel 0" }, + { F_CAUSE_PCMD_DDP_HINT_0, "ddp_hint_ctl_fifo FIFO, channel 0" }, + { F_CAUSE_PCMD_TPT_0, "tpt_ctl_fifo FIFO, channel 0" }, + { F_CAUSE_PCMD_DDP_0, "ddp_ctl_fifo FIFO, channel 0" }, + { F_CAUSE_PCMD_MPAR_0, "mpar_ctl_fifo FIFO, channel 0" }, + { F_CAUSE_PCMD_MPAC_0, "mpac_ctl_fifo FIFO, channel 0" }, + { 0 } + }; static const struct intr_info ulprx_int_cause_pcmd = { .name = "ULP_RX_INT_CAUSE_PCMD", .cause_reg = A_ULP_RX_INT_CAUSE_PCMD, .enable_reg = A_ULP_RX_INT_ENABLE_PCMD, .fatal = 0, .flags = 0, - .details = NULL, + .details = ulprx_int_cause_pcmd_details, .actions = NULL, }; + static const struct intr_details ulprx_int_cause_data_details[] = { + { F_CAUSE_DATA_SNOOP_3, "Snoop FIFO, channel 3" }, + { F_CAUSE_DATA_SFIFO_3, "Small FIFO, channel 3" }, + { F_CAUSE_DATA_FIFO_3, "data_ctl_fifo FIFO, channel 3" }, + { F_CAUSE_DATA_DDP_3, "ddp_ctl_fifo FIFO, channel 3" }, + { F_CAUSE_DATA_CTX_3, "ctx_ctl_fifo FIFO, channel 3" }, + { F_CAUSE_DATA_PARSER_3, "parser_ctl_fifo FIFO, channel 3" }, + { F_CAUSE_DATA_SNOOP_2, "Snoop FIFO, channel 2" }, + { F_CAUSE_DATA_SFIFO_2, "Small FIFO, channel 2" }, + { F_CAUSE_DATA_FIFO_2, "data_ctl_fifo FIFO, channel 2" }, + { F_CAUSE_DATA_DDP_2, "ddp_ctl_fifo FIFO, channel 2" }, + { F_CAUSE_DATA_CTX_2, "ctx_ctl_fifo FIFO, channel 2" }, + { F_CAUSE_DATA_PARSER_2, "parser_ctl_fifo FIFO, channel 2" }, + { F_CAUSE_DATA_SNOOP_1, "Snoop FIFO, channel 1" }, + { F_CAUSE_DATA_SFIFO_1, "Small FIFO, channel 1" }, + { F_CAUSE_DATA_FIFO_1, "data_ctl_fifo FIFO, channel 1" }, + { F_CAUSE_DATA_DDP_1, "ddp_ctl_fifo FIFO, channel 1" }, + { F_CAUSE_DATA_CTX_1, "ctx_ctl_fifo FIFO, channel 1" }, + { F_CAUSE_DATA_PARSER_1, "parser_ctl_fifo FIFO, channel 1" }, + { F_CAUSE_DATA_SNOOP_0, "Snoop FIFO, channel 0" }, + { F_CAUSE_DATA_SFIFO_0, "Small FIFO, channel 0" }, + { F_CAUSE_DATA_FIFO_0, "data_ctl_fifo FIFO, channel 0" }, + { F_CAUSE_DATA_DDP_0, "ddp_ctl_fifo FIFO, channel 0" }, + { F_CAUSE_DATA_CTX_0, "ctx_ctl_fifo FIFO, channel 0" }, + { F_CAUSE_DATA_PARSER_0, "parser_ctl_fifo FIFO, channel 0" }, + { 0 } + }; static const struct intr_info ulprx_int_cause_data = { .name = "ULP_RX_INT_CAUSE_DATA", .cause_reg = A_ULP_RX_INT_CAUSE_DATA, .enable_reg = A_ULP_RX_INT_ENABLE_DATA, .fatal = 0, .flags = 0, - .details = NULL, + .details = ulprx_int_cause_data_details, .actions = NULL, }; + static const struct intr_details ulprx_int_cause_arb_details[] = { + { F_CAUSE_ARB_PBL_PF_3, "pbl_pf_ctl_fifo FIFO, channel 3" }, + { F_CAUSE_ARB_PF_3, "pf_ctl_fifo FIFO, channel 3" }, + { F_CAUSE_ARB_TPT_PF_3, "tpt_pf_ctl_fifo FIFO, channel 3" }, + { F_CAUSE_ARB_F_3, "f_ctl_fifo FIFO, channel 3" }, + { F_CAUSE_ARB_PBL_PF_2, "pbl_pf_ctl_fifo FIFO, channel 2" }, + { F_CAUSE_ARB_PF_2, "pf_ctl_fifo FIFO, channel 2" }, + { F_CAUSE_ARB_TPT_PF_2, "tpt_pf_ctl_fifo FIFO, channel 2" }, + { F_CAUSE_ARB_F_2, "f_ctl_fifo FIFO, channel 2" }, + { F_CAUSE_ARB_PBL_PF_1, "pbl_pf_ctl_fifo FIFO, channel 1" }, + { F_CAUSE_ARB_PF_1, "pf_ctl_fifo FIFO, channel 1" }, + { F_CAUSE_ARB_TPT_PF_1, "tpt_pf_ctl_fifo FIFO, channel 1" }, + { F_CAUSE_ARB_F_1, "f_ctl_fifo FIFO, channel 1" }, + { F_CAUSE_ARB_PBL_PF_0, "pbl_pf_ctl_fifo FIFO, channel 0" }, + { F_CAUSE_ARB_PF_0, "pf_ctl_fifo FIFO, channel 0" }, + { F_CAUSE_ARB_TPT_PF_0, "tpt_pf_ctl_fifo FIFO, channel 0" }, + { F_CAUSE_ARB_F_0, "f_ctl_fifo FIFO, channel 0" }, + { 0 } + }; static const struct intr_info ulprx_int_cause_arb = { .name = "ULP_RX_INT_CAUSE_ARB", .cause_reg = A_ULP_RX_INT_CAUSE_ARB, .enable_reg = A_ULP_RX_INT_ENABLE_ARB, .fatal = 0, .flags = 0, - .details = NULL, + .details = ulprx_int_cause_arb_details, .actions = NULL, }; + static const struct intr_details ulprx_int_cause_interface_details[] = { + { F_CAUSE_ULPRX2SBT_RSPPERR, "ULPRX2SBT_RspPerr" }, + { F_CAUSE_ULPRX2MA_RSPPERR, "ULPRX2MA_RspPerr" }, + { F_CAUSE_PIO_BUS_PERR, "Pio_Bus_Perr" }, + { F_CAUSE_PM2ULP_SNOOPDATA_3, "PM2ULP_SnoopData, channel 3" }, + { F_CAUSE_PM2ULP_SNOOPDATA_2, "PM2ULP_SnoopData, channel 2" }, + { F_CAUSE_PM2ULP_SNOOPDATA_1, "PM2ULP_SnoopData, channel 1" }, + { F_CAUSE_PM2ULP_SNOOPDATA_0, "PM2ULP_SnoopData, channel 0" }, + { F_CAUSE_TLS2ULP_DATA_3, "TLS2ULP_Data, channel 3" }, + { F_CAUSE_TLS2ULP_DATA_2, "TLS2ULP_Data, channel 2" }, + { F_CAUSE_TLS2ULP_DATA_1, "TLS2ULP_Data, channel 1" }, + { F_CAUSE_TLS2ULP_DATA_0, "TLS2ULP_Data, channel 0" }, + { F_CAUSE_TLS2ULP_PLENDATA_3, "TLS2ULP_PLenData, channel 3" }, + { F_CAUSE_TLS2ULP_PLENDATA_2, "TLS2ULP_PLenData, channel 2" }, + { F_CAUSE_TLS2ULP_PLENDATA_1, "TLS2ULP_PLenData, channel 1" }, + { F_CAUSE_TLS2ULP_PLENDATA_0, "TLS2ULP_PLenData, channel 0" }, + { F_CAUSE_PM2ULP_DATA_3, "Pm2Ulp_Data, channel 3" }, + { F_CAUSE_PM2ULP_DATA_2, "Pm2Ulp_Data, channel 2" }, + { F_CAUSE_PM2ULP_DATA_1, "Pm2Ulp_Data, channel 1" }, + { F_CAUSE_PM2ULP_DATA_0, "Pm2Ulp_Data, channel 0" }, + { F_CAUSE_TP2ULP_PCMD_3, "Tp2Ulp_Pcmd, channel 3" }, + { F_CAUSE_TP2ULP_PCMD_2, "Tp2Ulp_Pcmd, channel 2" }, + { F_CAUSE_TP2ULP_PCMD_1, "Tp2Ulp_Pcmd, channel 1" }, + { F_CAUSE_TP2ULP_PCMD_0, "Tp2Ulp_Pcmd, channel 0" }, + { 0 } + }; static const struct intr_info ulprx_int_cause_intf = { .name = "ULP_RX_INT_CAUSE_INTERFACE", .cause_reg = A_ULP_RX_INT_CAUSE_INTERFACE, .enable_reg = A_ULP_RX_INT_ENABLE_INTERFACE, .fatal = 0, .flags = 0, - .details = NULL, + .details = ulprx_int_cause_interface_details, .actions = NULL, }; bool fatal = false; + if (chip_id(adap) <= CHELSIO_T5) + ulprx_intr_info.details = ulprx_intr_details; + else if (chip_id(adap) <= CHELSIO_T6) + ulprx_intr_info.details = t6_ulprx_int_cause_details; + else + ulprx_intr_info.details = t7_ulprx_int_cause_details; + fatal |= t4_handle_intr(adap, &ulprx_intr_info, 0, flags); if (chip_id(adap) < CHELSIO_T7) fatal |= t4_handle_intr(adap, &ulprx_intr2_info, 0, flags); @@ -5559,90 +6241,298 @@ static bool ulptx_intr_handler(struct adapter *adap, int arg, int flags) { 0x0fffffff, "ULPTX parity error" }, { 0 } }; - static const struct intr_info ulptx_intr_info = { + static const struct intr_details t6_ulptx_int_cause_details[] = { + { F_PBL_BOUND_ERR_CH3 | F_PBL_BOUND_ERR_CH2 | + F_PBL_BOUND_ERR_CH1 | F_PBL_BOUND_ERR_CH0, + "PBL address out of bounds" }, + { F_SGE2ULP_FIFO_PERR_SET3 | F_SGE2ULP_FIFO_PERR_SET2 | + F_SGE2ULP_FIFO_PERR_SET1 | F_SGE2ULP_FIFO_PERR_SET0, + "SGE2ULP fifo parity error" }, + { F_CIM2ULP_FIFO_PERR_SET3 | F_CIM2ULP_FIFO_PERR_SET2 | + F_CIM2ULP_FIFO_PERR_SET1 | F_CIM2ULP_FIFO_PERR_SET0, + "CIM2ULP fifo parity error" }, + { F_CQE_FIFO_PERR_SET3 | F_CQE_FIFO_PERR_SET2 | + F_CQE_FIFO_PERR_SET1 | F_CQE_FIFO_PERR_SET0, + "CQE fifo parity error" }, + { F_PBL_FIFO_PERR_SET3 | F_PBL_FIFO_PERR_SET2 | + F_PBL_FIFO_PERR_SET1 | F_PBL_FIFO_PERR_SET0, + "PBL fifo parity error" }, + { F_CMD_FIFO_PERR_SET3 | F_CMD_FIFO_PERR_SET2 | + F_CMD_FIFO_PERR_SET1 | F_CMD_FIFO_PERR_SET0, + "Command fifo parity error" }, + { F_LSO_HDR_SRAM_PERR_SET3 | F_LSO_HDR_SRAM_PERR_SET2 | + F_LSO_HDR_SRAM_PERR_SET1 | F_LSO_HDR_SRAM_PERR_SET0, + "LSO hdr parity error" }, + { 0 } + }; + struct intr_info ulptx_intr_info = { .name = "ULP_TX_INT_CAUSE", .cause_reg = A_ULP_TX_INT_CAUSE, .enable_reg = A_ULP_TX_INT_ENABLE, .fatal = 0x0fffffff, .flags = IHF_FATAL_IFF_ENABLED, - .details = ulptx_intr_details, + .details = NULL, + .actions = NULL, + }; + static const struct intr_details ulptx_int_cause_1_details[] = { + { F_PBL_BOUND_ERR_CH3 | F_PBL_BOUND_ERR_CH2 | + F_PBL_BOUND_ERR_CH1 | F_PBL_BOUND_ERR_CH0, + "PBL address out of bounds (configured PBL_ULIMIT/LLIMIT)" }, + { F_SGE2ULP_FIFO_PERR_SET3 | F_SGE2ULP_FIFO_PERR_SET2 | + F_SGE2ULP_FIFO_PERR_SET1 | F_SGE2ULP_FIFO_PERR_SET0, + "SGE2ULP FIFO parity error" }, + { F_CIM2ULP_FIFO_PERR_SET3 | F_CIM2ULP_FIFO_PERR_SET2 | + F_CIM2ULP_FIFO_PERR_SET1 | F_CIM2ULP_FIFO_PERR_SET0, + "CIM2ULP FIFO parity error" }, + { F_CQE_FIFO_PERR_SET3 | F_CQE_FIFO_PERR_SET2 | + F_CQE_FIFO_PERR_SET1 | F_CQE_FIFO_PERR_SET0, + "CQE FIFO parity error" }, + { F_PBL_FIFO_PERR_SET3 | F_PBL_FIFO_PERR_SET2 | + F_PBL_FIFO_PERR_SET1 | F_PBL_FIFO_PERR_SET0, + "PBL FIFO parity error" }, + { F_CMD_FIFO_PERR_SET3 | F_CMD_FIFO_PERR_SET2 | + F_CMD_FIFO_PERR_SET1 | F_CMD_FIFO_PERR_SET0, + "Command FIFO parity error" }, + { F_LSO_HDR_SRAM_PERR_SET3 | F_LSO_HDR_SRAM_PERR_SET2 | + F_LSO_HDR_SRAM_PERR_SET1 | F_LSO_HDR_SRAM_PERR_SET0, + "LSO HDR parity error" }, + { F_TLS_DSGL_PARERR3 | F_TLS_DSGL_PARERR2 | + F_TLS_DSGL_PARERR1 | F_TLS_DSGL_PARERR0, + "TLS Glue DSGL FIFO parity error" }, + { 0 } + }; + static const struct intr_info ulptx_intr_info1 = { + .name = "ULP_TX_INT_CAUSE_1", + .cause_reg = A_ULP_TX_INT_CAUSE_1, + .enable_reg = A_ULP_TX_INT_ENABLE_1, + .fatal = 0x0fffffff, + .flags = IHF_FATAL_IFF_ENABLED, + .details = ulptx_int_cause_1_details, .actions = NULL, }; + static const struct intr_details ulptx_int_cause_2_details[] = { + { F_EDMA_IN_FIFO_PERR_SET3 | F_EDMA_IN_FIFO_PERR_SET2 | + F_EDMA_IN_FIFO_PERR_SET1 | F_EDMA_IN_FIFO_PERR_SET0, + "EDMA input FIFO parity error" }, + { F_ALIGN_CTL_FIFO_PERR_SET3 | F_ALIGN_CTL_FIFO_PERR_SET2 | + F_ALIGN_CTL_FIFO_PERR_SET1 | F_ALIGN_CTL_FIFO_PERR_SET0, + "Align control FIFO parity error" }, + { F_SGE_FIFO_PERR_SET3 | F_SGE_FIFO_PERR_SET2 | + F_SGE_FIFO_PERR_SET1 | F_SGE_FIFO_PERR_SET0, + "SGE FIFO parity error" }, + { F_STAG_FIFO_PERR_SET3 | F_STAG_FIFO_PERR_SET2 | + F_STAG_FIFO_PERR_SET1 | F_STAG_FIFO_PERR_SET0, + "STAG FIFO parity error" }, + { F_MAP_FIFO_PERR_SET3 | F_MAP_FIFO_PERR_SET2 | + F_MAP_FIFO_PERR_SET1 | F_MAP_FIFO_PERR_SET0, + "MAP FIFO parity error" }, + { F_DMA_FIFO_PERR_SET3 | F_DMA_FIFO_PERR_SET2 | + F_DMA_FIFO_PERR_SET1 | F_DMA_FIFO_PERR_SET0, + "DMA FIFO parity error" }, + { F_FSO_HDR_SRAM_PERR_SET3 | F_FSO_HDR_SRAM_PERR_SET2 | + F_FSO_HDR_SRAM_PERR_SET1 | F_FSO_HDR_SRAM_PERR_SET0, + "FSO HDR memory parity error" }, + { F_T10_PI_SRAM_PERR_SET3 | F_T10_PI_SRAM_PERR_SET2 | + F_T10_PI_SRAM_PERR_SET1 | F_T10_PI_SRAM_PERR_SET0, + "T10 PI memory parity error" }, + { 0 } + }; static const struct intr_info ulptx_intr_info2 = { .name = "ULP_TX_INT_CAUSE_2", .cause_reg = A_ULP_TX_INT_CAUSE_2, .enable_reg = A_ULP_TX_INT_ENABLE_2, .fatal = 0xffffffff, .flags = IHF_FATAL_IFF_ENABLED, - .details = NULL, + .details = ulptx_int_cause_2_details, .actions = NULL, }; + static const struct intr_details ulptx_int_cause_3_details[] = { + { F_GF_SGE_FIFO_PARERR3 | F_GF_SGE_FIFO_PARERR2 | + F_GF_SGE_FIFO_PARERR1 | F_GF_SGE_FIFO_PARERR0, + "GF SGE interface FIFO parity error" }, + { F_DEDUPE_SGE_FIFO_PARERR3 | F_DEDUPE_SGE_FIFO_PARERR2 | + F_DEDUPE_SGE_FIFO_PARERR1 | F_DEDUPE_SGE_FIFO_PARERR0, + "DeDupe SGE interface FIFO parity error" }, + { F_GF3_DSGL_FIFO_PARERR | F_GF2_DSGL_FIFO_PARERR | + F_GF1_DSGL_FIFO_PARERR | F_GF0_DSGL_FIFO_PARERR, + "GF DSGL FIFO parity error" }, + { F_DEDUPE3_DSGL_FIFO_PARERR | F_DEDUPE2_DSGL_FIFO_PARERR | + F_DEDUPE1_DSGL_FIFO_PARERR | F_DEDUPE0_DSGL_FIFO_PARERR, + "DeDupe DSGL FIFO parity error" }, + { F_XP10_SGE_FIFO_PARERR, "XP10 SGE FIFO parity error (Ch0)" }, + { F_DSGL_PAR_ERR, "XP10 DSGL interface parity error" }, + { F_CDDIP_INT, "XP10 decompression interrupt" }, + { F_CCEIP_INT, "XP10 compression interrupt" }, + { F_TLS_SGE_FIFO_PARERR3 | F_TLS_SGE_FIFO_PARERR2 | + F_TLS_SGE_FIFO_PARERR1 | F_TLS_SGE_FIFO_PARERR0, + "TLS Glue SGE FIFO parity error" }, + { F_ULP2SMARBT_RSP_PERR, "ULP2SMARBT response data/CTL parity error" }, + { F_ULPTX2MA_RSP_PERR, "ULP2MA response data/CTL parity error" }, + { F_PCIE2ULP_PERR3 | F_PCIE2ULP_PERR2 | + F_PCIE2ULP_PERR1 | F_PCIE2ULP_PERR0, + "PCIE2ULP EDMA response parity error" }, + { F_CIM2ULP_PERR, "CIM2ULP command parity error (all ports)" }, + { 0 } + }; static const struct intr_info ulptx_intr_info3 = { .name = "ULP_TX_INT_CAUSE_3", .cause_reg = A_ULP_TX_INT_CAUSE_3, .enable_reg = A_ULP_TX_INT_ENABLE_3, .fatal = 0xffffffff, .flags = IHF_FATAL_IFF_ENABLED, - .details = NULL, + .details = ulptx_int_cause_3_details, .actions = NULL, }; + static const struct intr_details ulptx_int_cause_4_details[] = { + { F_XP10_2_ULP_PERR, "XP10 to ULP parity error" }, + { F_ULP_2_XP10_PERR, "ULP to XP10 parity error" }, + { F_CMD_FIFO_LB1 | F_CMD_FIFO_LB0, + "Command FIFO LB error" }, + { F_TF_TP_PERR, "TF TP parity error" }, + { F_TF_SGE_PERR, "TF SGE parity error" }, + { F_TF_MEM_PERR, "TF memory parity error" }, + { F_TF_MP_PERR, "TF MP parity error" }, + { 0 } + }; static const struct intr_info ulptx_intr_info4 = { .name = "ULP_TX_INT_CAUSE_4", .cause_reg = A_ULP_TX_INT_CAUSE_4, .enable_reg = A_ULP_TX_INT_ENABLE_4, .fatal = 0xffffffff, .flags = IHF_FATAL_IFF_ENABLED, - .details = NULL, + .details = ulptx_int_cause_4_details, .actions = NULL, }; + static const struct intr_details ulptx_int_cause_5_details[] = { + { F_DEDUPE_PERR3 | F_DEDUPE_PERR2 | + F_DEDUPE_PERR1 | F_DEDUPE_PERR0, + "DeDupe parity error" }, + { F_GF_PERR3 | F_GF_PERR2 | + F_GF_PERR1 | F_GF_PERR0, + "GF parity error" }, + { F_SGE2ULP_INV_PERR, "SGE2ULP invalid parity error" }, + { F_T7_PL_BUSPERR, "PL bus parity error" }, + { F_TLSTX2ULPTX_PERR3 | F_TLSTX2ULPTX_PERR2 | + F_TLSTX2ULPTX_PERR1 | F_TLSTX2ULPTX_PERR0, + "TLS to ULP parity error" }, + { F_XP10_2_ULP_PL_PERR, "XP10 to ULP PL parity error" }, + { F_ULP_2_XP10_PL_PERR, "ULP to XP10 PL parity error" }, + { 0 } + }; static const struct intr_info ulptx_intr_info5 = { .name = "ULP_TX_INT_CAUSE_5", .cause_reg = A_ULP_TX_INT_CAUSE_5, .enable_reg = A_ULP_TX_INT_ENABLE_5, .fatal = 0xffffffff, .flags = IHF_FATAL_IFF_ENABLED, - .details = NULL, + .details = ulptx_int_cause_5_details, .actions = NULL, }; + static const struct intr_details ulptx_int_cause_6_details[] = { + { F_DDR_HDR_FIFO_PERR_SET3 | F_DDR_HDR_FIFO_PERR_SET2 | + F_DDR_HDR_FIFO_PERR_SET1 | F_DDR_HDR_FIFO_PERR_SET0, + "DDR HDR FIFO parity error" }, + { F_PRE_MP_RSP_PERR_SET3 | F_PRE_MP_RSP_PERR_SET2 | + F_PRE_MP_RSP_PERR_SET1 | F_PRE_MP_RSP_PERR_SET0, + "Pre-MP response parity error" }, + { F_PRE_CQE_FIFO_PERR_SET3 | F_PRE_CQE_FIFO_PERR_SET2 | + F_PRE_CQE_FIFO_PERR_SET1 | F_PRE_CQE_FIFO_PERR_SET0, + "Pre-CQE FIFO parity error" }, + { F_RSP_FIFO_PERR_SET, "Response FIFO parity error" }, + { 0 } + }; static const struct intr_info ulptx_intr_info6 = { .name = "ULP_TX_INT_CAUSE_6", .cause_reg = A_ULP_TX_INT_CAUSE_6, .enable_reg = A_ULP_TX_INT_ENABLE_6, .fatal = 0xffffffff, .flags = IHF_FATAL_IFF_ENABLED, - .details = NULL, + .details = ulptx_int_cause_6_details, .actions = NULL, }; + static const struct intr_details ulptx_int_cause_7_details[] = { + { F_TLS_SGE_FIFO_CORERR3 | F_TLS_SGE_FIFO_CORERR2 | + F_TLS_SGE_FIFO_CORERR1 | F_TLS_SGE_FIFO_CORERR0, + "TLS SGE FIFO correctable error" }, + { F_LSO_HDR_SRAM_CERR_SET3 | F_LSO_HDR_SRAM_CERR_SET2 | + F_LSO_HDR_SRAM_CERR_SET1 | F_LSO_HDR_SRAM_CERR_SET0, + "LSO HDR SRAM correctable error" }, + { F_CORE_CMD_FIFO_CERR_SET_CH3_LB1 | F_CORE_CMD_FIFO_CERR_SET_CH2_LB1 | + F_CORE_CMD_FIFO_CERR_SET_CH1_LB1 | F_CORE_CMD_FIFO_CERR_SET_CH0_LB1, + "Core command FIFO LB1 correctable error" }, + { F_CORE_CMD_FIFO_CERR_SET_CH3_LB0 | F_CORE_CMD_FIFO_CERR_SET_CH2_LB0 | + F_CORE_CMD_FIFO_CERR_SET_CH1_LB0 | F_CORE_CMD_FIFO_CERR_SET_CH0_LB0, + "Core command FIFO LB0 correctable error" }, + { F_CQE_FIFO_CERR_SET3 | F_CQE_FIFO_CERR_SET2 | + F_CQE_FIFO_CERR_SET1 | F_CQE_FIFO_CERR_SET0, + "CQE FIFO correctable error" }, + { F_PRE_CQE_FIFO_CERR_SET3 | F_PRE_CQE_FIFO_CERR_SET2 | + F_PRE_CQE_FIFO_CERR_SET1 | F_PRE_CQE_FIFO_CERR_SET0, + "Pre-CQE FIFO correctable error" }, + { 0 } + }; static const struct intr_info ulptx_intr_info7 = { .name = "ULP_TX_INT_CAUSE_7", .cause_reg = A_ULP_TX_INT_CAUSE_7, .enable_reg = A_ULP_TX_INT_ENABLE_7, .fatal = 0, .flags = 0, - .details = NULL, + .details = ulptx_int_cause_7_details, .actions = NULL, }; + static const struct intr_details ulptx_int_cause_8_details[] = { + { F_MEM_RSP_FIFO_CERR_SET3 | F_MEM_RSP_FIFO_CERR_SET2 | + F_MEM_RSP_FIFO_CERR_SET1 | F_MEM_RSP_FIFO_CERR_SET0, + "Memory response FIFO correctable error" }, + { F_PI_SRAM_CERR_SET3 | F_PI_SRAM_CERR_SET2 | + F_PI_SRAM_CERR_SET1 | F_PI_SRAM_CERR_SET0, + "PI SRAM correctable error" }, + { F_PRE_MP_RSP_CERR_SET3 | F_PRE_MP_RSP_CERR_SET2 | + F_PRE_MP_RSP_CERR_SET1 | F_PRE_MP_RSP_CERR_SET0, + "Pre-MP response correctable error" }, + { F_DDR_HDR_FIFO_CERR_SET3 | F_DDR_HDR_FIFO_CERR_SET2 | + F_DDR_HDR_FIFO_CERR_SET1 | F_DDR_HDR_FIFO_CERR_SET0, + "DDR HDR FIFO correctable error" }, + { F_CMD_FIFO_CERR_SET3 | F_CMD_FIFO_CERR_SET2 | + F_CMD_FIFO_CERR_SET1 | F_CMD_FIFO_CERR_SET0, + "Command FIFO correctable error" }, + { F_GF_SGE_FIFO_CORERR3 | F_GF_SGE_FIFO_CORERR2 | + F_GF_SGE_FIFO_CORERR1 | F_GF_SGE_FIFO_CORERR0, + "GF SGE FIFO correctable error" }, + { F_DEDUPE_SGE_FIFO_CORERR3 | F_DEDUPE_SGE_FIFO_CORERR2 | + F_DEDUPE_SGE_FIFO_CORERR1 | F_DEDUPE_SGE_FIFO_CORERR0, + "DeDupe SGE FIFO correctable error" }, + { F_RSP_FIFO_CERR_SET, "Response FIFO correctable error" }, + { 0 } + }; static const struct intr_info ulptx_intr_info8 = { .name = "ULP_TX_INT_CAUSE_8", .cause_reg = A_ULP_TX_INT_CAUSE_8, .enable_reg = A_ULP_TX_INT_ENABLE_8, .fatal = 0, .flags = 0, - .details = NULL, + .details = ulptx_int_cause_8_details, .actions = NULL, }; bool fatal = false; - fatal |= t4_handle_intr(adap, &ulptx_intr_info, 0, flags); - if (chip_id(adap) > CHELSIO_T4) - fatal |= t4_handle_intr(adap, &ulptx_intr_info2, 0, flags); if (chip_id(adap) > CHELSIO_T6) { + fatal |= t4_handle_intr(adap, &ulptx_intr_info1, 0, flags); + fatal |= t4_handle_intr(adap, &ulptx_intr_info2, 0, flags); fatal |= t4_handle_intr(adap, &ulptx_intr_info3, 0, flags); fatal |= t4_handle_intr(adap, &ulptx_intr_info4, 0, flags); fatal |= t4_handle_intr(adap, &ulptx_intr_info5, 0, flags); fatal |= t4_handle_intr(adap, &ulptx_intr_info6, 0, flags); fatal |= t4_handle_intr(adap, &ulptx_intr_info7, 0, flags); fatal |= t4_handle_intr(adap, &ulptx_intr_info8, 0, flags); + } else { + if (chip_id(adap) == CHELSIO_T6) + ulptx_intr_info.details = t6_ulptx_int_cause_details; + else + ulptx_intr_info.details = ulptx_intr_details; + fatal |= t4_handle_intr(adap, &ulptx_intr_info, 0, flags); + if (chip_id(adap) > CHELSIO_T4) + fatal |= t4_handle_intr(adap, &ulptx_intr_info2, 0, flags); } return (fatal); @@ -5671,6 +6561,25 @@ static bool pmtx_dump_dbg_stats(struct adapter *adap, int arg, int flags) */ static bool pmtx_intr_handler(struct adapter *adap, int arg, int flags) { + static const struct intr_details t7_pmtx_int_cause_fields[] = { + { F_MASTER_PERR, "PM_TX master parity error" }, + { F_T7_ZERO_C_CMD_ERROR, "PM_TX PCMD with zero length error" }, + { F_OESPI_COR_ERR, " oespi FIFO Correctable Error" }, + { F_ICSPI_COR_ERR, " icspi FIFO Correctable Error" }, + { F_ICSPI_OVFL, " icspi FIFO overflow" }, + { F_T7_PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large" }, + { F_T7_PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large" }, + { F_T7_PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large" }, + { F_PCMD_LEN_OVFL3, "PMTX channel 2 pcmd too large" }, + { F_T7_ZERO_C_CMD_ERROR, "PMTX 0-length pcmd" }, + { 0x00f00000, "PM_TX PCMD length larger than oespi capacity" }, + { 0x000f0000, "PM_TX icspi 2x FIFO Rx framing error" }, + { 0x0000f000, "PM_TX icspi FIFO Tx framing error" }, + { 0x00000f00, "PM_TX oespi FIFO Rx framing error" }, + { 0x000000f0, "PM_TX oespi FIFO Tx framing error" }, + { 0x0000000f, "PM_TX oespi 2x FIFO Tx framing error" }, + { 0 } + }; static const struct intr_details pmtx_int_cause_fields[] = { { F_PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large" }, { F_PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large" }, @@ -5692,17 +6601,58 @@ static bool pmtx_intr_handler(struct adapter *adap, int arg, int flags) { 0xffffffff, -1, pmtx_dump_dbg_stats }, { 0 }, }; - static const struct intr_info pmtx_int_cause = { + struct intr_info pmtx_int_cause = { .name = "PM_TX_INT_CAUSE", .cause_reg = A_PM_TX_INT_CAUSE, .enable_reg = A_PM_TX_INT_ENABLE, .fatal = 0xffffffff, - .flags = 0, - .details = pmtx_int_cause_fields, + .flags = IHF_CLR_DELAYED, + .details = NULL, .actions = pmtx_int_cause_actions, }; + static const struct intr_details pmtx_perr_cause_details[] = { + { F_ICSPI_OVFL, "icspi FIFO Overflow" }, + { F_OSPI_OVERFLOW3_TX, " OSPI overflow on channel 3 error." }, + { F_OSPI_OVERFLOW2_TX, " OSPI overflow on channel 2 error." }, + { F_OSPI_OVERFLOW1_TX, " OSPI overflow on channel 1 error." }, + { F_OSPI_OVERFLOW0_TX, " OSPI overflow on channel 0 error." }, + { F_T7_BUNDLE_LEN_OVFL_EN, "This bit indicates bundle_len_ovfl_err." }, + { F_T7_M_INTFPERREN, "This bit indicates Parity error from MA interfaces." }, + { F_T7_1_SDC_ERR, + "SDC Error reported by Check PCMD which carries CRC16 from TP-CSide." }, + { F_MC_WCNT_FIFO_PERR, "MC Interface Write count FIFO Parity error" }, + { F_MC_WDATA_FIFO_PERR, "MC Interface Write Data FIFO Parity error" }, + { F_MC_RCNT_FIFO_PERR, "MC Interface Read count FIFO Parity error" }, + { F_MC_RDATA_FIFO_PERR, "MC Interface Read Data FIFO Parity error" }, + { F_TOKEN_PAR_ERROR, "c_pcmd, Token FIFO par error" }, + { F_BUNDLE_LEN_PAR_ERROR, "oespi par error" }, + { F_OESPI_PAR_ERROR, "oespi par error" }, + { F_DB_OPTIONS_PAR_ERROR, "db_options par error" }, + { F_ICSPI_PAR_ERROR, "icspi par error" }, + { F_C_PCMD_TOKEN_PAR_ERROR, "c_pcmd par error" }, + { 0 } + }; + static struct intr_info pmtx_perr_cause = { + .name = "PM_TX_PERR_CAUSE", + .cause_reg = A_PM_TX_PERR_CAUSE, + .enable_reg = A_PM_TX_PERR_ENABLE, + .fatal = 0xffffffff, + .flags = 0, + .details = pmtx_perr_cause_details, + .actions = NULL, + }; + bool fatal; + + if (chip_id(adap) >= CHELSIO_T7) + pmtx_int_cause.details = t7_pmtx_int_cause_fields; + else + pmtx_int_cause.details = pmtx_int_cause_fields; + fatal = t4_handle_intr(adap, &pmtx_int_cause, 0, flags); + if (chip_id(adap) >= CHELSIO_T7) + fatal |= t4_handle_intr(adap, &pmtx_perr_cause, 0, flags); + clear_int_cause_reg(adap, &pmtx_int_cause, flags); - return (t4_handle_intr(adap, &pmtx_int_cause, 0, flags)); + return (fatal); } /* @@ -5710,6 +6660,20 @@ static bool pmtx_intr_handler(struct adapter *adap, int arg, int flags) */ static bool pmrx_intr_handler(struct adapter *adap, int arg, int flags) { + static const struct intr_details t7_pmrx_int_cause_fields[] = { + { F_MASTER_PERR, "PM_RX master parity error" }, + { 0x18000000, "PMRX ospi overflow" }, + { F_BUNDLE_LEN_OVFL, "PMRX bundle len FIFO overflow" }, + { F_SDC_ERR, "PMRX SDC error" }, + { F_ZERO_E_CMD_ERROR, "PMRX 0-length pcmd" }, + { 0x003c0000, "PMRX iespi FIFO2X Rx framing error" }, + { 0x0003c000, "PMRX iespi Rx framing error" }, + { 0x00003c00, "PMRX iespi Tx framing error" }, + { 0x00000300, "PMRX ocspi Rx framing error" }, + { 0x000000c0, "PMRX ocspi Tx framing error" }, + { 0x00000030, "PMRX ocspi FIFO2X Tx framing error" }, + { 0 } + }; static const struct intr_details pmrx_int_cause_fields[] = { /* T6+ */ { 0x18000000, "PMRX ospi overflow" }, @@ -5732,17 +6696,90 @@ static bool pmrx_intr_handler(struct adapter *adap, int arg, int flags) { F_E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error"}, { 0 } }; - static const struct intr_info pmrx_int_cause = { + struct intr_info pmrx_int_cause = { .name = "PM_RX_INT_CAUSE", .cause_reg = A_PM_RX_INT_CAUSE, .enable_reg = A_PM_RX_INT_ENABLE, .fatal = 0x1fffffff, + .flags = IHF_FATAL_IFF_ENABLED | IHF_CLR_DELAYED, + .details = NULL, + .actions = NULL, + }; + static const struct intr_details pm_rx_int_cause_2_details[] = { + { F_CACHE_SRAM_ODD_CERR, "Cache Data Odd SRAM Correctable Error" }, + { F_CACHE_SRAM_EVEN_CERR, "Cache Data Even SRAM Correctable Error" }, + { F_CACHE_LRU_LEFT_CERR, "Cache LRU Left SRAM Correctable Error" }, + { F_CACHE_LRU_RIGHT_CERR, "Cache LRU Right SRAM Correctable Error" }, + { F_CACHE_ISLAND_CERR, "Cache Island SRAM Correctable Error" }, + { F_OCSPI_CERR, "ocspi FIFO Correctable Error" }, + { F_IESPI_CERR, "iespi FIFO Correctable Error" }, + { F_OCSPI2_RX_FRAMING_ERROR, "ocspi FIFO channel 2 Rx/wr framing error" }, + { F_OCSPI3_RX_FRAMING_ERROR, "ocspi FIFO channel 3 Rx/wr framing error" }, + { F_OCSPI2_TX_FRAMING_ERROR, "ocspi FIFO channel 2 Tx/rd framing error" }, + { F_OCSPI3_TX_FRAMING_ERROR, "ocspi FIFO channel 3 Tx/rd framing error" }, + { F_OCSPI2_OFIFO2X_TX_FRAMING_ERROR, "ocspi 2x FIFO 2 Tx/rd framing error" }, + { F_OCSPI3_OFIFO2X_TX_FRAMING_ERROR, "ocspi 2x FIFO 3 Tx/rd framing error" }, + { 0 } + }; + static struct intr_info pmrx_int_cause2 = { + .name = "PM_RX_INT_CAUSE_2", + .cause_reg = A_PM_RX_INT_CAUSE_2, + .enable_reg = A_PM_RX_INT_ENABLE_2, + .fatal = 0x1fffffff, + .flags = IHF_FATAL_IFF_ENABLED, + .details = pm_rx_int_cause_2_details, + .actions = NULL, + }; + static const struct intr_details pm_rx_perr_cause_details[] = { + { F_T7_SDC_ERR, "SDC error. CRC provided by TP and PM didn't match." }, + { F_T7_MA_INTF_SDC_ERR, "MA intf SDC perr" }, + { F_E_PCMD_PERR, "ulp_rx 2 pm_rx PCMD interface parity error." }, + { F_CACHE_RSP_DFIFO_PERR, "Cache Response Data FIFO Parity error" }, + { F_CACHE_SRAM_ODD_PERR, "Cache Odd SRAM error" }, + { F_CACHE_SRAM_EVEN_PERR, "Cache Even SRAM error" }, + { F_CACHE_RSVD_PERR, "Cache Reserved Parity error" }, + { F_CACHE_LRU_LEFT_PERR, "Cache LRU Left SRAM error" }, + { F_CACHE_LRU_RIGHT_PERR, "Cache LRU Rigth SRAM error" }, + { F_CACHE_RSP_CMD_PERR, "Cache Response Command FIFO error" }, + { F_CACHE_SRAM_CMD_PERR, "Cache SRAM Command FIFO error" }, + { F_CACHE_MA_CMD_PERR, "Cache MA Command FIFO error" }, + { F_CACHE_TCAM_PERR, "Cache TCAM Parity error" }, + { F_CACHE_ISLAND_PERR, "Cache island SRAM Parity error" }, + { F_MC_WCNT_FIFO_PERR, "MC Interface Write count FIFO Parity error" }, + { F_MC_WDATA_FIFO_PERR, "MC Interface Write Data FIFO Parity error" }, + { F_MC_RCNT_FIFO_PERR, "MC Interface Read count FIFO Parity error" }, + { F_MC_RDATA_FIFO_PERR, "MC Interface Read Data FIFO Parity error" }, + { F_TOKEN_FIFO_PERR, "Token FIFO Parity error" }, + { F_T7_BUNDLE_LEN_PARERR, "Bundle len fifo had parity error." }, + { F_OCSPI_PAR_ERROR, "ocspi par error vector" }, + { F_DB_OPTIONS_PAR_ERROR, "db_options par error" }, + { F_IESPI_PAR_ERROR, "iespi par error" }, + { F_E_PCMD_PAR_ERROR, "e_pcmd par error" }, + { 0 } + }; + static struct intr_info pmrx_perr_cause = { + .name = "PM_RX_PERR_CAUSE", + .cause_reg = A_PM_RX_PERR_CAUSE, + .enable_reg = A_PM_RX_PERR_ENABLE, + .fatal = 0x1fffffff, .flags = IHF_FATAL_IFF_ENABLED, - .details = pmrx_int_cause_fields, + .details = pm_rx_perr_cause_details, .actions = NULL, }; + bool fatal; + + if (chip_id(adap) >= CHELSIO_T7) { + pmrx_int_cause.details = t7_pmrx_int_cause_fields; + fatal = t4_handle_intr(adap, &pmrx_int_cause, 0, flags); + fatal |= t4_handle_intr(adap, &pmrx_int_cause2, 0, flags); + fatal |= t4_handle_intr(adap, &pmrx_perr_cause, 0, flags); + } else { + pmrx_int_cause.details = pmrx_int_cause_fields; + fatal = t4_handle_intr(adap, &pmrx_int_cause, 0, flags); + } + clear_int_cause_reg(adap, &pmrx_int_cause, flags); - return (t4_handle_intr(adap, &pmrx_int_cause, 0, flags)); + return (fatal); } /* @@ -5751,6 +6788,9 @@ static bool pmrx_intr_handler(struct adapter *adap, int arg, int flags) static bool cplsw_intr_handler(struct adapter *adap, int arg, int flags) { static const struct intr_details cplsw_int_cause_fields[] = { + /* T7+ */ + { F_PERR_CPL_128TO128_3, "CPLSW 128TO128 FIFO3 parity error" }, + { F_PERR_CPL_128TO128_2, "CPLSW 128TO128 FIFO2 parity error" }, /* T5+ */ { F_PERR_CPL_128TO128_1, "CPLSW 128TO128 FIFO1 parity error" }, { F_PERR_CPL_128TO128_0, "CPLSW 128TO128 FIFO0 parity error" }, @@ -5803,6 +6843,8 @@ static bool le_intr_handler(struct adapter *adap, int arg, int flags) { 0 } }; static const struct intr_details t6_le_intr_details[] = { + { F_CACHEINTPERR, "Parity error in cache module" }, + { F_CACHESRAMPERR, "Parity error in data sram " }, { F_CLIPSUBERR, "LE CLIP CAM reverse substitution error" }, { F_CLCAMFIFOERR, "LE CLIP CAM internal FIFO error" }, { F_CTCAMINVLDENT, "Invalid IPv6 CLIP TCAM entry" }, @@ -5865,51 +6907,206 @@ static bool mps_intr_handler(struct adapter *adap, int arg, int flags) .details = mps_rx_perr_intr_details, .actions = NULL, }; + static const struct intr_details mps_rx_func_intr_details[] = { + { F_MTU_ERR3, "MTU error interrupt enable bit for loopback group 3" }, + { F_MTU_ERR2, "MTU error interrupt enable bit for loopback group 2" }, + { F_MTU_ERR1, "MTU error interrupt enable bit for loopback group 1" }, + { F_MTU_ERR0, "MTU error interrupt enable bit for loopback group 0" }, + { F_DBG_LEN_ERR, "Oring of len error in traffic transfer b/w internal modules" }, + { F_DBG_SPI_ERR, "Oring of spi error in traffic transfer b/w internal modules" }, + { F_DBG_SE_CNT_ERR, "Oring of se cnt error in traffic transfer" }, + { F_DBG_SPI_LEN_SE_CNT_ERR, "Oring of all se_cnt|len|spi errors" }, + { 0 } + }; + static const struct intr_info mps_rx_func_intr_info = { + .name = "MPS_RX_FUNC_INT_CAUSE", + .cause_reg = A_MPS_RX_FUNC_INT_CAUSE, + .enable_reg = A_MPS_RX_FUNC_INT_ENABLE, + .fatal = 0xffffffff, + .flags = IHF_FATAL_IFF_ENABLED, + .details = mps_rx_func_intr_details, + .actions = NULL, + }; + static const struct intr_details mpsrx_int_cause_2_details[] = { + { F_CRYPTO2MPS_RX0_PERR | F_CRYPTO2MPS_RX1_PERR | + F_CRYPTO2MPS_RX2_PERR | F_CRYPTO2MPS_RX3_PERR, + "Crypto to MPS RX interface parity error" }, + { F_INIC2MPS_TX1_PERR | F_INIC2MPS_TX0_PERR, + "INIC to MPS TX interface parity error" }, + { F_XGMAC2MPS_RX1_PERR | F_XGMAC2MPS_RX0_PERR, + "XGMAC to MPS RX interface parity error" }, + { F_RX_FINAL_TF_FIFO_PERR, + "Final RX token FIFO output parity error" }, + { F_MPS_DWRR_FIFO_PERR, + "MPS DWRR MTU FIFO parity error" }, + { F_MAC_TF_FIFO_PERR, + "MAC token FIFO parity error" }, + { F_MAC2MPS_PT3_PERR | F_MAC2MPS_PT2_PERR | + F_MAC2MPS_PT1_PERR | F_MAC2MPS_PT0_PERR, + "MAC to MPS interface parity error" }, + { F_TP_LPBK_FIFO_PERR, "TP loopback FIFO parity error" }, + { F_TP_LPBK_TF_PERR, "Loopback token FIFO parity error" }, + { 0 } + }; static const struct intr_info mps_rx_perr_intr_info2 = { .name = "MPS_RX_PERR_INT_CAUSE2", .cause_reg = A_MPS_RX_PERR_INT_CAUSE2, .enable_reg = A_MPS_RX_PERR_INT_ENABLE2, .fatal = 0xffffffff, .flags = IHF_FATAL_IFF_ENABLED, - .details = NULL, + .details = mpsrx_int_cause_2_details, .actions = NULL, }; + static const struct intr_details mpsrx_int_cause_3_details[] = { + { F_FIFO_REPL_CH3_CERR | F_FIFO_REPL_CH2_CERR | + F_FIFO_REPL_CH1_CERR | F_FIFO_REPL_CH0_CERR, + "Replication FIFO ECC error" }, + { F_VLAN_FILTER_RAM_CERR, "VLAN filter SRAM ECC error" }, + { F_MPS_RX_TD_STAT_FIFO_PERR_CH3 | F_MPS_RX_TD_STAT_FIFO_PERR_CH2 | + F_MPS_RX_TD_STAT_FIFO_PERR_CH1 | F_MPS_RX_TD_STAT_FIFO_PERR_CH0, + "MPS RX TD status descriptor FIFO parity error" }, + { F_RPLCT_HDR_FIFO_IN_PERR_CH3 | F_RPLCT_HDR_FIFO_IN_PERR_CH2 | + F_RPLCT_HDR_FIFO_IN_PERR_CH1 | F_RPLCT_HDR_FIFO_IN_PERR_CH0, + "MPS RX replication header input FIFO parity error" }, + { F_ID_FIFO_IN_PERR_CH3 | F_ID_FIFO_IN_PERR_CH2 | + F_ID_FIFO_IN_PERR_CH1 | F_ID_FIFO_IN_PERR_CH0, + "MPS RX replication ID input FIFO parity error" }, + { F_DESC_HDR2_PERR_CH3 | F_DESC_HDR2_PERR_CH2 | + F_DESC_HDR2_PERR_CH1 | F_DESC_HDR2_PERR_CH0, + "MPS RX replication descriptor/header2 FIFO parity error" }, + { F_FIFO_REPL_PERR_CH3 | F_FIFO_REPL_PERR_CH2 | + F_FIFO_REPL_PERR_CH1 | F_FIFO_REPL_PERR_CH0, + "Replication FIFO parity error" }, + { F_MPS_RX_TD_PERR_CH3 | F_MPS_RX_TD_PERR_CH2 | + F_MPS_RX_TD_PERR_CH1 | F_MPS_RX_TD_PERR_CH0, + "MPS RX TD input FIFO parity error" }, + { 0 } + }; static const struct intr_info mps_rx_perr_intr_info3 = { .name = "MPS_RX_PERR_INT_CAUSE3", .cause_reg = A_MPS_RX_PERR_INT_CAUSE3, .enable_reg = A_MPS_RX_PERR_INT_ENABLE3, .fatal = 0xffffffff, .flags = IHF_FATAL_IFF_ENABLED, - .details = NULL, + .details = mpsrx_int_cause_3_details, .actions = NULL, }; + static const struct intr_details mpsrx_int_cause_4_details[] = { + { F_VNI_MULTICAST_FIFO_ECC_ERR_CH3 | F_VNI_MULTICAST_FIFO_ECC_ERR_CH2, + "RX out VNI multicast SRAM ECC error" }, + { F_HASH_SRAM_CLS_ENG1 | F_HASH_SRAM_CLS_ENG0, + "Classification engine hash SRAM ECC error" }, + { F_CLS_TCAM_SRAM_CLS_ENG1 | F_CLS_TCAM_SRAM_CLS_ENG0, + "Classification engine TCAM SRAM ECC error" }, + { F_CLS_TCAM_CRC_SRAM_CLS_ENG1 | F_CLS_TCAM_CRC_SRAM_CLS_ENG0, + "Classification engine TCAM CRC SRAM ECC error" }, + { F_DWRR_CH_FIFO_ECC_ERR, "DWRR output FIFO ECC error" }, + { F_MAC_RX_FIFO_ECC_ERR, "MAC RX FIFO ECC error" }, + { F_LPBK_RX_FIFO_ECC_ERR, "Loopback RX FIFO ECC error" }, + { F_CRS_DATA_STORE_N_FWD_CH3 | F_CRS_DATA_STORE_N_FWD_CH2 | + F_CRS_DATA_STORE_N_FWD_CH1 | F_CRS_DATA_STORE_N_FWD_CH0, + "CRS store and forward FIFO ECC error" }, + { F_TRACE_FWD_FIFO_CERR_CH3 | F_TRACE_FWD_FIFO_CERR_CH2 | + F_TRACE_FWD_FIFO_CERR_CH1 | F_TRACE_FWD_FIFO_CERR_CH0, + "Trace packet forward FIFO ECC error" }, + { F_TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH3 | F_TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH2 | + F_TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH1 | F_TRANSPARENT_ENCAP_FWD_FIFO_CERR_CH0, + "Transparent encap forward FIFO ECC error" }, + { F_PTP_TRACE_FWD_FIFO_CERR_CH3 | F_PTP_TRACE_FWD_FIFO_CERR_CH2 | + F_PTP_TRACE_FWD_FIFO_CERR_CH1 | F_PTP_TRACE_FWD_FIFO_CERR_CH0, + "PTP packet forward FIFO ECC error" }, + { 0 } + }; static const struct intr_info mps_rx_perr_intr_info4 = { .name = "MPS_RX_PERR_INT_CAUSE4", .cause_reg = A_MPS_RX_PERR_INT_CAUSE4, .enable_reg = A_MPS_RX_PERR_INT_ENABLE4, .fatal = 0xffffffff, .flags = IHF_FATAL_IFF_ENABLED, - .details = NULL, + .details = mpsrx_int_cause_4_details, .actions = NULL, }; + static const struct intr_details mpsrx_int_cause_5_details[] = { + { F_MPS2CRYP_RX_FIFO3_PERR | F_MPS2CRYP_RX_FIFO2_PERR | + F_MPS2CRYP_RX_FIFO1_PERR | F_MPS2CRYP_RX_FIFO0_PERR, + "MPS to Crypto RX interface FIFO parity error" }, + { F_VNI_MULTICAST_SRAM2_PERR | F_VNI_MULTICAST_SRAM1_PERR | + F_VNI_MULTICAST_SRAM0_PERR, + "VNI multicast SRAM parity error" }, + { F_MAC_MULTICAST_SRAM4_PERR | F_MAC_MULTICAST_SRAM3_PERR | + F_MAC_MULTICAST_SRAM2_PERR | F_MAC_MULTICAST_SRAM1_PERR | + F_MAC_MULTICAST_SRAM0_PERR, + "MAC multicast SRAM parity error" }, + { F_MEM_WRAP_IPSEC_HDR_UPD_FIFO3_PERR | F_MEM_WRAP_IPSEC_HDR_UPD_FIFO2_PERR | + F_MEM_WRAP_IPSEC_HDR_UPD_FIFO1_PERR | F_MEM_WRAP_IPSEC_HDR_UPD_FIFO0_PERR, + "IPsec header update storing FIFO parity error" }, + { F_MEM_WRAP_CR2MPS_RX_FIFO3_PERR | F_MEM_WRAP_CR2MPS_RX_FIFO2_PERR | + F_MEM_WRAP_CR2MPS_RX_FIFO1_PERR | F_MEM_WRAP_CR2MPS_RX_FIFO0_PERR, + "IPsec storing FIFO parity error" }, + { F_MEM_WRAP_NON_IPSEC_FIFO3_PERR | F_MEM_WRAP_NON_IPSEC_FIFO2_PERR | + F_MEM_WRAP_NON_IPSEC_FIFO1_PERR | F_MEM_WRAP_NON_IPSEC_FIFO0_PERR, + "Non-IPsec storing FIFO parity error" }, + { F_MEM_WRAP_TP_DB_REQ_FIFO3_PERR | F_MEM_WRAP_TP_DB_REQ_FIFO2_PERR | + F_MEM_WRAP_TP_DB_REQ_FIFO1_PERR | F_MEM_WRAP_TP_DB_REQ_FIFO0_PERR, + "TP DB request storing FIFO parity error" }, + { F_MEM_WRAP_CNTRL_FIFO3_PERR | F_MEM_WRAP_CNTRL_FIFO2_PERR | + F_MEM_WRAP_CNTRL_FIFO1_PERR | F_MEM_WRAP_CNTRL_FIFO0_PERR, + "Header flit storing FIFO parity error" }, + { 0 } + }; static const struct intr_info mps_rx_perr_intr_info5 = { .name = "MPS_RX_PERR_INT_CAUSE5", .cause_reg = A_MPS_RX_PERR_INT_CAUSE5, .enable_reg = A_MPS_RX_PERR_INT_ENABLE5, .fatal = 0xffffffff, .flags = IHF_FATAL_IFF_ENABLED, - .details = NULL, + .details = mpsrx_int_cause_5_details, .actions = NULL, }; + static const struct intr_details mpsrx_int_cause_6_details[] = { + { F_T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO3_PERR | F_T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO2_PERR | + F_T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO1_PERR | F_T7_MEM_WRAP_IPSEC_HDR_UPD_FIFO0_PERR, + "IPsec header update storing FIFO parity error" }, + { F_MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO3_PERR | F_MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO2_PERR | + F_MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO1_PERR | F_MEM_WRAP_CR2MPS_UPDTD_HDR_FIFO0_PERR, + "IPsec updated header only storing FIFO parity error" }, + { F_MEM_WRAP_CR2MPS_RX_FIFO3_PERR | F_MEM_WRAP_CR2MPS_RX_FIFO2_PERR | + F_MEM_WRAP_CR2MPS_RX_FIFO1_PERR | F_MEM_WRAP_CR2MPS_RX_FIFO0_PERR, + "IPsec storing FIFO parity error" }, + { F_MEM_WRAP_NON_IPSEC_FIFO3_PERR | F_MEM_WRAP_NON_IPSEC_FIFO2_PERR | + F_MEM_WRAP_NON_IPSEC_FIFO1_PERR | F_MEM_WRAP_NON_IPSEC_FIFO0_PERR, + "Non-IPsec storing FIFO parity error" }, + { F_MEM_WRAP_TP_DB_REQ_FIFO3_PERR | F_MEM_WRAP_TP_DB_REQ_FIFO2_PERR | + F_MEM_WRAP_TP_DB_REQ_FIFO1_PERR | F_MEM_WRAP_TP_DB_REQ_FIFO0_PERR, + "TP DB request storing FIFO parity error" }, + { F_MEM_WRAP_CNTRL_FIFO3_PERR | F_MEM_WRAP_CNTRL_FIFO2_PERR | + F_MEM_WRAP_CNTRL_FIFO1_PERR | F_MEM_WRAP_CNTRL_FIFO0_PERR, + "Header flit storing FIFO parity error" }, + { 0 } + }; static const struct intr_info mps_rx_perr_intr_info6 = { .name = "MPS_RX_PERR_INT_CAUSE6", .cause_reg = A_MPS_RX_PERR_INT_CAUSE6, .enable_reg = A_MPS_RX_PERR_INT_ENABLE6, .fatal = 0xffffffff, .flags = IHF_FATAL_IFF_ENABLED, - .details = NULL, + .details = mpsrx_int_cause_6_details, .actions = NULL, }; + static const struct intr_details t7_mpstx_int_cause_details[] = { + { F_T7_PORTERR, "Tx received a frame for TP destined to a disable port" }, + { F_T7_FRMERR, "Framing error in received Data from TP or Data to MAC" }, + { F_T7_SECNTERR, "SOP-EOP count error in received Data from TP or Data to MAC" }, + { F_T7_BUBBLE, "Valid is deasserted between SOP and EOP" }, + { F_TX_TF_FIFO_PERR, "Parity error of TX token fifo" }, + { F_TX_FIFO_PERR, "Parity error of TX MPS2MAC underrun fifo" }, + { 0x0003c000, "Parity error of fifo storing non-ipsec +1 flit ipsec pkt" }, + { 0x00003fc0, "Interface parity error on TP/Crypto to MPS TX" }, + { F_NCSI2MPS, "interface Parity Error on ncsi2mps_tx_ch3" }, + { F_NCSIFIFO, "Parity Error in mps_tx_arbiter input FIFO (from NCSI)" }, + { 0x0000000f, "Parity Error in mps_tx_arbiter input FIFO (from TP)" }, + { 0 } + }; static const struct intr_details mps_tx_intr_details[] = { { F_PORTERR, "MPS Tx destination port is disabled" }, { F_FRMERR, "MPS Tx framing error" }, @@ -5921,22 +7118,27 @@ static bool mps_intr_handler(struct adapter *adap, int arg, int flags) { V_TPFIFO(M_TPFIFO), "MPS Tx TP FIFO parity error" }, { 0 } }; - static const struct intr_info mps_tx_intr_info = { + struct intr_info mps_tx_intr_info = { .name = "MPS_TX_INT_CAUSE", .cause_reg = A_MPS_TX_INT_CAUSE, .enable_reg = A_MPS_TX_INT_ENABLE, .fatal = 0x1ffff, .flags = IHF_FATAL_IFF_ENABLED, - .details = mps_tx_intr_details, + .details = NULL, .actions = NULL, }; + static const struct intr_details mpstx_int_cause_2_details[] = { + { F_TX_FIFO_PERR, "ECC error of TX MPS2MAC underrun fifo" }, + { 0x0000000f, "ECC error of fifo storing non-ipsec +1 flit ipsec pkt" }, + { 0 } + }; static const struct intr_info mps_tx_intr_info2 = { .name = "MPS_TX_INT2_CAUSE", .cause_reg = A_MPS_TX_INT2_CAUSE, .enable_reg = A_MPS_TX_INT2_ENABLE, .fatal = 0xffffffff, .flags = IHF_FATAL_IFF_ENABLED, - .details = NULL, + .details = mpstx_int_cause_2_details, .actions = NULL, }; static const struct intr_info mps_tx_intr_info3 = { @@ -5972,22 +7174,51 @@ static bool mps_intr_handler(struct adapter *adap, int arg, int flags) .details = mps_trc_intr_details, .actions = NULL, }; + static const struct intr_details t7_mps_trc_intr_details[] = { + { F_T7_TRCPLERRENB, "TRC PL error" }, + { F_T7_MISCPERR, "TRC header register parity error" }, + { 0x0000ff00, "TRC packet FIFO parity error" }, + { 0x000000ff, "TRC filter memory parity error" }, + { 0 } + }; static const struct intr_info t7_mps_trc_intr_info = { .name = "MPS_TRC_INT_CAUSE", .cause_reg = A_T7_MPS_TRC_INT_CAUSE, .enable_reg = A_T7_MPS_TRC_INT_ENABLE, .fatal = 0xffffffff, .flags = IHF_FATAL_IFF_ENABLED, - .details = mps_trc_intr_details, + .details = t7_mps_trc_intr_details, .actions = NULL, }; + static const struct intr_details t7_trc_int_cause2_details[] = { + { 0x0001e000, "TRC Tx2Rx down-converter correctable error" }, + { 0x00001800, "TRC MPS2MAC down-converter correctable error" }, + { 0x00000600, "TRC MAC2MPS down-converter correctable error" }, + { 0x000001e0, "TRC Tx2Rx down-converter parity error" }, + { 0x00000018, "TRC MAC2MPS down-converter parity error" }, + { 0x00000006, "TRC MPS2MAC down-converter parity error" }, + { 0 } + }; static const struct intr_info t7_mps_trc_intr_info2 = { .name = "MPS_TRC_INT_CAUSE2", .cause_reg = A_MPS_TRC_INT_CAUSE2, .enable_reg = A_MPS_TRC_INT_ENABLE2, .fatal = 0xffffffff, .flags = IHF_FATAL_IFF_ENABLED, - .details = NULL, + .details = t7_trc_int_cause2_details, + .actions = NULL, + }; + static const struct intr_details mps_stat_intr_details[] = { + { F_PLREADSYNCERR, "MPS pl read sync error" }, + { 0 } + }; + static const struct intr_info mps_stat_intr_info = { + .name = "MPS_STAT_INT_CAUSE", + .cause_reg = A_MPS_STAT_INT_CAUSE, + .enable_reg = A_MPS_STAT_INT_ENABLE, + .fatal = 0xf, + .flags = IHF_FATAL_IFF_ENABLED, + .details = mps_stat_intr_details, .actions = NULL, }; static const struct intr_details mps_stat_sram_intr_details[] = { @@ -6030,6 +7261,9 @@ static bool mps_intr_handler(struct adapter *adap, int arg, int flags) .actions = NULL, }; static const struct intr_details mps_cls_intr_details[] = { + { F_T7_PLERRENB, "PL error"}, + { F_CIM2MPS_INTF_PAR, "cim2mps interface parity"}, + { F_TCAM_CRC_SRAM, "tcam crc sram parity error"}, { F_HASHSRAM, "MPS hash SRAM parity error" }, { F_MATCHTCAM, "MPS match TCAM parity error" }, { F_MATCHSRAM, "MPS match SRAM parity error" }, @@ -6058,9 +7292,14 @@ static bool mps_intr_handler(struct adapter *adap, int arg, int flags) .actions = NULL, }; bool fatal = false; + if (chip_id(adap) >= CHELSIO_T7) + mps_tx_intr_info.details = t7_mpstx_int_cause_details; + else + mps_tx_intr_info.details = mps_tx_intr_details; fatal |= t4_handle_intr(adap, &mps_rx_perr_intr_info, 0, flags); if (chip_id(adap) > CHELSIO_T6) { + fatal |= t4_handle_intr(adap, &mps_rx_func_intr_info, 0, flags); fatal |= t4_handle_intr(adap, &mps_rx_perr_intr_info2, 0, flags); fatal |= t4_handle_intr(adap, &mps_rx_perr_intr_info3, 0, flags); fatal |= t4_handle_intr(adap, &mps_rx_perr_intr_info4, 0, flags); @@ -6076,6 +7315,7 @@ static bool mps_intr_handler(struct adapter *adap, int arg, int flags) fatal |= t4_handle_intr(adap, &t7_mps_trc_intr_info2, 0, flags); } else fatal |= t4_handle_intr(adap, &mps_trc_intr_info, 0, flags); + fatal |= t4_handle_intr(adap, &mps_stat_intr_info, 0, flags); fatal |= t4_handle_intr(adap, &mps_stat_sram_intr_info, 0, flags); fatal |= t4_handle_intr(adap, &mps_stat_tx_intr_info, 0, flags); fatal |= t4_handle_intr(adap, &mps_stat_rx_intr_info, 0, flags); @@ -6087,7 +7327,6 @@ static bool mps_intr_handler(struct adapter *adap, int arg, int flags) t4_read_reg(adap, A_MPS_INT_CAUSE); /* flush */ return (fatal); - } /* @@ -6096,7 +7335,7 @@ static bool mps_intr_handler(struct adapter *adap, int arg, int flags) static bool mem_intr_handler(struct adapter *adap, int idx, int flags) { static const char name[4][5] = { "EDC0", "EDC1", "MC0", "MC1" }; - unsigned int count_reg, v; + unsigned int count_reg = 0, v; static const struct intr_details mem_intr_details[] = { { F_ECC_UE_INT_CAUSE, "Uncorrectable ECC data error(s)" }, { F_ECC_CE_INT_CAUSE, "Correctable ECC data error(s)" }, @@ -6104,10 +7343,10 @@ static bool mem_intr_handler(struct adapter *adap, int idx, int flags) { 0 } }; static const struct intr_details t7_mem_intr_details[] = { - { F_DDRPHY_INT_CAUSE, "DDRPHY" }, - { F_DDRCTL_INT_CAUSE, "DDRCTL" }, - { F_T7_ECC_CE_INT_CAUSE, "Correctable ECC data error(s)" }, + { F_DDRPHY_INT_CAUSE, "DDR PHY" }, + { F_DDRCTL_INT_CAUSE, "DDR Controller" }, { F_T7_ECC_UE_INT_CAUSE, "Uncorrectable ECC data error(s)" }, + { F_T7_ECC_CE_INT_CAUSE, "Correctable ECC data error(s)" }, { F_PERR_INT_CAUSE, "FIFO parity error" }, { 0 } }; @@ -6115,8 +7354,8 @@ static bool mem_intr_handler(struct adapter *adap, int idx, int flags) struct intr_info ii = { .name = &rname[0], .fatal = F_PERR_INT_CAUSE | F_ECC_UE_INT_CAUSE, + .flags = IHF_CLR_DELAYED, .details = mem_intr_details, - .flags = 0, .actions = NULL, }; bool fatal = false; @@ -6137,15 +7376,6 @@ static bool mem_intr_handler(struct adapter *adap, int idx, int flags) count_reg = EDC_T5_REG(A_EDC_H_ECC_STATUS, i); } fatal |= t4_handle_intr(adap, &ii, 0, flags); - if (chip_id(adap) > CHELSIO_T6) { - snprintf(rname, sizeof(rname), "EDC%u_PAR_CAUSE", i); - ii.cause_reg = EDC_T5_REG(A_EDC_H_PAR_CAUSE, i); - ii.enable_reg = EDC_T5_REG(A_EDC_H_PAR_ENABLE, i); - ii.fatal = 0xffffffff; - ii.details = NULL; - ii.flags = IHF_FATAL_IFF_ENABLED; - fatal |= t4_handle_intr(adap, &ii, 0, flags); - } break; case MEM_MC1: if (is_t4(adap) || is_t6(adap)) @@ -6167,52 +7397,30 @@ static bool mem_intr_handler(struct adapter *adap, int idx, int flags) ii.enable_reg = MC_T7_REG(A_T7_MC_P_INT_ENABLE, i); ii.fatal = F_PERR_INT_CAUSE | F_T7_ECC_UE_INT_CAUSE; ii.details = t7_mem_intr_details; - count_reg = MC_T7_REG(A_T7_MC_P_ECC_STATUS, i); } fatal |= t4_handle_intr(adap, &ii, 0, flags); - - snprintf(rname, sizeof(rname), "MC%u_PAR_CAUSE", i); - if (is_t4(adap)) { - ii.cause_reg = A_MC_PAR_CAUSE; - ii.enable_reg = A_MC_PAR_ENABLE; - } else if (chip_id(adap) < CHELSIO_T7) { - ii.cause_reg = MC_REG(A_MC_P_PAR_CAUSE, i); - ii.enable_reg = MC_REG(A_MC_P_PAR_ENABLE, i); - } else { - ii.cause_reg = MC_T7_REG(A_T7_MC_P_PAR_CAUSE, i); - ii.enable_reg = MC_T7_REG(A_T7_MC_P_PAR_ENABLE, i); - } - ii.fatal = 0xffffffff; - ii.details = NULL; - ii.flags = IHF_FATAL_IFF_ENABLED; - fatal |= t4_handle_intr(adap, &ii, 0, flags); - - if (chip_id(adap) > CHELSIO_T6) { - snprintf(rname, sizeof(rname), "MC%u_DDRCTL_INT_CAUSE", i); - ii.cause_reg = MC_T7_REG(A_MC_P_DDRCTL_INT_CAUSE, i); - ii.enable_reg = MC_T7_REG(A_MC_P_DDRCTL_INT_ENABLE, i); - fatal |= t4_handle_intr(adap, &ii, 0, flags); - } break; } - v = t4_read_reg(adap, count_reg); - if (v != 0) { - if (G_ECC_UECNT(v) != 0 && !(flags & IHF_NO_SHOW)) { - CH_ALERT(adap, - " %s: %u uncorrectable ECC data error(s)\n", - name[idx], G_ECC_UECNT(v)); - } - if (G_ECC_CECNT(v) != 0 && !(flags & IHF_NO_SHOW)) { - if (idx <= MEM_EDC1) - t4_edc_err_read(adap, idx); - CH_WARN_RATELIMIT(adap, - " %s: %u correctable ECC data error(s)\n", - name[idx], G_ECC_CECNT(v)); + if (count_reg != 0) { + v = t4_read_reg(adap, count_reg); + if (v != 0) { + if (G_ECC_UECNT(v) != 0 && !(flags & IHF_NO_SHOW)) { + CH_ALERT(adap, + " %s: %u uncorrectable ECC data error(s)\n", + name[idx], G_ECC_UECNT(v)); + } + if (G_ECC_CECNT(v) != 0 && !(flags & IHF_NO_SHOW)) { + if (idx <= MEM_EDC1) + t4_edc_err_read(adap, idx); + CH_WARN_RATELIMIT(adap, + " %s: %u correctable ECC data error(s)\n", + name[idx], G_ECC_CECNT(v)); + } + t4_write_reg(adap, count_reg, 0xffffffff); } - t4_write_reg(adap, count_reg, 0xffffffff); } - + clear_int_cause_reg(adap, &ii, flags); return (fatal); } @@ -6231,14 +7439,13 @@ static bool ma_wrap_status(struct adapter *adap, int arg, int flags) return (false); } - /* * MA interrupt handler. */ static bool ma_intr_handler(struct adapter *adap, int arg, int flags) { static const struct intr_action ma_intr_actions[] = { - { F_MEM_WRAP_INT_CAUSE, 0, ma_wrap_status }, + { F_MEM_WRAP_INT_CAUSE, -1, ma_wrap_status }, { 0 }, }; static const struct intr_info ma_intr_info = { @@ -6284,10 +7491,29 @@ static bool ma_intr_handler(struct adapter *adap, int arg, int flags) */ static bool smb_intr_handler(struct adapter *adap, int arg, int flags) { - static const struct intr_details smb_int_cause_fields[] = { - { F_MSTTXFIFOPARINT, "SMB master Tx FIFO parity error" }, - { F_MSTRXFIFOPARINT, "SMB master Rx FIFO parity error" }, - { F_SLVFIFOPARINT, "SMB slave FIFO parity error" }, + static const struct intr_details smb_int_cause_details[] = { + { F_MSTTXFIFOPARINT, "Master has Parity Error in Tx Fifo" }, + { F_MSTRXFIFOPARINT, "Master has Parity Error in Rx Fifo" }, + { F_SLVFIFOPARINT, "Slave has Parity Error in Fifo" }, + { F_SLVUNEXPBUSSTOPINT, "Slave get Unexpected BusStop" }, + { F_SLVUNEXPBUSSTARTINT, "Slave get Unexpected BusStart" }, + { F_SLVCOMMANDCODEINVINT, "Slave get Invalid Command Code" }, + { F_SLVBYTECNTERRINT, "Slave get Erroneous ByteCount value" }, + { F_SLVUNEXPACKMSTINT, "Slave get Unexpected Ack from Master" }, + { F_SLVUNEXPNACKMSTINT, "Slave get Unexpected Nack from Master" }, + { F_SLVNOBUSSTOPINT, "Slave did not get Bus Stop" }, + { F_SLVNOREPSTARTINT, "Slave has no Repeated Start" }, + { F_SLVRXADDRINT, "Slave has Address Error" }, + { F_SLVRXPECERRINT, "Slave has Pec Error" }, + { F_SLVPREPTOARPINT, "PL has invalid request" }, + { F_SLVTIMEOUTINT, "Slave has timed out" }, + { F_SLVERRINT, "Slave detected error during the current transfer" }, + { F_SLVDONEINT, "Slave has completed the current transaction" }, + { F_SLVRXRDYINT, "Slave has received bytes to be processed by uP" }, + { F_MSTTIMEOUTINT, "Master has timed out" }, + { F_MSTNACKINT, "Master has detected a NAck on the transfer" }, + { F_MSTLOSTARBINT, "Master has lost arbitration all the timeline" }, + { F_MSTDONEINT, "Master has completed the current transaction" }, { 0 } }; static const struct intr_info smb_int_cause = { @@ -6296,9 +7522,10 @@ static bool smb_intr_handler(struct adapter *adap, int arg, int flags) .enable_reg = A_SMB_INT_ENABLE, .fatal = F_SLVFIFOPARINT | F_MSTRXFIFOPARINT | F_MSTTXFIFOPARINT, .flags = 0, - .details = smb_int_cause_fields, + .details = smb_int_cause_details, .actions = NULL, }; + return (t4_handle_intr(adap, &smb_int_cause, 0, flags)); } @@ -6308,6 +7535,7 @@ static bool smb_intr_handler(struct adapter *adap, int arg, int flags) static bool ncsi_intr_handler(struct adapter *adap, int arg, int flags) { static const struct intr_details ncsi_int_cause_fields[] = { + { F_CIM2NC_PERR, " CIM to NC parity error" }, { F_CIM_DM_PRTY_ERR, "NC-SI CIM parity error" }, { F_MPS_DM_PRTY_ERR, "NC-SI MPS parity error" }, { F_TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error" }, @@ -6324,13 +7552,31 @@ static bool ncsi_intr_handler(struct adapter *adap, int arg, int flags) .details = ncsi_int_cause_fields, .actions = NULL, }; + static const struct intr_details ncsi_xgmac0_int_cause_details[] = { + { F_XAUIPCSDECERR, "RGMII PCS DEC Error" }, + { F_RGMIIRXFIFOOVERFLOW, "RGMII receive FIFO over flow" }, + { F_RGMIIRXFIFOUNDERFLOW, "RGMII receive FIFO under flow" }, + { F_RXPKTSIZEERROR, "Receive over size packet" }, + { F_WOLPATDETECTED, "WOL pattern detected" }, + { 0x000e0000, "Tx FIFO parity error" }, + { 0x0001c000, "Rx FIFO parity error" }, + { F_TXFIFO_UNDERRUN, "Tx FIFO underrun" }, + { F_RXFIFO_OVERFLOW, "Rx FIFO overflow" }, + { 0x00000f00, "XAUI SERDES BIST error" }, + { 0x000000f0, "XAUI SERDES receive low signal change" }, + { F_XAUIPCSCTCERR, "XAUI PCS CTC FIFO error" }, + { F_XAUIPCSALIGNCHANGE, "XAUI PCS alignment change" }, + { F_RGMIILINKSTSCHANGE, "RGMII link status change" }, + { F_XGM_INT, "XGM Core embedded interrupt (2nd level)" }, + { 0 } + }; static const struct intr_info ncsi_xgmac0_int_cause = { .name = "NCSI_XGMAC0_INT_CAUSE", .cause_reg = A_NCSI_XGMAC0_INT_CAUSE, .enable_reg = A_NCSI_XGMAC0_INT_ENABLE, .fatal = 0, .flags = 0, - .details = NULL, + .details = ncsi_xgmac0_int_cause_details, .actions = NULL, }; bool fatal = false; @@ -6346,32 +7592,71 @@ static bool ncsi_intr_handler(struct adapter *adap, int arg, int flags) */ static bool mac_intr_handler(struct adapter *adap, int port, int flags) { + static const struct intr_details mac_int_cause_cmn_details[] = { + { 0x3fffc0, "HSS PLL lock error " }, + { F_FLOCK_ASSERTED, "frequency lock coming out of DPLL sub-block is asserted" }, + { F_FLOCK_LOST, "frequency lock coming out of DPLL sub-blocki is lost." }, + { F_PHASE_LOCK_ASSERTED, "PHASE LOCK from DPLL sub-block is asserted" }, + { F_PHASE_LOCK_LOST, "PHASE LOCK from DPLL sub-block is lost." }, + { F_LOCK_ASSERTED, "Lock from frac_n PLL inside t7_clk module is asserted" }, + { F_LOCK_LOST, "Lock from frac_n PLL inside t7_clk module is lost " }, + { 0 } + }; static const struct intr_info mac_int_cause_cmn = { .name = "MAC_INT_CAUSE_CMN", .cause_reg = A_MAC_INT_CAUSE_CMN, .enable_reg = A_MAC_INT_EN_CMN, .fatal = 0, .flags = 0, - .details = NULL, + .details = mac_int_cause_cmn_details, .actions = NULL, }; + static const struct intr_details mac_perr_int_cause_mtip_details[] = { + { F_PERR_MAC0_TX, "MTIP MAC TX memory for MAC 0 (the 200G MAC for port 0)" }, + { F_PERR_MAC1_TX, "MTIP MAC TX memory for MAC 1 (the 200G MAC for port 1)" }, + { F_PERR_MAC2_TX, "MTIP MAC TX memory for MAC 2 (the 10-100G MAC for port 0)" }, + { F_PERR_MAC3_TX, "MTIP MAC TX memory for MAC 3 (the 10-100G MAC for port 1)" }, + { F_PERR_MAC4_TX, "MTIP MAC TX memory for MAC 4 (the 10-100G MAC for port 2)" }, + { F_PERR_MAC5_TX, "MTIP MAC TX memory for MAC 5 (the 10-100G MAC for port 3)" }, + { F_PERR_MAC0_RX, "MTIP MAC RX memory for MAC 0 (the 200G MAC for port 0)" }, + { F_PERR_MAC1_RX, "MTIP MAC RX memory for MAC 1 (the 200G MAC for port 1)" }, + { F_PERR_MAC2_RX, "MTIP MAC RX memory for MAC 2 (the 10-100G MAC for port 0)" }, + { F_PERR_MAC3_RX, "MTIP MAC RX memory for MAC 3 (the 10-100G MAC for port 1)" }, + { F_PERR_MAC4_RX, "MTIP MAC RX memory for MAC 4 (the 10-100G MAC for port 2)" }, + { F_PERR_MAC5_RX, "MTIP MAC RX memory for MAC 5 (the 10-100G MAC for port 3)" }, + { F_PERR_MAC_STAT_RX, "MTIP MAC RX statistics memory (1 for all 4 10-100G MACs)" }, + { F_PERR_MAC_STAT_TX, "MTIP MAC TX statistics memory (1 for all 4 10-100G MACs)" }, + { F_PERR_MAC_STAT_CAP, "MTIP MAC stat capture memory (1 for all 4 100G MACs)" }, + { 0 } + }; static const struct intr_info mac_perr_cause_mtip = { .name = "MAC_PERR_INT_CAUSE_MTIP", .cause_reg = A_MAC_PERR_INT_CAUSE_MTIP, .enable_reg = A_MAC_PERR_INT_EN_MTIP, .fatal = 0xffffffff, .flags = IHF_FATAL_IFF_ENABLED | IHF_IGNORE_IF_DISABLED, - .details = NULL, + .details = mac_perr_int_cause_mtip_details, .actions = NULL, }; - static const struct intr_info mac_cerr_cause_mtip = { - .name = "MAC_CERR_INT_CAUSE_MTIP", - .cause_reg = A_MAC_CERR_INT_CAUSE_MTIP, - .enable_reg = A_MAC_CERR_INT_EN_MTIP, - .fatal = 0, - .flags = 0, - .details = NULL, - .actions = NULL, + static const struct intr_details ios_intr_cause_quad0_details[] = { + { F_Q0_MAILBOX_INT_ASSERT, "Etopus Quad0 Mailbox interrupt cause" }, + { 0x00f00000, "Etopus Quad0 training failure" }, + { 0x000f0000, "Etopus Quad0 training complete" }, + { 0x0000f000, "Etopus Quad0 AN TX interrupt" }, + { 0x00000f00, "Etopus Quad0 signal detect assertion" }, + { 0x000000f0, "Etopus Quad0 CDR LOL assertion" }, + { 0x0000000f, "Etopus Quad0 LOS signal assertion" }, + { 0 } + }; + static const struct intr_details ios_intr_cause_quad1_details[] = { + { F_Q1_MAILBOX_INT_ASSERT, "Etopus Quad1 Mailbox interrupt cause" }, + { 0x00f00000, "Etopus Quad1 training failure" }, + { 0x000f0000, "Etopus Quad1 training complete" }, + { 0x0000f000, "Etopus Quad1 AN TX interrupt" }, + { 0x00000f00, "Etopus Quad1 signal detect assertion" }, + { 0x000000f0, "Etopus Quad1 CDR LOL assertion" }, + { 0x0000000f, "Etopus Quad1 LOS signal assertion" }, + { 0 } }; static const struct intr_info mac_ios_int_cause_quad0 = { .name = "MAC_IOS_INTR_CAUSE_QUAD0", @@ -6379,7 +7664,7 @@ static bool mac_intr_handler(struct adapter *adap, int port, int flags) .enable_reg = A_MAC_IOS_INTR_EN_QUAD0, .fatal = 0, .flags = 0, - .details = NULL, + .details = ios_intr_cause_quad0_details, .actions = NULL, }; static const struct intr_info mac_ios_int_cause_quad1 = { @@ -6388,7 +7673,7 @@ static bool mac_intr_handler(struct adapter *adap, int port, int flags) .enable_reg = A_MAC_IOS_INTR_EN_QUAD1, .fatal = 0, .flags = 0, - .details = NULL, + .details = ios_intr_cause_quad1_details, .actions = NULL, }; static const struct intr_details mac_intr_details[] = { @@ -6396,6 +7681,33 @@ static bool mac_intr_handler(struct adapter *adap, int port, int flags) { F_RXFIFO_PRTY_ERR, "MAC Rx FIFO parity error" }, { 0 } }; + static const struct intr_details t7_mac_int_cause_details[] = { + { F_MAC2MPS_PERR_CAUSE, "MPS2MAC Data parity error per port" }, + { F_MAC_PPS_INT_CAUSE, "One second interrupt based on PTP timer" }, + { F_MAC_TX_TS_AVAIL_INT_CAUSE, + "Time stamp is available for the last IEEE 1588 event frame" }, + { F_MAC_PATDETWAKE_INT_CAUSE, "Wake up pattern match packet received" }, + { F_MAC_MAGIC_WAKE_INT_CAUSE, "Magic packet received" }, + { F_MAC_SIGDETCHG_INT_CAUSE, "Signal Detect Change" }, + { F_MAC_PCS_LINK_GOOD_CAUSE, "PCS link good (xaui pcsr or 1g)" }, + { F_MAC_PCS_LINK_FAIL_CAUSE, "PCS Failure (xaui pcsr or 1g)" }, + { F_RXFIFOOVERFLOW, "RX Fifo Over flow error" }, + { F_MAC_REM_FAULT_INT_CAUSE, "Remote fault received by XGMAC" }, + { F_MAC_LOC_FAULT_INT_CAUSE, "Local fault received by XGMAC" }, + { F_MAC_LINK_DOWN_INT_CAUSE, "Link is down" }, + { F_MAC_LINK_UP_INT_CAUSE, "Link is up" }, + { F_MAC_AN_DONE_INT_CAUSE, "Autonegotiation complete" }, + { F_MAC_AN_PGRD_INT_CAUSE, "An page received" }, + { F_MAC_TXFIFO_ERR_INT_CAUSE, "Tx FIFO parity error" }, + { F_MAC_RXFIFO_ERR_INT_CAUSE, "Rx FIFO parity error" }, + { 0 } + }; + static const struct intr_details mac_perr_int_cause_details[] = { + { F_T6_PERR_PKT_RAM, "WoL packet data memory" }, + { F_T6_PERR_MASK_RAM, "WoL mask memory" }, + { F_T6_PERR_CRC_RAM, "WoL CRC memory" }, + { 0 } + }; char name[32]; struct intr_info ii; bool fatal = false; @@ -6428,7 +7740,7 @@ static bool mac_intr_handler(struct adapter *adap, int port, int flags) ii.enable_reg = T7_PORT_REG(port, A_T7_MAC_PORT_INT_EN); ii.fatal = 0xffffffff; ii.flags = IHF_FATAL_IFF_ENABLED; - ii.details = NULL; + ii.details = t7_mac_int_cause_details; ii.actions = NULL; } fatal |= t4_handle_intr(adap, &ii, 0, flags); @@ -6443,7 +7755,7 @@ static bool mac_intr_handler(struct adapter *adap, int port, int flags) ii.enable_reg = T7_PORT_REG(port, A_T7_MAC_PORT_PERR_INT_EN); ii.fatal = 0xffffffff; ii.flags = IHF_FATAL_IFF_ENABLED; - ii.details = NULL; + ii.details = mac_perr_int_cause_details; ii.actions = NULL; } else { ii.name = &name[0]; @@ -6484,7 +7796,6 @@ static bool mac_intr_handler(struct adapter *adap, int port, int flags) MPASS(chip_id(adap) >= CHELSIO_T7); fatal |= t4_handle_intr(adap, &mac_int_cause_cmn, 0, flags); fatal |= t4_handle_intr(adap, &mac_perr_cause_mtip, 0, flags); - fatal |= t4_handle_intr(adap, &mac_cerr_cause_mtip, 0, flags); fatal |= t4_handle_intr(adap, &mac_ios_int_cause_quad0, 0, flags); fatal |= t4_handle_intr(adap, &mac_ios_int_cause_quad1, 0, flags); @@ -6506,28 +7817,40 @@ static bool pl_timeout_status(struct adapter *adap, int arg, int flags) static bool plpl_intr_handler(struct adapter *adap, int arg, int flags) { static const struct intr_details plpl_int_cause_fields[] = { + { F_FATALPERR, "Fatal parity error" }, + { F_PERRVFID, "VFID_MAP parity error" }, + { 0 } + }; + static const struct intr_details t5_plpl_int_cause_fields[] = { { F_PL_BUSPERR, "Bus parity error" }, { F_FATALPERR, "Fatal parity error" }, { F_INVALIDACCESS, "Global reserved memory access" }, { F_TIMEOUT, "Bus timeout" }, { F_PLERR, "Module reserved access" }, - { F_PERRVFID, "VFID_MAP parity error" }, { 0 } }; static const struct intr_action plpl_int_cause_actions[] = { { F_TIMEOUT, -1, pl_timeout_status }, { 0 }, }; - static const struct intr_info plpl_int_cause = { + struct intr_info plpl_int_cause = { .name = "PL_PL_INT_CAUSE", .cause_reg = A_PL_PL_INT_CAUSE, .enable_reg = A_PL_PL_INT_ENABLE, - .fatal = F_FATALPERR | F_PERRVFID, - .flags = IHF_FATAL_IFF_ENABLED | IHF_IGNORE_IF_DISABLED, - .details = plpl_int_cause_fields, - .actions = plpl_int_cause_actions, + .fatal = F_FATALPERR, + .flags = IHF_FATAL_IFF_ENABLED, + .details = NULL, + .actions = NULL, }; + if (is_t4(adap)) { + plpl_int_cause.fatal |= F_PERRVFID; + plpl_int_cause.details = plpl_int_cause_fields; + } else { + plpl_int_cause.fatal |= F_INVALIDACCESS; + plpl_int_cause.details = t5_plpl_int_cause_fields; + plpl_int_cause.actions = plpl_int_cause_actions; + } return (t4_handle_intr(adap, &plpl_int_cause, 0, flags)); } @@ -6587,7 +7910,7 @@ static bool hma_intr_handler(struct adapter *adap, int idx, int flags) { F_RTF_INT_CAUSE, "Region translation fault" }, { F_PCIEMST_INT_CAUSE, "PCIe master access error" }, { F_MAMST_INT_CAUSE, "MA master access error" }, - { 1, "FIFO parity error" }, + { F_PERR_INT_CAUSE, "FIFO parity error" }, { 0 } }; static const struct intr_info hma_int_cause = { @@ -6682,15 +8005,6 @@ static bool gcache_intr_handler(struct adapter *adap, int idx, int flags) { F_ILLADDRACCESS0_INT_CAUSE, "GC0 illegal address access" }, { 0 } }; - static const struct intr_info gcache_perr_cause = { - .name = "GCACHE_PAR_CAUSE", - .cause_reg = A_GCACHE_PAR_CAUSE, - .enable_reg = A_GCACHE_PAR_ENABLE, - .fatal = 0xffffffff, - .flags = IHF_FATAL_IFF_ENABLED, - .details = NULL, - .actions = NULL, - }; static const struct intr_info gcache_int_cause = { .name = "GCACHE_INT_CAUSE", .cause_reg = A_GCACHE_INT_CAUSE, @@ -6700,12 +8014,7 @@ static bool gcache_intr_handler(struct adapter *adap, int idx, int flags) .details = gcache_int_cause_fields, .actions = NULL, }; - bool fatal = false; - - fatal |= t4_handle_intr(adap, &gcache_int_cause, 0, flags); - fatal |= t4_handle_intr(adap, &gcache_perr_cause, 0, flags); - - return (fatal); + return (t4_handle_intr(adap, &gcache_int_cause, 0, flags)); } /* @@ -6713,67 +8022,218 @@ static bool gcache_intr_handler(struct adapter *adap, int idx, int flags) */ static bool arm_intr_handler(struct adapter *adap, int idx, int flags) { + static const struct intr_details arm_perr_int_cause0_details[] = { + { F_INIC_WRDATA_FIFO_PERR, "INT CAUSE for INIC Write Data Fifo Parity Error" }, + { F_INIC_RDATA_FIFO_PERR, "INT CAUSE for INIC Read Data Fifo Parity Error" }, + { F_MSI_MEM_PERR, "INT CAUSE for MSI Memory Parity Error" }, + { 0x18000000, "INT CAUSE for ARM Doorbell SRAM Parity Error" }, + { F_EMMC_FIFOPARINT, "INT CAUSE for EMMC Fifo Parity Interrupt" }, + { F_ICB_RAM_PERR, "INT CAUSE for ICB SRAM Parity Error" }, + { F_MESS2AXI4_WRFIFO_PERR, "INT CAUSE for Message2AXI4 Write FIFO Parity Error" }, + { F_RC_WFIFO_OUTPERR, "INT CAUSE for AXI2RC Write FIFO Parity Error" }, + { 0x00600000, "INT CAUSE for AXI2RC SRAM Parity Error" }, + { F_MSI_FIFO_PAR_ERR, "INT CAUSE for APB2MSI FIFO Parity Error" }, + { F_INIC2MA_INTFPERR, "INT CAUSE for INIC to MA Interface Parity Error" }, + { F_RDATAFIFO0_PERR, "INT CAUSE for AXI2MA M0 Read Data Fifo Parity Error" }, + { F_RDATAFIFO1_PERR, "INT CAUSE for AXI2MA M1 Read Data Fifo Parity Error" }, + { F_WRDATAFIFO0_PERR, "INT CAUSE for AXI2MA M0 Write Data Fifo Parity Error" }, + { F_WRDATAFIFO1_PERR, "INT CAUSE for AXI2MA M1 Write Data Fifo Parity Error" }, + { F_WR512DATAFIFO0_PERR, + "INT CAUSE for AXI2MA M0 Write Data 512b Fifo Parity Error" }, + { F_WR512DATAFIFO1_PERR, + "INT CAUSE for AXI2MA M1 Write Data 512b Fifo Parity Error" }, + { F_ROBUFF_PARERR3, "INT CAUSE for Reorder Buffer Parity Error" }, + { F_ROBUFF_PARERR2, "INT CAUSE for Reorder Buffer Parity Error" }, + { F_ROBUFF_PARERR1, "INT CAUSE for Reorder Buffer Parity Error" }, + { F_ROBUFF_PARERR0, "INT CAUSE for Reorder Buffer Parity Error" }, + { F_MA2AXI_REQDATAPARERR, "INT CAUSE for MA2AXI Request Data Parity Error" }, + { F_MA2AXI_REQCTLPARERR, "INT CAUSE for MA2AXI Request Control Parity Error" }, + { F_MA_RSPPERR, "INT CAUSE for MA Response Parity Error" }, + { F_PCIE2MA_REQCTLPARERR, "INT CAUSE for PCIe to MA Control Parity Error" }, + { F_PCIE2MA_REQDATAPARERR, "INT CAUSE for PCIe to MA Data Parity Error" }, + { F_INIC2MA_REQCTLPARERR, "INT CAUSE for INIC to MA Control Parity Error" }, + { F_INIC2MA_REQDATAPARERR, "INT CAUSE for INIC to MA Data Parity Error" }, + { F_MA_RSPUE, "INT CAUSE for MA Response Uncorrectable Error" }, + { F_APB2PL_RSPDATAPERR, "INT CAUSE for APB2PL Response Data Parity Error" }, + { 0 } + }; static const struct intr_info arm_perr_cause0 = { .name = "ARM_PERR_INT_CAUSE0", .cause_reg = A_ARM_PERR_INT_CAUSE0, .enable_reg = A_ARM_PERR_INT_ENB0, .fatal = 0xffffffff, .flags = IHF_IGNORE_IF_DISABLED | IHF_FATAL_IFF_ENABLED, - .details = NULL, + .details = arm_perr_int_cause0_details, .actions = NULL, }; + static const struct intr_details arm_perr_int_cause1_details[] = { + { F_ARWFIFO0_PERR, "AXI2MA M0 Read-Write FIFO Parity Error" }, + { F_ARWFIFO1_PERR, "AXI2MA M1 Read-Write FIFO Parity Error" }, + { F_ARWIDFIFO0_PERR, "AXI2MA M0 Read-Write ID FIFO Parity Error" }, + { F_ARWIDFIFO1_PERR, "AXI2MA M1 Read-Write ID FIFO Parity Error" }, + { F_ARIDFIFO0_PERR, "AXI2MA M0 Read FIFO Parity Error" }, + { F_ARIDFIFO1_PERR, "AXI2MA M1 Read FIFO Parity Error" }, + { F_RRSPADDR_FIFO0_PERR, "AXI2MA M0 Read Response Address FIFO Parity Error" }, + { F_RRSPADDR_FIFO1_PERR, "AXI2MA M1 Read Response Address FIFO Parity Error" }, + { F_WRSTRB_FIFO0_PERR, "AXI2MA M0 Write Strobe FIFO Parity Error" }, + { F_WRSTRB_FIFO1_PERR, "AXI2MA M1 Write Strobe FIFO Parity Error" }, + { F_MA2AXI_RSPDATAPARERR, "MA2AXI Response FIFO Parity Error" }, + { F_MA2AXI_DATA_PAR_ERR, "MA2AXI Write Data FIFO Parity Error" }, + { F_MA2AXI_WR_ORD_FIFO_PARERR, "MA2AXI Ordered Write Data FIFO Parity Error" }, + { F_NVME_DB_EMU_TRACKER_FIFO_PERR, "NVMe DB Emulation Tracker FIFO Parity Error" }, + { F_NVME_DB_EMU_QUEUE_AW_ADDR_FIFO_PERR, + "NVMe DB Emulation Queue AW Addr Parity Error" }, + { F_NVME_DB_EMU_INTERRUPT_OFFSET_FIFO_PERR, + "NVMe DB Emulation Interrupt Offset FIFO Parity Error" }, + { F_NVME_DB_EMU_ID_FIFO0_PERR, "NVMe DB Emulation ID FIFO0 Parity Error" }, + { F_NVME_DB_EMU_ID_FIFO1_PERR, "NVMe DB Emulation ID FIFO1 Parity Error" }, + { F_RC_ARWFIFO_PERR, "AXI2RC Read-Write FIFO Parity Error" }, + { F_RC_ARIDBURSTADDRFIFO_PERR, + "AXI2RC Read ID, Burst and Address FIFO Parity Error" }, + { F_RC_CFG_FIFO_PERR, "AXI2RC Config FIFO Parity Error" }, + { F_RC_RSPFIFO_PERR, "AXI2RC Response Parity Error" }, + { F_INIC_ARIDFIFO_PERR, "CCI2INIC Read ID FIFO Parity Error" }, + { F_INIC_ARWFIFO_PERR, "CCI2INIC Read-Write FIFO ontrol Parity Error" }, + { F_AXI2MA_128_RD_ADDR_SIZE_FIFO_PERR, + "AXI2MA(CCI2INIC) Read Address Size FIFO Parity Error" }, + { F_AXI2RC_128_RD_ADDR_SIZE_FIFO_PERR, + "AXI2RC Read Address Size FIFO Parity Error" }, + { F_ARM_MA_512B_RD_ADDR_SIZE_FIFO0_PERR, + "ARM_MA_512b Read Address Size FIFO0 Parity Error" }, + { F_ARM_MA_512B_RD_ADDR_SIZE_FIFO1_PERR, + "ARM_MA_512b Read Address Size FIFO1 Parity Error" }, + { F_ARM_MA_512B_ARB_FIFO_PERR, "ARM_MA_512b Arbiter FIFO Parity Error" }, + { F_PCIE_INIC_MA_ARB_FIFO_PERR, "PCIe-INIC Arbiter FIFO Parity Error" }, + { F_PCIE_INIC_ARB_RSPPERR, "PCIe-INIC Arbiter Response Parity Error" }, + { F_ITE_CACHE_PERR, "GIC500 ITE Cache SRAM Parity Error" }, + { 0 } + }; static const struct intr_info arm_perr_cause1 = { .name = "ARM_PERR_INT_CAUSE1", .cause_reg = A_ARM_PERR_INT_CAUSE1, .enable_reg = A_ARM_PERR_INT_ENB1, .fatal = 0xffffffff, .flags = IHF_IGNORE_IF_DISABLED | IHF_FATAL_IFF_ENABLED, - .details = NULL, + .details = arm_perr_int_cause1_details, .actions = NULL, }; + static const struct intr_details arm_perr_int_cause2_details[] = { + { F_INIC_WSTRB_FIFO_PERR, "AXI2MA_128 INIC Write Strobe FIFO Parity Error" }, + { F_INIC_BID_FIFO_PERR, "AXI2MA_128 INIC bID FIFO Parity Error" }, + { F_CC_SRAM_PKA_PERR, "CryptoCell ram_pka_wrapper FIFO Parity Error" }, + { F_CC_SRAM_SEC_PERR, "CryptoCell sec_sram_wrapper FIFO Parity Error" }, + { F_MESS2AXI4_PARERR, "Message2AXI4 IBQ I/P Interface Parity Error" }, + { F_CCI2INIC_INTF_PARERR, "CCI2INIC Response Interface Parity Error" }, + { 0 } + }; static const struct intr_info arm_perr_cause2 = { .name = "ARM_PERR_INT_CAUSE2", .cause_reg = A_ARM_PERR_INT_CAUSE2, .enable_reg = A_ARM_PERR_INT_ENB2, .fatal = 0xffffffff, .flags = IHF_IGNORE_IF_DISABLED | IHF_FATAL_IFF_ENABLED, - .details = NULL, + .details = arm_perr_int_cause2_details, .actions = NULL, }; + static const struct intr_details arm_cerr_int_cause0_details[] = { + { F_WRDATA_FIFO0_CERR, "AXI2MA M0 Write Data FIFO Correctable Error" }, + { F_WRDATA_FIFO1_CERR, "AXI2MA M1 Write Data FIFO Correctable Error" }, + { F_WR512DATAFIFO0_CERR, "AXI2MA M0 Write Data 512b FIFO Correctable Error" }, + { F_WR512DATAFIFO1_CERR, "AXI2MA M1 Write Data 512b FIFO Correctable Error" }, + { F_RDATAFIFO0_CERR, "AXI2MA M0 Read Data FIFO Correctable Error" }, + { F_RDATAFIFO1_CERR, "AXI2MA M1 Read Data FIFO Correctable Error" }, + { F_ROBUFF_CORERR0, "Reorder Buffer Correctable Error" }, + { F_ROBUFF_CORERR1, "Reorder Buffer Correctable Error" }, + { F_ROBUFF_CORERR2, "Reorder Buffer Correctable Error" }, + { F_ROBUFF_CORERR3, "Reorder Buffer Correctable Error" }, + { F_MA2AXI_RSPDATACORERR, "MA2AXI Response FIFO Correctable Error" }, + { 0x00180000, "AXI2RC SRAM Correctable Error" }, + { F_RC_WFIFO_OUTCERR, "AXI2RC Write FIFO Correctable Error" }, + { F_RC_RSPFIFO_CERR, "AXI2RC Response Correctable Error" }, + { F_MSI_MEM_CERR, "MSI Memory FIFO Correctable Error" }, + { F_INIC_WRDATA_FIFO_CERR, "INIC Write Data FIFO Correctable Error" }, + { F_INIC_RDATAFIFO_CERR, "INIC Read Data FIFO Correctable Error" }, + { 0x00003000, "ARM Doorbell SRAM Correctable Error" }, + { F_ICB_RAM_CERR, "ICB SRAM Parity Error" }, + { F_CC_SRAM_PKA_CERR, "CryptoCell ram_pka_wrapper FIFO Correctable Error" }, + { F_CC_SRAM_SEC_CERR, "CryptoCell sec_sram_wrapper FIFO Correctable Error" }, + { 0 } + }; static const struct intr_info arm_cerr_cause0 = { - .name = "ARM_CERR_INT_CAUSE", + .name = "ARM_CERR_INT_CAUSE0", .cause_reg = A_ARM_CERR_INT_CAUSE0, .enable_reg = A_ARM_CERR_INT_ENB0, .fatal = 0, .flags = IHF_IGNORE_IF_DISABLED | IHF_FATAL_IFF_ENABLED, - .details = NULL, + .details = arm_cerr_int_cause0_details, .actions = NULL, }; + static const struct intr_details arm_err_int_cause0_details[] = { + { F_STRB0_ERROR, "Strobe Error from AXI2MA 0" }, + { F_STRB1_ERROR, "Strobe Error from AXI2MA 1" }, + { F_PCIE_INIC_MA_ARB_INV_RSP_TAG, "Invalid Response Tag for PCIE-INIc MA ARB" }, + { F_ERROR0_NOCMD_DATA, "AXI2MA 0 No Command Data Error" }, + { F_ERROR1_NOCMD_DATA, "AXI2MA 1 No Command Data Error" }, + { F_INIC_STRB_ERROR, "AXI2MA_128b INIC Strobe Error" }, + { 0 } + }; static const struct intr_info arm_err_cause0 = { - .name = "ARM_ERR_INT_CAUSE", + .name = "ARM_ERR_INT_CAUSE0", .cause_reg = A_ARM_ERR_INT_CAUSE0, .enable_reg = A_ARM_ERR_INT_ENB0, .fatal = 0, .flags = IHF_IGNORE_IF_DISABLED | IHF_FATAL_IFF_ENABLED, - .details = NULL, + .details = arm_err_int_cause0_details, .actions = NULL, }; + + static const struct intr_details arm_peripheral_int_cause_details[] = { + { F_TIMER_INT, "TIMER_INT" }, + { F_NVME_INT, "NVME_INT" }, + { F_EMMC_WAKEUP_INT, "EMMC_WAKEUP_INT" }, + { F_EMMC_INT, "EMMC_INT" }, + { F_USB_MC_INT, "USB_MC_INT" }, + { F_USB_DMA_INT, "USB_DMA_INT" }, + { 0 } + }; static const struct intr_info arm_periph_cause = { .name = "ARM_PERIPHERAL_INT_CAUSE", .cause_reg = A_ARM_PERIPHERAL_INT_CAUSE, .enable_reg = A_ARM_PERIPHERAL_INT_ENB, .fatal = 0, .flags = IHF_IGNORE_IF_DISABLED | IHF_FATAL_IFF_ENABLED, - .details = NULL, + .details = arm_peripheral_int_cause_details, .actions = NULL, }; + static const struct intr_details arm_arm_uart_int_cause_details[] = { + { F_RX_FIFO_NOT_EMPTY, "intcause for uart rx fifo" }, + { F_TX_FIFO_EMPTY, "intcause for uart tx fifo" }, + { 0 } + }; + static const struct intr_info arm_uart_cause = { + .name = "ARM_ARM_UART_INT_CAUSE", + .cause_reg = A_ARM_ARM_UART_INT_CAUSE, + .enable_reg = A_ARM_ARM_UART_INT_EN, + .fatal = 0, + .flags = IHF_FATAL_IFF_ENABLED, + .details = arm_arm_uart_int_cause_details, + .actions = NULL, + }; + static const struct intr_details arm_nvme_db_emu_int_cause_details[] = { + { F_INVALID_BRESP, "Invalid CCI Write Response" }, + { F_DATA_LEN_OF, + "Incorrect Write Request to be written to incorrect Devices/Regions" }, + { F_INVALID_EMU_ADDR, "Invalid Emulation Address Range Configuration" }, + { F_INVALID_AXI_ADDR_CFG, "Invalid AXI Address Configuration" }, + { 0 } + }; static const struct intr_info arm_nvme_db_emu_cause = { .name = "ARM_NVME_DB_EMU_INT_CAUSE", .cause_reg = A_ARM_NVME_DB_EMU_INT_CAUSE, .enable_reg = A_ARM_NVME_DB_EMU_INT_ENABLE, .fatal = 0, .flags = IHF_IGNORE_IF_DISABLED | IHF_FATAL_IFF_ENABLED, - .details = NULL, + .details = arm_nvme_db_emu_int_cause_details, .actions = NULL, }; bool fatal = false; @@ -6785,12 +8245,13 @@ static bool arm_intr_handler(struct adapter *adap, int idx, int flags) fatal |= t4_handle_intr(adap, &arm_err_cause0, 0, flags); fatal |= t4_handle_intr(adap, &arm_periph_cause, 0, flags); fatal |= t4_handle_intr(adap, &arm_nvme_db_emu_cause, 0, flags); + fatal |= t4_handle_intr(adap, &arm_uart_cause, 0, flags); return (fatal); } static inline uint32_t -get_perr_ucause(struct adapter *sc, const struct intr_info *ii) +get_ucause(struct adapter *sc, const struct intr_info *ii) { uint32_t cause; @@ -6977,7 +8438,8 @@ bool t4_slow_intr_handler(struct adapter *adap, int flags) .cause_reg = A_PL_PERR_CAUSE, .enable_reg = A_PL_PERR_ENABLE, .fatal = 0xffffffff, - .flags = IHF_IGNORE_IF_DISABLED | IHF_FATAL_IFF_ENABLED, + .flags = IHF_IGNORE_IF_DISABLED | IHF_FATAL_IFF_ENABLED | + IHF_CLR_DELAYED, .details = pl_int_cause_fields, .actions = NULL, }; @@ -7117,7 +8579,8 @@ bool t4_slow_intr_handler(struct adapter *adap, int flags) .cause_reg = A_PL_PERR_CAUSE, .enable_reg = A_PL_PERR_ENABLE, .fatal = 0xffffffff, - .flags = IHF_IGNORE_IF_DISABLED | IHF_FATAL_IFF_ENABLED, + .flags = IHF_IGNORE_IF_DISABLED | IHF_FATAL_IFF_ENABLED | + IHF_CLR_DELAYED, .details = t7_pl_perr_cause_fields, .actions = NULL, }; @@ -7125,23 +8588,19 @@ bool t4_slow_intr_handler(struct adapter *adap, int flags) uint32_t perr; if (chip_id(adap) < CHELSIO_T7) { - perr = get_perr_ucause(adap, &pl_perr_cause); - fatal |= t4_handle_intr(adap, &pl_perr_cause, 0, - flags & ~(IHF_CLR_ALL_SET | IHF_CLR_ALL_UNIGNORED)); + perr = get_ucause(adap, &pl_perr_cause); + fatal |= t4_handle_intr(adap, &pl_perr_cause, 0, flags); fatal |= t4_handle_intr(adap, &pl_int_cause, t4_perr_to_ic(adap, perr), flags); - t4_write_reg(adap, pl_perr_cause.cause_reg, perr); - (void)t4_read_reg(adap, pl_perr_cause.cause_reg); + clear_int_cause_reg(adap, &pl_perr_cause, flags); } else { - perr = get_perr_ucause(adap, &t7_pl_perr_cause); - fatal |= t4_handle_intr(adap, &t7_pl_perr_cause, 0, - flags & ~(IHF_CLR_ALL_SET | IHF_CLR_ALL_UNIGNORED)); + perr = get_ucause(adap, &t7_pl_perr_cause); + fatal |= t4_handle_intr(adap, &t7_pl_perr_cause, 0, flags); fatal |= t4_handle_intr(adap, &t7_pl_int_cause, t7_perr_to_ic1(perr), flags); fatal |= t4_handle_intr(adap, &t7_pl_int_cause2, t7_perr_to_ic2(perr), flags); - t4_write_reg(adap, t7_pl_perr_cause.cause_reg, perr); - (void)t4_read_reg(adap, t7_pl_perr_cause.cause_reg); + clear_int_cause_reg(adap, &t7_pl_perr_cause, flags); } return (fatal); } diff --git a/sys/dev/cxgbe/common/t4_regs.h b/sys/dev/cxgbe/common/t4_regs.h index 09d0d4aa2c08..9984461352d0 100644 --- a/sys/dev/cxgbe/common/t4_regs.h +++ b/sys/dev/cxgbe/common/t4_regs.h @@ -1465,10 +1465,10 @@ #define A_SGE_INT_ENABLE3 0x1040 #define A_SGE_FL_BUFFER_SIZE0 0x1044 -#define S_SIZE 4 +#define CXGBE_S_SIZE 4 #define CXGBE_M_SIZE 0xfffffffU -#define V_SIZE(x) ((x) << S_SIZE) -#define G_SIZE(x) (((x) >> S_SIZE) & CXGBE_M_SIZE) +#define CXGBE_V_SIZE(x) ((x) << S_SIZE) +#define CXGBE_G_SIZE(x) (((x) >> S_SIZE) & CXGBE_M_SIZE) #define S_T6_SIZE 4 #define M_T6_SIZE 0xfffffU @@ -26578,15 +26578,10 @@ #define V_CIM_ULP_TX_PKT_ERR_CODE(x) ((x) << S_CIM_ULP_TX_PKT_ERR_CODE) #define G_CIM_ULP_TX_PKT_ERR_CODE(x) (((x) >> S_CIM_ULP_TX_PKT_ERR_CODE) & M_CIM_ULP_TX_PKT_ERR_CODE) -#define S_CIM_SGE1_PKT_ERR_CODE 8 -#define M_CIM_SGE1_PKT_ERR_CODE 0xffU -#define V_CIM_SGE1_PKT_ERR_CODE(x) ((x) << S_CIM_SGE1_PKT_ERR_CODE) -#define G_CIM_SGE1_PKT_ERR_CODE(x) (((x) >> S_CIM_SGE1_PKT_ERR_CODE) & M_CIM_SGE1_PKT_ERR_CODE) - -#define S_CIM_SGE0_PKT_ERR_CODE 0 -#define M_CIM_SGE0_PKT_ERR_CODE 0xffU -#define V_CIM_SGE0_PKT_ERR_CODE(x) ((x) << S_CIM_SGE0_PKT_ERR_CODE) -#define G_CIM_SGE0_PKT_ERR_CODE(x) (((x) >> S_CIM_SGE0_PKT_ERR_CODE) & M_CIM_SGE0_PKT_ERR_CODE) +#define S_CIM_SGE_PKT_ERR_CODE 0 +#define M_CIM_SGE_PKT_ERR_CODE 0xffU +#define V_CIM_SGE_PKT_ERR_CODE(x) ((x) << S_CIM_SGE_PKT_ERR_CODE) +#define G_CIM_SGE_PKT_ERR_CODE(x) (((x) >> S_CIM_SGE_PKT_ERR_CODE) & M_CIM_SGE_PKT_ERR_CODE) #define S_CIM_PCIE_PKT_ERR_CODE 8 #define M_CIM_PCIE_PKT_ERR_CODE 0xffU @@ -60550,17 +60545,15 @@ #define A_MAC_PORT_PTP_DRIFT_ADJUST_COUNT 0x9a0 #define A_MAC_PORT_PTP_OFFSET_ADJUST_FINE 0x9a4 -#if 0 -#define S_B 16 -#define M_B 0xffffU -#define V_B(x) ((x) << S_B) -#define G_B(x) (((x) >> S_B) & M_B) -#endif +#define CXGBE_S_B 16 +#define CXGBE_M_B 0xffffU +#define CXGBE_V_B(x) ((x) << CXGBE_S_B) +#define CXGBE_G_B(x) (((x) >> CXGBE_S_B) & CXGBE_M_B) -#define S_A 0 -#define M_A 0xffffU -#define V_A(x) ((x) << S_A) -#define G_A(x) (((x) >> S_A) & M_A) +#define CXGBE_S_A 0 +#define CXGBE_M_A 0xffffU +#define CXGBE_V_A(x) ((x) << CXGBE_S_A) +#define CXGBE_G_A(x) (((x) >> CXGBE_S_A) & CXGBE_M_A) #define A_MAC_PORT_PTP_OFFSET_ADJUST_TOTAL 0x9a8 #define A_MAC_PORT_PTP_CFG 0x9ac @@ -62257,10 +62250,10 @@ #define A_MAC_PORT_MTIP_VLAN_TPID_0 0x1a00 -#define S_VLANTAG 0 +#define CXGBE_S_VLANTAG 0 #define CXGBE_M_VLANTAG 0xffffU -#define V_VLANTAG(x) ((x) << S_VLANTAG) -#define G_VLANTAG(x) (((x) >> S_VLANTAG) & M_VLANTAG) +#define CXGBE_V_VLANTAG(x) ((x) << CXGBE_S_VLANTAG) +#define CXGBE_G_VLANTAG(x) (((x) >> CXGBE_S_VLANTAG) & CXGBE_M_VLANTAG) #define A_MAC_PORT_MTIP_VLAN_TPID_1 0x1a04 #define A_MAC_PORT_MTIP_VLAN_TPID_2 0x1a08 @@ -69613,10 +69606,10 @@ #define V_INIT_ENABLE(x) ((x) << S_INIT_ENABLE) #define F_INIT_ENABLE V_INIT_ENABLE(1U) -#define S_WAIT 16 -#define M_WAIT 0xfffU -#define CXGBE_V_WAIT(x) ((x) << S_WAIT) -#define G_WAIT(x) (((x) >> S_WAIT) & M_WAIT) +#define CXGBE_S_WAIT 16 +#define CXGBE_M_WAIT 0xfffU +#define CXGBE_V_WAIT(x) ((x) << CXGBE_S_WAIT) +#define CXGBE_G_WAIT(x) (((x) >> CXGBE_S_WAIT) & CXGBE_M_WAIT) #define S_EN_MULTI_RANK_SEL 4 #define V_EN_MULTI_RANK_SEL(x) ((x) << S_EN_MULTI_RANK_SEL) diff --git a/sys/dev/cxgbe/firmware/t4fw_interface.h b/sys/dev/cxgbe/firmware/t4fw_interface.h index b11552dce021..6235a2c3fab4 100644 --- a/sys/dev/cxgbe/firmware/t4fw_interface.h +++ b/sys/dev/cxgbe/firmware/t4fw_interface.h @@ -2560,6 +2560,22 @@ struct fw_ri_wr { __be32 tpt_offset_t10_config; __be32 r8[2]; } nvmet_init; + struct fw_ri_iscsi_init { + __u8 type; + __u8 dcrc_dis_to_hcrc; + __u8 r4[3]; + __u8 qp_caps; + __be16 r5; + __be32 pdid; + __be32 qpid; + __be32 sq_eqid; + __be32 r6; + __be32 scqid; + __be32 rcqid; + __be32 r7[4]; + __be32 r8[2]; + __be64 r9; + } iscsi_init; struct fw_ri_fini { __u8 type; __u8 r3[7]; @@ -2634,6 +2650,37 @@ struct fw_ri_wr { #define G_FW_RI_WR_T10_CONFIG(x) \ (((x) >> S_FW_RI_WR_T10_CONFIG) & M_FW_RI_WR_T10_CONFIG) +#define S_FW_RI_WR_DCRC_DIS 7 +#define M_FW_RI_WR_DCRC_DIS 0x1 +#define V_FW_RI_WR_DCRC_DIS(x) ((x) << S_FW_RI_WR_DCRC_DIS) +#define G_FW_RI_WR_DCRC_DIS(x) \ + (((x) >> S_FW_RI_WR_DCRC_DIS) & M_FW_RI_WR_DCRC_DIS) +#define F_FW_RI_WR_DCRC_DIS V_FW_RI_WR_DCRC_DIS(1U) + +#define S_FW_RI_WR_HCRC_DIS 6 +#define M_FW_RI_WR_HCRC_DIS 0x1 +#define V_FW_RI_WR_HCRC_DIS(x) ((x) << S_FW_RI_WR_HCRC_DIS) +#define G_FW_RI_WR_HCRC_DIS(x) \ + (((x) >> S_FW_RI_WR_HCRC_DIS) & M_FW_RI_WR_HCRC_DIS) +#define F_FW_RI_WR_HCRC_DIS V_FW_RI_WR_HCRC_DIS(1U) + +#define S_FW_RI_WR_PSZ_IDX 4 +#define M_FW_RI_WR_PSZ_IDX 0x3 +#define V_FW_RI_WR_PSZ_IDX(x) ((x) << S_FW_RI_WR_PSZ_IDX) +#define G_FW_RI_WR_PSZ_IDX(x) \ + (((x) >> S_FW_RI_WR_PSZ_IDX) & M_FW_RI_WR_PSZ_IDX) + +#define S_FW_RI_WR_DCRC 1 +#define M_FW_RI_WR_DCRC 0x1 +#define V_FW_RI_WR_DCRC(x) ((x) << S_FW_RI_WR_DCRC) +#define G_FW_RI_WR_DCRC(x) (((x) >> S_FW_RI_WR_DCRC) & M_FW_RI_WR_DCRC) +#define F_FW_RI_WR_DCRC V_FW_RI_WR_DCRC(1U) + +#define S_FW_RI_WR_HCRC 0 +#define M_FW_RI_WR_HCRC 0x1 +#define V_FW_RI_WR_HCRC(x) ((x) << S_FW_RI_WR_HCRC) +#define G_FW_RI_WR_HCRC(x) (((x) >> S_FW_RI_WR_HCRC) & M_FW_RI_WR_HCRC) +#define F_FW_RI_WR_HCRC V_FW_RI_WR_HCRC(1U) /****************************************************************************** * R o C E V 2 W O R K R E Q U E S T s @@ -2951,6 +2998,24 @@ struct fw_v2_nvmet_tx_data_wr { #endif }; +#define S_FW_V2_NVMET_TX_DATA_WR_DACK_CHANGE 20 +#define M_FW_V2_NVMET_TX_DATA_WR_DACK_CHANGE 0x1 +#define V_FW_V2_NVMET_TX_DATA_WR_DACK_CHANGE(x) \ + ((x) << S_FW_V2_NVMET_TX_DATA_WR_DACK_CHANGE) +#define G_FW_V2_NVMET_TX_DATA_WR_DACK_CHANGE(x) \ + (((x) >> S_FW_V2_NVMET_TX_DATA_WR_DACK_CHANGE) & \ + M_FW_V2_NVMET_TX_DATA_WR_DACK_CHANGE) +#define F_FW_V2_NVMET_TX_DATA_WR_DACK_CHANGE \ + V_FW_V2_NVMET_TX_DATA_WR_DACK_CHANGE(1U) + +#define S_FW_V2_NVMET_TX_DATA_WR_DACK_MODE 18 +#define M_FW_V2_NVMET_TX_DATA_WR_DACK_MODE 0x3 +#define V_FW_V2_NVMET_TX_DATA_WR_DACK_MODE(x) \ + ((x) << S_FW_V2_NVMET_TX_DATA_WR_DACK_MODE) +#define G_FW_V2_NVMET_TX_DATA_WR_DACK_MODE(x) \ + (((x) >> S_FW_V2_NVMET_TX_DATA_WR_DACK_MODE) & \ + M_FW_V2_NVMET_TX_DATA_WR_DACK_MODE) + #define S_FW_V2_NVMET_TX_DATA_WR_FLAGS_HI 10 #define M_FW_V2_NVMET_TX_DATA_WR_FLAGS_HI 0x3fffff #define V_FW_V2_NVMET_TX_DATA_WR_FLAGS_HI(x) \ @@ -4990,6 +5055,16 @@ struct fw_crypto_update_sa_wr { } key; }; +#define S_FW_CRYPTO_UPDATE_SA_WR_EG_IPVER 3 +#define M_FW_CRYPTO_UPDATE_SA_WR_EG_IPVER 0x1 +#define V_FW_CRYPTO_UPDATE_SA_WR_EG_IPVER(x) \ + ((x) << S_FW_CRYPTO_UPDATE_SA_WR_EG_IPVER) +#define G_FW_CRYPTO_UPDATE_SA_WR_EG_IPVER(x) \ + (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_EG_IPVER) & \ + M_FW_CRYPTO_UPDATE_SA_WR_EG_IPVER) +#define F_FW_CRYPTO_UPDATE_SA_WR_EG_IPVER \ + V_FW_CRYPTO_UPDATE_SA_WR_EG_IPVER(1U) + #define S_FW_CRYPTO_UPDATE_SA_WR_SAOP 2 #define M_FW_CRYPTO_UPDATE_SA_WR_SAOP 0x1 #define V_FW_CRYPTO_UPDATE_SA_WR_SAOP(x) \ @@ -8952,24 +9027,40 @@ enum fw_port_type { FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */ FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */ FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */ - FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */ + FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G BP AN */ FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */ - FW_PORT_TYPE_BP_AP = 10, /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */ - FW_PORT_TYPE_BP4_AP = 11, /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */ + FW_PORT_TYPE_BP_AP = 10, /* No, 1, No, No, Yes, Yes, 10G, BP AN */ + FW_PORT_TYPE_BP4_AP = 11, /* No, 4, No, No, Yes, Yes, 10G, BP AN */ FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */ FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */ FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */ - FW_PORT_TYPE_BP40_BA = 15, /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */ - FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/25G, Backplane */ + FW_PORT_TYPE_BP40_BA = 15, /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP AN */ + FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/50G/25G/10G/1G, BP AN */ FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G/40G/25G */ - FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G Spider cable */ - FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */ + FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G, Spider cable */ + FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G, Spider cable */ FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */ FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */ FW_PORT_TYPE_KR_XLAUI = 22, /* No, 4, 40G/10G/1G, No AN*/ + FW_PORT_TYPE_BARE_LINK_50G = 23, /* No, 1, 50G */ + FW_PORT_TYPE_BARE_LINK_100G = 24, /* No, 2, 100G/50G */ + FW_PORT_TYPE_BARE_LINK_200G = 25, /* No, 4, 200G/100G/50G */ FW_PORT_TYPE_SFP56 = 26, /* No, 1, 50G/25G */ FW_PORT_TYPE_QSFP56 = 27, /* No, 4, 200G/100G/50G/25G */ - FW_PORT_TYPE_QSFPDD = 34, /* No, 8, 400G/200G/100G/50G */ + FW_PORT_TYPE_QSFP56_4_50G = 28, /* No, 1, 50G, Spider cable */ + FW_PORT_TYPE_KR_50G = 29, /* No, 1, 50G/25G/10G/1G, BP AN */ + FW_PORT_TYPE_KR2_100G = 30, /* No, 2, 100G/50G/25G/10G/1G, BP AN */ + FW_PORT_TYPE_KR4_200G = 31, /* No, 4, 200G/100G/40G/50G/25G/10G/1G, BP AN */ + FW_PORT_TYPE_QSFP56_2_50G = 32, /* No, 1, 50G, Spider cable */ + FW_PORT_TYPE_OSFP = 33, /* No, 8, 400G/200G/100G/50G */ + FW_PORT_TYPE_QSFPDD = 34, /* No, 8, 400G/200G/100G/50G */ + FW_PORT_TYPE_OSFP_2_200G = 35, /* No, 4, 200G, Spider cable */ + FW_PORT_TYPE_QSFPDD_2_200G = 36,/* No, 4, 200G, Spider cable */ + FW_PORT_TYPE_KR8_400G = 37, /* No, 8, 400G/200G/100G/50G/40G/25G/10G/1G, BP AN */ + FW_PORT_TYPE_QSFP56_2_100G = 38,/* No, 2, 100G, Spider cable */ + FW_PORT_TYPE_QSFPDD_4_100G = 39,/* No, 2, 100G, Spider cable */ + FW_PORT_TYPE_KR2_50G = 40, /* No, 1, 50G/25G/10G/1G, BP AN */ + FW_PORT_TYPE_MAX, FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PORTTYPE32 }; diff --git a/sys/dev/cxgbe/firmware/t7fw_cfg.txt b/sys/dev/cxgbe/firmware/t7fw_cfg.txt index 70b05da04a23..33c703fdc9d7 100644 --- a/sys/dev/cxgbe/firmware/t7fw_cfg.txt +++ b/sys/dev/cxgbe/firmware/t7fw_cfg.txt @@ -175,6 +175,11 @@ # TPT error. # Err2uP = 0 + # ULP_TX_ACCELERATOR_CTL + reg[0x8f90] = 0x00000015/0x00000015 # Compression block clock gating + # Dedupe clock gating + # Erasure Coding clock gating + #ULP_RX_CTL1 reg[0x19330] = 0x000000f0/0x000000f0 # RDMA_Invld_Msg_Dis = 3 # ROCE_Invld_Msg_Dis = 3 @@ -201,7 +206,7 @@ # default gc enabled. # HMA configuration (uncomment following lines to enable HMA) - hma_size = 128 # Size (in MBs) of host memory expected + hma_size = 256 # Size (in MBs) of host memory expected hma_regions = iscsi,rrq,tls,ddp,pmrx,stag,pbl,rq # What all regions to place in host memory #mc[0]=0 @@ -394,8 +399,7 @@ neq = 16 # niqflint + nethctrl Egress Queues nexactf = 8 # number of exact MPSTCAM MAC filters cmask = all # access to all channels - #pmask = 0x4 # access to only one port - pmask = 0x1 # access to only one port + pmask = 0x4 # access to only one port [function "3"] nvf = 16 # NVF on this function @@ -407,7 +411,7 @@ neq = 16 # niqflint + nethctrl Egress Queues nexactf = 8 # number of exact MPSTCAM MAC filters cmask = all # access to all channels - #pmask = 0x2 # access to only one port + pmask = 0x8 # access to only one port # Some OS Drivers manage all application functions for all ports via PF4. # Thus we need to provide a large number of resources here. For Egress @@ -421,7 +425,7 @@ r_caps = all # read permissions for all commands nvi = 28 # NVI_UNIFIED niqflint = 170 # NFLIQ_UNIFIED + NLFIQ_WD - nethctrl = 224 # NETHCTRL_UNIFIED + NETHCTRL_WD + nethctrl = 288 # NETHCTRL_UNIFIED + NETHCTRL_WD neq = 252 # NEQ_UNIFIED + NEQ_WD nqpcq = 12288 nexactf = 40 # NMPSTCAM_UNIFIED @@ -435,8 +439,7 @@ nserver = 480 # number of server region entries nhash = 12288 # number of hash region entries nhpfilter = 64 # number of high priority filter region entries - #protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside, ipsec_inline, rocev2, nic_hashfilter, ofld_sendpath - protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside, ipsec_inline, rocev2, nic_hashfilter, nvme_tcp + protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside, ipsec_inline, rocev2, nic_hashfilter, nvme_tcp, ofld_sendpath tp_l2t = 3072 tp_ddp = 2 tp_ddp_iscsi = 2 @@ -643,7 +646,7 @@ [fini] version = 0x1425001d - checksum = 0x3671da3b + checksum = 0x2419f987 # Total resources used by above allocations: # Virtual Interfaces: 104 diff --git a/sys/dev/cxgbe/firmware/t7fw_cfg_uwire.txt b/sys/dev/cxgbe/firmware/t7fw_cfg_uwire.txt index b1f5129238eb..9da841153138 100644 --- a/sys/dev/cxgbe/firmware/t7fw_cfg_uwire.txt +++ b/sys/dev/cxgbe/firmware/t7fw_cfg_uwire.txt @@ -175,6 +175,11 @@ # TPT error. # Err2uP = 0 + # ULP_TX_ACCELERATOR_CTL + reg[0x8f90] = 0x00000015/0x00000015 # Compression block clock gating + # Dedupe clock gating + # Erasure Coding clock gating + #ULP_RX_CTL1 reg[0x19330] = 0x000000f0/0x000000f0 # RDMA_Invld_Msg_Dis = 3 # ROCE_Invld_Msg_Dis = 3 @@ -201,7 +206,7 @@ # default gc enabled. # HMA configuration (uncomment following lines to enable HMA) - hma_size = 128 # Size (in MBs) of host memory expected + hma_size = 256 # Size (in MBs) of host memory expected hma_regions = iscsi,rrq,tls,ddp,pmrx,stag,pbl,rq # What all regions to place in host memory #mc[0]=0 @@ -394,8 +399,7 @@ neq = 16 # niqflint + nethctrl Egress Queues nexactf = 8 # number of exact MPSTCAM MAC filters cmask = all # access to all channels - #pmask = 0x4 # access to only one port - pmask = 0x1 # access to only one port + pmask = 0x4 # access to only one port [function "3"] nvf = 16 # NVF on this function @@ -407,7 +411,7 @@ neq = 16 # niqflint + nethctrl Egress Queues nexactf = 8 # number of exact MPSTCAM MAC filters cmask = all # access to all channels - #pmask = 0x2 # access to only one port + pmask = 0x8 # access to only one port # Some OS Drivers manage all application functions for all ports via PF4. # Thus we need to provide a large number of resources here. For Egress @@ -421,7 +425,7 @@ r_caps = all # read permissions for all commands nvi = 28 # NVI_UNIFIED niqflint = 170 # NFLIQ_UNIFIED + NLFIQ_WD - nethctrl = 224 # NETHCTRL_UNIFIED + NETHCTRL_WD + nethctrl = 288 # NETHCTRL_UNIFIED + NETHCTRL_WD neq = 252 # NEQ_UNIFIED + NEQ_WD nqpcq = 12288 nexactf = 40 # NMPSTCAM_UNIFIED @@ -435,8 +439,7 @@ nserver = 480 # number of server region entries nhash = 12288 # number of hash region entries nhpfilter = 64 # number of high priority filter region entries - #protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside, ipsec_inline, rocev2, nic_hashfilter, ofld_sendpath - protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside, ipsec_inline, rocev2, nic_hashfilter, nvme_tcp + protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside, ipsec_inline, rocev2, nic_hashfilter, nvme_tcp, ofld_sendpath tp_l2t = 3072 tp_ddp = 2 tp_ddp_iscsi = 2 @@ -643,7 +646,7 @@ [fini] version = 0x1425001d - checksum = 0x96513217 + checksum = 0x83f95163 # Total resources used by above allocations: # Virtual Interfaces: 104 diff --git a/sys/dev/cxgbe/t4_main.c b/sys/dev/cxgbe/t4_main.c index 69ecfce1dade..07906dac00a8 100644 --- a/sys/dev/cxgbe/t4_main.c +++ b/sys/dev/cxgbe/t4_main.c @@ -3760,10 +3760,17 @@ port_mword(struct port_info *pi, uint32_t speed) return (IFM_NONE); } break; - case M_FW_PORT_CMD_PTYPE: /* FW_PORT_TYPE_NONE for old firmware */ - if (chip_id(pi->adapter) >= CHELSIO_T7) - return (IFM_UNKNOWN); - /* fall through */ + case FW_PORT_TYPE_KR4_200G: { + /* + * Pre-T7 firmware used M_FW_PORT_CMD_PTYPE for PORT_TYPE_NONE + * and driver needs to deal with both. + */ + _Static_assert(M_FW_PORT_CMD_PTYPE == FW_PORT_TYPE_KR4_200G, + "driver/firmware mismatch"); + if (chip_id(pi->adapter) < CHELSIO_T7) + return (IFM_NONE); + return (IFM_200G_KR4_PAM4); + } case FW_PORT_TYPE_NONE: return (IFM_NONE); } @@ -5991,7 +5998,29 @@ get_params__post_init(struct adapter *sc) sc->vres.key.start = val[0]; sc->vres.key.size = val[1] - val[0] + 1; } - + if (sc->cryptocaps & FW_CAPS_CONFIG_IPSEC_INLINE) { + param[0] = FW_PARAM_PFVF(NIPSEC_TUNNEL); + param[1] = FW_PARAM_PFVF(NIPSEC_TRANSPORT); + rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val); + if (rc == 0) { + sc->params.nipsec_tunnel = val[0]; + sc->params.nipsec_transport = val[1]; + } else { + CH_ERR(sc, "failed to query IPsec params: %d.\n", rc); + MPASS(sc->params.nipsec_tunnel == 0); + MPASS(sc->params.nipsec_transport == 0); + } + } + if (sc->cryptocaps & FW_CAPS_CONFIG_OFLD_OVER_IPSEC_INLINE) { + param[0] = FW_PARAM_PFVF(OFLD_NIPSEC_TUNNEL); + rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, param, val); + if (rc == 0) { + sc->params.nofld_ipsec_tunnel = val[0]; + } else { + CH_ERR(sc, "failed to query TOE IPsec params: %d.\n", rc); + MPASS(sc->params.nofld_ipsec_tunnel == 0); + } + } /* * We've got the params we wanted to query directly from the firmware. * Grab some others via other means. @@ -7980,6 +8009,15 @@ t4_sysctls(struct adapter *sc) SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD, NULL, sc->tids.nftids, "number of filters"); + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "nipsec_tunnel", CTLFLAG_RD, + NULL, sc->params.nipsec_tunnel, "max hw IPsec tunnels"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "nipsec_transport", CTLFLAG_RD, + NULL, sc->params.nipsec_transport, "max hw IPsec transport pairs"); + + SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "nofld_ipsec_tunnel", CTLFLAG_RD, + NULL, sc->params.nofld_ipsec_tunnel, "max hw IPsec tunnels (TOE)"); + SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, sysctl_temperature, "I", "chip temperature (in Celsius)"); diff --git a/sys/dev/dpaa/if_memac_fdt.c b/sys/dev/dpaa/if_memac_fdt.c index f136608a906c..74a923f45580 100644 --- a/sys/dev/dpaa/if_memac_fdt.c +++ b/sys/dev/dpaa/if_memac_fdt.c @@ -4,6 +4,31 @@ * * SPDX-License-Identifier: BSD-2-Clause */ +/* + * Copyright (c) 2012 Semihalf. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ #include <sys/param.h> #include <sys/systm.h> diff --git a/sys/dev/eqos/if_eqos_starfive.c b/sys/dev/eqos/if_eqos_starfive.c index 62f8b3f38983..f81118fd3094 100644 --- a/sys/dev/eqos/if_eqos_starfive.c +++ b/sys/dev/eqos/if_eqos_starfive.c @@ -17,6 +17,7 @@ #include <sys/socket.h> #include <machine/bus.h> +#include <net/ethernet.h> #include <net/if.h> #include <net/if_media.h> #include <dev/mii/mii.h> @@ -40,6 +41,7 @@ #define JH7110_CSR_FREQ 198000000 #define WR4(sc, o, v) bus_write_4(sc->base.res[EQOS_RES_MEM], (o), (v)) +#define RD4(sc, o) bus_read_4(sc->base.res[EQOS_RES_MEM], (o)) static const struct ofw_compat_data compat_data[] = { {"starfive,jh7110-dwmac", 1}, @@ -131,6 +133,8 @@ if_eqos_starfive_init(device_t dev) struct if_eqos_starfive_softc *sc = device_get_softc(dev); hwreset_t rst_ahb, rst_stmmaceth; phandle_t node; + uint8_t eaddr[ETHER_ADDR_LEN]; + uint32_t maclo, machi; node = ofw_bus_get_node(dev); @@ -186,6 +190,14 @@ if_eqos_starfive_init(device_t dev) return (ENXIO); } + if (OF_getprop(node, "local-mac-address", eaddr, sizeof(eaddr)) == + sizeof(eaddr)) { + machi = eaddr[5] | (eaddr[4] << 8); + WR4(sc, GMAC_MAC_ADDRESS0_HIGH, machi); + maclo = eaddr[3] | (eaddr[2] << 8) | (eaddr[1] << 16) | + (eaddr[0] << 24); + WR4(sc, GMAC_MAC_ADDRESS0_LOW, maclo); + } return (0); } diff --git a/sys/dev/ffec/if_ffec.c b/sys/dev/ffec/if_ffec.c index 17fab283fc81..cf171a854406 100644 --- a/sys/dev/ffec/if_ffec.c +++ b/sys/dev/ffec/if_ffec.c @@ -850,7 +850,7 @@ ffec_rxfinish_onebuf(struct ffec_softc *sc, int len) * biggest header is, instead of the whole 1530ish-byte frame. */ if (sc->fecflags & FECFLAG_RACC) { - m->m_data = mtod(m, uint8_t *) + 2; + m_adj(m, 2); } else { src = mtod(m, uint8_t*); dst = src - ETHER_ALIGN; diff --git a/sys/dev/hwpmc/hwpmc_ibs.c b/sys/dev/hwpmc/hwpmc_ibs.c index 8cfe7b2df145..ae14f2ccb14c 100644 --- a/sys/dev/hwpmc/hwpmc_ibs.c +++ b/sys/dev/hwpmc/hwpmc_ibs.c @@ -510,6 +510,9 @@ pmc_ibs_intr(struct trapframe *tf) int retval, cpu; uint64_t config; + if (ibs_pcpu == NULL) + return (0); + cpu = curcpu; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[ibs,%d] out of range CPU %d", __LINE__, cpu)); diff --git a/sys/dev/hyperv/vmbus/amd64/vmbus_vector.S b/sys/dev/hyperv/vmbus/amd64/vmbus_vector.S index a15041ae7e32..f7479dc1f6f8 100644 --- a/sys/dev/hyperv/vmbus/amd64/vmbus_vector.S +++ b/sys/dev/hyperv/vmbus/amd64/vmbus_vector.S @@ -40,3 +40,5 @@ movq %rsp, %rdi call vmbus_handle_intr jmp doreti + + .section .note.GNU-stack,"",%progbits diff --git a/sys/dev/ichsmb/ichsmb_pci.c b/sys/dev/ichsmb/ichsmb_pci.c index af3e0f004b88..7f9409e4452c 100644 --- a/sys/dev/ichsmb/ichsmb_pci.c +++ b/sys/dev/ichsmb/ichsmb_pci.c @@ -110,7 +110,8 @@ #define ID_ELKHARTLAKE 0x4b23 #define ID_GEMINILAKE 0x31d4 #define ID_CEDARFORK 0x18df -#define ID_ICELAKE 0x34a3 +#define ID_ICELAKELP 0x34a3 +#define ID_ICELAKEN 0x38a3 #define ID_ALDERLAKE 0x7aa3 #define ID_ALDERLAKE2 0x51a3 #define ID_ALDERLAKE3 0x54a3 @@ -255,8 +256,10 @@ static const struct pci_device_table ichsmb_devices[] = { PCI_DESCR("Intel Gemini Lake SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_CEDARFORK), PCI_DESCR("Intel Cedar Fork SMBus controller") }, - { PCI_DEV(PCI_VENDOR_INTEL, ID_ICELAKE), - PCI_DESCR("Intel Ice Lake SMBus controller") }, + { PCI_DEV(PCI_VENDOR_INTEL, ID_ICELAKELP), + PCI_DESCR("Intel Ice Lake-LP SMBus controller") }, + { PCI_DEV(PCI_VENDOR_INTEL, ID_ICELAKEN), + PCI_DESCR("Intel Ice Lake-N SMBus controller") }, { PCI_DEV(PCI_VENDOR_INTEL, ID_ALDERLAKE), .driver_data = (uintptr_t)ICHSMB_FEATURE_BLOCK_BUFFER, PCI_DESCR("Intel Alder Lake SMBus controller") }, diff --git a/sys/dev/ichwd/ichwd.c b/sys/dev/ichwd/ichwd.c index 5481553cc175..b0c953e58956 100644 --- a/sys/dev/ichwd/ichwd.c +++ b/sys/dev/ichwd/ichwd.c @@ -561,13 +561,12 @@ static device_t ichwd_find_ich_lpc_bridge(device_t isa, struct ichwd_device **id_p) { struct ichwd_device *id; - device_t isab, pci; + device_t isab; uint16_t devid; /* Check whether parent ISA bridge looks familiar. */ isab = device_get_parent(isa); - pci = device_get_parent(isab); - if (pci == NULL || device_get_devclass(pci) != devclass_find("pci")) + if (!is_pci_device(isab)) return (NULL); if (pci_get_vendor(isab) != VENDORID_INTEL) return (NULL); diff --git a/sys/dev/iicbus/sensor/w83793g.c b/sys/dev/iicbus/sensor/w83793g.c new file mode 100644 index 000000000000..772384aa57a0 --- /dev/null +++ b/sys/dev/iicbus/sensor/w83793g.c @@ -0,0 +1,366 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2026 Justin Hibbits + */ + +#include <sys/param.h> +#include <sys/bus.h> +#include <sys/kernel.h> +#include <sys/module.h> +#include <sys/sysctl.h> + +#include <dev/iicbus/iicbus.h> +#include <dev/iicbus/iiconf.h> + +#include <dev/ofw/ofw_bus.h> +#include <dev/ofw/ofw_bus_subr.h> + +/* + * Driver for the Winbond W83793G hardware monitor. + * + * The hardware monitor supports the following sensors: + * - 6 temperature sensors + * - 4 with 1/4 integer precision + * - 2 with integer precision + * - 11 voltage sensors + * - 12 fan sensors + * - FanIn 6-12 are on multifunction pins, so may not be enabled. + * 8 DC/PWM fan outputs for fan speed control + * - Case open detection + */ + +#define WB_TD_BASE 0x1c +#define WB_TLOW 0x22 + +#define WB_VCORE_A 0x10 +#define WB_VCORE_B 0x11 +#define WB_VTT 0x12 +#define WB_VSEN1 0x14 +#define WB_VSEN2 0x15 +#define WB_VSEN3 0x16 +#define WB_VSEN4 0x17 +#define WB_5VDD 0x18 +#define WB_5VSB 0x19 +#define WB_VBAT 0x1a +#define WB_VLOW 0x1b +#define WB_FAN_BASE 0x23 + +#define INT_STS1 0x41 +#define INT_STS2 0x42 +#define INT_STS3 0x43 +#define INT_STS4 0x44 +#define CHASSIS 0x40 +#define INT_STS5 0x45 +#define INT_MASK1 0x46 +#define INT_MASK2 0x47 +#define INT_MASK3 0x48 +#define INT_MASK4 0x49 +#define CLR_CHS 0x80 +#define INT_MASK5 0x4a + +#define WB_MFC 0x58 /* Multi-function pin control */ +#define MFC_VIDBSEL 0x80 +#define MFC_SIB_SEL 0x40 +#define MFC_SID_SEL_M 0x30 +#define MFC_SID_VID 0x00 +#define MFC_SID_FANIN 0x20 +#define MFC_SIC_SEL_M 0x0c +#define MFC_SIC_VID 0x00 +#define MFC_SIC_FANIN 0x08 +#define MFC_SIA_SEL 0x02 +#define MFC_FAN8SEL 0x01 +#define WB_FANIN_CTRL 0x5c +#define FANIN_EN_12 0x40 +#define FANIN_EN_11 0x20 +#define FANIN_EN_10 0x10 +#define FANIN_EN_9 0x08 +#define FANIN_EN_8 0x04 +#define FANIN_EN_7 0x02 +#define FANIN_EN_6 0x01 +#define WB_FANIN_SEL 0x5d +#define WB_TD_MD 0x5e /* TD mode select register */ +#define TD_MD_M(n) (0x3 << ((n) * 2)) +#define TD_MD_S(n) ((n) * 2) +#define TD_STOP_M 0x0 +#define TD_INT_MD 0x1 +#define TD_EXT_MD 0x2 +#define WB_TR_MD 0x5f +#define TR2_MD 0x2 +#define TR1_MD 0x1 + +#define WB_TEMP_COUNT 6 /* Total temperature sensors */ +#define WB_TD_COUNT 4 /* Temp sensors with "low" part */ +#define WB_TR_COUNT 2 +#define WB_FAN_COUNT 12 +#define WB_FAN_ALWAYS_ON 5 /* First 5 are not controlled */ +#define WB_V_COUNT 11 + +static const struct wb_vsens { + const char *name; + int reg; + int scale; /* Scale in millivolts */ + int add; /* Scale in millivolts */ + int left_low; /* left bit in VLOW, if applicable */ +} voltages[] = { + { "v_core_a", WB_VCORE_A, 2, 0, 1 }, + { "v_core_b", WB_VCORE_B, 2, 0, 3 }, + { "v_tt", WB_VTT, 2, 0, 5 }, + { "v_sen_1", WB_VSEN1, 16 }, + { "v_sen_2", WB_VSEN2, 16 }, + { "v_sen_3", WB_VSEN3, 16 }, + { "v_sen_4", WB_VSEN4, 8 }, + { "5v", WB_5VDD, 24, 150 }, + { "5v_sb", WB_5VSB, 24, 150 }, + { "v_bat", WB_VBAT, 16 } +}; + +struct w83793g_softc { + device_t sc_dev; + +}; + +static device_probe_t w83793g_probe; +static device_attach_t w83793g_attach; +static device_detach_t w83793g_detach; +static int w83793g_temp_sysctl(SYSCTL_HANDLER_ARGS); +static int w83793g_fan_sysctl(SYSCTL_HANDLER_ARGS); +static int w83793g_voltage_sysctl(SYSCTL_HANDLER_ARGS); +static int w83793g_case_sysctl(SYSCTL_HANDLER_ARGS); + +static device_method_t w83793g_methods[] = { + DEVMETHOD(device_probe, w83793g_probe), + DEVMETHOD(device_attach, w83793g_attach), + DEVMETHOD(device_detach, w83793g_detach), + + DEVMETHOD_END +}; + +static struct ofw_compat_data compat[] = { + { "winbond,w83793", 1 }, + { NULL, 0 } +}; + +DEFINE_CLASS_0(w83793g, w83793g_driver, w83793g_methods, + sizeof(struct w83793g_softc)); +DRIVER_MODULE(w83793g, iicbus, w83793g_driver, NULL, NULL); +MODULE_VERSION(w83793g, 1); +MODULE_DEPEND(w83793g, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER); +IICBUS_FDT_PNP_INFO(compat); + +static int +w83793g_readreg(device_t dev, int reg, uint8_t *output) +{ + return (iicdev_readfrom(dev, reg, output, sizeof(*output), IIC_WAIT)); +} + +static int +w83793g_writereg(device_t dev, int reg, uint8_t *output) +{ + return (iicdev_writeto(dev, reg, output, sizeof(*output), IIC_WAIT)); +} + +static bool +temp_enabled(struct w83793g_softc *sc, int sensor) +{ + uint8_t reg; + int error; + + if (sensor < WB_TD_COUNT) { + error = w83793g_readreg(sc->sc_dev, WB_TD_MD, ®); + if (error != 0) + return (false); + return ((reg & TD_MD_M(sensor)) != 0); + } else { + error = w83793g_readreg(sc->sc_dev, WB_TR_MD, ®); + sensor -= WB_TD_COUNT; + if (error != 0) + return (false); + return ((reg & (1 << sensor)) != 0); + } +} + +static bool +fan_enabled(struct w83793g_softc *sc, int fan) +{ + int error; + uint8_t fanin_ctl; + + if (fan < WB_FAN_ALWAYS_ON) + return (true); + + error = w83793g_readreg(sc->sc_dev, WB_FANIN_CTRL, &fanin_ctl); + if (error != 0) + return (false); + + fan -= WB_FAN_ALWAYS_ON; + + return ((fanin_ctl & (1 << fan)) != 0); +} + +static int +w83793g_probe(device_t dev) +{ + if (ofw_bus_search_compatible(dev, compat)->ocd_data == 0) + return (ENXIO); + + device_set_desc(dev, "Winbond W83793 Hardware Monitor"); + + return (BUS_PROBE_DEFAULT); +} + +static int +w83793g_attach(device_t dev) +{ + struct w83793g_softc *sc = device_get_softc(dev); + struct sysctl_oid *root = device_get_sysctl_tree(dev); + struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); + struct sysctl_oid *node; + int i; + + sc->sc_dev = dev; + node = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(root), OID_AUTO, "voltages", + CTLFLAG_RD, NULL, NULL); + for (i = 0; i < nitems(voltages); i++) { + SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(node), OID_AUTO, + voltages[i].name, CTLTYPE_INT | CTLFLAG_RD, sc, + i, w83793g_voltage_sysctl, "I", + "voltage (millivolts)"); + } + node = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(root), OID_AUTO, "temp", + CTLFLAG_RD, NULL, NULL); + for (i = 0; i < WB_TEMP_COUNT; i++) { + /* Only supports single-digit sensors. */ + char name[sizeof("sensor_") + 1]; + + if (!temp_enabled(sc, i)) + continue; + snprintf(name, sizeof(name), "sensor_%d", i); + SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(node), OID_AUTO, name, + CTLTYPE_INT | CTLFLAG_RD, sc, WB_TD_BASE + i, + w83793g_temp_sysctl, "IK2", NULL); + } + node = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(root), OID_AUTO, "fans", + CTLFLAG_RD, NULL, NULL); + for (i = 0; i < WB_FAN_COUNT; i++) { + /* Supports up to 12 fans */ + char name[sizeof("fan_") + 2]; + + if (!fan_enabled(sc, i)) + continue; + snprintf(name, sizeof(name), "fan_%d", i); + SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(node), OID_AUTO, name, + CTLTYPE_INT | CTLFLAG_RD, sc, WB_FAN_BASE + i, + w83793g_fan_sysctl, "I", NULL); + } + SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(root), OID_AUTO, "chassis_open", + CTLTYPE_U8 | CTLFLAG_RD, sc, 0, w83793g_case_sysctl, "CU", + "report if the chassis_open was latched"); + return (0); +} + +static int +w83793g_detach(device_t dev) +{ + return (ENXIO); +} + +static int +w83793g_temp_sysctl(SYSCTL_HANDLER_ARGS) +{ + struct w83793g_softc *sc = arg1; + int reg = arg2; + int temp; + int error; + int8_t t_reg; + uint8_t t_low; + + error = w83793g_readreg(sc->sc_dev, reg, &t_reg); + if (error != 0) + return (error); + + if (reg < WB_TD_BASE + WB_TD_COUNT) { + error = w83793g_readreg(sc->sc_dev, WB_TLOW, &t_low); + if (error != 0) + return (error); + } else + t_low = 0; + + temp = (int)t_reg * 100; + temp += (t_low >> (2 * (reg - WB_TD_BASE)) & 0x3) * 25; + temp += 27315; /* Convert celsius to kelvin */ + + error = sysctl_handle_int(oidp, &temp, 0, req); + + return (error); +} + +static int +w83793g_fan_sysctl(SYSCTL_HANDLER_ARGS) +{ + struct w83793g_softc *sc = arg1; + int reg = arg2; + int count; + int error; + uint8_t reg_vals[2]; /* Fan count is 2 bytes */ + + error = iicdev_readfrom(sc->sc_dev, reg, reg_vals, sizeof(reg_vals), + IIC_WAIT); + if (error != 0) + return (error); + + count = ((int)reg_vals[0] << 8) | reg_vals[1]; + error = sysctl_handle_int(oidp, &count, 0, req); + + return (error); +} + +static int +w83793g_voltage_sysctl(SYSCTL_HANDLER_ARGS) +{ + struct w83793g_softc *sc = arg1; + const struct wb_vsens *sensor; + int index = arg2; + int volts; + int error; + uint8_t v_reg; + uint8_t v_low; + + sensor = &voltages[index]; + error = w83793g_readreg(sc->sc_dev, sensor->reg, &v_reg); + if (error != 0) + return (error); + + volts = v_reg; + if (sensor->left_low != 0) { + volts <<= 2; + error = w83793g_readreg(sc->sc_dev, WB_VLOW, &v_low); + if (error != 0) + return (error); + volts |= (v_low >> (sensor->left_low - 1) & 0x3); + } + + volts *= sensor->scale; + volts += sensor->add; + + error = sysctl_handle_int(oidp, &volts, 0, req); + + return (error); +} + +static int +w83793g_case_sysctl(SYSCTL_HANDLER_ARGS) +{ + struct w83793g_softc *sc = arg1; + int error; + uint8_t reg; + bool chassis; + + error = w83793g_readreg(sc->sc_dev, INT_STS4, ®); + if (error != 0) + return (error); + + chassis = ((reg & CHASSIS) != 0); + + return (sysctl_handle_bool(oidp, &chassis, 0, req)); +} diff --git a/sys/dev/iommu/busdma_iommu.c b/sys/dev/iommu/busdma_iommu.c index 82f73d469585..3852429c4a8a 100644 --- a/sys/dev/iommu/busdma_iommu.c +++ b/sys/dev/iommu/busdma_iommu.c @@ -117,17 +117,14 @@ iommu_bus_dma_is_dev_disabled(int domain, int bus, int slot, int func) int iommu_get_requester(device_t dev, device_t *requesterp, uint16_t *rid) { - devclass_t pci_class; device_t l, pci, pcib, pcip, pcibp, requester; int cap_offset; uint16_t pcie_flags; bool bridge_is_pcie; - pci_class = devclass_find("pci"); l = requester = dev; - pci = device_get_parent(dev); - if (pci == NULL || device_get_devclass(pci) != pci_class) { + if (!is_pci_device(dev)) { *rid = 0; /* XXXKIB: Could be ACPI HID */ *requesterp = NULL; return (ENOTTY); @@ -141,29 +138,18 @@ iommu_get_requester(device_t dev, device_t *requesterp, uint16_t *rid) * unit. */ for (;;) { - pci = device_get_parent(l); - if (pci == NULL) { + if (!is_pci_device(l)) { if (bootverbose) { printf( - "iommu_get_requester(%s): NULL parent for %s\n", + "iommu_get_requester(%s): non-pci ancestor %s\n", device_get_name(dev), device_get_name(l)); } *rid = 0; *requesterp = NULL; return (ENXIO); } - if (device_get_devclass(pci) != pci_class) { - if (bootverbose) { - printf( - "iommu_get_requester(%s): non-pci parent %s for %s\n", - device_get_name(dev), device_get_name(pci), - device_get_name(l)); - } - *rid = 0; - *requesterp = NULL; - return (ENXIO); - } + pci = device_get_parent(l); pcib = device_get_parent(pci); if (pcib == NULL) { if (bootverbose) { @@ -182,10 +168,8 @@ iommu_get_requester(device_t dev, device_t *requesterp, uint16_t *rid) * port, and the requester ID won't be translated * further. */ - pcip = device_get_parent(pcib); - if (device_get_devclass(pcip) != pci_class) + if (!is_pci_device(pcib)) break; - pcibp = device_get_parent(pcip); if (pci_find_cap(l, PCIY_EXPRESS, &cap_offset) == 0) { /* @@ -212,6 +196,8 @@ iommu_get_requester(device_t dev, device_t *requesterp, uint16_t *rid) * PCI bridge, then we know pcib is actually a * PCIe/PCI bridge. */ + pcip = device_get_parent(pcib); + pcibp = device_get_parent(pcip); if (!bridge_is_pcie && pci_find_cap(pcibp, PCIY_EXPRESS, &cap_offset) == 0) { pcie_flags = pci_read_config(pcibp, @@ -337,11 +323,9 @@ bool bus_dma_iommu_set_buswide(device_t dev) { struct iommu_unit *unit; - device_t parent; u_int busno, slot, func; - parent = device_get_parent(dev); - if (device_get_devclass(parent) != devclass_find("pci")) + if (!is_pci_device(dev)) return (false); unit = iommu_find(dev, bootverbose); if (unit == NULL) diff --git a/sys/dev/iwx/if_iwx.c b/sys/dev/iwx/if_iwx.c index 03ef775205e7..372fa440466c 100644 --- a/sys/dev/iwx/if_iwx.c +++ b/sys/dev/iwx/if_iwx.c @@ -433,7 +433,7 @@ static int iwx_rx_addbuf(struct iwx_softc *, int, int); static int iwx_rxmq_get_signal_strength(struct iwx_softc *, struct iwx_rx_mpdu_desc *); static void iwx_rx_rx_phy_cmd(struct iwx_softc *, struct iwx_rx_packet *, struct iwx_rx_data *); -static int iwx_get_noise(const struct iwx_statistics_rx_non_phy *); +static int iwx_get_noise(struct iwx_softc *, const struct iwx_statistics_rx_non_phy *); static int iwx_rx_hwdecrypt(struct iwx_softc *, struct mbuf *, uint32_t); #if 0 int iwx_ccmp_decap(struct iwx_softc *, struct mbuf *, @@ -4209,6 +4209,17 @@ iwx_rx_addbuf(struct iwx_softc *sc, int size, int idx) return 0; } +/* + * @brief Return a single signal strength for the given frame. + * + * The firmware communicates up an energy field which is the negative of + * the dBm value. Ie, the number is positive and it increases as the + * signal level decreases. + * + * Fetch the two values, map 0 (inactive antenna) to -256 dBm which is a + * very small number, negate a non-zero value so it's mapped into a dBm + * value, then choose the maximum value to return. + */ static int iwx_rxmq_get_signal_strength(struct iwx_softc *sc, struct iwx_rx_mpdu_desc *desc) @@ -4227,6 +4238,26 @@ iwx_rxmq_get_signal_strength(struct iwx_softc *sc, return MAX(energy_a, energy_b); } +/** + * @brief Calculate an RSSI from the given signal level and noise floor. + * + * This calculates an RSSI and clamps it at IWX_RSSI_MINIMUM at the lower level + * and IWX_RSSI_MAXIMUM at the upper level. + * + * All units are in dBm. + */ +static int +iwx_calculate_rssi(struct iwx_softc *sc, int ss, int nf) +{ + int rssi = (ss - nf); + if (rssi < IWX_RSSI_MINIMUM) + rssi = IWX_RSSI_MINIMUM; + else if (rssi > IWX_RSSI_MAXIMUM) + rssi = IWX_RSSI_MAXIMUM; + + return (rssi); +} + static int iwx_rxmq_get_chains(struct iwx_softc *sc, struct iwx_rx_mpdu_desc *desc) @@ -4254,12 +4285,18 @@ iwx_rx_rx_phy_cmd(struct iwx_softc *sc, struct iwx_rx_packet *pkt, } /* - * Retrieve the average noise (in dBm) among receivers. + * @brief Retrieve the average noise (in dBm) among receivers. + * + * Note: This routine calculates the noise floor sum incorrectly, as + * you can't just linearly add the logarithm based dB units together. + * + * If no noise floor is available then this routine will return -127. */ static int -iwx_get_noise(const struct iwx_statistics_rx_non_phy *stats) +iwx_get_noise(struct iwx_softc *sc, + const struct iwx_statistics_rx_non_phy *stats) { - int i, total, nbant, noise; + int i, total, nbant, noise, ret; total = nbant = noise = 0; for (i = 0; i < 3; i++) { @@ -4271,7 +4308,14 @@ iwx_get_noise(const struct iwx_statistics_rx_non_phy *stats) } /* There should be at least one antenna but check anyway. */ - return (nbant == 0) ? -127 : (total / nbant) - 107; + if (nbant == 0) + ret = -127; + else if (total == 0) + ret = -127; + else + ret = (total / nbant) - 127; + + return (ret); } #if 0 @@ -4669,9 +4713,8 @@ iwx_rx_mpdu_mq(struct iwx_softc *sc, struct mbuf *m, void *pktdata, phy_info = le16toh(desc->phy_info); + /* note: RSSI here is absolute signal strength, not relative */ rssi = iwx_rxmq_get_signal_strength(sc, desc); - rssi = (0 - IWX_MIN_DBM) + rssi; /* normalize */ - rssi = MIN(rssi, (IWX_MAX_DBM - IWX_MIN_DBM)); /* clip to max. 100% */ memset(&rxs, 0, sizeof(rxs)); rxs.r_flags |= IEEE80211_R_IEEE | IEEE80211_R_FREQ; @@ -4688,9 +4731,19 @@ iwx_rx_mpdu_mq(struct iwx_softc *sc, struct mbuf *m, void *pktdata, if (rxs.c_chain != 0) rxs.r_flags |= IEEE80211_R_C_CHAIN; - /* rssi is in 1/2db units */ - rxs.c_rssi = rssi * 2; - rxs.c_nf = sc->sc_noise; + /* noise floor is in 1dB units */ + if (sc->sc_noise < IWX_DEFAULT_NF) + /* + * For now choose /a/ default, net80211 expects nf to be passed + * in various places and older drivers fake NF values where + * needed. + */ + rxs.c_nf = IWX_DEFAULT_NF; + else + rxs.c_nf = sc->sc_noise; + + /* rssi is in 1/2db units relative to the noise floor */ + rxs.c_rssi = iwx_calculate_rssi(sc, rssi, rxs.c_nf) * 2; if (pad) { rxs.c_pktflags |= IEEE80211_RX_F_DECRYPTED; @@ -9142,11 +9195,16 @@ iwx_rx_pkt(struct iwx_softc *sc, struct iwx_rx_data *data, struct mbuf *ml) break; } + /* + * TODO: is this the right struct to use? Look at what + * mvm is doing for statistics notification (eg + * iwl_mvm_handle_rx_statistics() . + */ case IWX_STATISTICS_NOTIFICATION: { struct iwx_notif_statistics *stats; SYNC_RESP_STRUCT(stats, pkt); memcpy(&sc->sc_stats, stats, sizeof(sc->sc_stats)); - sc->sc_noise = iwx_get_noise(&stats->rx.general); + sc->sc_noise = iwx_get_noise(sc, &stats->rx.general); break; } @@ -10587,6 +10645,9 @@ iwx_attach(device_t dev) mbufq_init(&rxba->entries[j].frames, ifqmaxlen); } + /* Initialize to something to have a chance to get S:N values. */ + sc->sc_noise = IWX_DEFAULT_NF; + sc->sc_preinit_hook.ich_func = iwx_attach_hook; sc->sc_preinit_hook.ich_arg = sc; if (config_intrhook_establish(&sc->sc_preinit_hook) != 0) { diff --git a/sys/dev/iwx/if_iwxreg.h b/sys/dev/iwx/if_iwxreg.h index f3d1f078b48e..3f161b627a5f 100644 --- a/sys/dev/iwx/if_iwxreg.h +++ b/sys/dev/iwx/if_iwxreg.h @@ -7902,6 +7902,23 @@ iwx_rx_packet_payload_len(const struct iwx_rx_packet *pkt) #define IWX_MIN_DBM -100 #define IWX_MAX_DBM -33 /* realistic guess */ +/* + * NF values for various channel widths at 20C + * + * 20MHz - -98 dBm + * 40MHz - -94 dBm + * 80MHz - -92 dBm + * 160MHz - -88 dBm + * 320MHz - -85 dBm + */ +#define IWX_DEFAULT_NF -100 +/* + * Note; RSSI is for net80211, and it's calculated against the noise floor + * as a reference. + */ +#define IWX_RSSI_MINIMUM -10 +#define IWX_RSSI_MAXIMUM 60 + #define IWX_READ(sc, reg) \ bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) diff --git a/sys/dev/mii/miidevs b/sys/dev/mii/miidevs index ca7e78a1cdd5..89d8e54a1843 100644 --- a/sys/dev/mii/miidevs +++ b/sys/dev/mii/miidevs @@ -72,7 +72,7 @@ oui RDC 0x00d02d RDC Semiconductor oui REALTEK 0x00e04c Realtek Semicondctor oui SEEQ 0x00a07d Seeq Technology oui SIS 0x00e006 Silicon Integrated Systems -oui SMC 0x00800f SMC +oui SMSC 0x00800f Microchip (formerly SMSC) oui TI 0x080028 Texas Instruments oui TSC 0x00c039 TDK Semiconductor oui VITESSE 0x0001c1 Vitesse Semiconductor @@ -361,6 +361,6 @@ model xxVITESSE VSC8514 0x0027 Vitesse VSC8514 10/100/1000TX PHY /* XaQti Corp. PHYs */ model xxXAQTI XMACII 0x0000 XaQti Corp. XMAC II gigabit interface -/* SMC */ -model SMC LAN8710A 0x000F SMC LAN8710A 10/100 interface -model SMC LAN8700 0x000C SMC LAN8700 10/100 interface +/* Microchip (formerly SMSC) */ +model SMSC LAN8710A 0x000F Microchip LAN8710A 10/100 interface +model SMSC LAN8700 0x000C Microchip LAN8700 10/100 interface diff --git a/sys/dev/mii/smscphy.c b/sys/dev/mii/smscphy.c index 4e0d3cd3e18e..d578242f5a61 100644 --- a/sys/dev/mii/smscphy.c +++ b/sys/dev/mii/smscphy.c @@ -74,8 +74,8 @@ static driver_t smscphy_driver = { DRIVER_MODULE(smscphy, miibus, smscphy_driver, 0, 0); static const struct mii_phydesc smscphys[] = { - MII_PHY_DESC(SMC, LAN8710A), - MII_PHY_DESC(SMC, LAN8700), + MII_PHY_DESC(SMSC, LAN8710A), + MII_PHY_DESC(SMSC, LAN8700), MII_PHY_END }; diff --git a/sys/dev/mlx5/mlx5_en/mlx5_en_hw_tls_rx.c b/sys/dev/mlx5/mlx5_en/mlx5_en_hw_tls_rx.c index 89d2010656c5..b6a9a0c01d09 100644 --- a/sys/dev/mlx5/mlx5_en/mlx5_en_hw_tls_rx.c +++ b/sys/dev/mlx5/mlx5_en/mlx5_en_hw_tls_rx.c @@ -596,14 +596,21 @@ mlx5e_tls_rx_work(struct work_struct *work) if (ptag->flow_rule != NULL) mlx5e_accel_fs_del_inpcb(ptag->flow_rule); + /* + * Destroy TIR before DEK. DESTROY_TIR for a TLS- + * enabled TIR issues a TRA RX fence that drains all + * in-flight packets from the crypto pipeline. If the + * DEK were destroyed first, packets still in flight + * would hit a TPT encryption error (vendor syndrome + * 0x55) because the key they reference is already gone. + */ + if (ptag->tirn != 0) + mlx5_tls_close_tir(priv->mdev, ptag->tirn); + /* try to destroy DEK context by ID */ if (ptag->dek_index_ok) mlx5_encryption_key_destroy(priv->mdev, ptag->dek_index); - /* try to destroy TIR context by ID */ - if (ptag->tirn != 0) - mlx5_tls_close_tir(priv->mdev, ptag->tirn); - /* free tag */ mlx5e_tls_rx_tag_zfree(ptag); break; diff --git a/sys/dev/mlx5/mlx5_en/mlx5_en_main.c b/sys/dev/mlx5/mlx5_en/mlx5_en_main.c index 9bcb0dcf8e16..fb8b79c8f787 100644 --- a/sys/dev/mlx5/mlx5_en/mlx5_en_main.c +++ b/sys/dev/mlx5/mlx5_en/mlx5_en_main.c @@ -1135,25 +1135,6 @@ mlx5e_hw_clock(struct mlx5e_priv *priv) } /* - * Seed the first calibration point so that base_prev and clbr_hw_prev - * are always valid. Called once during attach before the first - * calibration callout fires. - */ -static void -mlx5e_seed_calibration(struct mlx5e_priv *priv) -{ - struct mlx5e_clbr_point *cp; - struct timespec ts; - - cp = &priv->clbr_points[0]; - cp->clbr_hw_curr = mlx5e_hw_clock(priv); - nanouptime(&ts); - cp->base_curr = mlx5e_timespec2usec(&ts); - cp->clbr_hw_prev = cp->clbr_hw_curr - 1; - cp->base_prev = cp->base_curr - 1; -} - -/* * The calibration callout, it runs either in the context of the * thread which enables calibration, or in callout. It takes the * snapshot of system and adapter clocks, then advances the pointers to @@ -1166,9 +1147,6 @@ mlx5e_calibration_callout(void *arg) struct mlx5e_priv *priv; struct mlx5e_clbr_point *next, *curr; struct timespec ts; - uint64_t hw_delta_new, hw_delta_old; - uint64_t old_nsec, old_projected, old_sec; - uint64_t res_n, res_s, res_s_mod, rt_delta_old; int clbr_curr_next; priv = arg; @@ -1197,33 +1175,6 @@ mlx5e_calibration_callout(void *arg) nanouptime(&ts); next->base_curr = mlx5e_timespec2usec(&ts); - /* - * Ensure monotonicity across calibration transitions. Compute - * what the old calibration would extrapolate to at the new - * hw_curr. If the new base_curr is less, clamp it so the new - * slope is at least as steep as the old one. This prevents - * packets from seeing time go backwards when the slope drops. - * - * Use the same split-seconds technique as mlx5e_mbuf_tstmp() - * to avoid overflowing uint64_t in the multiplication. - */ - hw_delta_new = next->clbr_hw_curr - curr->clbr_hw_curr; - rt_delta_old = curr->base_curr - curr->base_prev; - hw_delta_old = curr->clbr_hw_curr - curr->clbr_hw_prev; - old_sec = hw_delta_new / priv->cclk; - old_nsec = hw_delta_new % priv->cclk; - res_s = old_sec * rt_delta_old; - res_n = old_nsec * rt_delta_old; - res_s_mod = res_s % hw_delta_old; - res_s /= hw_delta_old; - res_s_mod *= priv->cclk; - res_n += res_s_mod; - res_n /= hw_delta_old; - res_s *= priv->cclk; - old_projected = curr->base_curr + res_s + res_n; - if (next->base_curr < old_projected) - next->base_curr = old_projected; - curr->clbr_gen = 0; atomic_thread_fence_rel(); priv->clbr_curr = clbr_curr_next; @@ -4936,7 +4887,6 @@ mlx5e_create_ifp(struct mlx5_core_dev *mdev) callout_init(&priv->tstmp_clbr, 1); /* Pull out the frequency of the clock in hz */ priv->cclk = (uint64_t)MLX5_CAP_GEN(mdev, device_frequency_khz) * 1000ULL; - mlx5e_seed_calibration(priv); mlx5e_reset_calibration_callout(priv); pa.pa_version = PFIL_VERSION; diff --git a/sys/dev/mwl/if_mwl.c b/sys/dev/mwl/if_mwl.c index 513c3d9c60e4..b7f85e65cfd9 100644 --- a/sys/dev/mwl/if_mwl.c +++ b/sys/dev/mwl/if_mwl.c @@ -129,7 +129,7 @@ static struct ieee80211_node *mwl_node_alloc(struct ieee80211vap *, static void mwl_node_cleanup(struct ieee80211_node *); static void mwl_node_drain(struct ieee80211_node *); static void mwl_node_getsignal(const struct ieee80211_node *, - int8_t *, int8_t *); + net80211_rssi_t *, int8_t *); static void mwl_node_getmimoinfo(const struct ieee80211_node *, struct ieee80211_mimo_info *); static int mwl_rxbuf_init(struct mwl_softc *, struct mwl_rxbuf *); @@ -2390,7 +2390,7 @@ mwl_node_drain(struct ieee80211_node *ni) } static void -mwl_node_getsignal(const struct ieee80211_node *ni, int8_t *rssi, int8_t *noise) +mwl_node_getsignal(const struct ieee80211_node *ni, net80211_rssi_t *rssi, int8_t *noise) { *rssi = ni->ni_ic->ic_node_getrssi(ni); #ifdef MWL_ANT_INFO_SUPPORT diff --git a/sys/dev/netmap/netmap_freebsd.c b/sys/dev/netmap/netmap_freebsd.c index 9fb4370129f3..2241bfc970a6 100644 --- a/sys/dev/netmap/netmap_freebsd.c +++ b/sys/dev/netmap/netmap_freebsd.c @@ -119,6 +119,7 @@ nm_os_selinfo_uninit(NM_SELINFO_T *si) taskqueue_drain(si->ntfytq, &si->ntfytask); taskqueue_free(si->ntfytq); si->ntfytq = NULL; + seldrain(&si->si); knlist_delete(&si->si.si_note, curthread, /*islocked=*/0); knlist_destroy(&si->si.si_note); /* now we don't need the mutex anymore */ diff --git a/sys/dev/nvme/nvme_sim.c b/sys/dev/nvme/nvme_sim.c index b9f09c8d1f61..a6ba1a498185 100644 --- a/sys/dev/nvme/nvme_sim.c +++ b/sys/dev/nvme/nvme_sim.c @@ -208,7 +208,7 @@ nvme_sim_action(struct cam_sim *sim, union ccb *ccb) cpi->xport_specific.nvme.bus = pci_get_bus(dev); cpi->xport_specific.nvme.slot = pci_get_slot(dev); cpi->xport_specific.nvme.function = pci_get_function(dev); - cpi->xport_specific.nvme.progif = pci_get_progif(dev); + cpi->xport_specific.nvme.extra = 0; strlcpy(cpi->xport_specific.nvme.dev_name, device_get_nameunit(dev), sizeof(cpi->xport_specific.nvme.dev_name)); cpi->hba_vendor = pci_get_vendor(dev); @@ -314,13 +314,6 @@ nvme_sim_probe(device_t dev) { if (nvme_use_nvd) return (ENXIO); - /* - * Only do storage devices with CAM. NVMHCI 1.0 interfaces are the only - * ones that have namespaces with LBA ranges on them. - */ - if (pci_get_progif(device_get_parent(dev)) != - PCIP_STORAGE_NVM_ENTERPRISE_NVMHCI_1_0) - return (ENXIO); device_set_desc(dev, "nvme cam"); return (BUS_PROBE_DEFAULT); diff --git a/sys/dev/pci/pci.c b/sys/dev/pci/pci.c index 0dddd2dd263f..034f34e2dde2 100644 --- a/sys/dev/pci/pci.c +++ b/sys/dev/pci/pci.c @@ -3756,7 +3756,7 @@ xhci_early_takeover(device_t self) struct resource *res; uint32_t cparams; uint32_t eec; - uint8_t eecp; + uint32_t eecp; uint8_t bios_sem; uint8_t offs; int rid; @@ -6535,11 +6535,9 @@ device_t pci_find_pcie_root_port(device_t dev) { struct pci_devinfo *dinfo; - devclass_t pci_class; device_t pcib, bus; - pci_class = devclass_find("pci"); - KASSERT(device_get_devclass(device_get_parent(dev)) == pci_class, + KASSERT(is_pci_device(dev), ("%s: non-pci device %s", __func__, device_get_nameunit(dev))); /* @@ -6555,11 +6553,7 @@ pci_find_pcie_root_port(device_t dev) KASSERT(pcib != NULL, ("%s: null bridge of %s", __func__, device_get_nameunit(bus))); - /* - * pcib's parent must be a PCI bus for this to be a - * PCI-PCI bridge. - */ - if (device_get_devclass(device_get_parent(pcib)) != pci_class) + if (!is_pci_device(pcib)) return (NULL); dinfo = device_get_ivars(pcib); @@ -6993,6 +6987,17 @@ pci_print_faulted_dev(void) } } +bool +is_pci_device(device_t dev) +{ + devclass_t pci_class; + + if (device_get_parent(dev) == NULL) + return (false); + pci_class = devclass_find("pci"); + return (device_get_devclass(device_get_parent(dev)) == pci_class); +} + #ifdef DDB DB_SHOW_COMMAND_FLAGS(pcierr, pci_print_faulted_dev_db, DB_CMD_MEMSAFE) { diff --git a/sys/dev/pci/pcivar.h b/sys/dev/pci/pcivar.h index 696e1c688c68..bcd4d2d35b54 100644 --- a/sys/dev/pci/pcivar.h +++ b/sys/dev/pci/pcivar.h @@ -676,6 +676,7 @@ pci_child_added(device_t dev) return (PCI_CHILD_ADDED(device_get_parent(dev), dev)); } +bool is_pci_device(device_t dev); device_t pci_find_bsf(uint8_t, uint8_t, uint8_t); device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t); device_t pci_find_device(uint16_t, uint16_t); diff --git a/sys/dev/pci/vga_pci.c b/sys/dev/pci/vga_pci.c index 39b2fcab67b4..72c93e201d96 100644 --- a/sys/dev/pci/vga_pci.c +++ b/sys/dev/pci/vga_pci.c @@ -111,8 +111,7 @@ vga_pci_is_boot_display(device_t dev) */ pcib = device_get_parent(device_get_parent(dev)); - if (device_get_devclass(device_get_parent(pcib)) == - devclass_find("pci")) { + if (is_pci_device(pcib)) { /* * The parent bridge is a PCI-to-PCI bridge: check the * value of the "VGA Enable" bit. @@ -186,8 +185,7 @@ vga_pci_map_bios(device_t dev, size_t *size) #endif pcib = device_get_parent(device_get_parent(dev)); - if (device_get_devclass(device_get_parent(pcib)) == - devclass_find("pci")) { + if (is_pci_device(pcib)) { /* * The parent bridge is a PCI-to-PCI bridge: check the * value of the "VGA Enable" bit. diff --git a/sys/dev/psci/psci.c b/sys/dev/psci/psci.c index 2b250401ae83..872fae056a4b 100644 --- a/sys/dev/psci/psci.c +++ b/sys/dev/psci/psci.c @@ -133,7 +133,7 @@ static int psci_def_callfn(register_t, register_t, register_t, register_t, psci_callfn_t psci_callfn = psci_def_callfn; -static void +void psci_init(void *dummy) { psci_callfn_t new_callfn; @@ -146,8 +146,11 @@ psci_init(void *dummy) psci_callfn = new_callfn; psci_present = true; } + +#ifdef __arm__ /* This needs to be before cpu_mp at SI_SUB_CPU, SI_ORDER_THIRD */ SYSINIT(psci_start, SI_SUB_CPU, SI_ORDER_FIRST, psci_init, NULL); +#endif static int psci_def_callfn(register_t a __unused, register_t b __unused, @@ -631,3 +634,9 @@ psci_v0_2_init(device_t dev, int default_version) device_printf(dev, "PSCI version number mismatched with DT\n"); return (1); } + +bool +psci_conduit_is_smc(void) +{ + return (psci_callfn == arm_smccc_smc); +} diff --git a/sys/dev/psci/psci.h b/sys/dev/psci/psci.h index 6704eaf26c71..c250bf45d344 100644 --- a/sys/dev/psci/psci.h +++ b/sys/dev/psci/psci.h @@ -44,6 +44,9 @@ void psci_reset(void); int32_t psci_features(uint32_t); int psci_get_version(void); +void psci_init(void *dummy); +bool psci_conduit_is_smc(void); + /* Handler to let us call into the PSCI/SMCCC firmware */ extern psci_callfn_t psci_callfn; static inline int diff --git a/sys/dev/qcom_tlmm/qcom_tlmm.c b/sys/dev/qcom_tlmm/qcom_tlmm.c index 3581e651fd59..5b2c11941d50 100644 --- a/sys/dev/qcom_tlmm/qcom_tlmm.c +++ b/sys/dev/qcom_tlmm/qcom_tlmm.c @@ -90,7 +90,6 @@ qcom_tlmm_probe(device_t dev) for (i = 0; qcom_tlmm_chipsets[i].id != 0; i++) { ql = &qcom_tlmm_chipsets[i]; - device_printf(dev, "%s: checking %s\n", __func__, ql->ofw_str); if (ofw_bus_is_compatible(dev, ql->ofw_str) == 1) { sc->sc_chipset = ql->id; sc->sc_attach_func = ql->attach_func; diff --git a/sys/dev/rge/if_rge.c b/sys/dev/rge/if_rge.c index 8887e8d39ae4..06f034ebd61d 100644 --- a/sys/dev/rge/if_rge.c +++ b/sys/dev/rge/if_rge.c @@ -113,6 +113,7 @@ struct rge_matchid { const struct rge_matchid rge_devices[] = { { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_E3000, "Killer E3000" }, + { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_E5000, "Killer E5000" }, { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RTL8125, "RTL8125" }, { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RTL8126, "RTL8126", }, { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RTL8127, "RTL8127" }, diff --git a/sys/dev/rge/if_rge_vendor.h b/sys/dev/rge/if_rge_vendor.h index eea94e39e20b..f80b99f1f8b6 100644 --- a/sys/dev/rge/if_rge_vendor.h +++ b/sys/dev/rge/if_rge_vendor.h @@ -21,6 +21,7 @@ #define PCI_VENDOR_REALTEK 0x10ec #define PCI_PRODUCT_REALTEK_E3000 0x3000 +#define PCI_PRODUCT_REALTEK_E5000 0x5000 #define PCI_PRODUCT_REALTEK_RTL8125 0x8125 #define PCI_PRODUCT_REALTEK_RTL8126 0x8126 #define PCI_PRODUCT_REALTEK_RTL8127 0x8127 diff --git a/sys/dev/rtwn/usb/rtwn_usb_attach.h b/sys/dev/rtwn/usb/rtwn_usb_attach.h index cd5485b36678..ca12480c8f19 100644 --- a/sys/dev/rtwn/usb/rtwn_usb_attach.h +++ b/sys/dev/rtwn/usb/rtwn_usb_attach.h @@ -117,6 +117,7 @@ static const STRUCT_USB_HOST_ID rtwn_devs[] = { { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, RTWN_CHIP_RTL8188EU) } RTWN_RTL8188EU_DEV(ABOCOM, RTL8188EU), RTWN_RTL8188EU_DEV(ASUS, USBN10NANOB1), + RTWN_RTL8188EU_DEV(DLINK, DWA121B1), RTWN_RTL8188EU_DEV(DLINK, DWA123D1), RTWN_RTL8188EU_DEV(DLINK, DWA125D1), RTWN_RTL8188EU_DEV(EDIMAX, EW7811UN_V2), diff --git a/sys/dev/smartpqi/smartpqi_cam.c b/sys/dev/smartpqi/smartpqi_cam.c index 690b38c9f855..6ded8aa97e39 100644 --- a/sys/dev/smartpqi/smartpqi_cam.c +++ b/sys/dev/smartpqi/smartpqi_cam.c @@ -1,5 +1,5 @@ /*- - * Copyright 2016-2025 Microchip Technology, Inc. and/or its subsidiaries. + * Copyright 2016-2026 Microchip Technology, Inc. and/or its subsidiaries. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -1300,7 +1300,7 @@ register_sim(struct pqisrc_softstate *softs, int card_index) csa.callback_arg = softs; xpt_action((union ccb *)&csa); if (csa.ccb_h.status != CAM_REQ_CMP) { - DBG_ERR("Unable to register smartpqi_aysnc handler: %d!\n", + DBG_ERR("Unable to register smartpqi_async handler: %d!\n", csa.ccb_h.status); } diff --git a/sys/dev/smartpqi/smartpqi_defines.h b/sys/dev/smartpqi/smartpqi_defines.h index 0277abd3e318..c4084f069588 100644 --- a/sys/dev/smartpqi/smartpqi_defines.h +++ b/sys/dev/smartpqi/smartpqi_defines.h @@ -1,5 +1,5 @@ /*- - * Copyright 2016-2025 Microchip Technology, Inc. and/or its subsidiaries. + * Copyright 2016-2026 Microchip Technology, Inc. and/or its subsidiaries. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -944,12 +944,12 @@ typedef uint8_t *passthru_buf_type_t; #define PQISRC_DRIVER_MAJOR __FreeBSD__ #if __FreeBSD__ <= 14 -#define PQISRC_DRIVER_MINOR 4690 +#define PQISRC_DRIVER_MINOR 4691 #else #define PQISRC_DRIVER_MINOR 2 #endif -#define PQISRC_DRIVER_RELEASE 0 -#define PQISRC_DRIVER_REVISION 2008 +#define PQISRC_DRIVER_RELEASE 1 +#define PQISRC_DRIVER_REVISION 2000 #define STR(s) # s #define PQISRC_VERSION(a, b, c, d) STR(a.b.c-d) diff --git a/sys/dev/smartpqi/smartpqi_discovery.c b/sys/dev/smartpqi/smartpqi_discovery.c index a7de5a149810..8682e6cabd7e 100644 --- a/sys/dev/smartpqi/smartpqi_discovery.c +++ b/sys/dev/smartpqi/smartpqi_discovery.c @@ -1,5 +1,5 @@ /*- - * Copyright 2016-2025 Microchip Technology, Inc. and/or its subsidiaries. + * Copyright 2016-2026 Microchip Technology, Inc. and/or its subsidiaries. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -155,7 +155,7 @@ pqisrc_remove_target_bit(pqisrc_softstate_t *softs, int target) softs->bit_map.bit_vector[target] = SLOT_AVAILABLE; } -/* Use bit map to find availible targets */ +/* Use bit map to find available targets */ int pqisrc_find_avail_target(pqisrc_softstate_t *softs) { @@ -1423,7 +1423,11 @@ pqisrc_add_device(pqisrc_softstate_t *softs, pqi_scsi_dev_t *device) if(device->expose_device) { pqisrc_init_device_active_io(softs, device); - /* TBD: Call OS upper layer function to add the device entry */ + device_printf(softs->os_specific.pqi_dev, + "device added: vendor=%s model=%s B%d:T%d:L%d type=%s\n", + device->vendor, device->model, + device->bus, device->target, device->lun, + device->is_physical_device ? "physical" : "logical"); os_add_device(softs,device); } DBG_FUNC("OUT\n"); @@ -1451,6 +1455,11 @@ pqisrc_remove_device(pqisrc_softstate_t *softs, pqi_scsi_dev_t *device) } /* Wait for device outstanding Io's */ pqisrc_wait_for_device_commands_to_complete(softs, device); + device_printf(softs->os_specific.pqi_dev, + "device removed: vendor=%s model=%s B%d:T%d:L%d type=%s\n", + device->vendor, device->model, + device->bus, device->target, device->lun, + device->is_physical_device ? "physical" : "logical"); /* Call OS upper layer function to remove the exposed device entry */ os_remove_device(softs,device); DBG_FUNC("OUT\n"); @@ -1674,10 +1683,14 @@ pqisrc_update_device_list(pqisrc_softstate_t *softs, case DEVICE_NOT_FOUND: /* Device not found in existing list */ device->new_device = true; + DBG_DISC("new device found B%d:T%d:L%d\n", + device->bus, device->target, device->lun); break; case DEVICE_CHANGED: /* Actual device gone need to add device to list*/ device->new_device = true; + DBG_DISC("device changed B%d:T%d:L%d\n", + device->bus, device->target, device->lun); break; case DEVICE_IN_REMOVE: /*Older device with same target/lun is in removal stage*/ @@ -1686,6 +1699,8 @@ pqisrc_update_device_list(pqisrc_softstate_t *softs, * free call*/ device->new_device = false; same_device->schedule_rescan = true; + DBG_DISC("device in removal B%d:T%d:L%d, scheduling rescan\n", + device->bus, device->target, device->lun); break; default: break; diff --git a/sys/dev/smartpqi/smartpqi_event.c b/sys/dev/smartpqi/smartpqi_event.c index 77a70f9fb031..c3c27c9e1c0b 100644 --- a/sys/dev/smartpqi/smartpqi_event.c +++ b/sys/dev/smartpqi/smartpqi_event.c @@ -1,5 +1,5 @@ /*- - * Copyright 2016-2025 Microchip Technology, Inc. and/or its subsidiaries. + * Copyright 2016-2026 Microchip Technology, Inc. and/or its subsidiaries. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -204,6 +204,17 @@ pqisrc_process_event_intr_src(pqisrc_softstate_t *softs,int obq_id) } if (event_index >= 0) { + static const char *event_names[] = { + [PQI_EVENT_HOTPLUG] = "hotplug", + [PQI_EVENT_HARDWARE] = "hardware", + [PQI_EVENT_PHYSICAL_DEVICE] = "physical device", + [PQI_EVENT_LOGICAL_DEVICE] = "logical device", + [PQI_EVENT_AIO_STATE_CHANGE] = "AIO state change", + [PQI_EVENT_AIO_CONFIG_CHANGE] = "AIO config change", + }; + device_printf(softs->os_specific.pqi_dev, + "event: %s (type=0x%x)\n", + event_names[event_index], response.event_type); if(response.request_acknowledge) { pending_event = &softs->pending_events[event_index]; pending_event->pending = true; @@ -385,7 +396,7 @@ pqisrc_report_event_config(pqisrc_softstate_t *softs) pqi_event_config_request_t request; pqi_event_config_t *event_config_p ; dma_mem_t buf_report_event ; - /*bytes to be allocaed for report event config data-in buffer */ + /*bytes to be allocated for report event config data-in buffer */ uint32_t alloc_size = sizeof(pqi_event_config_t) ; memset(&request, 0 , sizeof(request)); @@ -446,7 +457,7 @@ pqisrc_set_event_config(pqisrc_softstate_t *softs) pqi_event_config_request_t request; pqi_event_config_t *event_config_p; dma_mem_t buf_set_event; - /*bytes to be allocaed for set event config data-out buffer */ + /*bytes to be allocated for set event config data-out buffer */ uint32_t alloc_size = sizeof(pqi_event_config_t); memset(&request, 0 , sizeof(request)); diff --git a/sys/dev/smartpqi/smartpqi_main.c b/sys/dev/smartpqi/smartpqi_main.c index 1f006939bf7c..fbfbcc962f35 100644 --- a/sys/dev/smartpqi/smartpqi_main.c +++ b/sys/dev/smartpqi/smartpqi_main.c @@ -1,5 +1,5 @@ /*- - * Copyright 2016-2025 Microchip Technology, Inc. and/or its subsidiaries. + * Copyright 2016-2026 Microchip Technology, Inc. and/or its subsidiaries. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -427,6 +427,16 @@ smartpqi_attach(device_t dev) goto out; } + /* Register sysctl for runtime debug_level changes */ + { + struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); + struct sysctl_oid *tree = device_get_sysctl_tree(dev); + + SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, + "debug_level", CTLFLAG_RW, &logging_level, + "Debug logging bitmask"); + } + goto out; dma_out: diff --git a/sys/dev/smartpqi/smartpqi_misc.c b/sys/dev/smartpqi/smartpqi_misc.c index 6db0d80ed993..fd0b907aa252 100644 --- a/sys/dev/smartpqi/smartpqi_misc.c +++ b/sys/dev/smartpqi/smartpqi_misc.c @@ -1,5 +1,5 @@ /*- - * Copyright 2016-2025 Microchip Technology, Inc. and/or its subsidiaries. + * Copyright 2016-2026 Microchip Technology, Inc. and/or its subsidiaries. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -252,7 +252,7 @@ bsd_set_hint_scatter_gather_config(struct pqisrc_softstate *softs) DBG_FUNC("IN\n"); - /* At least > 16 sg's required to wotk hint correctly. + /* At least > 16 sg's required to work hint correctly. * Default the sg count set by driver/controller. */ if ((!softs->hint.sg_segments) || (softs->hint.sg_segments > diff --git a/sys/dev/smartpqi/smartpqi_queue.c b/sys/dev/smartpqi/smartpqi_queue.c index e8a467531aa4..679d956f6f36 100644 --- a/sys/dev/smartpqi/smartpqi_queue.c +++ b/sys/dev/smartpqi/smartpqi_queue.c @@ -1,5 +1,5 @@ /*- - * Copyright 2016-2025 Microchip Technology, Inc. and/or its subsidiaries. + * Copyright 2016-2026 Microchip Technology, Inc. and/or its subsidiaries. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -729,7 +729,7 @@ pqisrc_create_op_ibq(pqisrc_softstate_t *softs, op_ib_q->pi_register_offset); } else { int i = 0; - DBG_WARN("Error Status Decsriptors\n"); + DBG_WARN("Error Status Descriptors\n"); for (i = 0; i < 4; i++) DBG_WARN(" %x\n",admin_resp.resp_type.create_op_iq.status_desc[i]); } diff --git a/sys/dev/smartpqi/smartpqi_request.c b/sys/dev/smartpqi/smartpqi_request.c index c5f8ac3c41ba..655660615797 100644 --- a/sys/dev/smartpqi/smartpqi_request.c +++ b/sys/dev/smartpqi/smartpqi_request.c @@ -1,5 +1,5 @@ /*- - * Copyright 2016-2025 Microchip Technology, Inc. and/or its subsidiaries. + * Copyright 2016-2026 Microchip Technology, Inc. and/or its subsidiaries. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -1998,7 +1998,7 @@ pqisrc_send_raid_tmf(pqisrc_softstate_t *softs, pqi_scsi_dev_t const *devp, if (softs->timeout_in_tmf && tmf_type == SOP_TASK_MANAGEMENT_LUN_RESET) { - /* OS_TMF_TIMEOUT_SEC - 1 to accomodate driver processing */ + /* OS_TMF_TIMEOUT_SEC - 1 to accommodate driver processing */ tmf_req.timeout_in_sec = OS_TMF_TIMEOUT_SEC - 1; } diff --git a/sys/dev/smartpqi/smartpqi_response.c b/sys/dev/smartpqi/smartpqi_response.c index 38695860e520..1ae74a5b95ff 100644 --- a/sys/dev/smartpqi/smartpqi_response.c +++ b/sys/dev/smartpqi/smartpqi_response.c @@ -1,5 +1,5 @@ /*- - * Copyright 2016-2025 Microchip Technology, Inc. and/or its subsidiaries. + * Copyright 2016-2026 Microchip Technology, Inc. and/or its subsidiaries. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -275,7 +275,7 @@ pqisrc_is_innocuous_error(pqisrc_softstate_t *softs, rcb_t *rcb, void *err_info) if (raid_err->data_out_result == PQI_RAID_DATA_IN_OUT_UNDERFLOW) return true; - /* We get these a alot: leave a tiny breadcrumb about the error, + /* We get these a lot: leave a tiny breadcrumb about the error, but don't do full spew about it */ if (raid_err->status == PQI_AIO_STATUS_CHECK_CONDITION) { diff --git a/sys/dev/smartpqi/smartpqi_sis.c b/sys/dev/smartpqi/smartpqi_sis.c index 82eb999ca4b8..99aa952eb149 100644 --- a/sys/dev/smartpqi/smartpqi_sis.c +++ b/sys/dev/smartpqi/smartpqi_sis.c @@ -1,5 +1,5 @@ /*- - * Copyright 2016-2025 Microchip Technology, Inc. and/or its subsidiaries. + * Copyright 2016-2026 Microchip Technology, Inc. and/or its subsidiaries. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -26,7 +26,7 @@ #include "smartpqi_includes.h" -/* Function for disabling msix interrupots */ +/* Function for disabling msix interrupts */ void sis_disable_msix(pqisrc_softstate_t *softs) { @@ -96,7 +96,7 @@ sis_disable_interrupt(pqisrc_softstate_t *softs) sis_disable_msix(softs); break; default: - DBG_ERR("Inerrupt mode none!\n"); + DBG_ERR("Interrupt mode none!\n"); break; } diff --git a/sys/dev/smartpqi/smartpqi_structures.h b/sys/dev/smartpqi/smartpqi_structures.h index 0c9ad375823d..ada6676ada8f 100644 --- a/sys/dev/smartpqi/smartpqi_structures.h +++ b/sys/dev/smartpqi/smartpqi_structures.h @@ -1,5 +1,5 @@ /*- - * Copyright 2016-2025 Microchip Technology, Inc. and/or its subsidiaries. + * Copyright 2016-2026 Microchip Technology, Inc. and/or its subsidiaries. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -1168,7 +1168,7 @@ typedef struct bmic_sense_feature_page_header { uint8_t page; uint8_t sub_page; uint16_t total_length; /** Total length of the page. - * The length is the same wheteher the request buffer is too short or not. + * The length is the same whether the request buffer is too short or not. * When printing out the page, only print the buffer length. */ } OS_ATTRIBUTE_PACKED bmic_sense_feature_page_header_t; diff --git a/sys/dev/sound/macio/onyx.c b/sys/dev/sound/macio/onyx.c index f4f825a705cc..5ba22dd7c495 100644 --- a/sys/dev/sound/macio/onyx.c +++ b/sys/dev/sound/macio/onyx.c @@ -268,38 +268,21 @@ static int onyx_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right) { struct onyx_softc *sc; - struct mtx *mixer_lock; - int locked; uint8_t l, r; sc = device_get_softc(mix_getdevinfo(m)); - mixer_lock = mixer_get_lock(m); - locked = mtx_owned(mixer_lock); switch (dev) { case SOUND_MIXER_VOLUME: - - /* - * We need to unlock the mixer lock because iicbus_transfer() - * may sleep. The mixer lock itself is unnecessary here - * because it is meant to serialize hardware access, which - * is taken care of by the I2C layer, so this is safe. - */ if (left > 100 || right > 100) return (0); l = left + 128; r = right + 128; - if (locked) - mtx_unlock(mixer_lock); - onyx_write(sc, PCM3052_REG_LEFT_ATTN, l); onyx_write(sc, PCM3052_REG_RIGHT_ATTN, r); - if (locked) - mtx_lock(mixer_lock); - return (left | (right << 8)); } diff --git a/sys/dev/sound/macio/snapper.c b/sys/dev/sound/macio/snapper.c index f14009f447a8..ed83990d563b 100644 --- a/sys/dev/sound/macio/snapper.c +++ b/sys/dev/sound/macio/snapper.c @@ -436,14 +436,10 @@ static int snapper_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right) { struct snapper_softc *sc; - struct mtx *mixer_lock; - int locked; u_int l, r; u_char reg[6]; sc = device_get_softc(mix_getdevinfo(m)); - mixer_lock = mixer_get_lock(m); - locked = mtx_owned(mixer_lock); if (left > 100 || right > 100) return (0); @@ -460,21 +456,8 @@ snapper_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right) reg[4] = (r & 0x00ff00) >> 8; reg[5] = r & 0x0000ff; - /* - * We need to unlock the mixer lock because iicbus_transfer() - * may sleep. The mixer lock itself is unnecessary here - * because it is meant to serialize hardware access, which - * is taken care of by the I2C layer, so this is safe. - */ - - if (locked) - mtx_unlock(mixer_lock); - snapper_write(sc, SNAPPER_VOLUME, reg); - if (locked) - mtx_lock(mixer_lock); - return (left | (right << 8)); } diff --git a/sys/dev/sound/macio/tumbler.c b/sys/dev/sound/macio/tumbler.c index bd40ea6b4f6b..89af4434e7fe 100644 --- a/sys/dev/sound/macio/tumbler.c +++ b/sys/dev/sound/macio/tumbler.c @@ -383,14 +383,10 @@ static int tumbler_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right) { struct tumbler_softc *sc; - struct mtx *mixer_lock; - int locked; u_int l, r; u_char reg[6]; sc = device_get_softc(mix_getdevinfo(m)); - mixer_lock = mixer_get_lock(m); - locked = mtx_owned(mixer_lock); switch (dev) { case SOUND_MIXER_VOLUME: @@ -407,21 +403,8 @@ tumbler_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right) reg[4] = (r & 0x00ff00) >> 8; reg[5] = r & 0x0000ff; - /* - * We need to unlock the mixer lock because iicbus_transfer() - * may sleep. The mixer lock itself is unnecessary here - * because it is meant to serialize hardware access, which - * is taken care of by the I2C layer, so this is safe. - */ - - if (locked) - mtx_unlock(mixer_lock); - tumbler_write(sc, TUMBLER_VOLUME, reg); - if (locked) - mtx_lock(mixer_lock); - return (left | (right << 8)); } diff --git a/sys/dev/sound/pci/hda/hdaa.c b/sys/dev/sound/pci/hda/hdaa.c index 7dec437de944..8add23217d1b 100644 --- a/sys/dev/sound/pci/hda/hdaa.c +++ b/sys/dev/sound/pci/hda/hdaa.c @@ -3268,10 +3268,51 @@ hdaa_audio_as_parse(struct hdaa_devinfo *devinfo) first = seq; /* Check association correctness. */ if (as[cnt].pins[seq] != 0) { - device_printf(devinfo->dev, "%s: Duplicate pin %d (%d) " - "in association %d! Disabling association.\n", - __func__, seq, w->nid, j); - as[cnt].enable = 0; + int newseq = -1; + + /* + * Some firmware (e.g. Apple EFI on Mac hardware) + * assigns seq=0 to all HDMI/DP output pins in + * an association. Reassign the duplicate to + * the next free slot rather than disabling the + * whole association. Limit to seq=0 duplicates: + * any other duplicate sequence is more likely a + * genuine firmware error and should still disable. + */ + if (seq == 0 && dir == HDAA_CTL_OUT && + HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL( + w->param.widget_cap) && + (HDA_PARAM_PIN_CAP_HDMI(w->wclass.pin.cap) || + HDA_PARAM_PIN_CAP_DP(w->wclass.pin.cap))) { + int cand; + + for (cand = 1; cand < 16; cand++) { + if (as[cnt].pins[cand] == 0) { + newseq = cand; + break; + } + } + } + if (newseq >= 0) { + HDA_BOOTVERBOSE( + device_printf(devinfo->dev, + "%s: Duplicate pin %d (%d) " + "in association %d, " + "reassigning to seq %d.\n", + __func__, seq, w->nid, + j, newseq); + ); + seq = newseq; + /* Update hpredir anchor to lowest seq. */ + first = min(first, newseq); + } else { + device_printf(devinfo->dev, + "%s: Duplicate pin %d (%d) " + "in association %d! " + "Disabling association.\n", + __func__, seq, w->nid, j); + as[cnt].enable = 0; + } } if (dir != as[cnt].dir) { device_printf(devinfo->dev, "%s: Pin %d has wrong " diff --git a/sys/dev/sound/pci/hda/hdaa_patches.c b/sys/dev/sound/pci/hda/hdaa_patches.c index d4267aae80f8..2f3a044195c4 100644 --- a/sys/dev/sound/pci/hda/hdaa_patches.c +++ b/sys/dev/sound/pci/hda/hdaa_patches.c @@ -328,6 +328,15 @@ hdac_pin_patch(struct hdaa_widget *w) patch_str = "as=1 seq=15"; break; } + } else if (id == HDA_CODEC_ALC255 && subid == DELL_WYSE7040_SUBVENDOR) { + switch (nid) { + case 20: + patch_str = "as=1 seq=0 device=Speaker"; + break; + case 33: + patch_str = "as=1 seq=15 device=Headphones"; + break; + } } else if (id == HDA_CODEC_ALC256 && (subid == DELL_I7577_SUBVENDOR || subid == DELL_L7480_SUBVENDOR)) { switch (nid) { diff --git a/sys/dev/sound/pci/hda/hdac.h b/sys/dev/sound/pci/hda/hdac.h index 27d592242578..36fd7b6a60ab 100644 --- a/sys/dev/sound/pci/hda/hdac.h +++ b/sys/dev/sound/pci/hda/hdac.h @@ -282,6 +282,7 @@ #define DELL_164AID_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x164a) #define DELL_164BID_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x164b) #define DELL_I7577_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0802) +#define DELL_WYSE7040_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0727) #define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) /* Clevo */ diff --git a/sys/dev/sound/pcm/ac97.c b/sys/dev/sound/pcm/ac97.c index 1407d202a0d1..ec742ccbbfaa 100644 --- a/sys/dev/sound/pcm/ac97.c +++ b/sys/dev/sound/pcm/ac97.c @@ -628,7 +628,7 @@ ac97_initmixer(struct ac97_info *codec) } pdev = codec->dev; - while (strcmp(device_get_name(device_get_parent(pdev)), "pci") != 0) { + while (!is_pci_device(pdev)) { /* find the top-level PCI device handler */ pdev = device_get_parent(pdev); } diff --git a/sys/dev/sound/pcm/channel.c b/sys/dev/sound/pcm/channel.c index c1e0d8d3bc52..a0ee16a14386 100644 --- a/sys/dev/sound/pcm/channel.c +++ b/sys/dev/sound/pcm/channel.c @@ -2177,7 +2177,7 @@ chn_syncstate(struct pcm_channel *c) if (c->feederflags & (1 << FEEDER_EQ)) { struct pcm_feeder *f; - int treble, bass, state; + int treble, bass; /* CHN_UNLOCK(c); */ treble = mix_get(m, SOUND_MIXER_TREBLE); @@ -2209,15 +2209,6 @@ chn_syncstate(struct pcm_channel *c) device_printf(c->dev, "EQ: Failed to set preamp -- %d\n", d->eqpreamp); - if (d->flags & SD_F_EQ_BYPASSED) - state = FEEDEQ_BYPASS; - else if (d->flags & SD_F_EQ_ENABLED) - state = FEEDEQ_ENABLE; - else - state = FEEDEQ_DISABLE; - if (FEEDER_SET(f, FEEDEQ_STATE, state) != 0) - device_printf(c->dev, - "EQ: Failed to set state -- %d\n", state); } } } diff --git a/sys/dev/sound/pcm/dsp.c b/sys/dev/sound/pcm/dsp.c index 797bfba81023..bc92a3fbd530 100644 --- a/sys/dev/sound/pcm/dsp.c +++ b/sys/dev/sound/pcm/dsp.c @@ -54,10 +54,10 @@ struct dsp_cdevpriv { struct pcm_channel *wrch; }; -static int dsp_mmap_allow_prot_exec = 0; +static int dsp_mmap_allow_prot_exec = -1; SYSCTL_INT(_hw_snd, OID_AUTO, compat_linux_mmap, CTLFLAG_RWTUN, &dsp_mmap_allow_prot_exec, 0, - "linux mmap compatibility (-1=force disable 0=auto 1=force enable)"); + "linux mmap compatibility (-1=force-disable 0=auto)"); static int dsp_basename_clone = 1; SYSCTL_INT(_hw_snd, OID_AUTO, basename_clone, CTLFLAG_RWTUN, @@ -728,8 +728,7 @@ dsp_ioctl(struct cdev *i_dev, u_long cmd, caddr_t arg, int mode, if (d->mixer_dev != NULL) { PCM_ACQUIRE_QUICK(d); - ret = mixer_ioctl_cmd(d->mixer_dev, cmd, arg, -1, td, - MIXER_CMD_DIRECT); + ret = mixer_ioctl_cmd(d->mixer_dev, cmd, arg, -1, td); PCM_RELEASE_QUICK(d); } else ret = EBADF; @@ -1526,8 +1525,7 @@ dsp_ioctl(struct cdev *i_dev, u_long cmd, caddr_t arg, int mode, if (d->mixer_dev != NULL) { PCM_ACQUIRE_QUICK(d); - ret = mixer_ioctl_cmd(d->mixer_dev, xcmd, arg, -1, td, - MIXER_CMD_DIRECT); + ret = mixer_ioctl_cmd(d->mixer_dev, xcmd, arg, -1, td); PCM_RELEASE_QUICK(d); } else ret = ENOTSUP; @@ -1539,8 +1537,7 @@ dsp_ioctl(struct cdev *i_dev, u_long cmd, caddr_t arg, int mode, case SNDCTL_DSP_SET_RECSRC: if (d->mixer_dev != NULL) { PCM_ACQUIRE_QUICK(d); - ret = mixer_ioctl_cmd(d->mixer_dev, cmd, arg, -1, td, - MIXER_CMD_DIRECT); + ret = mixer_ioctl_cmd(d->mixer_dev, cmd, arg, -1, td); PCM_RELEASE_QUICK(d); } else ret = ENOTSUP; @@ -1877,24 +1874,25 @@ dsp_poll(struct cdev *i_dev, int events, struct thread *td) ret = 0; - dsp_lock_chans(priv, FREAD | FWRITE); wrch = priv->wrch; rdch = priv->rdch; if (wrch != NULL && !(wrch->flags & CHN_F_DEAD)) { + CHN_LOCK(wrch); e = (events & (POLLOUT | POLLWRNORM)); if (e) ret |= chn_poll(wrch, e, td); + CHN_UNLOCK(wrch); } if (rdch != NULL && !(rdch->flags & CHN_F_DEAD)) { + CHN_LOCK(rdch); e = (events & (POLLIN | POLLRDNORM)); if (e) ret |= chn_poll(rdch, e, td); + CHN_UNLOCK(rdch); } - dsp_unlock_chans(priv, FREAD | FWRITE); - PCM_GIANT_LEAVE(d); return (ret); @@ -1923,20 +1921,11 @@ dsp_mmap_single(struct cdev *i_dev, vm_ooffset_t *offset, int err; /* - * Reject PROT_EXEC by default. It just doesn't makes sense. - * Unfortunately, we have to give up this one due to linux_mmap - * changes. - * * https://lists.freebsd.org/pipermail/freebsd-emulation/2007-June/003698.html - * */ -#ifdef SV_ABI_LINUX if ((nprot & PROT_EXEC) && (dsp_mmap_allow_prot_exec < 0 || (dsp_mmap_allow_prot_exec == 0 && SV_CURPROC_ABI() != SV_ABI_LINUX))) -#else - if ((nprot & PROT_EXEC) && dsp_mmap_allow_prot_exec < 1) -#endif return (EINVAL); /* diff --git a/sys/dev/sound/pcm/feeder.h b/sys/dev/sound/pcm/feeder.h index e1e91d468455..127b479cd7c9 100644 --- a/sys/dev/sound/pcm/feeder.h +++ b/sys/dev/sound/pcm/feeder.h @@ -119,11 +119,6 @@ enum { FEEDEQ_TREBLE, FEEDEQ_BASS, FEEDEQ_PREAMP, - FEEDEQ_STATE, - FEEDEQ_DISABLE, - FEEDEQ_ENABLE, - FEEDEQ_BYPASS, - FEEDEQ_UNKNOWN }; int feeder_eq_validrate(uint32_t); diff --git a/sys/dev/sound/pcm/feeder_chain.c b/sys/dev/sound/pcm/feeder_chain.c index 4fc846f77496..35bb12a062ec 100644 --- a/sys/dev/sound/pcm/feeder_chain.c +++ b/sys/dev/sound/pcm/feeder_chain.c @@ -725,7 +725,7 @@ feeder_chain(struct pcm_channel *c) /* Soft EQ only applicable for PLAY. */ if (cdesc.dummy == 0 && - c->direction == PCMDIR_PLAY && (d->flags & SD_F_EQ) && + c->direction == PCMDIR_PLAY && (d->flags & SD_F_EQ_ENABLED) && (((d->flags & SD_F_EQ_PC) && !(c->flags & CHN_F_HAS_VCHAN)) || (!(d->flags & SD_F_EQ_PC) && !(c->flags & CHN_F_VIRTUAL)))) diff --git a/sys/dev/sound/pcm/feeder_eq.c b/sys/dev/sound/pcm/feeder_eq.c index 4cf9d4f6695f..0a28dfa1ba17 100644 --- a/sys/dev/sound/pcm/feeder_eq.c +++ b/sys/dev/sound/pcm/feeder_eq.c @@ -3,7 +3,7 @@ * * Copyright (c) 2008-2009 Ariff Abdullah <ariff@FreeBSD.org> * All rights reserved. - * Copyright (c) 2024-2025 The FreeBSD Foundation + * Copyright (c) 2024-2026 The FreeBSD Foundation * * Portions of this software were developed by Christos Margiolis * <christos@FreeBSD.org> under sponsorship from the FreeBSD Foundation. @@ -122,7 +122,6 @@ struct feed_eq_info { uint32_t rate; uint32_t align; int32_t preamp; - int state; }; #if !defined(_KERNEL) && defined(FEEDEQ_ERR_CLIP) @@ -148,19 +147,6 @@ feed_eq_biquad(struct feed_eq_info *info, uint8_t *dst, uint32_t count, pmul = feed_eq_preamp[info->preamp].mul; pshift = feed_eq_preamp[info->preamp].shift; - if (info->state == FEEDEQ_DISABLE) { - j = count * info->channels; - dst += j * AFMT_BPS(fmt); - do { - dst -= AFMT_BPS(fmt); - v = pcm_sample_read(dst, fmt); - v = ((intpcm64_t)pmul * v) >> pshift; - pcm_sample_write(dst, v, fmt); - } while (--j != 0); - - return; - } - treble = &(info->coeff[info->treble.gain].treble); bass = &(info->coeff[info->bass.gain].bass); @@ -290,7 +276,6 @@ feed_eq_init(struct pcm_feeder *f) info->treble.gain = FEEDEQ_L2GAIN(50); info->bass.gain = FEEDEQ_L2GAIN(50); info->preamp = FEEDEQ_PREAMP2IDX(FEEDEQ_PREAMP_DEFAULT); - info->state = FEEDEQ_UNKNOWN; f->data = info; @@ -316,8 +301,6 @@ feed_eq_set(struct pcm_feeder *f, int what, int value) if (feeder_eq_validrate(value) == 0) return (EINVAL); info->rate = (uint32_t)value; - if (info->state == FEEDEQ_UNKNOWN) - info->state = FEEDEQ_ENABLE; return (feed_eq_setup(info)); case FEEDEQ_TREBLE: case FEEDEQ_BASS: @@ -333,13 +316,6 @@ feed_eq_set(struct pcm_feeder *f, int what, int value) return (EINVAL); info->preamp = FEEDEQ_PREAMP2IDX(value); break; - case FEEDEQ_STATE: - if (!(value == FEEDEQ_BYPASS || value == FEEDEQ_ENABLE || - value == FEEDEQ_DISABLE)) - return (EINVAL); - info->state = value; - feed_eq_reset(info); - break; default: return (EINVAL); } @@ -370,15 +346,6 @@ feed_eq_feed(struct pcm_feeder *f, struct pcm_channel *c, uint8_t *b, info = f->data; - /* - * 3 major states: - * FEEDEQ_BYPASS - Bypass entirely, nothing happened. - * FEEDEQ_ENABLE - Preamp+biquad filtering. - * FEEDEQ_DISABLE - Preamp only. - */ - if (info->state == FEEDEQ_BYPASS) - return (FEEDER_FEED(f->source, c, b, count, source)); - dst = b; count = SND_FXROUND(count, info->align); @@ -472,8 +439,6 @@ static int sysctl_dev_pcm_eq(SYSCTL_HANDLER_ARGS) { struct snddev_info *d; - struct pcm_channel *c; - struct pcm_feeder *f; int err, val, oval; d = oidp->oid_arg1; @@ -482,9 +447,7 @@ sysctl_dev_pcm_eq(SYSCTL_HANDLER_ARGS) PCM_LOCK(d); PCM_WAIT(d); - if (d->flags & SD_F_EQ_BYPASSED) - val = 2; - else if (d->flags & SD_F_EQ_ENABLED) + if (d->flags & SD_F_EQ_ENABLED) val = 1; else val = 0; @@ -495,30 +458,17 @@ sysctl_dev_pcm_eq(SYSCTL_HANDLER_ARGS) err = sysctl_handle_int(oidp, &val, 0, req); if (err == 0 && req->newptr != NULL && val != oval) { - if (!(val == 0 || val == 1 || val == 2)) { + if (!(val == 0 || val == 1)) { PCM_RELEASE_QUICK(d); return (EINVAL); } PCM_LOCK(d); - d->flags &= ~(SD_F_EQ_ENABLED | SD_F_EQ_BYPASSED); - if (val == 2) { - val = FEEDEQ_BYPASS; - d->flags |= SD_F_EQ_BYPASSED; - } else if (val == 1) { - val = FEEDEQ_ENABLE; + if (val == 1) d->flags |= SD_F_EQ_ENABLED; - } else - val = FEEDEQ_DISABLE; - - CHN_FOREACH(c, d, channels.pcm.busy) { - CHN_LOCK(c); - f = feeder_find(c, FEEDER_EQ); - if (f != NULL) - (void)FEEDER_SET(f, FEEDEQ_STATE, val); - CHN_UNLOCK(c); - } + else + d->flags &= ~SD_F_EQ_ENABLED; PCM_RELEASE(d); PCM_UNLOCK(d); @@ -592,17 +542,11 @@ void feeder_eq_initsys(device_t dev) { struct snddev_info *d; - const char *preamp; char buf[64]; d = device_get_softc(dev); - if (!(resource_string_value(device_get_name(dev), device_get_unit(dev), - "eq_preamp", &preamp) == 0 && - (d->eqpreamp = feed_eq_scan_preamp_arg(preamp)) != - FEEDEQ_PREAMP_INVALID)) - d->eqpreamp = FEEDEQ_PREAMP_DEFAULT; - + d->eqpreamp = FEEDEQ_PREAMP_DEFAULT; if (d->eqpreamp < FEEDEQ_PREAMP_MIN) d->eqpreamp = FEEDEQ_PREAMP_MIN; else if (d->eqpreamp > FEEDEQ_PREAMP_MAX) @@ -612,7 +556,7 @@ feeder_eq_initsys(device_t dev) SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "eq", CTLTYPE_INT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE, d, sizeof(d), sysctl_dev_pcm_eq, "I", - "Bass/Treble Equalizer (0=disable, 1=enable, 2=bypass)"); + "Bass/Treble Equalizer (0=disable, 1=enable)"); (void)snprintf(buf, sizeof(buf), "Bass/Treble Equalizer Preamp " "(-/+ %d.0dB , %d.%ddB step)", diff --git a/sys/dev/sound/pcm/mixer.c b/sys/dev/sound/pcm/mixer.c index 6ed2d0c3ce5c..3ddee24417cc 100644 --- a/sys/dev/sound/pcm/mixer.c +++ b/sys/dev/sound/pcm/mixer.c @@ -5,6 +5,10 @@ * Portions Copyright (c) Ryan Beasley <ryan.beasley@gmail.com> - GSoC 2006 * Copyright (c) 1999 Cameron Grant <cg@FreeBSD.org> * All rights reserved. + * Copyright (c) 2026 The FreeBSD Foundation + * + * Portions of this software were developed by Christos Margiolis + * <christos@FreeBSD.org> under sponsorship from the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -37,36 +41,6 @@ #include "feeder_if.h" #include "mixer_if.h" -static MALLOC_DEFINE(M_MIXER, "mixer", "mixer"); - -static int mixer_bypass = 1; -SYSCTL_INT(_hw_snd, OID_AUTO, vpc_mixer_bypass, CTLFLAG_RWTUN, - &mixer_bypass, 0, - "control channel pcm/rec volume, bypassing real mixer device"); - -#define MIXER_NAMELEN 16 -struct snd_mixer { - KOBJ_FIELDS; - void *devinfo; - int hwvol_mixer; - int hwvol_step; - int type; - device_t dev; - u_int32_t devs; - u_int32_t mutedevs; - u_int32_t recdevs; - u_int32_t recsrc; - u_int16_t level[32]; - u_int16_t level_muted[32]; - u_int8_t parent[32]; - u_int32_t child[32]; - u_int8_t realdev[32]; - char name[MIXER_NAMELEN]; - struct mtx lock; - oss_mixer_enuminfo enuminfo; - int modify_counter; -}; - static u_int16_t snd_mixerdefaults[SOUND_MIXER_NRDEVICES] = { [SOUND_MIXER_VOLUME] = 75, [SOUND_MIXER_BASS] = 50, @@ -304,7 +278,7 @@ mixer_set(struct snd_mixer *m, u_int dev, u_int32_t muted, u_int lev) if (dev == SOUND_MIXER_PCM && (d->flags & SD_F_SOFTPCMVOL)) (void)mixer_set_softpcmvol(m, d, l, r); else if ((dev == SOUND_MIXER_TREBLE || - dev == SOUND_MIXER_BASS) && (d->flags & SD_F_EQ)) + dev == SOUND_MIXER_BASS) && (d->flags & SD_F_EQ_ENABLED)) (void)mixer_set_eq(m, d, dev, (l + r) >> 1); else if (realdev != SOUND_MIXER_NONE && MIXER_SET(m, realdev, l, r) < 0) { @@ -484,8 +458,7 @@ mix_setdevs(struct snd_mixer *m, u_int32_t v) d = device_get_softc(m->dev); if (d != NULL && (d->flags & SD_F_SOFTPCMVOL)) v |= SOUND_MASK_PCM; - if (d != NULL && (d->flags & SD_F_EQ)) - v |= SOUND_MASK_TREBLE | SOUND_MASK_BASS; + v |= SOUND_MASK_TREBLE | SOUND_MASK_BASS; for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { if (m->parent[i] < SOUND_MIXER_NRDEVICES) v |= 1 << m->parent[i]; @@ -501,64 +474,12 @@ mix_setdevs(struct snd_mixer *m, u_int32_t v) * recording devices. This function records that value in a structure * used by the rest of the mixer code. * - * This function also populates a structure used by the SNDCTL_DSP_*RECSRC* - * family of ioctls that are part of OSSV4. All recording device labels - * are concatenated in ascending order corresponding to their routing - * numbers. (Ex: a system might have 0 => 'vol', 1 => 'cd', 2 => 'line', - * etc.) For now, these labels are just the standard recording device - * names (cd, line1, etc.), but will eventually be fully dynamic and user - * controlled. - * * @param m mixer device context container thing * @param v mask of recording devices */ void mix_setrecdevs(struct snd_mixer *m, u_int32_t v) { - oss_mixer_enuminfo *ei; - char *loc; - int i, nvalues, nwrote, nleft, ncopied; - - ei = &m->enuminfo; - - nvalues = 0; - nwrote = 0; - nleft = sizeof(ei->strings); - loc = ei->strings; - - for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { - if ((1 << i) & v) { - ei->strindex[nvalues] = nwrote; - ncopied = strlcpy(loc, snd_mixernames[i], nleft) + 1; - /* strlcpy retval doesn't include terminator */ - - nwrote += ncopied; - nleft -= ncopied; - nvalues++; - - /* - * XXX I don't think this should ever be possible. - * Even with a move to dynamic device/channel names, - * each label is limited to ~16 characters, so that'd - * take a LOT to fill this buffer. - */ - if ((nleft <= 0) || (nvalues >= OSS_ENUM_MAXVALUE)) { - device_printf(m->dev, - "mix_setrecdevs: Not enough room to store device names--please file a bug report.\n"); - device_printf(m->dev, - "mix_setrecdevs: Please include details about your sound hardware, OS version, etc.\n"); - break; - } - - loc = &ei->strings[nwrote]; - } - } - - /* - * NB: The SNDCTL_DSP_GET_RECSRC_NAMES ioctl ignores the dev - * and ctrl fields. - */ - ei->nvalues = nvalues; m->recdevs = v; } @@ -639,7 +560,7 @@ mixer_obj_create(device_t dev, kobj_class_t cls, void *devinfo, KASSERT(type == MIXER_TYPE_PRIMARY || type == MIXER_TYPE_SECONDARY, ("invalid mixer type=%d", type)); - m = (struct snd_mixer *)kobj_create(cls, M_MIXER, M_WAITOK | M_ZERO); + m = (struct snd_mixer *)kobj_create(cls, M_DEVBUF, M_WAITOK | M_ZERO); snprintf(m->name, sizeof(m->name), "%s:mixer", device_get_nameunit(dev)); if (desc != NULL) { @@ -658,9 +579,8 @@ mixer_obj_create(device_t dev, kobj_class_t cls, void *devinfo, } if (MIXER_INIT(m)) { - mtx_lock(&m->lock); mtx_destroy(&m->lock); - kobj_delete((kobj_t)m, M_MIXER); + kobj_delete((kobj_t)m, M_DEVBUF); return (NULL); } @@ -679,7 +599,7 @@ mixer_delete(struct snd_mixer *m) MIXER_UNINIT(m); mtx_destroy(&m->lock); - kobj_delete((kobj_t)m, M_MIXER); + kobj_delete((kobj_t)m, M_DEVBUF); return (0); } @@ -706,15 +626,6 @@ mixer_init(device_t dev, kobj_class_t cls, void *devinfo) name = device_get_name(dev); unit = device_get_unit(dev); - if (resource_int_value(name, unit, "eq", &val) == 0 && - val != 0) { - snddev->flags |= SD_F_EQ; - if ((val & SD_F_EQ_MASK) == val) - snddev->flags |= val; - else - snddev->flags |= SD_F_EQ_DEFAULT; - snddev->eqpreamp = 0; - } m = mixer_obj_create(dev, cls, devinfo, MIXER_TYPE_PRIMARY, NULL); if (m == NULL) @@ -762,8 +673,7 @@ mixer_init(device_t dev, kobj_class_t cls, void *devinfo) } if (snddev->flags & SD_F_SOFTPCMVOL) device_printf(dev, "Soft PCM mixer ENABLED\n"); - if (snddev->flags & SD_F_EQ) - device_printf(dev, "EQ Treble/Bass ENABLED\n"); + device_printf(dev, "EQ Treble/Bass ENABLED\n"); } return (0); @@ -804,7 +714,7 @@ mixer_uninit(device_t dev) MIXER_UNINIT(m); mtx_destroy(&m->lock); - kobj_delete((kobj_t)m, M_MIXER); + kobj_delete((kobj_t)m, M_DEVBUF); d->mixer_dev = NULL; @@ -1046,113 +956,6 @@ mixer_close(struct cdev *i_dev, int flags, int mode, struct thread *td) } static int -mixer_ioctl_channel(struct cdev *dev, u_long cmd, caddr_t arg, int mode, - struct thread *td, int from) -{ - struct snddev_info *d; - struct snd_mixer *m; - struct pcm_channel *c, *rdch, *wrch; - pid_t pid; - int j, ret; - - if (td == NULL || td->td_proc == NULL) - return (-1); - - m = dev->si_drv1; - d = device_get_softc(m->dev); - j = cmd & 0xff; - - switch (j) { - case SOUND_MIXER_PCM: - case SOUND_MIXER_RECLEV: - case SOUND_MIXER_DEVMASK: - case SOUND_MIXER_CAPS: - case SOUND_MIXER_STEREODEVS: - break; - default: - return (-1); - } - - pid = td->td_proc->p_pid; - rdch = NULL; - wrch = NULL; - c = NULL; - ret = -1; - - /* - * This is unfair. Imagine single proc opening multiple - * instances of same direction. What we do right now - * is looking for the first matching proc/pid, and just - * that. Nothing more. Consider it done. - * - * The better approach of controlling specific channel - * pcm or rec volume is by doing mixer ioctl - * (SNDCTL_DSP_[SET|GET][PLAY|REC]VOL / SOUND_MIXER_[PCM|RECLEV] - * on its open fd, rather than cracky mixer bypassing here. - */ - CHN_FOREACH(c, d, channels.pcm.opened) { - CHN_LOCK(c); - if (c->pid != pid || - !(c->feederflags & (1 << FEEDER_VOLUME))) { - CHN_UNLOCK(c); - continue; - } - if (rdch == NULL && c->direction == PCMDIR_REC) { - rdch = c; - if (j == SOUND_MIXER_RECLEV) - goto mixer_ioctl_channel_proc; - } else if (wrch == NULL && c->direction == PCMDIR_PLAY) { - wrch = c; - if (j == SOUND_MIXER_PCM) - goto mixer_ioctl_channel_proc; - } - CHN_UNLOCK(c); - if (rdch != NULL && wrch != NULL) - break; - } - - if (rdch == NULL && wrch == NULL) - return (-1); - - if ((j == SOUND_MIXER_DEVMASK || j == SOUND_MIXER_CAPS || - j == SOUND_MIXER_STEREODEVS) && - (cmd & ~0xff) == MIXER_READ(0)) { - mtx_lock(&m->lock); - *(int *)arg = mix_getdevs(m); - mtx_unlock(&m->lock); - if (rdch != NULL) - *(int *)arg |= SOUND_MASK_RECLEV; - if (wrch != NULL) - *(int *)arg |= SOUND_MASK_PCM; - ret = 0; - } - - return (ret); - -mixer_ioctl_channel_proc: - - KASSERT(c != NULL, ("%s(): NULL channel", __func__)); - CHN_LOCKASSERT(c); - - if ((cmd & ~0xff) == MIXER_WRITE(0)) { - int left, right, center; - - left = *(int *)arg & 0x7f; - right = (*(int *)arg >> 8) & 0x7f; - center = (left + right) >> 1; - chn_setvolume_multi(c, SND_VOL_C_PCM, left, right, center); - } else if ((cmd & ~0xff) == MIXER_READ(0)) { - *(int *)arg = chn_getvolume_matrix(c, SND_VOL_C_PCM, SND_CHN_T_FL); - *(int *)arg |= - chn_getvolume_matrix(c, SND_VOL_C_PCM, SND_CHN_T_FR) << 8; - } - - CHN_UNLOCK(c); - - return (0); -} - -static int mixer_ioctl(struct cdev *i_dev, u_long cmd, caddr_t arg, int mode, struct thread *td) { @@ -1169,15 +972,7 @@ mixer_ioctl(struct cdev *i_dev, u_long cmd, caddr_t arg, int mode, PCM_GIANT_ENTER(d); PCM_ACQUIRE_QUICK(d); - ret = -1; - - if (mixer_bypass != 0 && (d->flags & SD_F_VPC)) - ret = mixer_ioctl_channel(i_dev, cmd, arg, mode, td, - MIXER_CMD_CDEV); - - if (ret == -1) - ret = mixer_ioctl_cmd(i_dev, cmd, arg, mode, td, - MIXER_CMD_CDEV); + ret = mixer_ioctl_cmd(i_dev, cmd, arg, mode, td); PCM_RELEASE_QUICK(d); PCM_GIANT_LEAVE(d); @@ -1200,7 +995,7 @@ mixer_mixerinfo(struct snd_mixer *m, mixer_info *mi) */ int mixer_ioctl_cmd(struct cdev *i_dev, u_long cmd, caddr_t arg, int mode, - struct thread *td, int from) + struct thread *td) { struct snd_mixer *m; int ret = EINVAL, *arg_i = (int *)arg; @@ -1238,10 +1033,31 @@ mixer_ioctl_cmd(struct cdev *i_dev, u_long cmd, caddr_t arg, int mode, mtx_lock(&m->lock); switch (cmd) { - case SNDCTL_DSP_GET_RECSRC_NAMES: - bcopy((void *)&m->enuminfo, arg, sizeof(oss_mixer_enuminfo)); + case SNDCTL_DSP_GET_RECSRC_NAMES: { + oss_mixer_enuminfo *ei = (oss_mixer_enuminfo *)arg; + char *loc; + int i, nvalues, nwrote, nleft, ncopied; + + nvalues = 0; + nwrote = 0; + nleft = sizeof(ei->strings); + loc = ei->strings; + + for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { + if (!((1 << i) & m->recdevs)) + continue; + ei->strindex[nvalues] = nwrote; + ncopied = strlcpy(loc, snd_mixernames[i], nleft) + 1; + nwrote += ncopied; + nleft -= ncopied; + nvalues++; + loc = &ei->strings[nwrote]; + } + ei->nvalues = nvalues; + ret = 0; goto done; + } case SNDCTL_DSP_GET_RECSRC: ret = mixer_get_recroute(m, arg_i); goto done; @@ -1515,13 +1331,3 @@ mixer_oss_mixerinfo(struct cdev *i_dev, oss_mixerinfo *mi) return (EINVAL); } - -/* - * Allow the sound driver to use the mixer lock to protect its mixer - * data: - */ -struct mtx * -mixer_get_lock(struct snd_mixer *m) -{ - return (&m->lock); -} diff --git a/sys/dev/sound/pcm/mixer.h b/sys/dev/sound/pcm/mixer.h index 3ce8a4f5adee..6f764307cfc8 100644 --- a/sys/dev/sound/pcm/mixer.h +++ b/sys/dev/sound/pcm/mixer.h @@ -4,6 +4,10 @@ * Copyright (c) 2005-2009 Ariff Abdullah <ariff@FreeBSD.org> * Copyright (c) 1999 Cameron Grant <cg@FreeBSD.org> * All rights reserved. + * Copyright (c) 2026 The FreeBSD Foundation + * + * Portions of this software were developed by Christos Margiolis + * <christos@FreeBSD.org> under sponsorship from the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -30,13 +34,35 @@ #ifndef _PCM_MIXER_H_ #define _PCM_MIXER_H_ +#define MIXER_NAMELEN 16 +struct snd_mixer { + KOBJ_FIELDS; + void *devinfo; + int hwvol_mixer; + int hwvol_step; + int type; + device_t dev; + u_int32_t devs; + u_int32_t mutedevs; + u_int32_t recdevs; + u_int32_t recsrc; + u_int16_t level[32]; + u_int16_t level_muted[32]; + u_int8_t parent[32]; + u_int32_t child[32]; + u_int8_t realdev[32]; + char name[MIXER_NAMELEN]; + struct mtx lock; + int modify_counter; +}; + struct snd_mixer *mixer_create(device_t dev, kobj_class_t cls, void *devinfo, const char *desc); int mixer_delete(struct snd_mixer *m); int mixer_init(device_t dev, kobj_class_t cls, void *devinfo); int mixer_uninit(device_t dev); int mixer_reinit(device_t dev); -int mixer_ioctl_cmd(struct cdev *i_dev, u_long cmd, caddr_t arg, int mode, struct thread *td, int from); +int mixer_ioctl_cmd(struct cdev *i_dev, u_long cmd, caddr_t arg, int mode, struct thread *td); int mixer_oss_mixerinfo(struct cdev *i_dev, oss_mixerinfo *mi); int mixer_hwvol_init(device_t dev); @@ -61,21 +87,11 @@ void mix_setparentchild(struct snd_mixer *m, u_int32_t parent, u_int32_t childs) void mix_setrealdev(struct snd_mixer *m, u_int32_t dev, u_int32_t realdev); u_int32_t mix_getparent(struct snd_mixer *m, u_int32_t dev); void *mix_getdevinfo(struct snd_mixer *m); -struct mtx *mixer_get_lock(struct snd_mixer *m); - -#define MIXER_CMD_DIRECT 0 /* send command within driver */ -#define MIXER_CMD_CDEV 1 /* send command from cdev/ioctl */ #define MIXER_TYPE_PRIMARY 0 /* mixer_init() */ #define MIXER_TYPE_SECONDARY 1 /* mixer_create() */ -/* - * this is a kludge to allow hiding of the struct snd_mixer definition - * 512 should be enough for all architectures - */ -#define MIXER_SIZE (512 + sizeof(struct kobj) + \ - sizeof(oss_mixer_enuminfo)) - -#define MIXER_DECLARE(name) static DEFINE_CLASS(name, name ## _methods, MIXER_SIZE) +#define MIXER_DECLARE(name) static DEFINE_CLASS(name, name ## _methods, \ + sizeof(struct snd_mixer)) #endif /* _PCM_MIXER_H_ */ diff --git a/sys/dev/sound/pcm/sound.c b/sys/dev/sound/pcm/sound.c index 9eb2dffeb908..235142eb5209 100644 --- a/sys/dev/sound/pcm/sound.c +++ b/sys/dev/sound/pcm/sound.c @@ -77,11 +77,30 @@ snd_setup_intr(device_t dev, struct resource *res, int flags, driver_intr_t hand return bus_setup_intr(dev, res, flags, NULL, hand, param, cookiep); } +static void +pcm_hotswap(void) +{ + struct snddev_info *d; + char buf[32]; + + bus_topo_assert(); + if (snd_unit >= 0) { + d = devclass_get_softc(pcm_devclass, snd_unit); + if (!PCM_REGISTERED(d)) + return; + snprintf(buf, sizeof(buf), "cdev=dsp%d", snd_unit); + if (d->reccount > 0) + devctl_notify("SND", "CONN", "IN", buf); + if (d->playcount > 0) + devctl_notify("SND", "CONN", "OUT", buf); + } else + devctl_notify("SND", "CONN", "NODEV", NULL); +} + static int sysctl_hw_snd_default_unit(SYSCTL_HANDLER_ARGS) { struct snddev_info *d; - char buf[32]; int error, unit; unit = snd_unit; @@ -95,13 +114,8 @@ sysctl_hw_snd_default_unit(SYSCTL_HANDLER_ARGS) } snd_unit = unit; snd_unit_auto = 0; + pcm_hotswap(); bus_topo_unlock(); - - snprintf(buf, sizeof(buf), "cdev=dsp%d", snd_unit); - if (d->reccount > 0) - devctl_notify("SND", "CONN", "IN", buf); - if (d->playcount > 0) - devctl_notify("SND", "CONN", "OUT", buf); } return (error); } @@ -373,6 +387,7 @@ int pcm_register(device_t dev, char *str) { struct snddev_info *d = device_get_softc(dev); + int err; /* should only be called once */ if (d->flags & SD_F_REGISTERED) @@ -415,9 +430,15 @@ pcm_register(device_t dev, char *str) "mode (1=mixer, 2=play, 4=rec. The values are OR'ed if more than " "one mode is supported)"); vchan_initsys(dev); - if (d->flags & SD_F_EQ) - feeder_eq_initsys(dev); + feeder_eq_initsys(dev); + + sndstat_register(dev, SNDST_TYPE_PCM, d->status); + err = dsp_make_dev(dev); + if (err) + return (err); + + bus_topo_lock(); if (snd_unit_auto < 0) snd_unit_auto = (snd_unit < 0) ? 1 : 0; if (snd_unit < 0 || snd_unit_auto > 1) @@ -425,9 +446,11 @@ pcm_register(device_t dev, char *str) else if (snd_unit_auto == 1) snd_unit = pcm_best_unit(snd_unit); - sndstat_register(dev, SNDST_TYPE_PCM, d->status); + if (snd_unit == device_get_unit(dev)) + pcm_hotswap(); + bus_topo_unlock(); - return (dsp_make_dev(dev)); + return (0); } int @@ -470,13 +493,14 @@ pcm_unregister(device_t dev) cv_destroy(&d->cv); mtx_destroy(&d->lock); + bus_topo_lock(); if (snd_unit == device_get_unit(dev)) { snd_unit = pcm_best_unit(-1); if (snd_unit_auto == 0) snd_unit_auto = 1; - if (snd_unit < 0) - devctl_notify("SND", "CONN", "NODEV", NULL); + pcm_hotswap(); } + bus_topo_unlock(); return (0); } diff --git a/sys/dev/sound/pcm/sound.h b/sys/dev/sound/pcm/sound.h index 4795eb7585c5..4d527d69086a 100644 --- a/sys/dev/sound/pcm/sound.h +++ b/sys/dev/sound/pcm/sound.h @@ -105,17 +105,13 @@ struct snd_mixer; #define SD_F_REGISTERED 0x00000020 #define SD_F_BITPERFECT 0x00000040 #define SD_F_VPC 0x00000080 /* volume-per-channel */ -#define SD_F_EQ 0x00000100 /* EQ */ +/* unused 0x00000100 */ #define SD_F_EQ_ENABLED 0x00000200 /* EQ enabled */ -#define SD_F_EQ_BYPASSED 0x00000400 /* EQ bypassed */ +/* unused 0x00000400 */ #define SD_F_EQ_PC 0x00000800 /* EQ per-channel */ #define SD_F_PVCHANS 0x00001000 /* Playback vchans enabled */ #define SD_F_RVCHANS 0x00002000 /* Recording vchans enabled */ -#define SD_F_EQ_DEFAULT (SD_F_EQ | SD_F_EQ_ENABLED) -#define SD_F_EQ_MASK (SD_F_EQ | SD_F_EQ_ENABLED | \ - SD_F_EQ_BYPASSED | SD_F_EQ_PC) - #define SD_F_BITS "\020" \ "\001SIMPLEX" \ /* "\002 */ \ @@ -125,9 +121,9 @@ struct snd_mixer; "\006REGISTERED" \ "\007BITPERFECT" \ "\010VPC" \ - "\011EQ" \ + /* "\011 */ \ "\012EQ_ENABLED" \ - "\013EQ_BYPASSED" \ + /* "\013 */ \ "\014EQ_PC" \ "\015PVCHANS" \ "\016RVCHANS" diff --git a/sys/dev/sound/usb/uaudio.c b/sys/dev/sound/usb/uaudio.c index f477eb768fde..eedd52774b70 100644 --- a/sys/dev/sound/usb/uaudio.c +++ b/sys/dev/sound/usb/uaudio.c @@ -356,7 +356,7 @@ struct uaudio_hid { struct uaudio_softc_child { device_t pcm_device; - struct mtx *mixer_lock; + struct mtx mixer_lock; struct snd_mixer *mixer_dev; uint32_t mix_info; @@ -2955,12 +2955,9 @@ uaudio_mixer_sysctl_handler(SYSCTL_HANDLER_ARGS) sc = (struct uaudio_softc *)oidp->oid_arg1; hint = oidp->oid_arg2; - if (sc->sc_child[0].mixer_lock == NULL) - return (ENXIO); - /* lookup mixer node */ - mtx_lock(sc->sc_child[0].mixer_lock); + mtx_lock(&sc->sc_child[0].mixer_lock); for (pmc = sc->sc_mixer_root; pmc != NULL; pmc = pmc->next) { for (chan = 0; chan != (int)pmc->nchan; chan++) { if (pmc->wValue[chan] != -1 && @@ -2971,7 +2968,7 @@ uaudio_mixer_sysctl_handler(SYSCTL_HANDLER_ARGS) } } found: - mtx_unlock(sc->sc_child[0].mixer_lock); + mtx_unlock(&sc->sc_child[0].mixer_lock); error = sysctl_handle_int(oidp, &temp, 0, req); if (error != 0 || req->newptr == NULL) @@ -2979,7 +2976,7 @@ found: /* update mixer value */ - mtx_lock(sc->sc_child[0].mixer_lock); + mtx_lock(&sc->sc_child[0].mixer_lock); if (pmc != NULL && temp >= pmc->minval && temp <= pmc->maxval) { @@ -2989,7 +2986,7 @@ found: /* start the transfer, if not already started */ usbd_transfer_start(sc->sc_mixer_xfer[0]); } - mtx_unlock(sc->sc_child[0].mixer_lock); + mtx_unlock(&sc->sc_child[0].mixer_lock); return (0); } @@ -3220,10 +3217,7 @@ uaudio_mixer_reload_all(struct uaudio_softc *sc) struct uaudio_mixer_node *pmc; int chan; - if (sc->sc_child[0].mixer_lock == NULL) - return; - - mtx_lock(sc->sc_child[0].mixer_lock); + mtx_lock(&sc->sc_child[0].mixer_lock); for (pmc = sc->sc_mixer_root; pmc != NULL; pmc = pmc->next) { /* use reset defaults for non-oss controlled settings */ if (pmc->ctl == SOUND_MIXER_NRDEVICES) @@ -3235,7 +3229,7 @@ uaudio_mixer_reload_all(struct uaudio_softc *sc) /* start HID volume keys, if any */ usbd_transfer_start(sc->sc_hid.xfer[0]); - mtx_unlock(sc->sc_child[0].mixer_lock); + mtx_unlock(&sc->sc_child[0].mixer_lock); } static void @@ -5392,8 +5386,8 @@ uaudio_mixer_bsd2value(struct uaudio_mixer_node *mc, int val) } static void -uaudio_mixer_ctl_set(struct uaudio_softc *sc, struct uaudio_mixer_node *mc, - uint8_t chan, int val) +uaudio_mixer_ctl_set(struct uaudio_softc *sc, unsigned index, + struct uaudio_mixer_node *mc, uint8_t chan, int val) { val = uaudio_mixer_bsd2value(mc, val); @@ -5402,7 +5396,9 @@ uaudio_mixer_ctl_set(struct uaudio_softc *sc, struct uaudio_mixer_node *mc, /* start the transfer, if not already started */ + mtx_lock(&sc->sc_child[index].mixer_lock); usbd_transfer_start(sc->sc_mixer_xfer[0]); + mtx_unlock(&sc->sc_child[index].mixer_lock); } static void @@ -5439,13 +5435,13 @@ uaudio_mixer_init_sub(struct uaudio_softc *sc, struct snd_mixer *m) DPRINTF("child=%u\n", i); - sc->sc_child[i].mixer_lock = mixer_get_lock(m); + mtx_init(&sc->sc_child[i].mixer_lock, "uaudio mixer lock", NULL, MTX_DEF); sc->sc_child[i].mixer_dev = m; if (i == 0 && usbd_transfer_setup(sc->sc_udev, &sc->sc_mixer_iface_index, sc->sc_mixer_xfer, uaudio_mixer_config, 1, sc, - sc->sc_child[i].mixer_lock)) { + &sc->sc_child[i].mixer_lock)) { DPRINTFN(0, "could not allocate USB transfer for mixer!\n"); return (ENOMEM); } @@ -5470,7 +5466,7 @@ uaudio_mixer_uninit_sub(struct uaudio_softc *sc, struct snd_mixer *m) if (index == 0) usbd_transfer_unsetup(sc->sc_mixer_xfer, 1); - sc->sc_child[index].mixer_lock = NULL; + mtx_destroy(&sc->sc_child[index].mixer_lock); return (0); } @@ -5488,7 +5484,7 @@ uaudio_mixer_set(struct uaudio_softc *sc, struct snd_mixer *m, for (mc = sc->sc_mixer_root; mc != NULL; mc = mc->next) { if (mc->ctl == type) { for (chan = 0; chan < mc->nchan; chan++) { - uaudio_mixer_ctl_set(sc, mc, chan, + uaudio_mixer_ctl_set(sc, index, mc, chan, chan == 0 ? left : right); } } @@ -5529,7 +5525,7 @@ uaudio_mixer_setrecsrc(struct uaudio_softc *sc, struct snd_mixer *m, uint32_t sr for (i = mc->minval; (i > 0) && (i <= mc->maxval); i++) { if (temp != (1U << mc->slctrtype[i - 1])) continue; - uaudio_mixer_ctl_set(sc, mc, 0, i); + uaudio_mixer_ctl_set(sc, index, mc, 0, i); break; } } @@ -6186,9 +6182,6 @@ uaudio_hid_attach(struct uaudio_softc *sc, if (!(sc->sc_hid.flags & UAUDIO_HID_VALID)) return (-1); - if (sc->sc_child[0].mixer_lock == NULL) - return (-1); - /* Get HID descriptor */ error = usbd_req_get_hid_desc(uaa->device, NULL, &d_ptr, &d_len, M_TEMP, sc->sc_hid.iface_index); @@ -6247,7 +6240,7 @@ uaudio_hid_attach(struct uaudio_softc *sc, /* allocate USB transfers */ error = usbd_transfer_setup(uaa->device, &sc->sc_hid.iface_index, sc->sc_hid.xfer, uaudio_hid_config, UAUDIO_HID_N_TRANSFER, - sc, sc->sc_child[0].mixer_lock); + sc, &sc->sc_child[0].mixer_lock); if (error) { DPRINTF("error=%s\n", usbd_errstr(error)); return (-1); diff --git a/sys/dev/sound/usb/uaudio_pcm.c b/sys/dev/sound/usb/uaudio_pcm.c index c24c111f983c..4b1762cfc3ec 100644 --- a/sys/dev/sound/usb/uaudio_pcm.c +++ b/sys/dev/sound/usb/uaudio_pcm.c @@ -134,39 +134,18 @@ ua_mixer_init(struct snd_mixer *m) static int ua_mixer_set(struct snd_mixer *m, unsigned type, unsigned left, unsigned right) { - struct mtx *mtx = mixer_get_lock(m); - uint8_t do_unlock; - - if (mtx_owned(mtx)) { - do_unlock = 0; - } else { - do_unlock = 1; - mtx_lock(mtx); - } uaudio_mixer_set(mix_getdevinfo(m), m, type, left, right); - if (do_unlock) { - mtx_unlock(mtx); - } + return (left | (right << 8)); } static uint32_t ua_mixer_setrecsrc(struct snd_mixer *m, uint32_t src) { - struct mtx *mtx = mixer_get_lock(m); int retval; - uint8_t do_unlock; - if (mtx_owned(mtx)) { - do_unlock = 0; - } else { - do_unlock = 1; - mtx_lock(mtx); - } retval = uaudio_mixer_setrecsrc(mix_getdevinfo(m), m, src); - if (do_unlock) { - mtx_unlock(mtx); - } + return (retval); } diff --git a/sys/dev/syscons/syscons.c b/sys/dev/syscons/syscons.c index 1a2969d6f2d8..9167da23efd8 100644 --- a/sys/dev/syscons/syscons.c +++ b/sys/dev/syscons/syscons.c @@ -3987,10 +3987,10 @@ next_code: break; case SUSP: - power_pm_suspend(POWER_SSTATE_TRANSITION_SUSPEND); + (void)power_pm_suspend(POWER_TRANSITION_SUSPEND); break; case STBY: - power_pm_suspend(POWER_SSTATE_TRANSITION_STANDBY); + (void)power_pm_suspend(POWER_TRANSITION_STANDBY); break; case DBG: diff --git a/sys/dev/thunderbolt/nhi.c b/sys/dev/thunderbolt/nhi.c index 9550de258dab..6cbe79779c13 100644 --- a/sys/dev/thunderbolt/nhi.c +++ b/sys/dev/thunderbolt/nhi.c @@ -788,8 +788,11 @@ nhi_tx_schedule(struct nhi_ring_pair *r, struct nhi_cmd_frame *cmd) int nhi_tx_synchronous(struct nhi_ring_pair *r, struct nhi_cmd_frame *cmd) { + struct nhi_softc *sc __diagused; int error, count; + sc = r->sc; + if ((error = nhi_tx_schedule(r, cmd)) != 0) return (error); @@ -812,16 +815,16 @@ nhi_tx_synchronous(struct nhi_ring_pair *r, struct nhi_cmd_frame *cmd) if ((cmd->flags & CMD_REQ_COMPLETE) == 0) error = ETIMEDOUT; - tb_debug(r->sc, DBG_TXQ|DBG_FULL, "tx_synchronous done waiting, " + tb_debug(sc, DBG_TXQ|DBG_FULL, "tx_synchronous done waiting, " "err= %d, TX_COMPLETE= %d\n", error, !!(cmd->flags & CMD_REQ_COMPLETE)); if (error == ERESTART) { - tb_printf(r->sc, "TX command interrupted\n"); + tb_printf(sc, "TX command interrupted\n"); } else if ((error == EWOULDBLOCK) || (error == ETIMEDOUT)) { - tb_printf(r->sc, "TX command timed out\n"); + tb_printf(sc, "TX command timed out\n"); } else if (error != 0) { - tb_printf(r->sc, "TX command failed error= %d\n", error); + tb_printf(sc, "TX command failed error= %d\n", error); } return (error); @@ -831,7 +834,7 @@ static int nhi_tx_complete(struct nhi_ring_pair *r, struct nhi_tx_buffer_desc *desc, struct nhi_cmd_frame *cmd) { - struct nhi_softc *sc; + struct nhi_softc *sc __diagused; struct nhi_pdf_dispatch *txpdf; u_int sof; @@ -865,9 +868,10 @@ static int nhi_rx_complete(struct nhi_ring_pair *r, struct nhi_rx_post_desc *desc, struct nhi_cmd_frame *cmd) { - struct nhi_softc *sc; + struct nhi_softc *sc __diagused; struct nhi_pdf_dispatch *rxpdf; - u_int eof, len; + u_int eof; + u_int len __diagused; sc = r->sc; eof = desc->eof_len >> RX_BUFFER_DESC_EOF_SHIFT; diff --git a/sys/dev/thunderbolt/router.c b/sys/dev/thunderbolt/router.c index a3b418d77fac..fe7ad7026b2e 100644 --- a/sys/dev/thunderbolt/router.c +++ b/sys/dev/thunderbolt/router.c @@ -277,7 +277,8 @@ _tb_router_attach(struct router_softc *sc) { struct tb_cfg_router *cfg; uint32_t *buf; - int error, up; + int error; + int up __diagused; buf = malloc(9 * 4, M_THUNDERBOLT, M_NOWAIT|M_ZERO); if (buf == NULL) @@ -297,8 +298,9 @@ _tb_router_attach(struct router_softc *sc) sc->uuid[1] = cfg->uuid_hi; sc->uuid[2] = 0xffffffff; sc->uuid[3] = 0xffffffff; - tb_debug(sc, DBG_ROUTER, "Router upstream_port= %d, max_port= %d, " - "depth= %d\n", up, sc->max_adap, sc->depth); + tb_debug(sc, DBG_ROUTER, + "Router upstream_port= %d, max_port= %d, depth= %d\n", + up, sc->max_adap, sc->depth); free(buf, M_THUNDERBOLT); /* Downstream adapters are indexed in the array allocated here. */ @@ -718,7 +720,8 @@ router_notify_intr(void *context, union nhi_ring_desc *ring, struct nhi_cmd_fram struct router_softc *sc; struct router_command *cmd; struct tb_cfg_notify event; - u_int ev, adap; + u_int adap __diagused; + u_int ev; KASSERT(context != NULL, ("context cannot be NULL\n")); diff --git a/sys/dev/thunderbolt/tb_acpi_pcib.c b/sys/dev/thunderbolt/tb_acpi_pcib.c index 947df3688535..57ad916d4435 100644 --- a/sys/dev/thunderbolt/tb_acpi_pcib.c +++ b/sys/dev/thunderbolt/tb_acpi_pcib.c @@ -120,7 +120,7 @@ tb_acpi_pcib_attach(device_t dev) ACPI_OBJECT_LIST list; ACPI_OBJECT arg; ACPI_BUFFER buf; - ACPI_STATUS s; + ACPI_STATUS s __diagused; tb_debug(sc, DBG_BRIDGE, "Executing OSUP\n"); diff --git a/sys/dev/thunderbolt/tb_debug.c b/sys/dev/thunderbolt/tb_debug.c index f455ee72e9f6..fe65b2a5c034 100644 --- a/sys/dev/thunderbolt/tb_debug.c +++ b/sys/dev/thunderbolt/tb_debug.c @@ -206,7 +206,7 @@ int tb_debug_sysctl(SYSCTL_HANDLER_ARGS) { struct sbuf *sbuf; -#if defined (THUNDERBOLT_DEBUG) && (THUNDERBOLT_DEBUG > 0) +#ifdef THUNDERBOLT_DEBUG struct tb_debug_string *string; char *buffer; size_t sz; @@ -221,7 +221,7 @@ tb_debug_sysctl(SYSCTL_HANDLER_ARGS) sbuf = sbuf_new_for_sysctl(NULL, NULL, 128, req); -#if defined (THUNDERBOLT_DEBUG) && (THUNDERBOLT_DEBUG > 0) +#ifdef THUNDERBOLT_DEBUG debug = (u_int *)arg1; sbuf_printf(sbuf, "%#x", *debug); @@ -317,7 +317,7 @@ tb_parse_debug(u_int *debug, char *list) void tbdbg_dprintf(device_t dev, u_int debug, u_int val, const char *fmt, ...) { -#if defined(THUNDERBOLT_DEBUG) && (THUNDERBOLT_DEBUG > 0) +#ifdef THUNDERBOLT_DEBUG va_list ap; u_int lvl, dbg; diff --git a/sys/dev/thunderbolt/tb_debug.h b/sys/dev/thunderbolt/tb_debug.h index 4f5584420882..6ce479a42389 100644 --- a/sys/dev/thunderbolt/tb_debug.h +++ b/sys/dev/thunderbolt/tb_debug.h @@ -81,7 +81,7 @@ enum { */ void tbdbg_dprintf(device_t dev, u_int debug, u_int val, const char *fmt, ...) __printflike(4, 5); -#if defined(THUNDERBOLT_DEBUG) && (THUNDERBOLT_DEBUG > 0) +#ifdef THUNDERBOLT_DEBUG #define tb_debug(sc, level, fmt...) \ tbdbg_dprintf((sc)->dev, (sc)->debug, level, ##fmt) #else diff --git a/sys/dev/thunderbolt/tb_pcib.c b/sys/dev/thunderbolt/tb_pcib.c index b30de5a7493c..876722a0076d 100644 --- a/sys/dev/thunderbolt/tb_pcib.c +++ b/sys/dev/thunderbolt/tb_pcib.c @@ -304,7 +304,7 @@ static int tb_pcib_detach(device_t dev) { struct tb_pcib_softc *sc; - int error; + int error __diagused; sc = device_get_softc(dev); @@ -548,16 +548,13 @@ tb_pci_probe(device_t dev) { struct tb_pcib_ident *n; device_t parent; - devclass_t dc; /* * This driver is only valid if the parent device is a PCI-PCI - * bridge. To determine that, check if the grandparent is a - * PCI bus. + * bridge. */ parent = device_get_parent(dev); - dc = device_get_devclass(device_get_parent(parent)); - if (strcmp(devclass_get_name(dc), "pci") != 0) + if (!is_pci_device(parent)) return (ENXIO); if ((n = tb_pcib_find_ident(parent)) != NULL) { diff --git a/sys/dev/thunderbolt/tbcfg_reg.h b/sys/dev/thunderbolt/tbcfg_reg.h index bb68faa543b0..6ae5c6fea7fa 100644 --- a/sys/dev/thunderbolt/tbcfg_reg.h +++ b/sys/dev/thunderbolt/tbcfg_reg.h @@ -52,7 +52,7 @@ struct tb_cfg_read { uint32_t crc; }; -/* Config space read request, 6.4.2.4 */ +/* Config space read response, 6.4.2.4 */ struct tb_cfg_read_resp { tb_route_t route; uint32_t addr_attrs; diff --git a/sys/dev/uart/uart_dev_ns8250.c b/sys/dev/uart/uart_dev_ns8250.c index c13eabe9055e..d6940dc80005 100644 --- a/sys/dev/uart/uart_dev_ns8250.c +++ b/sys/dev/uart/uart_dev_ns8250.c @@ -529,40 +529,40 @@ UART_CLASS(uart_ns8250_class); */ #ifdef DEV_ACPI static struct acpi_spcr_compat_data acpi_spcr_compat_data[] = { - { &uart_ns8250_class, ACPI_DBG2_16550_COMPATIBLE }, - { &uart_ns8250_class, ACPI_DBG2_16550_SUBSET }, - { &uart_ns8250_class, ACPI_DBG2_16550_WITH_GAS }, + { &uart_ns8250_class, ACPI_DBG2_16550_COMPATIBLE }, + { &uart_ns8250_class, ACPI_DBG2_16550_SUBSET }, + { &uart_ns8250_class, ACPI_DBG2_16550_WITH_GAS }, { NULL, 0 }, }; UART_ACPI_SPCR_CLASS(acpi_spcr_compat_data); static struct acpi_uart_compat_data acpi_compat_data[] = { {"AMD0020", &uart_ns8250_class, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"}, - {"AMDI0020", &uart_ns8250_class, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"}, - {"APMC0D08", &uart_ns8250_class, 2, 4, 0, 0, "APM compatible UART"}, - {"MRVL0001", &uart_ns8250_class, 2, 0, 200000000, UART_F_BUSY_DETECT, "Marvell / Synopsys Designware UART"}, - {"SCX0006", &uart_ns8250_class, 2, 0, 62500000, UART_F_BUSY_DETECT, "SynQuacer / Synopsys Designware UART"}, - {"HISI0031", &uart_ns8250_class, 2, 0, 200000000, UART_F_BUSY_DETECT, "HiSilicon / Synopsys Designware UART"}, - {"INTC1006", &uart_ns8250_class, 2, 0, 25000000, 0, "Intel ARM64 UART"}, - {"NXP0018", &uart_ns8250_class, 0, 0, 350000000, UART_F_BUSY_DETECT, "NXP / Synopsys Designware UART"}, - {"PNP0500", &uart_ns8250_class, 0, 0, 0, 0, "Standard PC COM port"}, - {"PNP0501", &uart_ns8250_class, 0, 0, 0, 0, "16550A-compatible COM port"}, - {"PNP0502", &uart_ns8250_class, 0, 0, 0, 0, "Multiport serial device (non-intelligent 16550)"}, - {"PNP0510", &uart_ns8250_class, 0, 0, 0, 0, "Generic IRDA-compatible device"}, - {"PNP0511", &uart_ns8250_class, 0, 0, 0, 0, "Generic IRDA-compatible device"}, - {"WACF004", &uart_ns8250_class, 0, 0, 0, 0, "Wacom Tablet PC Screen"}, - {"WACF00E", &uart_ns8250_class, 0, 0, 0, 0, "Wacom Tablet PC Screen 00e"}, - {"FUJ02E5", &uart_ns8250_class, 0, 0, 0, 0, "Wacom Tablet at FuS Lifebook T"}, - {NULL, NULL, 0 , 0, 0, 0, NULL}, + {"AMDI0020", &uart_ns8250_class, 2, 0, 48000000, UART_F_BUSY_DETECT, "AMD / Synopsys Designware UART"}, + {"APMC0D08", &uart_ns8250_class, 2, 4, 0, 0, "APM compatible UART"}, + {"MRVL0001", &uart_ns8250_class, 2, 0, 200000000, UART_F_BUSY_DETECT, "Marvell / Synopsys Designware UART"}, + {"SCX0006", &uart_ns8250_class, 2, 0, 62500000, UART_F_BUSY_DETECT, "SynQuacer / Synopsys Designware UART"}, + {"HISI0031", &uart_ns8250_class, 2, 0, 200000000, UART_F_BUSY_DETECT, "HiSilicon / Synopsys Designware UART"}, + {"INTC1006", &uart_ns8250_class, 2, 0, 25000000, 0, "Intel ARM64 UART"}, + {"NXP0018", &uart_ns8250_class, 0, 0, 350000000, UART_F_BUSY_DETECT, "NXP / Synopsys Designware UART"}, + {"PNP0500", &uart_ns8250_class, 0, 0, 0, 0, "Standard PC COM port"}, + {"PNP0501", &uart_ns8250_class, 0, 0, 0, 0, "16550A-compatible COM port"}, + {"PNP0502", &uart_ns8250_class, 0, 0, 0, 0, "Multiport serial device (non-intelligent 16550)"}, + {"PNP0510", &uart_ns8250_class, 0, 0, 0, 0, "Generic IRDA-compatible device"}, + {"PNP0511", &uart_ns8250_class, 0, 0, 0, 0, "Generic IRDA-compatible device"}, + {"WACF004", &uart_ns8250_class, 0, 0, 0, 0, "Wacom Tablet PC Screen"}, + {"WACF00E", &uart_ns8250_class, 0, 0, 0, 0, "Wacom Tablet PC Screen 00e"}, + {"FUJ02E5", &uart_ns8250_class, 0, 0, 0, 0, "Wacom Tablet at FuS Lifebook T"}, + {NULL, NULL, 0, 0, 0, 0, NULL}, }; UART_ACPI_CLASS_AND_DEVICE(acpi_compat_data); #endif #ifdef FDT static struct ofw_compat_data compat_data[] = { - {"ns16550", (uintptr_t)&uart_ns8250_class}, - {"ns16550a", (uintptr_t)&uart_ns8250_class}, - {NULL, (uintptr_t)NULL}, + {"ns16550", (uintptr_t)&uart_ns8250_class}, + {"ns16550a", (uintptr_t)&uart_ns8250_class}, + {NULL, (uintptr_t)NULL}, }; UART_FDT_CLASS_AND_DEVICE(compat_data); #endif diff --git a/sys/dev/uart/uart_dev_pl011.c b/sys/dev/uart/uart_dev_pl011.c index ae3c4d3218cf..f0d7bcda1fa4 100644 --- a/sys/dev/uart/uart_dev_pl011.c +++ b/sys/dev/uart/uart_dev_pl011.c @@ -382,32 +382,32 @@ static struct uart_class uart_pl011_class = { }; UART_CLASS(uart_pl011_class); -#ifdef FDT -static struct ofw_compat_data fdt_compat_data[] = { - {"arm,pl011", (uintptr_t)&uart_pl011_class}, - {NULL, (uintptr_t)NULL}, -}; -UART_FDT_CLASS_AND_DEVICE(fdt_compat_data); -#endif - #ifdef DEV_ACPI static struct acpi_spcr_compat_data acpi_spcr_compat_data[] = { - { &uart_pl011_class, ACPI_DBG2_ARM_PL011 }, - { &uart_pl011_class, ACPI_DBG2_ARM_SBSA_GENERIC }, - { &uart_pl011_class, ACPI_DBG2_ARM_SBSA_32BIT }, + { &uart_pl011_class, ACPI_DBG2_ARM_PL011 }, + { &uart_pl011_class, ACPI_DBG2_ARM_SBSA_GENERIC }, + { &uart_pl011_class, ACPI_DBG2_ARM_SBSA_32BIT }, { NULL, 0 }, }; UART_ACPI_SPCR_CLASS(acpi_spcr_compat_data); static struct acpi_uart_compat_data acpi_compat_data[] = { - {"ARMH0011", &uart_pl011_class, 2, 0, 0, 0, "uart pl011"}, - {"ARMHB000", &uart_pl011_class, 2, 0, 0, 0, "uart pl011"}, - {"ARMHB000", &uart_pl011_class, 2, 0, 0, 0, "uart pl011"}, - {NULL, NULL, 0, 0, 0, 0, NULL}, + {"ARMH0011", &uart_pl011_class, 2, 0, 0, 0, "uart pl011"}, + {"ARMHB000", &uart_pl011_class, 2, 0, 0, 0, "uart pl011"}, + {"ARMHB000", &uart_pl011_class, 2, 0, 0, 0, "uart pl011"}, + {NULL, NULL, 0, 0, 0, 0, NULL}, }; UART_ACPI_CLASS_AND_DEVICE(acpi_compat_data); #endif +#ifdef FDT +static struct ofw_compat_data fdt_compat_data[] = { + {"arm,pl011", (uintptr_t)&uart_pl011_class}, + {NULL, (uintptr_t)NULL}, +}; +UART_FDT_CLASS_AND_DEVICE(fdt_compat_data); +#endif + static int uart_pl011_bus_attach(struct uart_softc *sc) { diff --git a/sys/dev/ufshci/ufshci_private.h b/sys/dev/ufshci/ufshci_private.h index 067b51a419e8..8d18fab982d7 100644 --- a/sys/dev/ufshci/ufshci_private.h +++ b/sys/dev/ufshci/ufshci_private.h @@ -262,11 +262,11 @@ static const struct ufshci_power_entry power_map[POWER_STYPE_COUNT] = { UFSHCI_UIC_LINK_STATE_ACTIVE }, [POWER_STYPE_STANDBY] = { UFSHCI_DEV_PWR_SLEEP, SSS_PC_IDLE, UFSHCI_UIC_LINK_STATE_HIBERNATE }, - [POWER_STYPE_SUSPEND_TO_MEM] = { UFSHCI_DEV_PWR_POWERDOWN, + [POWER_STYPE_FW_SUSPEND] = { UFSHCI_DEV_PWR_POWERDOWN, SSS_PC_STANDBY, UFSHCI_UIC_LINK_STATE_HIBERNATE }, [POWER_STYPE_SUSPEND_TO_IDLE] = { UFSHCI_DEV_PWR_SLEEP, SSS_PC_IDLE, UFSHCI_UIC_LINK_STATE_HIBERNATE }, - [POWER_STYPE_HIBERNATE] = { UFSHCI_DEV_PWR_DEEPSLEEP, 0x40, + [POWER_STYPE_FW_HIBERNATE] = { UFSHCI_DEV_PWR_DEEPSLEEP, 0x40, UFSHCI_UIC_LINK_STATE_OFF }, [POWER_STYPE_POWEROFF] = { UFSHCI_DEV_PWR_POWERDOWN, SSS_PC_STANDBY, UFSHCI_UIC_LINK_STATE_OFF }, diff --git a/sys/dev/usb/controller/xhci.c b/sys/dev/usb/controller/xhci.c index 3dad0985b39d..b522c5fdc5a3 100644 --- a/sys/dev/usb/controller/xhci.c +++ b/sys/dev/usb/controller/xhci.c @@ -3898,10 +3898,8 @@ xhci_configure_reset_endpoint(struct usb_xfer *xfer) */ switch (xhci_get_endpoint_state(udev, epno)) { case XHCI_EPCTX_0_EPSTATE_DISABLED: - drop = 0; - break; case XHCI_EPCTX_0_EPSTATE_STOPPED: - drop = 1; + drop = 0; break; case XHCI_EPCTX_0_EPSTATE_HALTED: err = xhci_cmd_reset_ep(sc, 0, epno, index); @@ -3910,9 +3908,15 @@ xhci_configure_reset_endpoint(struct usb_xfer *xfer) DPRINTF("Could not reset endpoint %u\n", epno); break; default: - drop = 1; + /* + * xHCI spec 4.6.8: + * The Drop and Add operation resets the toggle bit, which can + * cause a toggle mismatch between the device and host. As a + * result, xHCI may refuse to receive or process the packet. + */ err = xhci_cmd_stop_ep(sc, 0, epno, index); - if (err != 0) + drop = (err != 0); + if (drop) DPRINTF("Could not stop endpoint %u\n", epno); break; } diff --git a/sys/dev/usb/input/ukbd.c b/sys/dev/usb/input/ukbd.c index 104e51c082c3..d012af99fee4 100644 --- a/sys/dev/usb/input/ukbd.c +++ b/sys/dev/usb/input/ukbd.c @@ -957,13 +957,6 @@ ukbd_set_leds_callback(struct usb_xfer *xfer, usb_error_t error) break; sc->sc_flags &= ~UKBD_FLAG_SET_LEDS; - req.bmRequestType = UT_WRITE_CLASS_INTERFACE; - req.bRequest = UR_SET_REPORT; - USETW2(req.wValue, UHID_OUTPUT_REPORT, 0); - req.wIndex[0] = sc->sc_iface_no; - req.wIndex[1] = 0; - req.wLength[1] = 0; - memset(sc->sc_buffer, 0, UKBD_BUFFER_SIZE); id = 0; @@ -1017,11 +1010,18 @@ ukbd_set_leds_callback(struct usb_xfer *xfer, usb_error_t error) } else { usbd_copy_in(pc, 0, sc->sc_buffer + 1, len); } - req.wLength[0] = len; usbd_xfer_set_frame_len(xfer, 1, len); DPRINTF("len=%d, id=%d\n", len, id); + req.bmRequestType = UT_WRITE_CLASS_INTERFACE; + req.bRequest = UR_SET_REPORT; + USETW2(req.wValue, UHID_OUTPUT_REPORT, id); + req.wIndex[0] = sc->sc_iface_no; + req.wIndex[1] = 0; + req.wLength[0] = len; + req.wLength[1] = 0; + /* setup control request last */ pc = usbd_xfer_get_frame(xfer, 0); usbd_copy_in(pc, 0, &req, sizeof(req)); diff --git a/sys/dev/usb/net/if_smsc.c b/sys/dev/usb/net/if_smsc.c index 8e16b8609144..c3c21fd22472 100644 --- a/sys/dev/usb/net/if_smsc.c +++ b/sys/dev/usb/net/if_smsc.c @@ -1296,7 +1296,7 @@ smsc_phy_init(struct smsc_softc *sc) } while ((bmcr & BMCR_RESET) && ((ticks - start_ticks) < max_ticks)); if (((usb_ticks_t)(ticks - start_ticks)) >= max_ticks) { - smsc_err_printf(sc, "PHY reset timed-out"); + smsc_err_printf(sc, "PHY reset timed-out\n"); return (EIO); } diff --git a/sys/dev/usb/serial/u3g.c b/sys/dev/usb/serial/u3g.c index 0fc774d83ee1..6e3d9395359b 100644 --- a/sys/dev/usb/serial/u3g.c +++ b/sys/dev/usb/serial/u3g.c @@ -624,6 +624,8 @@ static const STRUCT_USB_HOST_ID u3g_devs[] = { U3G_DEV(TCTMOBILE, X080S, U3GINIT_TCT), U3G_DEV(TELIT, UC864E, 0), U3G_DEV(TELIT, UC864G, 0), + U3G_DEV(TELIT, LM960, 0), + U3G_DEV(TELIT, LM960_ECM, 0), U3G_DEV(TLAYTECH, TEU800, 0), U3G_DEV(TOSHIBA, G450, 0), U3G_DEV(TOSHIBA, HSDPA, 0), diff --git a/sys/dev/usb/usb_transfer.c b/sys/dev/usb/usb_transfer.c index 67745cf49397..d41121ed3a06 100644 --- a/sys/dev/usb/usb_transfer.c +++ b/sys/dev/usb/usb_transfer.c @@ -1889,8 +1889,10 @@ usbd_transfer_submit(struct usb_xfer *xfer) */ #if USB_HAVE_BUSDMA if (xfer->flags_int.bdma_enable) { + USB_BUS_LOCK(bus); /* insert the USB transfer last in the BUS-DMA queue */ usb_command_wrapper(&xfer->xroot->dma_q, xfer); + USB_BUS_UNLOCK(bus); return; } #endif diff --git a/sys/dev/usb/usbdevs b/sys/dev/usb/usbdevs index 594afafbb07f..7a9c7431f53d 100644 --- a/sys/dev/usb/usbdevs +++ b/sys/dev/usb/usbdevs @@ -1792,6 +1792,7 @@ product DLINK DWA182C1 0x3315 DWA-182 rev C1 product DLINK DWA180A1 0x3316 DWA-180 rev A1 product DLINK DWA172A1 0x3318 DWA-172 rev A1 product DLINK DWA131E1 0x3319 DWA-131 rev E1 +product DLINK DWA121B1 0x331b DWA-121 rev B1 product DLINK DWA182D1 0x331c DWA-182 rev D1 product DLINK DWA181A1 0x331e DWA-181 rev A1 product DLINK DWL122 0x3700 DWL-122 @@ -4807,6 +4808,8 @@ product TELEX MIC1 0x0001 Enhanced USB Microphone /* Telit products */ product TELIT UC864E 0x1003 UC864E 3G modem product TELIT UC864G 0x1004 UC864G 3G modem +product TELIT LM960 0x1040 LM960A18 LTE modem (RNDIS) +product TELIT LM960_ECM 0x1042 LM960A18 LTE modem (ECM) /* Ten X Technology, Inc. */ product TENX UAUDIO0 0xf211 USB audio headset @@ -4860,6 +4863,7 @@ product TPLINK T2UV3 0x011f Archer T2U ver 3 product TPLINK T2UPLUS 0x0120 Archer T2U Plus product TPLINK RTL8153 0x0601 RTL8153 USB 10/100/1000 LAN product TPLINK RTL8153_2 0x0602 RTL8153 USB 10/100/1000 LAN +product TPLINK UB500 0x0604 UB500 RTL8761BUV Bluetooth /* Trek Technology products */ product TREK THUMBDRIVE 0x1111 ThumbDrive diff --git a/sys/dev/virtio/network/if_vtnet.c b/sys/dev/virtio/network/if_vtnet.c index 40792482672c..ef01833b9e03 100644 --- a/sys/dev/virtio/network/if_vtnet.c +++ b/sys/dev/virtio/network/if_vtnet.c @@ -96,17 +96,6 @@ #define VTNET_ETHER_ALIGN ETHER_ALIGN #endif -/* - * Worst case offset to ensure header doesn't share any cache lines with - * payload. - */ -#define VTNET_RX_BUFFER_HEADER_OFFSET 128 - -struct vtnet_rx_buffer_header { - bus_addr_t addr; - bus_dmamap_t dmap; -}; - static int vtnet_modevent(module_t, int, void *); static int vtnet_probe(device_t); @@ -219,7 +208,7 @@ static void vtnet_init_locked(struct vtnet_softc *, int); static void vtnet_init(void *); static void vtnet_free_ctrl_vq(struct vtnet_softc *); -static int vtnet_exec_ctrl_cmd(struct vtnet_softc *, uint8_t *, +static void vtnet_exec_ctrl_cmd(struct vtnet_softc *, void *, struct sglist *, int, int); static int vtnet_ctrl_mac_cmd(struct vtnet_softc *, uint8_t *); static int vtnet_ctrl_guest_offloads(struct vtnet_softc *, uint64_t); @@ -395,17 +384,6 @@ MODULE_DEPEND(vtnet, netmap, 1, 1, 1); VIRTIO_SIMPLE_PNPINFO(vtnet, VIRTIO_ID_NETWORK, "VirtIO Networking Adapter"); -static struct vtnet_rx_buffer_header * -vtnet_mbuf_to_rx_buffer_header(struct vtnet_softc *sc, struct mbuf *m) -{ - if (VTNET_ETHER_ALIGN != 0 && sc->vtnet_hdr_size % 4 == 0) - return (struct vtnet_rx_buffer_header *)((uintptr_t)m->m_data - - VTNET_RX_BUFFER_HEADER_OFFSET - VTNET_ETHER_ALIGN); - else - return (struct vtnet_rx_buffer_header *)((uintptr_t)m->m_data - - VTNET_RX_BUFFER_HEADER_OFFSET); -} - static int vtnet_modevent(module_t mod __unused, int type, void *unused __unused) { @@ -479,106 +457,6 @@ vtnet_attach(device_t dev) goto fail; } - mtx_init(&sc->vtnet_rx_mtx, device_get_nameunit(dev), - "VirtIO Net RX lock", MTX_DEF); - - error = bus_dma_tag_create( - bus_get_dma_tag(dev), /* parent */ - sizeof(uint16_t), /* alignment */ - 0, /* boundary */ - BUS_SPACE_MAXADDR, /* lowaddr */ - BUS_SPACE_MAXADDR, /* highaddr */ - NULL, NULL, /* filter, filterarg */ - MJUM9BYTES, /* max request size */ - 1, /* max # segments */ - MJUM9BYTES, /* maxsegsize - worst case */ - BUS_DMA_COHERENT, /* flags */ - busdma_lock_mutex, /* lockfunc */ - &sc->vtnet_rx_mtx, /* lockarg */ - &sc->vtnet_rx_dmat); - if (error) { - device_printf(dev, "cannot create bus_dma_tag\n"); - goto fail; - } - - mtx_init(&sc->vtnet_tx_mtx, device_get_nameunit(dev), - "VirtIO Net TX lock", MTX_DEF); - - error = bus_dma_tag_create( - bus_get_dma_tag(dev), /* parent */ - sizeof(uint16_t), /* alignment */ - 0, /* boundary */ - BUS_SPACE_MAXADDR, /* lowaddr */ - BUS_SPACE_MAXADDR, /* highaddr */ - NULL, NULL, /* filter, filterarg */ - sc->vtnet_tx_nsegs * MJUM9BYTES, /* max request size */ - sc->vtnet_tx_nsegs, /* max # segments */ - MJUM9BYTES, /* maxsegsize */ - BUS_DMA_COHERENT, /* flags */ - busdma_lock_mutex, /* lockfunc */ - &sc->vtnet_tx_mtx, /* lockarg */ - &sc->vtnet_tx_dmat); - if (error) { - device_printf(dev, "cannot create bus_dma_tag\n"); - goto fail; - } - - mtx_init(&sc->vtnet_hdr_mtx, device_get_nameunit(dev), - "VirtIO Net header lock", MTX_DEF); - - error = bus_dma_tag_create( - bus_get_dma_tag(dev), /* parent */ - sizeof(uint16_t), /* alignment */ - 0, /* boundary */ - BUS_SPACE_MAXADDR, /* lowaddr */ - BUS_SPACE_MAXADDR, /* highaddr */ - NULL, NULL, /* filter, filterarg */ - PAGE_SIZE, /* max request size */ - 1, /* max # segments */ - PAGE_SIZE, /* maxsegsize */ - BUS_DMA_COHERENT, /* flags */ - busdma_lock_mutex, /* lockfunc */ - &sc->vtnet_hdr_mtx, /* lockarg */ - &sc->vtnet_hdr_dmat); - if (error) { - device_printf(dev, "cannot create bus_dma_tag\n"); - goto fail; - } - - mtx_init(&sc->vtnet_ack_mtx, device_get_nameunit(dev), - "VirtIO Net ACK lock", MTX_DEF); - - error = bus_dma_tag_create( - bus_get_dma_tag(dev), /* parent */ - sizeof(uint8_t), /* alignment */ - 0, /* boundary */ - BUS_SPACE_MAXADDR, /* lowaddr */ - BUS_SPACE_MAXADDR, /* highaddr */ - NULL, NULL, /* filter, filterarg */ - sizeof(uint8_t), /* max request size */ - 1, /* max # segments */ - sizeof(uint8_t), /* maxsegsize */ - BUS_DMA_COHERENT, /* flags */ - busdma_lock_mutex, /* lockfunc */ - &sc->vtnet_ack_mtx, /* lockarg */ - &sc->vtnet_ack_dmat); - if (error) { - device_printf(dev, "cannot create bus_dma_tag\n"); - goto fail; - } - -#ifdef __powerpc__ - /* - * Virtio uses physical addresses rather than bus addresses, so we - * need to ask busdma to skip the iommu physical->bus mapping. At - * present, this is only a thing on the powerpc architectures. - */ - bus_dma_tag_set_iommu(sc->vtnet_rx_dmat, NULL, NULL); - bus_dma_tag_set_iommu(sc->vtnet_tx_dmat, NULL, NULL); - bus_dma_tag_set_iommu(sc->vtnet_hdr_dmat, NULL, NULL); - bus_dma_tag_set_iommu(sc->vtnet_ack_dmat, NULL, NULL); -#endif - error = vtnet_alloc_rx_filters(sc); if (error) { device_printf(dev, "cannot allocate Rx filters\n"); @@ -1667,11 +1545,6 @@ static struct mbuf * vtnet_rx_alloc_buf(struct vtnet_softc *sc, int nbufs, struct mbuf **m_tailp) { struct mbuf *m_head, *m_tail, *m; - struct vtnet_rx_buffer_header *vthdr; - bus_dma_segment_t segs[1]; - bus_dmamap_t dmap; - int nsegs; - int err; int i, size; m_head = NULL; @@ -1689,43 +1562,13 @@ vtnet_rx_alloc_buf(struct vtnet_softc *sc, int nbufs, struct mbuf **m_tailp) } m->m_len = size; - vthdr = (struct vtnet_rx_buffer_header *)m->m_data; - - /* Reserve space for header */ - m_adj(m, VTNET_RX_BUFFER_HEADER_OFFSET); - /* * Need to offset the mbuf if the header we're going to add * will misalign. */ - if (VTNET_ETHER_ALIGN != 0 && sc->vtnet_hdr_size % 4 == 0) + if (VTNET_ETHER_ALIGN != 0 && sc->vtnet_hdr_size % 4 == 0) { m_adj(m, VTNET_ETHER_ALIGN); - - err = bus_dmamap_create(sc->vtnet_rx_dmat, 0, &dmap); - if (err) { - printf("Failed to create dmamap, err :%d\n", - err); - m_freem(m); - return (NULL); - } - - nsegs = 0; - err = bus_dmamap_load_mbuf_sg(sc->vtnet_rx_dmat, dmap, m, segs, - &nsegs, BUS_DMA_NOWAIT); - if (err != 0) { - printf("Failed to map mbuf into DMA visible memory, err: %d\n", - err); - m_freem(m); - bus_dmamap_destroy(sc->vtnet_rx_dmat, dmap); - return (NULL); } - KASSERT(nsegs == 1, - ("%s: unexpected number of DMA segments for rx buffer: %d", - __func__, nsegs)); - - vthdr->addr = segs[0].ds_addr; - vthdr->dmap = dmap; - if (m_head != NULL) { m_tail->m_next = m; m_tail = m; @@ -1751,7 +1594,7 @@ vtnet_rxq_replace_lro_nomrg_buf(struct vtnet_rxq *rxq, struct mbuf *m0, int len, clustersz, nreplace, error; sc = rxq->vtnrx_sc; - clustersz = sc->vtnet_rx_clustersz - VTNET_RX_BUFFER_HEADER_OFFSET; + clustersz = sc->vtnet_rx_clustersz; /* * Need to offset the mbuf if the header we're going to add will * misalign, account for that here. @@ -1866,12 +1709,9 @@ vtnet_rxq_replace_buf(struct vtnet_rxq *rxq, struct mbuf *m, int len) static int vtnet_rxq_enqueue_buf(struct vtnet_rxq *rxq, struct mbuf *m) { - struct vtnet_rx_buffer_header *hdr; struct vtnet_softc *sc; struct sglist *sg; int header_inlined, error; - bus_addr_t paddr; - struct mbuf *mp; sc = rxq->vtnrx_sc; sg = rxq->vtnrx_sg; @@ -1884,38 +1724,28 @@ vtnet_rxq_enqueue_buf(struct vtnet_rxq *rxq, struct mbuf *m) header_inlined = vtnet_modern(sc) || (sc->vtnet_flags & VTNET_FLAG_MRG_RXBUFS) != 0; /* TODO: ANY_LAYOUT */ - hdr = vtnet_mbuf_to_rx_buffer_header(sc, m); - paddr = hdr->addr; - /* * Note: The mbuf has been already adjusted when we allocate it if we * have to do strict alignment. */ - if (header_inlined) { - error = sglist_append_phys(sg, paddr, m->m_len); - } else { + if (header_inlined) + error = sglist_append_mbuf(sg, m); + else { + struct vtnet_rx_header *rxhdr = + mtod(m, struct vtnet_rx_header *); MPASS(sc->vtnet_hdr_size == sizeof(struct virtio_net_hdr)); /* Append the header and remaining mbuf data. */ - error = sglist_append_phys(sg, paddr, sc->vtnet_hdr_size); + error = sglist_append(sg, &rxhdr->vrh_hdr, sc->vtnet_hdr_size); if (error) return (error); - error = sglist_append_phys(sg, - paddr + sizeof(struct vtnet_rx_header), + error = sglist_append(sg, &rxhdr[1], m->m_len - sizeof(struct vtnet_rx_header)); if (error) return (error); - mp = m->m_next; - while (mp) { - hdr = vtnet_mbuf_to_rx_buffer_header(sc, mp); - paddr = hdr->addr; - error = sglist_append_phys(sg, paddr, mp->m_len); - if (error) - return (error); - - mp = mp->m_next; - } + if (m->m_next != NULL) + error = sglist_append_mbuf(sg, m->m_next); } if (error) @@ -2101,7 +1931,6 @@ vtnet_rxq_merged_eof(struct vtnet_rxq *rxq, struct mbuf *m_head, int nbufs) m_tail = m_head; while (--nbufs > 0) { - struct vtnet_rx_buffer_header *vthdr; struct mbuf *m; uint32_t len; @@ -2111,10 +1940,6 @@ vtnet_rxq_merged_eof(struct vtnet_rxq *rxq, struct mbuf *m_head, int nbufs) goto fail; } - vthdr = vtnet_mbuf_to_rx_buffer_header(sc, m); - bus_dmamap_sync(sc->vtnet_rx_dmat, vthdr->dmap, - BUS_DMASYNC_POSTREAD); - if (vtnet_rxq_new_buf(rxq) != 0) { rxq->vtnrx_stats.vrxs_iqdrops++; vtnet_rxq_discard_buf(rxq, m); @@ -2235,7 +2060,6 @@ static int vtnet_rxq_eof(struct vtnet_rxq *rxq) { struct virtio_net_hdr lhdr, *hdr; - struct vtnet_rx_buffer_header *vthdr; struct vtnet_softc *sc; if_t ifp; struct virtqueue *vq; @@ -2251,31 +2075,14 @@ vtnet_rxq_eof(struct vtnet_rxq *rxq) CURVNET_SET(if_getvnet(ifp)); while (count-- > 0) { - struct mbuf *m, *mp; + struct mbuf *m; uint32_t len, nbufs, adjsz; - uint32_t synced; m = virtqueue_dequeue(vq, &len); if (m == NULL) break; deq++; - mp = m; - - /* - * Sync all mbufs in this packet. There will only be a single - * mbuf unless LRO is in use. - */ - synced = 0; - while (mp && synced < len) { - vthdr = vtnet_mbuf_to_rx_buffer_header(sc, mp); - bus_dmamap_sync(sc->vtnet_rx_dmat, vthdr->dmap, - BUS_DMASYNC_POSTREAD); - - synced += mp->m_len; - mp = mp->m_next; - } - if (len < sc->vtnet_hdr_size + ETHER_HDR_LEN) { rxq->vtnrx_stats.vrxs_ierrors++; vtnet_rxq_discard_buf(rxq, m); @@ -2535,14 +2342,6 @@ vtnet_txq_free_mbufs(struct vtnet_txq *txq) while ((txhdr = virtqueue_drain(vq, &last)) != NULL) { if (kring == NULL) { - bus_dmamap_unload(txq->vtntx_sc->vtnet_tx_dmat, - txhdr->dmap); - bus_dmamap_destroy(txq->vtntx_sc->vtnet_tx_dmat, - txhdr->dmap); - bus_dmamap_unload(txq->vtntx_sc->vtnet_tx_dmat, - txhdr->hdr_dmap); - bus_dmamap_destroy(txq->vtntx_sc->vtnet_tx_dmat, - txhdr->hdr_dmap); m_freem(txhdr->vth_mbuf); uma_zfree(vtnet_tx_header_zone, txhdr); } @@ -2712,36 +2511,15 @@ drop: return (NULL); } -static void -vtnet_txq_enqueue_callback(void *arg, bus_dma_segment_t *segs, - int nsegs, int error) -{ - vm_paddr_t *hdr_paddr; - - if (error != 0) - return; - - KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); - - hdr_paddr = (vm_paddr_t *)arg; - *hdr_paddr = segs[0].ds_addr; -} - static int vtnet_txq_enqueue_buf(struct vtnet_txq *txq, struct mbuf **m_head, struct vtnet_tx_header *txhdr) { - bus_dma_segment_t segs[VTNET_TX_SEGS_MAX]; - int nsegs; struct vtnet_softc *sc; struct virtqueue *vq; struct sglist *sg; struct mbuf *m; int error; - vm_paddr_t hdr_paddr; - bus_dmamap_t hdr_dmap; - bus_dmamap_t dmap; - int i; sc = txq->vtntx_sc; vq = txq->vtntx_vq; @@ -2749,55 +2527,15 @@ vtnet_txq_enqueue_buf(struct vtnet_txq *txq, struct mbuf **m_head, m = *m_head; sglist_reset(sg); - - error = bus_dmamap_create(sc->vtnet_tx_dmat, 0, &hdr_dmap); - if (error) - goto fail; - - error = bus_dmamap_load(sc->vtnet_tx_dmat, hdr_dmap, &txhdr->vth_uhdr, - sc->vtnet_hdr_size, vtnet_txq_enqueue_callback, &hdr_paddr, - BUS_DMA_NOWAIT); - if (error) - goto fail_hdr_dmamap_destroy; - - error = sglist_append_phys(sg, hdr_paddr, sc->vtnet_hdr_size); + error = sglist_append(sg, &txhdr->vth_uhdr, sc->vtnet_hdr_size); if (error != 0 || sg->sg_nseg != 1) { KASSERT(0, ("%s: cannot add header to sglist error %d nseg %d", __func__, error, sg->sg_nseg)); - goto fail_hdr_dmamap_unload; + goto fail; } - bus_dmamap_sync(sc->vtnet_tx_dmat, hdr_dmap, BUS_DMASYNC_PREWRITE); - - error = bus_dmamap_create(sc->vtnet_tx_dmat, 0, &dmap); - if (error) - goto fail_hdr_dmamap_unload; - - nsegs = 0; - error = bus_dmamap_load_mbuf_sg(sc->vtnet_tx_dmat, dmap, m, segs, - &nsegs, BUS_DMA_NOWAIT); - if (error != 0) - goto fail_dmamap_destroy; - KASSERT(nsegs <= sc->vtnet_tx_nsegs, - ("%s: unexpected number of DMA segments for tx buffer: %d (max %d)", - __func__, nsegs, sc->vtnet_tx_nsegs)); - - bus_dmamap_sync(sc->vtnet_tx_dmat, dmap, BUS_DMASYNC_PREWRITE); - - for (i = 0; i < nsegs && !error; i++) - error = sglist_append_phys(sg, segs[i].ds_addr, segs[i].ds_len); - + error = sglist_append_mbuf(sg, m); if (error) { - sglist_reset(sg); - bus_dmamap_unload(sc->vtnet_tx_dmat, dmap); - - error = sglist_append_phys(sg, hdr_paddr, sc->vtnet_hdr_size); - if (error != 0 || sg->sg_nseg != 1) { - KASSERT(0, ("%s: cannot add header to sglist error %d nseg %d", - __func__, error, sg->sg_nseg)); - goto fail_dmamap_destroy; - } - m = m_defrag(m, M_NOWAIT); if (m == NULL) { sc->vtnet_stats.tx_defrag_failed++; @@ -2807,41 +2545,16 @@ vtnet_txq_enqueue_buf(struct vtnet_txq *txq, struct mbuf **m_head, *m_head = m; sc->vtnet_stats.tx_defragged++; - nsegs = 0; - error = bus_dmamap_load_mbuf_sg(sc->vtnet_tx_dmat, dmap, m, - segs, &nsegs, BUS_DMA_NOWAIT); - if (error != 0) - goto fail_dmamap_destroy; - KASSERT(nsegs <= sc->vtnet_tx_nsegs, - ("%s: unexpected number of DMA segments for tx buffer: %d (max %d)", - __func__, nsegs, sc->vtnet_tx_nsegs)); - - bus_dmamap_sync(sc->vtnet_tx_dmat, dmap, BUS_DMASYNC_PREWRITE); - - for (i = 0; i < nsegs && !error; i++) - error = sglist_append_phys(sg, segs[i].ds_addr, - segs[i].ds_len); - + error = sglist_append_mbuf(sg, m); if (error) - goto fail_dmamap_unload; + goto fail; } txhdr->vth_mbuf = m; - txhdr->dmap = dmap; - txhdr->hdr_dmap = hdr_dmap; - error = virtqueue_enqueue(vq, txhdr, sg, sg->sg_nseg, 0); return (error); -fail_dmamap_unload: - bus_dmamap_unload(sc->vtnet_tx_dmat, dmap); -fail_dmamap_destroy: - bus_dmamap_destroy(sc->vtnet_tx_dmat, dmap); -fail_hdr_dmamap_unload: - bus_dmamap_unload(sc->vtnet_tx_dmat, hdr_dmap); -fail_hdr_dmamap_destroy: - bus_dmamap_destroy(sc->vtnet_tx_dmat, hdr_dmap); fail: m_freem(*m_head); *m_head = NULL; @@ -3797,43 +3510,10 @@ vtnet_free_ctrl_vq(struct vtnet_softc *sc) } static void -vtnet_load_callback(void *arg, bus_dma_segment_t *segs, int nsegs, - int error) -{ - bus_addr_t *paddr; - - if (error != 0) - return; - - KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); - - paddr = (bus_addr_t *)arg; - *paddr = segs[0].ds_addr; -} - -static int -vtnet_exec_ctrl_cmd(struct vtnet_softc *sc, uint8_t *ack, struct sglist *sg, - int readable, int writable) +vtnet_exec_ctrl_cmd(struct vtnet_softc *sc, void *cookie, + struct sglist *sg, int readable, int writable) { - bus_dmamap_t ack_dmap; - bus_addr_t ack_paddr; struct virtqueue *vq; - int error; - - error = bus_dmamap_create(sc->vtnet_ack_dmat, 0, &ack_dmap); - if (error) - goto error_out; - - error = bus_dmamap_load(sc->vtnet_ack_dmat, ack_dmap, ack, - sizeof(uint8_t), vtnet_load_callback, &ack_paddr, BUS_DMA_NOWAIT); - if (error) - goto error_destroy; - - bus_dmamap_sync(sc->vtnet_ack_dmat, ack_dmap, BUS_DMASYNC_PREWRITE); - - error = sglist_append_phys(sg, ack_paddr, sizeof(uint8_t)); - if (error) - goto error_unload; vq = sc->vtnet_ctrl_vq; @@ -3841,237 +3521,152 @@ vtnet_exec_ctrl_cmd(struct vtnet_softc *sc, uint8_t *ack, struct sglist *sg, VTNET_CORE_LOCK_ASSERT(sc); if (!virtqueue_empty(vq)) - goto error_unload; + return; /* * Poll for the response, but the command is likely completed before * returning from the notify. */ - if (virtqueue_enqueue(vq, (void *)ack, sg, readable, writable) == 0) { + if (virtqueue_enqueue(vq, cookie, sg, readable, writable) == 0) { virtqueue_notify(vq); virtqueue_poll(vq, NULL); } - - bus_dmamap_sync(sc->vtnet_ack_dmat, ack_dmap, BUS_DMASYNC_POSTREAD); - -error_unload: - bus_dmamap_unload(sc->vtnet_ack_dmat, ack_dmap); -error_destroy: - bus_dmamap_destroy(sc->vtnet_ack_dmat, ack_dmap); -error_out: - return (error); } static int vtnet_ctrl_mac_cmd(struct vtnet_softc *sc, uint8_t *hwaddr) { struct sglist_seg segs[3]; - bus_dmamap_t hdr_dmap; - bus_addr_t hdr_paddr; struct sglist sg; struct { struct virtio_net_ctrl_hdr hdr __aligned(2); uint8_t pad1; uint8_t addr[ETHER_ADDR_LEN] __aligned(8); uint8_t pad2; + uint8_t ack; } s; - uint8_t ack; int error; - error = bus_dmamap_create(sc->vtnet_hdr_dmat, 0, &hdr_dmap); - if (error) - goto error_out; - - error = bus_dmamap_load(sc->vtnet_hdr_dmat, hdr_dmap, &s, - sizeof(s), vtnet_load_callback, &hdr_paddr, BUS_DMA_NOWAIT); - if (error) - goto error_destroy_hdr; - + error = 0; MPASS(sc->vtnet_flags & VTNET_FLAG_CTRL_MAC); s.hdr.class = VIRTIO_NET_CTRL_MAC; s.hdr.cmd = VIRTIO_NET_CTRL_MAC_ADDR_SET; bcopy(hwaddr, &s.addr[0], ETHER_ADDR_LEN); - ack = VIRTIO_NET_ERR; - bus_dmamap_sync(sc->vtnet_hdr_dmat, hdr_dmap, BUS_DMASYNC_PREWRITE); + s.ack = VIRTIO_NET_ERR; sglist_init(&sg, nitems(segs), segs); - error |= sglist_append_phys(&sg, hdr_paddr, - sizeof(struct virtio_net_ctrl_hdr)); - error |= sglist_append_phys(&sg, - hdr_paddr + ((uintptr_t)&s.addr - (uintptr_t)&s), - ETHER_ADDR_LEN); - MPASS(error == 0 && sg.sg_nseg == nitems(segs) - 1); + error |= sglist_append(&sg, &s.hdr, sizeof(struct virtio_net_ctrl_hdr)); + error |= sglist_append(&sg, &s.addr[0], ETHER_ADDR_LEN); + error |= sglist_append(&sg, &s.ack, sizeof(uint8_t)); + MPASS(error == 0 && sg.sg_nseg == nitems(segs)); if (error == 0) - error = vtnet_exec_ctrl_cmd(sc, &ack, &sg, sg.sg_nseg, 1); - if (error == 0) - error = (ack == VIRTIO_NET_OK ? 0 : EIO); + vtnet_exec_ctrl_cmd(sc, &s.ack, &sg, sg.sg_nseg - 1, 1); - bus_dmamap_unload(sc->vtnet_hdr_dmat, hdr_dmap); -error_destroy_hdr: - bus_dmamap_destroy(sc->vtnet_hdr_dmat, hdr_dmap); -error_out: - return (error); + return (s.ack == VIRTIO_NET_OK ? 0 : EIO); } static int vtnet_ctrl_guest_offloads(struct vtnet_softc *sc, uint64_t offloads) { struct sglist_seg segs[3]; - bus_dmamap_t hdr_dmap; - bus_addr_t hdr_paddr; struct sglist sg; struct { struct virtio_net_ctrl_hdr hdr __aligned(2); uint8_t pad1; uint64_t offloads __aligned(8); uint8_t pad2; + uint8_t ack; } s; - uint8_t ack; int error; - error = bus_dmamap_create(sc->vtnet_hdr_dmat, 0, &hdr_dmap); - if (error) - goto error_out; - - error = bus_dmamap_load(sc->vtnet_hdr_dmat, hdr_dmap, &s, - sizeof(s), vtnet_load_callback, &hdr_paddr, BUS_DMA_NOWAIT); - if (error) - goto error_destroy_hdr; - + error = 0; MPASS(sc->vtnet_features & VIRTIO_NET_F_CTRL_GUEST_OFFLOADS); s.hdr.class = VIRTIO_NET_CTRL_GUEST_OFFLOADS; s.hdr.cmd = VIRTIO_NET_CTRL_GUEST_OFFLOADS_SET; s.offloads = vtnet_gtoh64(sc, offloads); - ack = VIRTIO_NET_ERR; - bus_dmamap_sync(sc->vtnet_hdr_dmat, hdr_dmap, BUS_DMASYNC_PREWRITE); + s.ack = VIRTIO_NET_ERR; sglist_init(&sg, nitems(segs), segs); - error |= sglist_append_phys(&sg, hdr_paddr, - sizeof(struct virtio_net_ctrl_hdr)); - error |= sglist_append_phys(&sg, - hdr_paddr + ((uintptr_t)&s.offloads - (uintptr_t)&s), - sizeof(uint64_t)); - MPASS(error == 0 && sg.sg_nseg == nitems(segs) - 1); + error |= sglist_append(&sg, &s.hdr, sizeof(struct virtio_net_ctrl_hdr)); + error |= sglist_append(&sg, &s.offloads, sizeof(uint64_t)); + error |= sglist_append(&sg, &s.ack, sizeof(uint8_t)); + MPASS(error == 0 && sg.sg_nseg == nitems(segs)); if (error == 0) - error = vtnet_exec_ctrl_cmd(sc, &ack, &sg, sg.sg_nseg, 1); - if (error == 0) - error = (ack == VIRTIO_NET_OK ? 0 : EIO); + vtnet_exec_ctrl_cmd(sc, &s.ack, &sg, sg.sg_nseg - 1, 1); - bus_dmamap_unload(sc->vtnet_hdr_dmat, hdr_dmap); -error_destroy_hdr: - bus_dmamap_destroy(sc->vtnet_hdr_dmat, hdr_dmap); -error_out: - return (error); + return (s.ack == VIRTIO_NET_OK ? 0 : EIO); } static int vtnet_ctrl_mq_cmd(struct vtnet_softc *sc, uint16_t npairs) { struct sglist_seg segs[3]; - bus_dmamap_t hdr_dmap; - bus_addr_t hdr_paddr; struct sglist sg; struct { struct virtio_net_ctrl_hdr hdr __aligned(2); uint8_t pad1; struct virtio_net_ctrl_mq mq __aligned(2); uint8_t pad2; + uint8_t ack; } s; - uint8_t ack; int error; - error = bus_dmamap_create(sc->vtnet_hdr_dmat, 0, &hdr_dmap); - if (error) - goto error_out; - - error = bus_dmamap_load(sc->vtnet_hdr_dmat, hdr_dmap, &s, - sizeof(s), vtnet_load_callback, &hdr_paddr, BUS_DMA_NOWAIT); - if (error) - goto error_destroy_hdr; - + error = 0; MPASS(sc->vtnet_flags & VTNET_FLAG_MQ); s.hdr.class = VIRTIO_NET_CTRL_MQ; s.hdr.cmd = VIRTIO_NET_CTRL_MQ_VQ_PAIRS_SET; s.mq.virtqueue_pairs = vtnet_gtoh16(sc, npairs); - ack = VIRTIO_NET_ERR; - bus_dmamap_sync(sc->vtnet_hdr_dmat, hdr_dmap, BUS_DMASYNC_PREWRITE); + s.ack = VIRTIO_NET_ERR; sglist_init(&sg, nitems(segs), segs); - error |= sglist_append_phys(&sg, hdr_paddr, - sizeof(struct virtio_net_ctrl_hdr)); - error |= sglist_append_phys(&sg, - hdr_paddr + ((uintptr_t)&s.mq - (uintptr_t)&s), - sizeof(struct virtio_net_ctrl_mq)); - MPASS(error == 0 && sg.sg_nseg == nitems(segs) - 1); + error |= sglist_append(&sg, &s.hdr, sizeof(struct virtio_net_ctrl_hdr)); + error |= sglist_append(&sg, &s.mq, sizeof(struct virtio_net_ctrl_mq)); + error |= sglist_append(&sg, &s.ack, sizeof(uint8_t)); + MPASS(error == 0 && sg.sg_nseg == nitems(segs)); if (error == 0) - error = vtnet_exec_ctrl_cmd(sc, &ack, &sg, sg.sg_nseg, 1); - if (error == 0) - error = (ack == VIRTIO_NET_OK ? 0 : EIO); + vtnet_exec_ctrl_cmd(sc, &s.ack, &sg, sg.sg_nseg - 1, 1); - bus_dmamap_unload(sc->vtnet_hdr_dmat, hdr_dmap); -error_destroy_hdr: - bus_dmamap_destroy(sc->vtnet_hdr_dmat, hdr_dmap); -error_out: - return (error); + return (s.ack == VIRTIO_NET_OK ? 0 : EIO); } static int vtnet_ctrl_rx_cmd(struct vtnet_softc *sc, uint8_t cmd, bool on) { struct sglist_seg segs[3]; - bus_dmamap_t hdr_dmap; - bus_addr_t hdr_paddr; struct sglist sg; struct { struct virtio_net_ctrl_hdr hdr __aligned(2); uint8_t pad1; uint8_t onoff; uint8_t pad2; + uint8_t ack; } s; - uint8_t ack; int error; - error = bus_dmamap_create(sc->vtnet_hdr_dmat, 0, &hdr_dmap); - if (error) - goto error_out; - - error = bus_dmamap_load(sc->vtnet_hdr_dmat, hdr_dmap, &s, - sizeof(s), vtnet_load_callback, &hdr_paddr, BUS_DMA_NOWAIT); - if (error) - goto error_destroy_hdr; - + error = 0; MPASS(sc->vtnet_flags & VTNET_FLAG_CTRL_RX); s.hdr.class = VIRTIO_NET_CTRL_RX; s.hdr.cmd = cmd; s.onoff = on; - ack = VIRTIO_NET_ERR; - bus_dmamap_sync(sc->vtnet_hdr_dmat, hdr_dmap, BUS_DMASYNC_PREWRITE); + s.ack = VIRTIO_NET_ERR; sglist_init(&sg, nitems(segs), segs); - error |= sglist_append_phys(&sg, hdr_paddr, - sizeof(struct virtio_net_ctrl_hdr)); - error |= sglist_append_phys(&sg, - hdr_paddr + ((uintptr_t)&s.onoff - (uintptr_t)&s), - sizeof(uint8_t)); - MPASS(error == 0 && sg.sg_nseg == nitems(segs) - 1); + error |= sglist_append(&sg, &s.hdr, sizeof(struct virtio_net_ctrl_hdr)); + error |= sglist_append(&sg, &s.onoff, sizeof(uint8_t)); + error |= sglist_append(&sg, &s.ack, sizeof(uint8_t)); + MPASS(error == 0 && sg.sg_nseg == nitems(segs)); if (error == 0) - error = vtnet_exec_ctrl_cmd(sc, &ack, &sg, sg.sg_nseg, 1); - if (error == 0) - error = (ack == VIRTIO_NET_OK ? 0 : EIO); + vtnet_exec_ctrl_cmd(sc, &s.ack, &sg, sg.sg_nseg - 1, 1); - bus_dmamap_unload(sc->vtnet_hdr_dmat, hdr_dmap); -error_destroy_hdr: - bus_dmamap_destroy(sc->vtnet_hdr_dmat, hdr_dmap); -error_out: - return (error); + return (s.ack == VIRTIO_NET_OK ? 0 : EIO); } static int @@ -4142,10 +3737,6 @@ vtnet_rx_filter_mac(struct vtnet_softc *sc) struct virtio_net_ctrl_hdr hdr __aligned(2); struct vtnet_mac_filter *filter; struct sglist_seg segs[4]; - bus_dmamap_t filter_dmap; - bus_addr_t filter_paddr; - bus_dmamap_t hdr_dmap; - bus_addr_t hdr_paddr; struct sglist sg; if_t ifp; bool promisc, allmulti; @@ -4185,25 +3776,6 @@ vtnet_rx_filter_mac(struct vtnet_softc *sc) if (promisc && allmulti) goto out; - error = bus_dmamap_create(sc->vtnet_hdr_dmat, 0, &hdr_dmap); - if (error) - goto out_error; - - error = bus_dmamap_load(sc->vtnet_hdr_dmat, hdr_dmap, &hdr, - sizeof(hdr), vtnet_load_callback, &hdr_paddr, BUS_DMA_NOWAIT); - if (error) - goto out_destroy_hdr; - - error = bus_dmamap_create(sc->vtnet_hdr_dmat, 0, &filter_dmap); - if (error) - goto out_unload_hdr; - - error = bus_dmamap_load(sc->vtnet_hdr_dmat, hdr_dmap, filter, - sizeof(*filter), vtnet_load_callback, &filter_paddr, - BUS_DMA_NOWAIT); - if (error) - goto out_destroy_filter; - filter->vmf_unicast.nentries = vtnet_gtoh32(sc, ucnt); filter->vmf_multicast.nentries = vtnet_gtoh32(sc, mcnt); @@ -4212,33 +3784,19 @@ vtnet_rx_filter_mac(struct vtnet_softc *sc) ack = VIRTIO_NET_ERR; sglist_init(&sg, nitems(segs), segs); - error |= sglist_append_phys(&sg, hdr_paddr, - sizeof(struct virtio_net_ctrl_hdr)); - error |= sglist_append_phys(&sg, - filter_paddr + ((uintptr_t)&filter->vmf_unicast - - (uintptr_t)filter), + error |= sglist_append(&sg, &hdr, sizeof(struct virtio_net_ctrl_hdr)); + error |= sglist_append(&sg, &filter->vmf_unicast, sizeof(uint32_t) + ucnt * ETHER_ADDR_LEN); - error |= sglist_append_phys(&sg, - filter_paddr + ((uintptr_t)&filter->vmf_multicast - - (uintptr_t)filter), + error |= sglist_append(&sg, &filter->vmf_multicast, sizeof(uint32_t) + mcnt * ETHER_ADDR_LEN); - MPASS(error == 0 && sg.sg_nseg == nitems(segs) - 1); + error |= sglist_append(&sg, &ack, sizeof(uint8_t)); + MPASS(error == 0 && sg.sg_nseg == nitems(segs)); if (error == 0) - error = vtnet_exec_ctrl_cmd(sc, &ack, &sg, sg.sg_nseg, 1); - if (error == 0) - error = (ack == VIRTIO_NET_OK ? 0 : EIO); - - bus_dmamap_unload(sc->vtnet_hdr_dmat, filter_dmap); -out_destroy_filter: - bus_dmamap_destroy(sc->vtnet_hdr_dmat, filter_dmap); -out_unload_hdr: - bus_dmamap_unload(sc->vtnet_hdr_dmat, hdr_dmap); -out_destroy_hdr: - bus_dmamap_destroy(sc->vtnet_hdr_dmat, hdr_dmap); -out_error: - if (error != 0) + vtnet_exec_ctrl_cmd(sc, &ack, &sg, sg.sg_nseg - 1, 1); + if (ack != VIRTIO_NET_OK) if_printf(ifp, "error setting host MAC filter table\n"); + out: if (promisc && vtnet_set_promisc(sc, true) != 0) if_printf(ifp, "cannot enable promiscuous mode\n"); @@ -4250,53 +3808,34 @@ static int vtnet_exec_vlan_filter(struct vtnet_softc *sc, int add, uint16_t tag) { struct sglist_seg segs[3]; - bus_dmamap_t hdr_dmap; - bus_addr_t hdr_paddr; struct sglist sg; struct { struct virtio_net_ctrl_hdr hdr __aligned(2); uint8_t pad1; uint16_t tag __aligned(2); uint8_t pad2; + uint8_t ack; } s; - uint8_t ack; int error; - error = bus_dmamap_create(sc->vtnet_hdr_dmat, 0, &hdr_dmap); - if (error) - goto error_out; - - error = bus_dmamap_load(sc->vtnet_hdr_dmat, hdr_dmap, &s, - sizeof(s), vtnet_load_callback, &hdr_paddr, BUS_DMA_NOWAIT); - if (error) - goto error_destroy_hdr; - + error = 0; MPASS(sc->vtnet_flags & VTNET_FLAG_VLAN_FILTER); s.hdr.class = VIRTIO_NET_CTRL_VLAN; s.hdr.cmd = add ? VIRTIO_NET_CTRL_VLAN_ADD : VIRTIO_NET_CTRL_VLAN_DEL; s.tag = vtnet_gtoh16(sc, tag); - ack = VIRTIO_NET_ERR; - bus_dmamap_sync(sc->vtnet_hdr_dmat, hdr_dmap, BUS_DMASYNC_PREWRITE); + s.ack = VIRTIO_NET_ERR; sglist_init(&sg, nitems(segs), segs); - error |= sglist_append_phys(&sg, hdr_paddr, - sizeof(struct virtio_net_ctrl_hdr)); - error |= sglist_append_phys(&sg, - hdr_paddr + ((uintptr_t)&s.tag - (uintptr_t)&s), - sizeof(uint16_t)); - MPASS(error == 0 && sg.sg_nseg == nitems(segs) - 1); + error |= sglist_append(&sg, &s.hdr, sizeof(struct virtio_net_ctrl_hdr)); + error |= sglist_append(&sg, &s.tag, sizeof(uint16_t)); + error |= sglist_append(&sg, &s.ack, sizeof(uint8_t)); + MPASS(error == 0 && sg.sg_nseg == nitems(segs)); if (error == 0) - error = vtnet_exec_ctrl_cmd(sc, &ack, &sg, sg.sg_nseg, 1); - if (error == 0) - error = (ack == VIRTIO_NET_OK ? 0 : EIO); + vtnet_exec_ctrl_cmd(sc, &s.ack, &sg, sg.sg_nseg - 1, 1); - bus_dmamap_unload(sc->vtnet_hdr_dmat, hdr_dmap); -error_destroy_hdr: - bus_dmamap_destroy(sc->vtnet_hdr_dmat, hdr_dmap); -error_out: - return (error); + return (s.ack == VIRTIO_NET_OK ? 0 : EIO); } static void diff --git a/sys/dev/virtio/network/if_vtnetvar.h b/sys/dev/virtio/network/if_vtnetvar.h index e445bdf6d6cb..eb5e6784b07f 100644 --- a/sys/dev/virtio/network/if_vtnetvar.h +++ b/sys/dev/virtio/network/if_vtnetvar.h @@ -190,18 +190,6 @@ struct vtnet_softc { struct mtx vtnet_mtx; char vtnet_mtx_name[16]; uint8_t vtnet_hwaddr[ETHER_ADDR_LEN]; - - bus_dma_tag_t vtnet_rx_dmat; - struct mtx vtnet_rx_mtx; - - bus_dma_tag_t vtnet_tx_dmat; - struct mtx vtnet_tx_mtx; - - bus_dma_tag_t vtnet_hdr_dmat; - struct mtx vtnet_hdr_mtx; - - bus_dma_tag_t vtnet_ack_dmat; - struct mtx vtnet_ack_mtx; }; /* vtnet flag descriptions for use with printf(9) %b identifier. */ #define VTNET_FLAGS_BITS \ @@ -285,10 +273,6 @@ struct vtnet_tx_header { } vth_uhdr; struct mbuf *vth_mbuf; - - bus_dmamap_t dmap; - - bus_dmamap_t hdr_dmap; }; /* diff --git a/sys/dev/virtio/p9fs/virtio_p9fs.c b/sys/dev/virtio/p9fs/virtio_p9fs.c index 2b276a60aa9a..c347458b4f8e 100644 --- a/sys/dev/virtio/p9fs/virtio_p9fs.c +++ b/sys/dev/virtio/p9fs/virtio_p9fs.c @@ -112,7 +112,7 @@ SYSCTL_UINT(_vfs_9p, OID_AUTO, ackmaxidle, CTLFLAG_RW, &vt9p_ackmaxidle, 0, static int vt9p_req_wait(struct vt9p_softc *chan, struct p9_req_t *req) { - KASSERT(req->tc->tag != req->rc->tag, + KASSERT(req->tc.tag != req->rc.tag, ("%s: request %p already completed", __func__, req)); if (msleep(req, VT9P_MTX(chan), 0, "chan lock", vt9p_ackmaxidle * hz)) { @@ -124,7 +124,7 @@ vt9p_req_wait(struct vt9p_softc *chan, struct p9_req_t *req) "for an ack from host\n", vt9p_ackmaxidle); return (EIO); } - KASSERT(req->tc->tag == req->rc->tag, + KASSERT(req->tc.tag == req->rc.tag, ("%s spurious event on request %p", __func__, req)); return (0); } @@ -157,7 +157,7 @@ vt9p_request(void *handle, struct p9_req_t *req) req_retry: sglist_reset(sg); /* Handle out VirtIO ring buffers */ - error = sglist_append(sg, req->tc->sdata, req->tc->size); + error = sglist_append(sg, req->tc.sdata, req->tc.size); if (error != 0) { P9_DEBUG(ERROR, "%s: sglist append failed\n", __func__); VT9P_UNLOCK(chan); @@ -165,7 +165,7 @@ req_retry: } readable = sg->sg_nseg; - error = sglist_append(sg, req->rc->sdata, req->rc->capacity); + error = sglist_append(sg, req->rc.sdata, req->rc.capacity); if (error != 0) { P9_DEBUG(ERROR, "%s: sglist append failed\n", __func__); VT9P_UNLOCK(chan); @@ -226,7 +226,7 @@ vt9p_intr_complete(void *xsc) VT9P_LOCK(chan); again: while ((curreq = virtqueue_dequeue(vq, NULL)) != NULL) { - curreq->rc->tag = curreq->tc->tag; + curreq->rc.tag = curreq->tc.tag; wakeup_one(curreq); } if (virtqueue_enable_intr(vq) != 0) { @@ -464,16 +464,20 @@ static int vt9p_modevent(module_t mod, int type, void *unused) { int error; + static int loaded = 0; error = 0; switch (type) { case MOD_LOAD: - p9_init_zones(); - p9_register_trans(&vt9p_trans); + if (loaded++ == 0) { + p9_register_trans(&vt9p_trans); + } break; case MOD_UNLOAD: - p9_destroy_zones(); + if (--loaded == 0) { + p9_unregister_trans(&vt9p_trans); + } break; case MOD_SHUTDOWN: break; @@ -481,6 +485,7 @@ vt9p_modevent(module_t mod, int type, void *unused) error = EOPNOTSUPP; break; } + return (error); } diff --git a/sys/dev/vnic/thunder_bgx_fdt.c b/sys/dev/vnic/thunder_bgx_fdt.c index 20a5b54f7448..e038c0b728eb 100644 --- a/sys/dev/vnic/thunder_bgx_fdt.c +++ b/sys/dev/vnic/thunder_bgx_fdt.c @@ -52,6 +52,7 @@ #include <dev/ofw/openfirm.h> #include <dev/ofw/ofw_bus.h> #include <dev/mii/miivar.h> +#include <dev/pci/pcivar.h> #include "thunder_bgx.h" #include "thunder_bgx_var.h" @@ -285,11 +286,9 @@ bgx_fdt_traverse_nodes(uint8_t unit, phandle_t start, char *name, static device_t bgx_find_root_pcib(device_t dev) { - devclass_t pci_class; device_t pcib, bus; - pci_class = devclass_find("pci"); - KASSERT(device_get_devclass(device_get_parent(dev)) == pci_class, + KASSERT(is_pci_device(dev), ("%s: non-pci device %s", __func__, device_get_nameunit(dev))); /* Walk the bridge hierarchy until we find a non-PCI device */ @@ -298,9 +297,6 @@ bgx_find_root_pcib(device_t dev) KASSERT(bus != NULL, ("%s: null parent of %s", __func__, device_get_nameunit(dev))); - if (device_get_devclass(bus) != pci_class) - return (NULL); - pcib = device_get_parent(bus); KASSERT(pcib != NULL, ("%s: null bridge of %s", __func__, device_get_nameunit(bus))); @@ -309,7 +305,7 @@ bgx_find_root_pcib(device_t dev) * If the parent of this PCIB is not PCI * then we found our root PCIB. */ - if (device_get_devclass(device_get_parent(pcib)) != pci_class) + if (!is_pci_device(pcib)) return (pcib); dev = pcib; diff --git a/sys/dev/vt/vt.h b/sys/dev/vt/vt.h index 4abe99e4ab13..6ff242562c87 100644 --- a/sys/dev/vt/vt.h +++ b/sys/dev/vt/vt.h @@ -248,6 +248,8 @@ void vtbuf_cursor_visibility(struct vt_buf *, int); int vtbuf_set_mark(struct vt_buf *vb, int type, int col, int row); int vtbuf_get_marked_len(struct vt_buf *vb); void vtbuf_extract_marked(struct vt_buf *vb, term_char_t *buf, int sz, int mark); +void vtbuf_unmark(struct vt_buf *vb); +void vtbuf_unmark_on_cross(struct vt_buf *vb, int target_begin, int target_end); #endif #define VTB_MARK_NONE 0 diff --git a/sys/dev/vt/vt_buf.c b/sys/dev/vt/vt_buf.c index e1e4ebc23491..8596342c139a 100644 --- a/sys/dev/vt/vt_buf.c +++ b/sys/dev/vt/vt_buf.c @@ -202,6 +202,36 @@ vtbuf_in_this_range(int begin, int test, int end, int sz) else return (test >= begin && test < end); } + +void +vtbuf_unmark(struct vt_buf *vb) +{ + + vtbuf_set_mark(vb, VTB_MARK_START, 0, 0); +} + +void +vtbuf_unmark_on_cross(struct vt_buf *vb, int target_begin, int target_end) +{ + int hsz, mb, me, tb, te; + + tb = vtbuf_wth(vb, target_begin); + te = vtbuf_wth(vb, target_end); + mb = vb->vb_mark_start.tp_row; + me = vb->vb_mark_end.tp_row; + hsz = vb->vb_history_size; + + /* + * Test intersection with vtbuf_in_this_range due to use of + * the circular buffer. + */ + if (vtbuf_in_this_range(tb, mb, te, hsz) || + vtbuf_in_this_range(tb, me, te, hsz) || + vtbuf_in_this_range(mb, tb, me, hsz) || + vtbuf_in_this_range(mb, te, me, hsz)) { + vtbuf_unmark(vb); + } +} #endif int diff --git a/sys/dev/vt/vt_core.c b/sys/dev/vt/vt_core.c index f7cffcea5b92..db54cb426844 100644 --- a/sys/dev/vt/vt_core.c +++ b/sys/dev/vt/vt_core.c @@ -804,11 +804,11 @@ vt_machine_kbdevent(struct vt_device *vd, int c) return (1); case SPCLKEY | STBY: /* XXX Not present in kbdcontrol parser. */ /* Put machine into Stand-By mode. */ - power_pm_suspend(POWER_SSTATE_TRANSITION_STANDBY); + (void)power_pm_suspend(POWER_TRANSITION_STANDBY); return (1); case SPCLKEY | SUSP: /* kbdmap(5) keyword `susp`. */ /* Suspend machine. */ - power_pm_suspend(POWER_SSTATE_TRANSITION_SUSPEND); + (void)power_pm_suspend(POWER_TRANSITION_SUSPEND); return (1); } @@ -1197,6 +1197,10 @@ vtterm_fill(struct terminal *tm, const term_rect_t *r, term_char_t c) { struct vt_window *vw = tm->tm_softc; +#ifndef SC_NO_CUTPASTE + vtbuf_unmark_on_cross(&vw->vw_buf, r->tr_begin.tp_row, + r->tr_end.tp_row); +#endif vtbuf_fill(&vw->vw_buf, r, c); } @@ -2465,9 +2469,7 @@ vt_mouse_event(int type, int x, int y, int event, int cnt, int mlevel) default: vt_mouse_paste(); /* clear paste buffer selection after paste */ - vtbuf_set_mark(&vw->vw_buf, VTB_MARK_START, - vd->vd_mx / vf->vf_width, - vd->vd_my / vf->vf_height); + vtbuf_unmark(&vw->vw_buf); break; } return; /* Done */ diff --git a/sys/dev/wtap/if_wtap.c b/sys/dev/wtap/if_wtap.c index dd332c538c8f..376b63e38f2b 100644 --- a/sys/dev/wtap/if_wtap.c +++ b/sys/dev/wtap/if_wtap.c @@ -495,6 +495,7 @@ wtap_rx_proc(void *arg, int npending) struct mbuf *m; struct ieee80211_node *ni; struct wtap_buf *bf; + int8_t rssi, nf; #if 0 DWTAP_PRINTF("%s\n", __func__); @@ -529,6 +530,15 @@ wtap_rx_proc(void *arg, int npending) #endif /* + * Use arbitrary but sane values, and do the correct conversion + * for net80211 using 0.5 dBm values relative to the noise floor. + */ + nf = -95; + rssi = 42; + rssi -= nf; + rssi *= 2; + + /* * Locate the node for sender, track state, and then * pass the (referenced) node up to the 802.11 layer * for its use. @@ -540,10 +550,10 @@ wtap_rx_proc(void *arg, int npending) /* * Sending station is known, dispatch directly. */ - ieee80211_input(ni, m, 1<<7, 10); + ieee80211_input(ni, m, rssi, nf); ieee80211_free_node(ni); } else { - ieee80211_input_all(ic, m, 1<<7, 10); + ieee80211_input_all(ic, m, rssi, nf); } /* The mbufs are freed by the Net80211 stack */ diff --git a/sys/dev/xen/control/control.c b/sys/dev/xen/control/control.c index 2c61b48c0451..e363ea1700f6 100644 --- a/sys/dev/xen/control/control.c +++ b/sys/dev/xen/control/control.c @@ -176,12 +176,12 @@ xctrl_suspend(void) cpuset_t cpu_suspend_map; #endif - EVENTHANDLER_INVOKE(power_suspend_early, POWER_STYPE_SUSPEND_TO_MEM); + EVENTHANDLER_INVOKE(power_suspend_early, POWER_STYPE_FW_SUSPEND); xs_lock(); stop_all_proc(); xs_unlock(); suspend_all_fs(); - EVENTHANDLER_INVOKE(power_suspend, POWER_STYPE_SUSPEND_TO_MEM); + EVENTHANDLER_INVOKE(power_suspend, POWER_STYPE_FW_SUSPEND); #ifdef EARLY_AP_STARTUP MPASS(mp_ncpus == 1 || smp_started); @@ -298,7 +298,7 @@ xctrl_suspend(void) resume_all_fs(); resume_all_proc(); - EVENTHANDLER_INVOKE(power_resume, POWER_STYPE_SUSPEND_TO_MEM); + EVENTHANDLER_INVOKE(power_resume, POWER_STYPE_FW_SUSPEND); if (bootverbose) printf("System resumed after suspension\n"); |