diff options
Diffstat (limited to 'sys/powerpc/include')
84 files changed, 10884 insertions, 0 deletions
diff --git a/sys/powerpc/include/_align.h b/sys/powerpc/include/_align.h new file mode 100644 index 000000000000..0a7b6039b087 --- /dev/null +++ b/sys/powerpc/include/_align.h @@ -0,0 +1,51 @@ +/*- + * SPDX-License-Identifier: BSD-4-Clause + * + * Copyright (c) 2001 David E. O'Brien + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * William Jolitz. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _POWERPC_INCLUDE__ALIGN_H_ +#define _POWERPC_INCLUDE__ALIGN_H_ + +/* + * Round p (pointer or byte index) up to a correctly-aligned value + * for all data types (int, long, ...). The result is unsigned int + * and must be cast to any desired pointer type. + */ +#define _ALIGNBYTES (sizeof(register_t) - 1) +#define _ALIGN(p) (((uintptr_t)(p) + _ALIGNBYTES) & ~_ALIGNBYTES) + +#endif /* !_POWERPC_INCLUDE__ALIGN_H_ */ diff --git a/sys/powerpc/include/_bus.h b/sys/powerpc/include/_bus.h new file mode 100644 index 000000000000..bf6372ac6aea --- /dev/null +++ b/sys/powerpc/include/_bus.h @@ -0,0 +1,30 @@ +/*- + * Copyright (c) 2005 The FreeBSD Foundation. + * + * SPDX-License-Identifier: BSD-2-Clause + * + * Derived in part from NetBSD's bus.h files by (alphabetically): + * Christopher G. Demetriou + * Charles M. Hannum + * Jason Thorpe + * The NetBSD Foundation. + */ + +#ifndef POWERPC_INCLUDE__BUS_H +#define POWERPC_INCLUDE__BUS_H + +#include <vm/vm_param.h> + +/* + * Bus address and size types + */ +typedef vm_paddr_t bus_addr_t; +typedef vm_size_t bus_size_t; + +/* + * Access methods for bus resources and address space. + */ +typedef struct bus_space *bus_space_tag_t; +typedef vm_offset_t bus_space_handle_t; + +#endif /* POWERPC_INCLUDE__BUS_H */ diff --git a/sys/powerpc/include/_inttypes.h b/sys/powerpc/include/_inttypes.h new file mode 100644 index 000000000000..4d1b52da6cea --- /dev/null +++ b/sys/powerpc/include/_inttypes.h @@ -0,0 +1,222 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2001 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Klaus Klein. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * From: $NetBSD: int_fmtio.h,v 1.2 2001/04/26 16:25:21 kleink Exp $ + */ + +#ifndef _MACHINE_INTTYPES_H_ +#define _MACHINE_INTTYPES_H_ + +/* + * Macros for format specifiers. + */ + +#ifdef __LP64__ +#define __PRI64 "l" +#define __PRIptr "l" +#else +#define __PRI64 "ll" +#define __PRIptr +#endif + +/* fprintf(3) macros for signed integers. */ + +#define PRId8 "d" /* int8_t */ +#define PRId16 "d" /* int16_t */ +#define PRId32 "d" /* int32_t */ +#define PRId64 __PRI64"d" /* int64_t */ +#define PRIdLEAST8 "d" /* int_least8_t */ +#define PRIdLEAST16 "d" /* int_least16_t */ +#define PRIdLEAST32 "d" /* int_least32_t */ +#define PRIdLEAST64 __PRI64"d" /* int_least64_t */ +#define PRIdFAST8 "d" /* int_fast8_t */ +#define PRIdFAST16 "d" /* int_fast16_t */ +#define PRIdFAST32 "d" /* int_fast32_t */ +#define PRIdFAST64 __PRI64"d" /* int_fast64_t */ +#define PRIdMAX "jd" /* intmax_t */ +#define PRIdPTR __PRIptr"d" /* intptr_t */ + +#define PRIi8 "i" /* int8_t */ +#define PRIi16 "i" /* int16_t */ +#define PRIi32 "i" /* int32_t */ +#define PRIi64 __PRI64"i" /* int64_t */ +#define PRIiLEAST8 "i" /* int_least8_t */ +#define PRIiLEAST16 "i" /* int_least16_t */ +#define PRIiLEAST32 "i" /* int_least32_t */ +#define PRIiLEAST64 __PRI64"i" /* int_least64_t */ +#define PRIiFAST8 "i" /* int_fast8_t */ +#define PRIiFAST16 "i" /* int_fast16_t */ +#define PRIiFAST32 "i" /* int_fast32_t */ +#define PRIiFAST64 __PRI64"i" /* int_fast64_t */ +#define PRIiMAX "ji" /* intmax_t */ +#define PRIiPTR __PRIptr"i" /* intptr_t */ + +/* fprintf(3) macros for unsigned integers. */ + +#define PRIo8 "o" /* uint8_t */ +#define PRIo16 "o" /* uint16_t */ +#define PRIo32 "o" /* uint32_t */ +#define PRIo64 __PRI64"o" /* uint64_t */ +#define PRIoLEAST8 "o" /* uint_least8_t */ +#define PRIoLEAST16 "o" /* uint_least16_t */ +#define PRIoLEAST32 "o" /* uint_least32_t */ +#define PRIoLEAST64 __PRI64"o" /* uint_least64_t */ +#define PRIoFAST8 "o" /* uint_fast8_t */ +#define PRIoFAST16 "o" /* uint_fast16_t */ +#define PRIoFAST32 "o" /* uint_fast32_t */ +#define PRIoFAST64 __PRI64"o" /* uint_fast64_t */ +#define PRIoMAX "jo" /* uintmax_t */ +#define PRIoPTR __PRIptr"o" /* uintptr_t */ + +#define PRIu8 "u" /* uint8_t */ +#define PRIu16 "u" /* uint16_t */ +#define PRIu32 "u" /* uint32_t */ +#define PRIu64 __PRI64"u" /* uint64_t */ +#define PRIuLEAST8 "u" /* uint_least8_t */ +#define PRIuLEAST16 "u" /* uint_least16_t */ +#define PRIuLEAST32 "u" /* uint_least32_t */ +#define PRIuLEAST64 __PRI64"u" /* uint_least64_t */ +#define PRIuFAST8 "u" /* uint_fast8_t */ +#define PRIuFAST16 "u" /* uint_fast16_t */ +#define PRIuFAST32 "u" /* uint_fast32_t */ +#define PRIuFAST64 __PRI64"u" /* uint_fast64_t */ +#define PRIuMAX "ju" /* uintmax_t */ +#define PRIuPTR __PRIptr"u" /* uintptr_t */ + +#define PRIx8 "x" /* uint8_t */ +#define PRIx16 "x" /* uint16_t */ +#define PRIx32 "x" /* uint32_t */ +#define PRIx64 __PRI64"x" /* uint64_t */ +#define PRIxLEAST8 "x" /* uint_least8_t */ +#define PRIxLEAST16 "x" /* uint_least16_t */ +#define PRIxLEAST32 "x" /* uint_least32_t */ +#define PRIxLEAST64 __PRI64"x" /* uint_least64_t */ +#define PRIxFAST8 "x" /* uint_fast8_t */ +#define PRIxFAST16 "x" /* uint_fast16_t */ +#define PRIxFAST32 "x" /* uint_fast32_t */ +#define PRIxFAST64 __PRI64"x" /* uint_fast64_t */ +#define PRIxMAX "jx" /* uintmax_t */ +#define PRIxPTR __PRIptr"x" /* uintptr_t */ + +#define PRIX8 "X" /* uint8_t */ +#define PRIX16 "X" /* uint16_t */ +#define PRIX32 "X" /* uint32_t */ +#define PRIX64 __PRI64"X" /* uint64_t */ +#define PRIXLEAST8 "X" /* uint_least8_t */ +#define PRIXLEAST16 "X" /* uint_least16_t */ +#define PRIXLEAST32 "X" /* uint_least32_t */ +#define PRIXLEAST64 __PRI64"X" /* uint_least64_t */ +#define PRIXFAST8 "X" /* uint_fast8_t */ +#define PRIXFAST16 "X" /* uint_fast16_t */ +#define PRIXFAST32 "X" /* uint_fast32_t */ +#define PRIXFAST64 __PRI64"X" /* uint_fast64_t */ +#define PRIXMAX "jX" /* uintmax_t */ +#define PRIXPTR __PRIptr"X" /* uintptr_t */ + +/* fscanf(3) macros for signed integers. */ + +#define SCNd8 "hhd" /* int8_t */ +#define SCNd16 "hd" /* int16_t */ +#define SCNd32 "d" /* int32_t */ +#define SCNd64 __PRI64"d" /* int64_t */ +#define SCNdLEAST8 "hhd" /* int_least8_t */ +#define SCNdLEAST16 "hd" /* int_least16_t */ +#define SCNdLEAST32 "d" /* int_least32_t */ +#define SCNdLEAST64 __PRI64"d" /* int_least64_t */ +#define SCNdFAST8 "d" /* int_fast8_t */ +#define SCNdFAST16 "d" /* int_fast16_t */ +#define SCNdFAST32 "d" /* int_fast32_t */ +#define SCNdFAST64 __PRI64"d" /* int_fast64_t */ +#define SCNdMAX "jd" /* intmax_t */ +#define SCNdPTR __PRIptr"d" /* intptr_t */ + +#define SCNi8 "hhi" /* int8_t */ +#define SCNi16 "hi" /* int16_t */ +#define SCNi32 "i" /* int32_t */ +#define SCNi64 __PRI64"i" /* int64_t */ +#define SCNiLEAST8 "hhi" /* int_least8_t */ +#define SCNiLEAST16 "hi" /* int_least16_t */ +#define SCNiLEAST32 "i" /* int_least32_t */ +#define SCNiLEAST64 __PRI64"i" /* int_least64_t */ +#define SCNiFAST8 "i" /* int_fast8_t */ +#define SCNiFAST16 "i" /* int_fast16_t */ +#define SCNiFAST32 "i" /* int_fast32_t */ +#define SCNiFAST64 __PRI64"i" /* int_fast64_t */ +#define SCNiMAX "ji" /* intmax_t */ +#define SCNiPTR __PRIptr"i" /* intptr_t */ + +/* fscanf(3) macros for unsigned integers. */ + +#define SCNo8 "hho" /* uint8_t */ +#define SCNo16 "ho" /* uint16_t */ +#define SCNo32 "o" /* uint32_t */ +#define SCNo64 __PRI64"o" /* uint64_t */ +#define SCNoLEAST8 "hho" /* uint_least8_t */ +#define SCNoLEAST16 "ho" /* uint_least16_t */ +#define SCNoLEAST32 "o" /* uint_least32_t */ +#define SCNoLEAST64 __PRI64"o" /* uint_least64_t */ +#define SCNoFAST8 "o" /* uint_fast8_t */ +#define SCNoFAST16 "o" /* uint_fast16_t */ +#define SCNoFAST32 "o" /* uint_fast32_t */ +#define SCNoFAST64 __PRI64"o" /* uint_fast64_t */ +#define SCNoMAX "jo" /* uintmax_t */ +#define SCNoPTR __PRIptr"o" /* uintptr_t */ + +#define SCNu8 "hhu" /* uint8_t */ +#define SCNu16 "hu" /* uint16_t */ +#define SCNu32 "u" /* uint32_t */ +#define SCNu64 __PRI64"u" /* uint64_t */ +#define SCNuLEAST8 "hhu" /* uint_least8_t */ +#define SCNuLEAST16 "hu" /* uint_least16_t */ +#define SCNuLEAST32 "u" /* uint_least32_t */ +#define SCNuLEAST64 __PRI64"u" /* uint_least64_t */ +#define SCNuFAST8 "u" /* uint_fast8_t */ +#define SCNuFAST16 "u" /* uint_fast16_t */ +#define SCNuFAST32 "u" /* uint_fast32_t */ +#define SCNuFAST64 __PRI64"u" /* uint_fast64_t */ +#define SCNuMAX "ju" /* uintmax_t */ +#define SCNuPTR __PRIptr"u" /* uintptr_t */ + +#define SCNx8 "hhx" /* uint8_t */ +#define SCNx16 "hx" /* uint16_t */ +#define SCNx32 "x" /* uint32_t */ +#define SCNx64 __PRI64"x" /* uint64_t */ +#define SCNxLEAST8 "hhx" /* uint_least8_t */ +#define SCNxLEAST16 "hx" /* uint_least16_t */ +#define SCNxLEAST32 "x" /* uint_least32_t */ +#define SCNxLEAST64 __PRI64"x" /* uint_least64_t */ +#define SCNxFAST8 "x" /* uint_fast8_t */ +#define SCNxFAST16 "x" /* uint_fast16_t */ +#define SCNxFAST32 "x" /* uint_fast32_t */ +#define SCNxFAST64 __PRI64"x" /* uint_fast64_t */ +#define SCNxMAX "jx" /* uintmax_t */ +#define SCNxPTR __PRIptr"x" /* uintptr_t */ + +#endif /* !_MACHINE_INTTYPES_H_ */ diff --git a/sys/powerpc/include/_limits.h b/sys/powerpc/include/_limits.h new file mode 100644 index 000000000000..542248e51498 --- /dev/null +++ b/sys/powerpc/include/_limits.h @@ -0,0 +1,96 @@ +/*- + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 1988, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _MACHINE__LIMITS_H_ +#define _MACHINE__LIMITS_H_ + +/* + * According to ANSI (section 2.2.4.2), the values below must be usable by + * #if preprocessing directives. Additionally, the expression must have the + * same type as would an expression that is an object of the corresponding + * type converted according to the integral promotions. The subtraction for + * INT_MIN, etc., is so the value is not unsigned; e.g., 0x80000000 is an + * unsigned int for 32-bit two's complement ANSI compilers (section 3.1.3.2). + */ + +#define __CHAR_BIT 8 /* number of bits in a char */ + +#define __SCHAR_MAX 0x7f /* max value for a signed char */ +#define __SCHAR_MIN (-0x7f - 1) /* min value for a signed char */ + +#define __UCHAR_MAX 0xff /* max value for an unsigned char */ + +#define __USHRT_MAX 0xffff /* max value for an unsigned short */ +#define __SHRT_MAX 0x7fff /* max value for a short */ +#define __SHRT_MIN (-0x7fff - 1) /* min value for a short */ + +#define __UINT_MAX 0xffffffff /* max value for an unsigned int */ +#define __INT_MAX 0x7fffffff /* max value for an int */ +#define __INT_MIN (-0x7fffffff - 1) /* min value for an int */ + +#ifdef __LP64__ +#define __ULONG_MAX 0xffffffffffffffff +#define __LONG_MAX 0x7fffffffffffffff +#define __LONG_MIN (-0x7fffffffffffffff - 1) +#define __LONG_BIT 64 +#else +#define __ULONG_MAX 0xffffffffUL /* max value for an unsigned long */ +#define __LONG_MAX 0x7fffffffL /* max value for a long */ +#define __LONG_MIN (-0x7fffffffL - 1) /* min value for a long */ +#define __LONG_BIT 32 +#endif + +#define __ULLONG_MAX 0xffffffffffffffffULL +#define __LLONG_MAX 0x7fffffffffffffffLL /* max value for a long long */ +#define __LLONG_MIN (-0x7fffffffffffffffLL - 1) /* min for a long long */ + +#ifdef __LP64__ +#define __SSIZE_MAX __LONG_MAX /* max value for a ssize_t */ +#define __SIZE_T_MAX __ULONG_MAX /* max value for a size_t */ +#else +#define __SSIZE_MAX __INT_MAX /* max value for a ssize_t */ +#define __SIZE_T_MAX __UINT_MAX /* max value for a size_t */ +#endif + +#define __OFF_MAX __LLONG_MAX /* max value for an off_t */ +#define __OFF_MIN __LLONG_MIN /* min value for an off_t */ + +/* Quads and long longs are the same size. Ensure they stay in sync. */ +#define __UQUAD_MAX __ULLONG_MAX /* max value for a uquad_t */ +#define __QUAD_MAX __LLONG_MAX /* max value for a quad_t */ +#define __QUAD_MIN __LLONG_MIN /* min value for a quad_t */ + +#define __WORD_BIT 32 + +/* Minimum signal stack size. */ +#define __MINSIGSTKSZ (512 * 4) + +#endif /* !_MACHINE__LIMITS_H_ */ diff --git a/sys/powerpc/include/_stdint.h b/sys/powerpc/include/_stdint.h new file mode 100644 index 000000000000..67719432259d --- /dev/null +++ b/sys/powerpc/include/_stdint.h @@ -0,0 +1,200 @@ +/*- + * SPDX-License-Identifier: BSD-4-Clause + * + * Copyright (c) 2001, 2002 Mike Barcroft <mike@FreeBSD.org> + * Copyright (c) 2001 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Klaus Klein. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _MACHINE__STDINT_H_ +#define _MACHINE__STDINT_H_ + +#if !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) + +#define INT8_C(c) (c) +#define INT16_C(c) (c) +#define INT32_C(c) (c) + +#define UINT8_C(c) (c) +#define UINT16_C(c) (c) +#define UINT32_C(c) (c ## U) + +#ifdef __LP64__ +#define INT64_C(c) (c ## L) +#define UINT64_C(c) (c ## UL) +#else +#define INT64_C(c) (c ## LL) +#define UINT64_C(c) (c ## ULL) +#endif + +#define INTMAX_C(c) INT64_C(c) +#define UINTMAX_C(c) UINT64_C(c) + +#endif /* !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) */ + +#if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) + +#ifndef __INT64_C +#ifdef __LP64__ +#define __INT64_C(c) (c ## L) +#define __UINT64_C(c) (c ## UL) +#else +#define __INT64_C(c) (c ## LL) +#define __UINT64_C(c) (c ## ULL) +#endif +#endif + +/* + * ISO/IEC 9899:1999 + * 7.18.2.1 Limits of exact-width integer types + */ +/* Minimum values of exact-width signed integer types. */ +#define INT8_MIN (-0x7f-1) +#define INT16_MIN (-0x7fff-1) +#define INT32_MIN (-0x7fffffff-1) +#define INT64_MIN (-__INT64_C(0x7fffffffffffffff)-1) + +/* Maximum values of exact-width signed integer types. */ +#define INT8_MAX 0x7f +#define INT16_MAX 0x7fff +#define INT32_MAX 0x7fffffff +#define INT64_MAX __INT64_C(0x7fffffffffffffff) + +/* Maximum values of exact-width unsigned integer types. */ +#define UINT8_MAX 0xff +#define UINT16_MAX 0xffff +#define UINT32_MAX 0xffffffff +#define UINT64_MAX __UINT64_C(0xffffffffffffffff) + +/* + * ISO/IEC 9899:1999 + * 7.18.2.2 Limits of minimum-width integer types + */ +/* Minimum values of minimum-width signed integer types. */ +#define INT_LEAST8_MIN INT8_MIN +#define INT_LEAST16_MIN INT16_MIN +#define INT_LEAST32_MIN INT32_MIN +#define INT_LEAST64_MIN INT64_MIN + +/* Maximum values of minimum-width signed integer types. */ +#define INT_LEAST8_MAX INT8_MAX +#define INT_LEAST16_MAX INT16_MAX +#define INT_LEAST32_MAX INT32_MAX +#define INT_LEAST64_MAX INT64_MAX + +/* Maximum values of minimum-width unsigned integer types. */ +#define UINT_LEAST8_MAX UINT8_MAX +#define UINT_LEAST16_MAX UINT16_MAX +#define UINT_LEAST32_MAX UINT32_MAX +#define UINT_LEAST64_MAX UINT64_MAX + +/* + * ISO/IEC 9899:1999 + * 7.18.2.3 Limits of fastest minimum-width integer types + */ +/* Minimum values of fastest minimum-width signed integer types. */ +#define INT_FAST8_MIN INT32_MIN +#define INT_FAST16_MIN INT32_MIN +#define INT_FAST32_MIN INT32_MIN +#define INT_FAST64_MIN INT64_MIN + +/* Maximum values of fastest minimum-width signed integer types. */ +#define INT_FAST8_MAX INT32_MAX +#define INT_FAST16_MAX INT32_MAX +#define INT_FAST32_MAX INT32_MAX +#define INT_FAST64_MAX INT64_MAX + +/* Maximum values of fastest minimum-width unsigned integer types. */ +#define UINT_FAST8_MAX UINT32_MAX +#define UINT_FAST16_MAX UINT32_MAX +#define UINT_FAST32_MAX UINT32_MAX +#define UINT_FAST64_MAX UINT64_MAX + +/* + * ISO/IEC 9899:1999 + * 7.18.2.4 Limits of integer types capable of holding object pointers + */ +#ifdef __LP64__ +#define INTPTR_MIN INT64_MIN +#define INTPTR_MAX INT64_MAX +#define UINTPTR_MAX UINT64_MAX +#else +#define INTPTR_MIN INT32_MIN +#define INTPTR_MAX INT32_MAX +#define UINTPTR_MAX UINT32_MAX +#endif + +/* + * ISO/IEC 9899:1999 + * 7.18.2.5 Limits of greatest-width integer types + */ +#define INTMAX_MIN INT64_MIN +#define INTMAX_MAX INT64_MAX +#define UINTMAX_MAX UINT64_MAX + +/* + * ISO/IEC 9899:1999 + * 7.18.3 Limits of other integer types + */ +#ifdef __LP64__ +/* Limits of ptrdiff_t. */ +#define PTRDIFF_MIN INT64_MIN +#define PTRDIFF_MAX INT64_MAX + +/* Limits of sig_atomic_t. */ +#define SIG_ATOMIC_MIN INT64_MIN +#define SIG_ATOMIC_MAX INT64_MAX + +/* Limit of size_t. */ +#define SIZE_MAX UINT64_MAX +#else +/* Limits of ptrdiff_t. */ +#define PTRDIFF_MIN INT32_MIN +#define PTRDIFF_MAX INT32_MAX + +/* Limits of sig_atomic_t. */ +#define SIG_ATOMIC_MIN INT32_MIN +#define SIG_ATOMIC_MAX INT32_MAX + +/* Limit of size_t. */ +#define SIZE_MAX UINT32_MAX +#endif + +/* Limits of wint_t. */ +#define WINT_MIN INT32_MIN +#define WINT_MAX INT32_MAX + +#endif /* !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) */ + +#endif /* !_MACHINE__STDINT_H_ */ diff --git a/sys/powerpc/include/_types.h b/sys/powerpc/include/_types.h new file mode 100644 index 000000000000..33cc6e731b50 --- /dev/null +++ b/sys/powerpc/include/_types.h @@ -0,0 +1,89 @@ +/*- + * SPDX-License-Identifier: BSD-4-Clause + * + * Copyright (c) 2002 Mike Barcroft <mike@FreeBSD.org> + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _MACHINE__TYPES_H_ +#define _MACHINE__TYPES_H_ + +#ifndef _SYS__TYPES_H_ +#error do not include this header, use sys/_types.h +#endif + +/* + * Standard type definitions. + */ +typedef __uint32_t __clock_t; /* clock()... */ +#ifndef _STANDALONE +typedef double __double_t; +typedef float __float_t; +#endif +#ifdef __LP64__ +typedef __int64_t __critical_t; +#else +typedef __int32_t __critical_t; +#endif +typedef __int32_t __int_fast8_t; +typedef __int32_t __int_fast16_t; +typedef __int32_t __int_fast32_t; +typedef __int64_t __int_fast64_t; +#ifdef __LP64__ +typedef __int64_t __register_t; +typedef __int64_t __segsz_t; /* segment size (in pages) */ +#else +typedef __int32_t __register_t; +typedef __int32_t __segsz_t; /* segment size (in pages) */ +#endif +typedef __int64_t __time_t; /* time()... */ +typedef __uint32_t __uint_fast8_t; +typedef __uint32_t __uint_fast16_t; +typedef __uint32_t __uint_fast32_t; +typedef __uint64_t __uint_fast64_t; +#ifdef __LP64__ +typedef __uint64_t __u_register_t; +typedef __uint64_t __vm_paddr_t; +#else +typedef __uint32_t __u_register_t; +#ifdef BOOKE +typedef __uint64_t __vm_paddr_t; +#else +typedef __uint32_t __vm_paddr_t; +#endif +#endif +typedef int ___wchar_t; + +#define __WCHAR_MIN __INT_MIN /* min value for a wchar_t */ +#define __WCHAR_MAX __INT_MAX /* max value for a wchar_t */ + +#endif /* !_MACHINE__TYPES_H_ */ diff --git a/sys/powerpc/include/altivec.h b/sys/powerpc/include/altivec.h new file mode 100644 index 000000000000..e5151529f698 --- /dev/null +++ b/sys/powerpc/include/altivec.h @@ -0,0 +1,41 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2008 Nathan Whitehorn + * All rights reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _MACHINE_ALTIVEC_H_ +#define _MACHINE_ALTIVEC_H_ + +#define ALTIVEC_VSCR_NJ 0x00010000 /* Enable non-Java mode */ +#define ALTIVEC_VSCR_SAT 0x00000001 /* Saturation status bit */ + +void enable_vec(struct thread *); +void save_vec(struct thread *); +void save_vec_nodrop(struct thread *); +void enable_vec_kern(void); +void disable_vec(struct thread *td); + +#endif /* _MACHINE_ALTIVEC_H_ */ diff --git a/sys/powerpc/include/asm.h b/sys/powerpc/include/asm.h new file mode 100644 index 000000000000..35a8536776ea --- /dev/null +++ b/sys/powerpc/include/asm.h @@ -0,0 +1,267 @@ +/*- + * SPDX-License-Identifier: BSD-4-Clause + * + * Copyright (C) 1995, 1996 Wolfgang Solfrank. + * Copyright (C) 1995, 1996 TooLs GmbH. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by TooLs GmbH. + * 4. The name of TooLs GmbH may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $NetBSD: asm.h,v 1.6.18.1 2000/07/25 08:37:14 kleink Exp $ + */ + +#ifndef _MACHINE_ASM_H_ +#define _MACHINE_ASM_H_ + +#include <sys/cdefs.h> + +#if defined(PIC) && !defined(__powerpc64__) +#define PIC_PROLOGUE XXX +#define PIC_EPILOGUE XXX +#define PIC_PLT(x) x@plt +#ifdef __STDC__ +#define PIC_GOT(x) XXX +#else /* not __STDC__ */ +#define PIC_GOT(x) XXX +#endif /* __STDC__ */ +#else +#define PIC_PROLOGUE +#define PIC_EPILOGUE +#define PIC_PLT(x) x +#define PIC_GOT(x) x +#endif + +#define CNAME(csym) csym +#define ASMNAME(asmsym) asmsym +#ifdef __powerpc64__ +#define HIDENAME(asmsym) __CONCAT(_,asmsym) +#else +#define HIDENAME(asmsym) __CONCAT(.,asmsym) +#endif + +#if !defined(_CALL_ELF) || _CALL_ELF == 1 +#ifdef _KERNEL +/* ELFv1 kernel uses global dot symbols */ +#define DOT_LABEL(name) __CONCAT(.,name) +#define TYPE_ENTRY(name) .size name,24; \ + .type DOT_LABEL(name),@function; \ + .globl DOT_LABEL(name); +#define END_SIZE(name) .size DOT_LABEL(name),.-DOT_LABEL(name); +#else /* !_KERNEL */ +/* ELFv1 user code uses local function entry points */ +#define DOT_LABEL(name) __CONCAT(.L.,name) +#define TYPE_ENTRY(name) .type name,@function; +#define END_SIZE(name) .size name,.-DOT_LABEL(name); +#endif /* _KERNEL */ +#else +/* ELFv2 doesn't have any of this complication */ +#define DOT_LABEL(name) name +#define TYPE_ENTRY(name) .type name,@function; +#define END_SIZE(name) .size name,.-DOT_LABEL(name); +#endif + +#define _GLOBAL(name) \ + .data; \ + .p2align 2; \ + .globl name; \ + name: + +#ifdef __powerpc64__ +#define TOC_NAME_FOR_REF(name) __CONCAT(.L,name) +#define TOC_REF(name) TOC_NAME_FOR_REF(name)@toc +#define TOC_ENTRY(name) \ + .section ".toc","aw"; \ + TOC_NAME_FOR_REF(name): \ + .tc name[TC],name +#endif + +#ifdef __powerpc64__ + +#if !defined(_CALL_ELF) || _CALL_ELF == 1 +#define _ENTRY(name) \ + .section ".text"; \ + .p2align 2; \ + .globl name; \ + .section ".opd","aw"; \ + .p2align 3; \ +name: \ + .quad DOT_LABEL(name),.TOC.@tocbase,0; \ + .previous; \ + .p2align 4; \ + TYPE_ENTRY(name) \ +DOT_LABEL(name): \ + .cfi_startproc +#define _NAKED_ENTRY(name) _ENTRY(name) +#else +#define _ENTRY(name) \ + .text; \ + .p2align 4; \ + .globl name; \ + .type name,@function; \ +name: \ + .cfi_startproc; \ + addis %r2, %r12, (.TOC.-name)@ha; \ + addi %r2, %r2, (.TOC.-name)@l; \ + .localentry name, .-name; + +/* "Naked" function entry. No TOC prologue for ELFv2. */ +#define _NAKED_ENTRY(name) \ + .text; \ + .p2align 4; \ + .globl name; \ + .type name,@function; \ +name: \ + .cfi_startproc; \ + .localentry name, .-name; +#endif + +#define _END(name) \ + .cfi_endproc; \ + .long 0; \ + .byte 0,0,0,0,0,0,0,0; \ + END_SIZE(name) + +#define LOAD_ADDR(reg, var) \ + lis reg, var@highest; \ + ori reg, reg, var@higher; \ + rldicr reg, reg, 32, 31; \ + oris reg, reg, var@h; \ + ori reg, reg, var@l; +#else /* !__powerpc64__ */ +#define _ENTRY(name) \ + .text; \ + .p2align 4; \ + .globl name; \ + .type name,@function; \ +name: \ + .cfi_startproc +#define _END(name) \ + .cfi_endproc; \ + .size name, . - name + +#define _NAKED_ENTRY(name) _ENTRY(name) + +#define LOAD_ADDR(reg, var) \ + lis reg, var@ha; \ + ori reg, reg, var@l; +#endif /* __powerpc64__ */ + +#if defined(PROF) || (defined(_KERNEL) && defined(GPROF)) +# ifdef __powerpc64__ +# define _PROF_PROLOGUE mflr 0; \ + std 3,48(1); \ + std 4,56(1); \ + std 5,64(1); \ + std 0,16(1); \ + stdu 1,-112(1); \ + bl _mcount; \ + nop; \ + ld 0,112+16(1); \ + ld 3,112+48(1); \ + ld 4,112+56(1); \ + ld 5,112+64(1); \ + mtlr 0; \ + addi 1,1,112 +# else +# define _PROF_PROLOGUE mflr 0; stw 0,4(1); bl _mcount +# endif +#else +# define _PROF_PROLOGUE +#endif + +#define ASEND(y) _END(ASMNAME(y)) +#define ASENTRY(y) _ENTRY(ASMNAME(y)); _PROF_PROLOGUE +#define END(y) _END(CNAME(y)) +#define ENTRY(y) _ENTRY(CNAME(y)); _PROF_PROLOGUE +#define GLOBAL(y) _GLOBAL(CNAME(y)) + +#define ASENTRY_NOPROF(y) _ENTRY(ASMNAME(y)) +#define ENTRY_NOPROF(y) _ENTRY(CNAME(y)) + +/* Load NIA without affecting branch prediction */ +#define LOAD_LR_NIA bcl 20, 31, .+4 + +/* + * Magic sequence to return to native endian. + * Overwrites r0 and r11. + * + * The encoding of the instruction "tdi 0, %r0, 0x48" in opposite endian + * happens to be "b . + 8". This is useful because we can write a sequence + * of instructions that can execute in either endian. + * + * Use a sequence of handcoded instructions that switches contexts to the + * instruction following the sequence, but with the correct PSL_LE bit. + * + * The same sequence works for both BE and LE because the xori will flip + * the bit to the other state, and the code only runs when running in the + * wrong endian. + * + * This sequence is NMI-reentrant. + * + * Do not change the length of this sequence without looking at the users, + * this is used in size-constrained places like the reset vector! + */ +#define RETURN_TO_NATIVE_ENDIAN \ + tdi 0, %r0, 0x48; /* Endian swapped: b . + 8 */\ + b 1f; /* Will fall through to here if correct */\ + .long 0xa600607d; /* mfmsr %r11 */\ + .long 0x00000038; /* li %r0, 0 */\ + .long 0x6401617d; /* mtmsrd %r0, 1 (L=1 EE,RI bits only) */\ + .long 0x01006b69; /* xori %r11, %r11, 0x1 (PSL_LE) */\ + .long 0xa602087c; /* mflr %r0 */\ + .long 0x05009f42; /* LOAD_LR_NIA */\ + .long 0xa6037b7d; /* 0: mtsrr1 %r11 */\ + .long 0xa602687d; /* mflr %r11 */\ + .long 0x18006b39; /* addi %r11, %r11, (1f - 0b) */\ + .long 0xa6037a7d; /* mtsrr0 %r11 */\ + .long 0xa603087c; /* mtlr %r0 */\ + .long 0x2400004c; /* rfid */\ +1: /* RETURN_TO_NATIVE_ENDIAN */ + +#define ASMSTR .asciz + +#define RCSID(x) .text; .asciz x + +#undef __FBSDID +#if !defined(lint) && !defined(STRIP_FBSDID) +#define __FBSDID(s) .ident s +#else +#define __FBSDID(s) /* nothing */ +#endif /* not lint and not STRIP_FBSDID */ + +#define WEAK_REFERENCE(sym, alias) \ + .weak alias; \ + .equ alias,sym + +#ifdef __STDC__ +#define WARN_REFERENCES(_sym,_msg) \ + .section .gnu.warning. ## _sym ; .ascii _msg ; .text +#else +#define WARN_REFERENCES(_sym,_msg) \ + .section .gnu.warning./**/_sym ; .ascii _msg ; .text +#endif /* __STDC__ */ + +#endif /* !_MACHINE_ASM_H_ */ diff --git a/sys/powerpc/include/atomic.h b/sys/powerpc/include/atomic.h new file mode 100644 index 000000000000..b2d7549e5bd0 --- /dev/null +++ b/sys/powerpc/include/atomic.h @@ -0,0 +1,1183 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2008 Marcel Moolenaar + * Copyright (c) 2001 Benno Rice + * Copyright (c) 2001 David E. O'Brien + * Copyright (c) 1998 Doug Rabson + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _MACHINE_ATOMIC_H_ +#define _MACHINE_ATOMIC_H_ + +#include <sys/atomic_common.h> + +#ifndef __powerpc64__ +#include <sys/_atomic64e.h> +#endif + +/* + * The __ATOMIC_REL/ACQ() macros provide memory barriers only in conjunction + * with the atomic lXarx/stXcx. sequences below. They are not exposed outside + * of this file. See also Appendix B.2 of Book II of the architecture manual. + * + * Note that not all Book-E processors accept the light-weight sync variant. + * In particular, early models of E500 cores are known to wedge. Bank on all + * 64-bit capable CPUs to accept lwsync properly and pressimize 32-bit CPUs + * to use the heavier-weight sync. + */ + +#ifdef __powerpc64__ +#define mb() __asm __volatile("sync" : : : "memory") +#define rmb() __asm __volatile("lwsync" : : : "memory") +#define wmb() __asm __volatile("lwsync" : : : "memory") +#define __ATOMIC_REL() __asm __volatile("lwsync" : : : "memory") +#define __ATOMIC_ACQ() __asm __volatile("isync" : : : "memory") +#else +#define mb() __asm __volatile("sync" : : : "memory") +#define rmb() __asm __volatile("sync" : : : "memory") +#define wmb() __asm __volatile("sync" : : : "memory") +#define __ATOMIC_REL() __asm __volatile("sync" : : : "memory") +#define __ATOMIC_ACQ() __asm __volatile("isync" : : : "memory") +#endif + +static __inline void +powerpc_lwsync(void) +{ + +#ifdef __powerpc64__ + __asm __volatile("lwsync" : : : "memory"); +#else + __asm __volatile("sync" : : : "memory"); +#endif +} + +/* + * atomic_add(p, v) + * { *p += v; } + */ + +#define __atomic_add_int(p, v, t) \ + __asm __volatile( \ + "1: lwarx %0, 0, %2\n" \ + " add %0, %3, %0\n" \ + " stwcx. %0, 0, %2\n" \ + " bne- 1b\n" \ + : "=&r" (t), "=m" (*p) \ + : "r" (p), "r" (v), "m" (*p) \ + : "cr0", "memory") \ + /* __atomic_add_int */ + +#ifdef __powerpc64__ +#define __atomic_add_long(p, v, t) \ + __asm __volatile( \ + "1: ldarx %0, 0, %2\n" \ + " add %0, %3, %0\n" \ + " stdcx. %0, 0, %2\n" \ + " bne- 1b\n" \ + : "=&r" (t), "=m" (*p) \ + : "r" (p), "r" (v), "m" (*p) \ + : "cr0", "memory") \ + /* __atomic_add_long */ +#else +#define __atomic_add_long(p, v, t) \ + __asm __volatile( \ + "1: lwarx %0, 0, %2\n" \ + " add %0, %3, %0\n" \ + " stwcx. %0, 0, %2\n" \ + " bne- 1b\n" \ + : "=&r" (t), "=m" (*p) \ + : "r" (p), "r" (v), "m" (*p) \ + : "cr0", "memory") \ + /* __atomic_add_long */ +#endif + +#define _ATOMIC_ADD(type) \ + static __inline void \ + atomic_add_##type(volatile u_##type *p, u_##type v) { \ + u_##type t; \ + __atomic_add_##type(p, v, t); \ + } \ + \ + static __inline void \ + atomic_add_acq_##type(volatile u_##type *p, u_##type v) { \ + u_##type t; \ + __atomic_add_##type(p, v, t); \ + __ATOMIC_ACQ(); \ + } \ + \ + static __inline void \ + atomic_add_rel_##type(volatile u_##type *p, u_##type v) { \ + u_##type t; \ + __ATOMIC_REL(); \ + __atomic_add_##type(p, v, t); \ + } \ + /* _ATOMIC_ADD */ + +_ATOMIC_ADD(int) +_ATOMIC_ADD(long) + +#define atomic_add_32 atomic_add_int +#define atomic_add_acq_32 atomic_add_acq_int +#define atomic_add_rel_32 atomic_add_rel_int + +#ifdef __powerpc64__ +#define atomic_add_64 atomic_add_long +#define atomic_add_acq_64 atomic_add_acq_long +#define atomic_add_rel_64 atomic_add_rel_long + +#define atomic_add_ptr atomic_add_long +#define atomic_add_acq_ptr atomic_add_acq_long +#define atomic_add_rel_ptr atomic_add_rel_long +#else +#define atomic_add_ptr atomic_add_int +#define atomic_add_acq_ptr atomic_add_acq_int +#define atomic_add_rel_ptr atomic_add_rel_int +#endif +#undef _ATOMIC_ADD +#undef __atomic_add_long +#undef __atomic_add_int + +/* + * atomic_clear(p, v) + * { *p &= ~v; } + */ + +#define __atomic_clear_int(p, v, t) \ + __asm __volatile( \ + "1: lwarx %0, 0, %2\n" \ + " andc %0, %0, %3\n" \ + " stwcx. %0, 0, %2\n" \ + " bne- 1b\n" \ + : "=&r" (t), "=m" (*p) \ + : "r" (p), "r" (v), "m" (*p) \ + : "cr0", "memory") \ + /* __atomic_clear_int */ + +#ifdef __powerpc64__ +#define __atomic_clear_long(p, v, t) \ + __asm __volatile( \ + "1: ldarx %0, 0, %2\n" \ + " andc %0, %0, %3\n" \ + " stdcx. %0, 0, %2\n" \ + " bne- 1b\n" \ + : "=&r" (t), "=m" (*p) \ + : "r" (p), "r" (v), "m" (*p) \ + : "cr0", "memory") \ + /* __atomic_clear_long */ +#else +#define __atomic_clear_long(p, v, t) \ + __asm __volatile( \ + "1: lwarx %0, 0, %2\n" \ + " andc %0, %0, %3\n" \ + " stwcx. %0, 0, %2\n" \ + " bne- 1b\n" \ + : "=&r" (t), "=m" (*p) \ + : "r" (p), "r" (v), "m" (*p) \ + : "cr0", "memory") \ + /* __atomic_clear_long */ +#endif + +#define _ATOMIC_CLEAR(type) \ + static __inline void \ + atomic_clear_##type(volatile u_##type *p, u_##type v) { \ + u_##type t; \ + __atomic_clear_##type(p, v, t); \ + } \ + \ + static __inline void \ + atomic_clear_acq_##type(volatile u_##type *p, u_##type v) { \ + u_##type t; \ + __atomic_clear_##type(p, v, t); \ + __ATOMIC_ACQ(); \ + } \ + \ + static __inline void \ + atomic_clear_rel_##type(volatile u_##type *p, u_##type v) { \ + u_##type t; \ + __ATOMIC_REL(); \ + __atomic_clear_##type(p, v, t); \ + } \ + /* _ATOMIC_CLEAR */ + +_ATOMIC_CLEAR(int) +_ATOMIC_CLEAR(long) + +#define atomic_clear_32 atomic_clear_int +#define atomic_clear_acq_32 atomic_clear_acq_int +#define atomic_clear_rel_32 atomic_clear_rel_int + +#ifdef __powerpc64__ +#define atomic_clear_64 atomic_clear_long +#define atomic_clear_acq_64 atomic_clear_acq_long +#define atomic_clear_rel_64 atomic_clear_rel_long + +#define atomic_clear_ptr atomic_clear_long +#define atomic_clear_acq_ptr atomic_clear_acq_long +#define atomic_clear_rel_ptr atomic_clear_rel_long +#else +#define atomic_clear_ptr atomic_clear_int +#define atomic_clear_acq_ptr atomic_clear_acq_int +#define atomic_clear_rel_ptr atomic_clear_rel_int +#endif +#undef _ATOMIC_CLEAR +#undef __atomic_clear_long +#undef __atomic_clear_int + +/* + * atomic_cmpset(p, o, n) + */ +/* TODO -- see below */ + +/* + * atomic_load_acq(p) + */ +/* TODO -- see below */ + +/* + * atomic_readandclear(p) + */ +/* TODO -- see below */ + +/* + * atomic_set(p, v) + * { *p |= v; } + */ + +#define __atomic_set_int(p, v, t) \ + __asm __volatile( \ + "1: lwarx %0, 0, %2\n" \ + " or %0, %3, %0\n" \ + " stwcx. %0, 0, %2\n" \ + " bne- 1b\n" \ + : "=&r" (t), "=m" (*p) \ + : "r" (p), "r" (v), "m" (*p) \ + : "cr0", "memory") \ + /* __atomic_set_int */ + +#ifdef __powerpc64__ +#define __atomic_set_long(p, v, t) \ + __asm __volatile( \ + "1: ldarx %0, 0, %2\n" \ + " or %0, %3, %0\n" \ + " stdcx. %0, 0, %2\n" \ + " bne- 1b\n" \ + : "=&r" (t), "=m" (*p) \ + : "r" (p), "r" (v), "m" (*p) \ + : "cr0", "memory") \ + /* __atomic_set_long */ +#else +#define __atomic_set_long(p, v, t) \ + __asm __volatile( \ + "1: lwarx %0, 0, %2\n" \ + " or %0, %3, %0\n" \ + " stwcx. %0, 0, %2\n" \ + " bne- 1b\n" \ + : "=&r" (t), "=m" (*p) \ + : "r" (p), "r" (v), "m" (*p) \ + : "cr0", "memory") \ + /* __atomic_set_long */ +#endif + +#define _ATOMIC_SET(type) \ + static __inline void \ + atomic_set_##type(volatile u_##type *p, u_##type v) { \ + u_##type t; \ + __atomic_set_##type(p, v, t); \ + } \ + \ + static __inline void \ + atomic_set_acq_##type(volatile u_##type *p, u_##type v) { \ + u_##type t; \ + __atomic_set_##type(p, v, t); \ + __ATOMIC_ACQ(); \ + } \ + \ + static __inline void \ + atomic_set_rel_##type(volatile u_##type *p, u_##type v) { \ + u_##type t; \ + __ATOMIC_REL(); \ + __atomic_set_##type(p, v, t); \ + } \ + /* _ATOMIC_SET */ + +_ATOMIC_SET(int) +_ATOMIC_SET(long) + +#define atomic_set_32 atomic_set_int +#define atomic_set_acq_32 atomic_set_acq_int +#define atomic_set_rel_32 atomic_set_rel_int + +#ifdef __powerpc64__ +#define atomic_set_64 atomic_set_long +#define atomic_set_acq_64 atomic_set_acq_long +#define atomic_set_rel_64 atomic_set_rel_long + +#define atomic_set_ptr atomic_set_long +#define atomic_set_acq_ptr atomic_set_acq_long +#define atomic_set_rel_ptr atomic_set_rel_long +#else +#define atomic_set_ptr atomic_set_int +#define atomic_set_acq_ptr atomic_set_acq_int +#define atomic_set_rel_ptr atomic_set_rel_int +#endif +#undef _ATOMIC_SET +#undef __atomic_set_long +#undef __atomic_set_int + +/* + * atomic_subtract(p, v) + * { *p -= v; } + */ + +#define __atomic_subtract_int(p, v, t) \ + __asm __volatile( \ + "1: lwarx %0, 0, %2\n" \ + " subf %0, %3, %0\n" \ + " stwcx. %0, 0, %2\n" \ + " bne- 1b\n" \ + : "=&r" (t), "=m" (*p) \ + : "r" (p), "r" (v), "m" (*p) \ + : "cr0", "memory") \ + /* __atomic_subtract_int */ + +#ifdef __powerpc64__ +#define __atomic_subtract_long(p, v, t) \ + __asm __volatile( \ + "1: ldarx %0, 0, %2\n" \ + " subf %0, %3, %0\n" \ + " stdcx. %0, 0, %2\n" \ + " bne- 1b\n" \ + : "=&r" (t), "=m" (*p) \ + : "r" (p), "r" (v), "m" (*p) \ + : "cr0", "memory") \ + /* __atomic_subtract_long */ +#else +#define __atomic_subtract_long(p, v, t) \ + __asm __volatile( \ + "1: lwarx %0, 0, %2\n" \ + " subf %0, %3, %0\n" \ + " stwcx. %0, 0, %2\n" \ + " bne- 1b\n" \ + : "=&r" (t), "=m" (*p) \ + : "r" (p), "r" (v), "m" (*p) \ + : "cr0", "memory") \ + /* __atomic_subtract_long */ +#endif + +#define _ATOMIC_SUBTRACT(type) \ + static __inline void \ + atomic_subtract_##type(volatile u_##type *p, u_##type v) { \ + u_##type t; \ + __atomic_subtract_##type(p, v, t); \ + } \ + \ + static __inline void \ + atomic_subtract_acq_##type(volatile u_##type *p, u_##type v) { \ + u_##type t; \ + __atomic_subtract_##type(p, v, t); \ + __ATOMIC_ACQ(); \ + } \ + \ + static __inline void \ + atomic_subtract_rel_##type(volatile u_##type *p, u_##type v) { \ + u_##type t; \ + __ATOMIC_REL(); \ + __atomic_subtract_##type(p, v, t); \ + } \ + /* _ATOMIC_SUBTRACT */ + +_ATOMIC_SUBTRACT(int) +_ATOMIC_SUBTRACT(long) + +#define atomic_subtract_32 atomic_subtract_int +#define atomic_subtract_acq_32 atomic_subtract_acq_int +#define atomic_subtract_rel_32 atomic_subtract_rel_int + +#ifdef __powerpc64__ +#define atomic_subtract_64 atomic_subtract_long +#define atomic_subtract_acq_64 atomic_subract_acq_long +#define atomic_subtract_rel_64 atomic_subtract_rel_long + +#define atomic_subtract_ptr atomic_subtract_long +#define atomic_subtract_acq_ptr atomic_subtract_acq_long +#define atomic_subtract_rel_ptr atomic_subtract_rel_long +#else +#define atomic_subtract_ptr atomic_subtract_int +#define atomic_subtract_acq_ptr atomic_subtract_acq_int +#define atomic_subtract_rel_ptr atomic_subtract_rel_int +#endif +#undef _ATOMIC_SUBTRACT +#undef __atomic_subtract_long +#undef __atomic_subtract_int + +/* + * atomic_store_rel(p, v) + */ +/* TODO -- see below */ + +/* + * Old/original implementations that still need revisiting. + */ + +static __inline u_int +atomic_readandclear_int(volatile u_int *addr) +{ + u_int result,temp; + + __asm __volatile ( + "\tsync\n" /* drain writes */ + "1:\tlwarx %0, 0, %3\n\t" /* load old value */ + "li %1, 0\n\t" /* load new value */ + "stwcx. %1, 0, %3\n\t" /* attempt to store */ + "bne- 1b\n\t" /* spin if failed */ + : "=&r"(result), "=&r"(temp), "=m" (*addr) + : "r" (addr), "m" (*addr) + : "cr0", "memory"); + + return (result); +} + +#ifdef __powerpc64__ +static __inline u_long +atomic_readandclear_long(volatile u_long *addr) +{ + u_long result,temp; + + __asm __volatile ( + "\tsync\n" /* drain writes */ + "1:\tldarx %0, 0, %3\n\t" /* load old value */ + "li %1, 0\n\t" /* load new value */ + "stdcx. %1, 0, %3\n\t" /* attempt to store */ + "bne- 1b\n\t" /* spin if failed */ + : "=&r"(result), "=&r"(temp), "=m" (*addr) + : "r" (addr), "m" (*addr) + : "cr0", "memory"); + + return (result); +} +#endif + +#define atomic_readandclear_32 atomic_readandclear_int + +#ifdef __powerpc64__ +#define atomic_readandclear_64 atomic_readandclear_long + +#define atomic_readandclear_ptr atomic_readandclear_long +#else +static __inline u_long +atomic_readandclear_long(volatile u_long *addr) +{ + + return ((u_long)atomic_readandclear_int((volatile u_int *)addr)); +} + +#define atomic_readandclear_ptr atomic_readandclear_int +#endif + +/* + * We assume that a = b will do atomic loads and stores. + */ +#define ATOMIC_STORE_LOAD(TYPE) \ +static __inline u_##TYPE \ +atomic_load_acq_##TYPE(const volatile u_##TYPE *p) \ +{ \ + u_##TYPE v; \ + \ + v = *p; \ + powerpc_lwsync(); \ + return (v); \ +} \ + \ +static __inline void \ +atomic_store_rel_##TYPE(volatile u_##TYPE *p, u_##TYPE v) \ +{ \ + \ + powerpc_lwsync(); \ + *p = v; \ +} + +ATOMIC_STORE_LOAD(int) + +#define atomic_load_acq_32 atomic_load_acq_int +#define atomic_store_rel_32 atomic_store_rel_int + +#ifdef __powerpc64__ +ATOMIC_STORE_LOAD(long) + +#define atomic_load_acq_64 atomic_load_acq_long +#define atomic_store_rel_64 atomic_store_rel_long + +#define atomic_load_acq_ptr atomic_load_acq_long +#define atomic_store_rel_ptr atomic_store_rel_long +#else +static __inline u_long +atomic_load_acq_long(const volatile u_long *addr) +{ + + return ((u_long)atomic_load_acq_int((const volatile u_int *)addr)); +} + +static __inline void +atomic_store_rel_long(volatile u_long *addr, u_long val) +{ + + atomic_store_rel_int((volatile u_int *)addr, (u_int)val); +} + +#define atomic_load_acq_ptr atomic_load_acq_int +#define atomic_store_rel_ptr atomic_store_rel_int +#endif +#undef ATOMIC_STORE_LOAD + +/* + * Atomically compare the value stored at *p with cmpval and if the + * two values are equal, update the value of *p with newval. Returns + * zero if the compare failed, nonzero otherwise. + */ +#ifdef ISA_206_ATOMICS +static __inline int +atomic_cmpset_char(volatile u_char *p, u_char cmpval, u_char newval) +{ + int ret; + + __asm __volatile ( + "1:\tlbarx %0, 0, %2\n\t" /* load old value */ + "cmplw %3, %0\n\t" /* compare */ + "bne- 2f\n\t" /* exit if not equal */ + "stbcx. %4, 0, %2\n\t" /* attempt to store */ + "bne- 1b\n\t" /* spin if failed */ + "li %0, 1\n\t" /* success - retval = 1 */ + "b 3f\n\t" /* we've succeeded */ + "2:\n\t" + "stbcx. %0, 0, %2\n\t" /* clear reservation (74xx) */ + "li %0, 0\n\t" /* failure - retval = 0 */ + "3:\n\t" + : "=&r" (ret), "=m" (*p) + : "r" (p), "r" (cmpval), "r" (newval), "m" (*p) + : "cr0", "memory"); + + return (ret); +} + +static __inline int +atomic_cmpset_short(volatile u_short *p, u_short cmpval, u_short newval) +{ + int ret; + + __asm __volatile ( + "1:\tlharx %0, 0, %2\n\t" /* load old value */ + "cmplw %3, %0\n\t" /* compare */ + "bne- 2f\n\t" /* exit if not equal */ + "sthcx. %4, 0, %2\n\t" /* attempt to store */ + "bne- 1b\n\t" /* spin if failed */ + "li %0, 1\n\t" /* success - retval = 1 */ + "b 3f\n\t" /* we've succeeded */ + "2:\n\t" + "sthcx. %0, 0, %2\n\t" /* clear reservation (74xx) */ + "li %0, 0\n\t" /* failure - retval = 0 */ + "3:\n\t" + : "=&r" (ret), "=m" (*p) + : "r" (p), "r" (cmpval), "r" (newval), "m" (*p) + : "cr0", "memory"); + + return (ret); +} +#else +static __inline int +atomic_cmpset_masked(uint32_t *p, uint32_t cmpval, uint32_t newval, + uint32_t mask) +{ + int ret; + uint32_t tmp; + + __asm __volatile ( + "1:\tlwarx %2, 0, %3\n\t" /* load old value */ + "and %0, %2, %7\n\t" + "cmplw %4, %0\n\t" /* compare */ + "bne- 2f\n\t" /* exit if not equal */ + "andc %2, %2, %7\n\t" + "or %2, %2, %5\n\t" + "stwcx. %2, 0, %3\n\t" /* attempt to store */ + "bne- 1b\n\t" /* spin if failed */ + "li %0, 1\n\t" /* success - retval = 1 */ + "b 3f\n\t" /* we've succeeded */ + "2:\n\t" + "stwcx. %2, 0, %3\n\t" /* clear reservation (74xx) */ + "li %0, 0\n\t" /* failure - retval = 0 */ + "3:\n\t" + : "=&r" (ret), "=m" (*p), "+&r" (tmp) + : "r" (p), "r" (cmpval), "r" (newval), "m" (*p), + "r" (mask) + : "cr0", "memory"); + + return (ret); +} + +#define _atomic_cmpset_masked_word(a,o,v,m) atomic_cmpset_masked(a, o, v, m) +#endif + +static __inline int +atomic_cmpset_int(volatile u_int* p, u_int cmpval, u_int newval) +{ + int ret; + + __asm __volatile ( + "1:\tlwarx %0, 0, %2\n\t" /* load old value */ + "cmplw %3, %0\n\t" /* compare */ + "bne- 2f\n\t" /* exit if not equal */ + "stwcx. %4, 0, %2\n\t" /* attempt to store */ + "bne- 1b\n\t" /* spin if failed */ + "li %0, 1\n\t" /* success - retval = 1 */ + "b 3f\n\t" /* we've succeeded */ + "2:\n\t" + "stwcx. %0, 0, %2\n\t" /* clear reservation (74xx) */ + "li %0, 0\n\t" /* failure - retval = 0 */ + "3:\n\t" + : "=&r" (ret), "=m" (*p) + : "r" (p), "r" (cmpval), "r" (newval), "m" (*p) + : "cr0", "memory"); + + return (ret); +} +static __inline int +atomic_cmpset_long(volatile u_long* p, u_long cmpval, u_long newval) +{ + int ret; + + __asm __volatile ( + #ifdef __powerpc64__ + "1:\tldarx %0, 0, %2\n\t" /* load old value */ + "cmpld %3, %0\n\t" /* compare */ + "bne- 2f\n\t" /* exit if not equal */ + "stdcx. %4, 0, %2\n\t" /* attempt to store */ + #else + "1:\tlwarx %0, 0, %2\n\t" /* load old value */ + "cmplw %3, %0\n\t" /* compare */ + "bne- 2f\n\t" /* exit if not equal */ + "stwcx. %4, 0, %2\n\t" /* attempt to store */ + #endif + "bne- 1b\n\t" /* spin if failed */ + "li %0, 1\n\t" /* success - retval = 1 */ + "b 3f\n\t" /* we've succeeded */ + "2:\n\t" + #ifdef __powerpc64__ + "stdcx. %0, 0, %2\n\t" /* clear reservation (74xx) */ + #else + "stwcx. %0, 0, %2\n\t" /* clear reservation (74xx) */ + #endif + "li %0, 0\n\t" /* failure - retval = 0 */ + "3:\n\t" + : "=&r" (ret), "=m" (*p) + : "r" (p), "r" (cmpval), "r" (newval), "m" (*p) + : "cr0", "memory"); + + return (ret); +} + +#define ATOMIC_CMPSET_ACQ_REL(type) \ + static __inline int \ + atomic_cmpset_acq_##type(volatile u_##type *p, \ + u_##type cmpval, u_##type newval)\ + {\ + u_##type retval; \ + retval = atomic_cmpset_##type(p, cmpval, newval);\ + __ATOMIC_ACQ();\ + return (retval);\ + }\ + static __inline int \ + atomic_cmpset_rel_##type(volatile u_##type *p, \ + u_##type cmpval, u_##type newval)\ + {\ + __ATOMIC_REL();\ + return (atomic_cmpset_##type(p, cmpval, newval));\ + }\ + struct hack + +ATOMIC_CMPSET_ACQ_REL(int); +ATOMIC_CMPSET_ACQ_REL(long); + +#ifdef ISA_206_ATOMICS +#define atomic_cmpset_8 atomic_cmpset_char +#endif +#define atomic_cmpset_acq_8 atomic_cmpset_acq_char +#define atomic_cmpset_rel_8 atomic_cmpset_rel_char + +#ifdef ISA_206_ATOMICS +#define atomic_cmpset_16 atomic_cmpset_short +#endif +#define atomic_cmpset_acq_16 atomic_cmpset_acq_short +#define atomic_cmpset_rel_16 atomic_cmpset_rel_short + +#define atomic_cmpset_32 atomic_cmpset_int +#define atomic_cmpset_acq_32 atomic_cmpset_acq_int +#define atomic_cmpset_rel_32 atomic_cmpset_rel_int + +#ifdef __powerpc64__ +#define atomic_cmpset_64 atomic_cmpset_long +#define atomic_cmpset_acq_64 atomic_cmpset_acq_long +#define atomic_cmpset_rel_64 atomic_cmpset_rel_long + +#define atomic_cmpset_ptr atomic_cmpset_long +#define atomic_cmpset_acq_ptr atomic_cmpset_acq_long +#define atomic_cmpset_rel_ptr atomic_cmpset_rel_long +#else +#define atomic_cmpset_ptr atomic_cmpset_int +#define atomic_cmpset_acq_ptr atomic_cmpset_acq_int +#define atomic_cmpset_rel_ptr atomic_cmpset_rel_int +#endif + +/* + * Atomically compare the value stored at *p with *cmpval and if the + * two values are equal, update the value of *p with newval. Returns + * zero if the compare failed and sets *cmpval to the read value from *p, + * nonzero otherwise. + */ +#ifdef ISA_206_ATOMICS +static __inline int +atomic_fcmpset_char(volatile u_char *p, u_char *cmpval, u_char newval) +{ + int ret; + + __asm __volatile ( + "lbarx %0, 0, %3\n\t" /* load old value */ + "cmplw %4, %0\n\t" /* compare */ + "bne- 1f\n\t" /* exit if not equal */ + "stbcx. %5, 0, %3\n\t" /* attempt to store */ + "bne- 1f\n\t" /* exit if failed */ + "li %0, 1\n\t" /* success - retval = 1 */ + "b 2f\n\t" /* we've succeeded */ + "1:\n\t" + "stbcx. %0, 0, %3\n\t" /* clear reservation (74xx) */ + "stbx %0, 0, %7\n\t" + "li %0, 0\n\t" /* failure - retval = 0 */ + "2:\n\t" + : "=&r" (ret), "=m" (*p), "=m" (*cmpval) + : "r" (p), "r" (*cmpval), "r" (newval), "m" (*p), "r"(cmpval) + : "cr0", "memory"); + + return (ret); +} + +static __inline int +atomic_fcmpset_short(volatile u_short *p, u_short *cmpval, u_short newval) +{ + int ret; + + __asm __volatile ( + "lharx %0, 0, %3\n\t" /* load old value */ + "cmplw %4, %0\n\t" /* compare */ + "bne- 1f\n\t" /* exit if not equal */ + "sthcx. %5, 0, %3\n\t" /* attempt to store */ + "bne- 1f\n\t" /* exit if failed */ + "li %0, 1\n\t" /* success - retval = 1 */ + "b 2f\n\t" /* we've succeeded */ + "1:\n\t" + "sthcx. %0, 0, %3\n\t" /* clear reservation (74xx) */ + "sthx %0, 0, %7\n\t" + "li %0, 0\n\t" /* failure - retval = 0 */ + "2:\n\t" + : "=&r" (ret), "=m" (*p), "=m" (*cmpval) + : "r" (p), "r" (*cmpval), "r" (newval), "m" (*p), "r"(cmpval) + : "cr0", "memory"); + + return (ret); +} +#endif /* ISA_206_ATOMICS */ + +static __inline int +atomic_fcmpset_int(volatile u_int *p, u_int *cmpval, u_int newval) +{ + int ret; + + __asm __volatile ( + "lwarx %0, 0, %3\n\t" /* load old value */ + "cmplw %4, %0\n\t" /* compare */ + "bne- 1f\n\t" /* exit if not equal */ + "stwcx. %5, 0, %3\n\t" /* attempt to store */ + "bne- 1f\n\t" /* exit if failed */ + "li %0, 1\n\t" /* success - retval = 1 */ + "b 2f\n\t" /* we've succeeded */ + "1:\n\t" + "stwcx. %0, 0, %3\n\t" /* clear reservation (74xx) */ + "stwx %0, 0, %7\n\t" + "li %0, 0\n\t" /* failure - retval = 0 */ + "2:\n\t" + : "=&r" (ret), "=m" (*p), "=m" (*cmpval) + : "r" (p), "r" (*cmpval), "r" (newval), "m" (*p), "r"(cmpval) + : "cr0", "memory"); + + return (ret); +} +static __inline int +atomic_fcmpset_long(volatile u_long *p, u_long *cmpval, u_long newval) +{ + int ret; + + __asm __volatile ( + #ifdef __powerpc64__ + "ldarx %0, 0, %3\n\t" /* load old value */ + "cmpld %4, %0\n\t" /* compare */ + "bne- 1f\n\t" /* exit if not equal */ + "stdcx. %5, 0, %3\n\t" /* attempt to store */ + #else + "lwarx %0, 0, %3\n\t" /* load old value */ + "cmplw %4, %0\n\t" /* compare */ + "bne- 1f\n\t" /* exit if not equal */ + "stwcx. %5, 0, %3\n\t" /* attempt to store */ + #endif + "bne- 1f\n\t" /* exit if failed */ + "li %0, 1\n\t" /* success - retval = 1 */ + "b 2f\n\t" /* we've succeeded */ + "1:\n\t" + #ifdef __powerpc64__ + "stdcx. %0, 0, %3\n\t" /* clear reservation (74xx) */ + "stdx %0, 0, %7\n\t" + #else + "stwcx. %0, 0, %3\n\t" /* clear reservation (74xx) */ + "stwx %0, 0, %7\n\t" + #endif + "li %0, 0\n\t" /* failure - retval = 0 */ + "2:\n\t" + : "=&r" (ret), "=m" (*p), "=m" (*cmpval) + : "r" (p), "r" (*cmpval), "r" (newval), "m" (*p), "r"(cmpval) + : "cr0", "memory"); + + return (ret); +} + +#define ATOMIC_FCMPSET_ACQ_REL(type) \ + static __inline int \ + atomic_fcmpset_acq_##type(volatile u_##type *p, \ + u_##type *cmpval, u_##type newval)\ + {\ + u_##type retval; \ + retval = atomic_fcmpset_##type(p, cmpval, newval);\ + __ATOMIC_ACQ();\ + return (retval);\ + }\ + static __inline int \ + atomic_fcmpset_rel_##type(volatile u_##type *p, \ + u_##type *cmpval, u_##type newval)\ + {\ + __ATOMIC_REL();\ + return (atomic_fcmpset_##type(p, cmpval, newval));\ + }\ + struct hack + +ATOMIC_FCMPSET_ACQ_REL(int); +ATOMIC_FCMPSET_ACQ_REL(long); + +#ifdef ISA_206_ATOMICS +#define atomic_fcmpset_8 atomic_fcmpset_char +#endif +#define atomic_fcmpset_acq_8 atomic_fcmpset_acq_char +#define atomic_fcmpset_rel_8 atomic_fcmpset_rel_char + +#ifdef ISA_206_ATOMICS +#define atomic_fcmpset_16 atomic_fcmpset_short +#endif +#define atomic_fcmpset_acq_16 atomic_fcmpset_acq_short +#define atomic_fcmpset_rel_16 atomic_fcmpset_rel_short + +#define atomic_fcmpset_32 atomic_fcmpset_int +#define atomic_fcmpset_acq_32 atomic_fcmpset_acq_int +#define atomic_fcmpset_rel_32 atomic_fcmpset_rel_int + +#ifdef __powerpc64__ +#define atomic_fcmpset_64 atomic_fcmpset_long +#define atomic_fcmpset_acq_64 atomic_fcmpset_acq_long +#define atomic_fcmpset_rel_64 atomic_fcmpset_rel_long + +#define atomic_fcmpset_ptr atomic_fcmpset_long +#define atomic_fcmpset_acq_ptr atomic_fcmpset_acq_long +#define atomic_fcmpset_rel_ptr atomic_fcmpset_rel_long +#else +#define atomic_fcmpset_ptr atomic_fcmpset_int +#define atomic_fcmpset_acq_ptr atomic_fcmpset_acq_int +#define atomic_fcmpset_rel_ptr atomic_fcmpset_rel_int +#endif + +static __inline u_int +atomic_fetchadd_int(volatile u_int *p, u_int v) +{ + u_int value; + + do { + value = *p; + } while (!atomic_cmpset_int(p, value, value + v)); + return (value); +} + +static __inline u_long +atomic_fetchadd_long(volatile u_long *p, u_long v) +{ + u_long value; + + do { + value = *p; + } while (!atomic_cmpset_long(p, value, value + v)); + return (value); +} + +static __inline u_int +atomic_swap_32(volatile u_int *p, u_int v) +{ + u_int prev; + + __asm __volatile( + "1: lwarx %0,0,%2\n" + " stwcx. %3,0,%2\n" + " bne- 1b\n" + : "=&r" (prev), "+m" (*(volatile u_int *)p) + : "r" (p), "r" (v) + : "cr0", "memory"); + + return (prev); +} + +#ifdef __powerpc64__ +static __inline u_long +atomic_swap_64(volatile u_long *p, u_long v) +{ + u_long prev; + + __asm __volatile( + "1: ldarx %0,0,%2\n" + " stdcx. %3,0,%2\n" + " bne- 1b\n" + : "=&r" (prev), "+m" (*(volatile u_long *)p) + : "r" (p), "r" (v) + : "cr0", "memory"); + + return (prev); +} +#endif + +#define atomic_fetchadd_32 atomic_fetchadd_int +#define atomic_swap_int atomic_swap_32 + +#ifdef __powerpc64__ +#define atomic_fetchadd_64 atomic_fetchadd_long +#define atomic_swap_long atomic_swap_64 +#define atomic_swap_ptr atomic_swap_64 +#else +#define atomic_swap_long(p,v) atomic_swap_32((volatile u_int *)(p), v) +#define atomic_swap_ptr(p,v) atomic_swap_32((volatile u_int *)(p), v) +#endif + +static __inline int +atomic_testandset_int(volatile u_int *p, u_int v) +{ + u_int m = (1u << (v & 0x1f)); + u_int res; + u_int tmp; + + __asm __volatile( + "1: lwarx %0,0,%3\n" + " and %1,%0,%4\n" + " or %0,%0,%4\n" + " stwcx. %0,0,%3\n" + " bne- 1b\n" + : "=&r"(tmp), "=&r"(res), "+m"(*p) + : "r"(p), "r"(m) + : "cr0", "memory"); + + return (res != 0); +} + +static __inline int +atomic_testandclear_int(volatile u_int *p, u_int v) +{ + u_int m = (1u << (v & 0x1f)); + u_int res; + u_int tmp; + + __asm __volatile( + "1: lwarx %0,0,%3\n" + " and %1,%0,%4\n" + " andc %0,%0,%4\n" + " stwcx. %0,0,%3\n" + " bne- 1b\n" + : "=&r"(tmp), "=&r"(res), "+m"(*p) + : "r"(p), "r"(m) + : "cr0", "memory"); + + return (res != 0); +} + +#ifdef __powerpc64__ +static __inline int +atomic_testandset_long(volatile u_long *p, u_int v) +{ + u_long m = (1ul << (v & 0x3f)); + u_long res; + u_long tmp; + + __asm __volatile( + "1: ldarx %0,0,%3\n" + " and %1,%0,%4\n" + " or %0,%0,%4\n" + " stdcx. %0,0,%3\n" + " bne- 1b\n" + : "=&r"(tmp), "=&r"(res), "+m"(*(volatile u_long *)p) + : "r"(p), "r"(m) + : "cr0", "memory"); + + return (res != 0); +} + +static __inline int +atomic_testandclear_long(volatile u_long *p, u_int v) +{ + u_long m = (1ul << (v & 0x3f)); + u_long res; + u_long tmp; + + __asm __volatile( + "1: ldarx %0,0,%3\n" + " and %1,%0,%4\n" + " andc %0,%0,%4\n" + " stdcx. %0,0,%3\n" + " bne- 1b\n" + : "=&r"(tmp), "=&r"(res), "+m"(*p) + : "r"(p), "r"(m) + : "cr0", "memory"); + + return (res != 0); +} +#else +static __inline int +atomic_testandset_long(volatile u_long *p, u_int v) +{ + return (atomic_testandset_int((volatile u_int *)p, v)); +} + +static __inline int +atomic_testandclear_long(volatile u_long *p, u_int v) +{ + return (atomic_testandclear_int((volatile u_int *)p, v)); +} +#endif + +#define atomic_testandclear_32 atomic_testandclear_int +#define atomic_testandset_32 atomic_testandset_int + +static __inline int +atomic_testandset_acq_long(volatile u_long *p, u_int v) +{ + u_int a = atomic_testandset_long(p, v); + __ATOMIC_ACQ(); + return (a); +} + +#ifdef __powerpc64__ +#define atomic_testandclear_ptr atomic_testandclear_long +#define atomic_testandset_ptr atomic_testandset_long +#else +#define atomic_testandclear_ptr(p,v) \ + atomic_testandclear_32((volatile u_int *)(p), v) +#define atomic_testandset_ptr(p,v) \ + atomic_testandset_32((volatile u_int *)(p), v) +#endif + +static __inline void +atomic_thread_fence_acq(void) +{ + + powerpc_lwsync(); +} + +static __inline void +atomic_thread_fence_rel(void) +{ + + powerpc_lwsync(); +} + +static __inline void +atomic_thread_fence_acq_rel(void) +{ + + powerpc_lwsync(); +} + +static __inline void +atomic_thread_fence_seq_cst(void) +{ + + __asm __volatile("sync" : : : "memory"); +} + +#ifndef ISA_206_ATOMICS +#include <sys/_atomic_subword.h> +#define atomic_cmpset_char atomic_cmpset_8 +#define atomic_cmpset_short atomic_cmpset_16 +#define atomic_fcmpset_char atomic_fcmpset_8 +#define atomic_fcmpset_short atomic_fcmpset_16 +#define atomic_set_short atomic_set_16 +#define atomic_clear_short atomic_clear_16 +#else + +static __inline void +atomic_set_short(volatile u_short *p, u_short bit) +{ + u_short v; + + v = atomic_load_short(p); + for (;;) { + if (atomic_fcmpset_16(p, &v, v | bit)) + break; + } +} + +static __inline void +atomic_clear_short(volatile u_short *p, u_short bit) +{ + u_short v; + + v = atomic_load_short(p); + for (;;) { + if (atomic_fcmpset_16(p, &v, v & ~bit)) + break; + } +} + +#define atomic_set_16 atomic_set_short +#define atomic_clear_16 atomic_clear_short + +#endif /* ISA_206_ATOMICS */ + +/* These need sys/_atomic_subword.h on non-ISA-2.06-atomic platforms. */ +ATOMIC_CMPSET_ACQ_REL(char); +ATOMIC_CMPSET_ACQ_REL(short); + +ATOMIC_FCMPSET_ACQ_REL(char); +ATOMIC_FCMPSET_ACQ_REL(short); + +#undef __ATOMIC_REL +#undef __ATOMIC_ACQ + +#endif /* ! _MACHINE_ATOMIC_H_ */ diff --git a/sys/powerpc/include/bat.h b/sys/powerpc/include/bat.h new file mode 100644 index 000000000000..e6f1ab72f51e --- /dev/null +++ b/sys/powerpc/include/bat.h @@ -0,0 +1,167 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause AND BSD-4-Clause + * + * Copyright (c) 1999 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Jason R. Thorpe. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/*- + * Copyright (C) 1995, 1996 Wolfgang Solfrank. + * Copyright (C) 1995, 1996 TooLs GmbH. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by TooLs GmbH. + * 4. The name of TooLs GmbH may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $NetBSD: bat.h,v 1.2 1999/12/18 01:36:06 thorpej Exp $ + */ + +#ifndef _MACHINE_BAT_H_ +#define _MACHINE_BAT_H_ + +#ifndef LOCORE +struct bat { + u_int32_t batu; + u_int32_t batl; +}; +#endif + +/* Lower BAT bits (all but PowerPC 601): */ +#define BAT_PBS 0xfffe0000 /* physical block start */ +#define BAT_W 0x00000040 /* 1 = write-through, 0 = write-back */ +#define BAT_I 0x00000020 /* cache inhibit */ +#define BAT_M 0x00000010 /* memory coherency enable */ +#define BAT_G 0x00000008 /* guarded region */ + +#define BAT_PP_NONE 0x00000000 /* no access permission */ +#define BAT_PP_RO_S 0x00000001 /* read-only (soft) */ +#define BAT_PP_RW 0x00000002 /* read/write */ +#define BAT_PP_RO 0x00000003 /* read-only */ + +/* Upper BAT bits (all but PowerPC 601): */ +#define BAT_EBS 0xfffe0000 /* effective block start */ +#define BAT_BL 0x00001ffc /* block length */ +#define BAT_Vs 0x00000002 /* valid in supervisor mode */ +#define BAT_Vu 0x00000001 /* valid in user mode */ + +#define BAT_V (BAT_Vs|BAT_Vu) + +/* Block Length encoding (all but PowerPC 601): */ +#define BAT_BL_128K 0x00000000 +#define BAT_BL_256K 0x00000004 +#define BAT_BL_512K 0x0000000c +#define BAT_BL_1M 0x0000001c +#define BAT_BL_2M 0x0000003c +#define BAT_BL_4M 0x0000007c +#define BAT_BL_8M 0x000000fc +#define BAT_BL_16M 0x000001fc +#define BAT_BL_32M 0x000003fc +#define BAT_BL_64M 0x000007fc +#define BAT_BL_128M 0x00000ffc +#define BAT_BL_256M 0x00001ffc + +#define BATU(va, len, v) \ + (((va) & BAT_EBS) | ((len) & BAT_BL) | ((v) & BAT_V)) + +#define BATL(pa, wimg, pp) \ + (((pa) & BAT_PBS) | (wimg) | (pp)) + +/* Lower BAT bits (PowerPC 601): */ +#define BAT601_PBN 0xfffe0000 /* physical block number */ +#define BAT601_V 0x00000040 /* valid */ +#define BAT601_BSM 0x0000003f /* block size mask */ + +/* Upper BAT bits (PowerPC 601): */ +#define BAT601_BLPI 0xfffe0000 /* block logical page index */ +#define BAT601_W 0x00000040 /* 1 = write-through, 0 = write-back */ +#define BAT601_I 0x00000020 /* cache inhibit */ +#define BAT601_M 0x00000010 /* memory coherency enable */ +#define BAT601_Ks 0x00000008 /* key-supervisor */ +#define BAT601_Ku 0x00000004 /* key-user */ + +/* + * Permission bits on the PowerPC 601 are modified by the appropriate + * Key bit: + * + * Key PP Access + * 0 NONE read/write + * 0 RO_S read/write + * 0 RW read/write + * 0 RO read-only + * + * 1 NONE none + * 1 RO_S read-only + * 1 RW read/write + * 1 RO read-only + */ +#define BAT601_PP_NONE 0x00000000 /* no access permission */ +#define BAT601_PP_RO_S 0x00000001 /* read-only (soft) */ +#define BAT601_PP_RW 0x00000002 /* read/write */ +#define BAT601_PP_RO 0x00000003 /* read-only */ + +/* Block Size Mask encoding (PowerPC 601): */ +#define BAT601_BSM_128K 0x00000000 +#define BAT601_BSM_256K 0x00000001 +#define BAT601_BSM_512K 0x00000003 +#define BAT601_BSM_1M 0x00000007 +#define BAT601_BSM_2M 0x0000000f +#define BAT601_BSM_4M 0x0000001f +#define BAT601_BSM_8M 0x0000003f + +#define BATU601(va, wim, key, pp) \ + (((va) & BAT601_BLPI) | (wim) | (key) | (pp)) + +#define BATL601(pa, size, v) \ + (((pa) & BAT601_PBN) | (v) | (size)) + +#if defined(_KERNEL) && !defined(LOCORE) +extern struct bat battable[16]; +#endif + +#endif /* _MACHINE_BAT_H_ */ diff --git a/sys/powerpc/include/bus.h b/sys/powerpc/include/bus.h new file mode 100644 index 000000000000..ddb4737d9b76 --- /dev/null +++ b/sys/powerpc/include/bus.h @@ -0,0 +1,493 @@ +/* $NetBSD: bus.h,v 1.11 2003/07/28 17:35:54 thorpej Exp $ */ + +/*- + * SPDX-License-Identifier: BSD-2-Clause AND BSD-4-Clause + * + * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, + * NASA Ames Research Center. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/*- + * Copyright (c) 1996 Charles M. Hannum. All rights reserved. + * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Christopher G. Demetriou + * for the NetBSD Project. + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _MACHINE_BUS_H_ +#define _MACHINE_BUS_H_ + +#include <machine/_bus.h> + +#define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t) + +#define BUS_SPACE_MAXADDR_24BIT 0xFFFFFFUL +#define BUS_SPACE_MAXADDR_32BIT 0xFFFFFFFFUL +#define BUS_SPACE_MAXSIZE_24BIT 0xFFFFFFUL +#define BUS_SPACE_MAXSIZE_32BIT 0xFFFFFFFFUL + +#ifdef __powerpc64__ +#define BUS_SPACE_MAXADDR 0xFFFFFFFFFFFFFFFFUL +#define BUS_SPACE_MAXSIZE 0xFFFFFFFFFFFFFFFFUL +#else +#ifdef BOOKE +#define BUS_SPACE_MAXADDR 0xFFFFFFFFFULL +#define BUS_SPACE_MAXSIZE 0xFFFFFFFFUL +#else +#define BUS_SPACE_MAXADDR 0xFFFFFFFFUL +#define BUS_SPACE_MAXSIZE 0xFFFFFFFFUL +#endif +#endif + +#define BUS_SPACE_MAP_CACHEABLE 0x01 +#define BUS_SPACE_MAP_LINEAR 0x02 +#define BUS_SPACE_MAP_PREFETCHABLE 0x04 + +#define BUS_SPACE_UNRESTRICTED (~0) + +#define BUS_SPACE_BARRIER_READ 0x01 +#define BUS_SPACE_BARRIER_WRITE 0x02 + +struct bus_space_access; + +struct bus_space { + /* mapping/unmapping */ + int (*bs_map)(bus_addr_t, bus_size_t, int, + bus_space_handle_t *); + void (*bs_unmap)(bus_space_handle_t, bus_size_t); + int (*bs_subregion)(bus_space_handle_t, bus_size_t, + bus_size_t, bus_space_handle_t *); + + /* allocation/deallocation */ + int (*bs_alloc)(bus_addr_t, bus_addr_t, bus_size_t, + bus_size_t, bus_size_t, int, bus_addr_t *, bus_space_handle_t *); + void (*bs_free)(bus_space_handle_t, bus_size_t); + + void (*bs_barrier)(bus_space_handle_t, bus_size_t, + bus_size_t, int); + + /* Read single. */ + uint8_t (*bs_r_1)(bus_space_handle_t, bus_size_t); + uint16_t (*bs_r_2)(bus_space_handle_t, bus_size_t); + uint32_t (*bs_r_4)(bus_space_handle_t, bus_size_t); + uint64_t (*bs_r_8)(bus_space_handle_t, bus_size_t); + + uint16_t (*bs_r_s_2)(bus_space_handle_t, bus_size_t); + uint32_t (*bs_r_s_4)(bus_space_handle_t, bus_size_t); + uint64_t (*bs_r_s_8)(bus_space_handle_t, bus_size_t); + + /* read multiple */ + void (*bs_rm_1)(bus_space_handle_t, bus_size_t, uint8_t *, + bus_size_t); + void (*bs_rm_2)(bus_space_handle_t, bus_size_t, uint16_t *, + bus_size_t); + void (*bs_rm_4)(bus_space_handle_t, bus_size_t, uint32_t *, + bus_size_t); + void (*bs_rm_8)(bus_space_handle_t, bus_size_t, uint64_t *, + bus_size_t); + + void (*bs_rm_s_2)(bus_space_handle_t, bus_size_t, uint16_t *, + bus_size_t); + void (*bs_rm_s_4)(bus_space_handle_t, bus_size_t, uint32_t *, + bus_size_t); + void (*bs_rm_s_8)(bus_space_handle_t, bus_size_t, uint64_t *, + bus_size_t); + + /* read region */ + void (*bs_rr_1)(bus_space_handle_t, bus_size_t, uint8_t *, + bus_size_t); + void (*bs_rr_2)(bus_space_handle_t, bus_size_t, uint16_t *, + bus_size_t); + void (*bs_rr_4)(bus_space_handle_t, bus_size_t, uint32_t *, + bus_size_t); + void (*bs_rr_8)(bus_space_handle_t, bus_size_t, uint64_t *, + bus_size_t); + + void (*bs_rr_s_2)(bus_space_handle_t, bus_size_t, uint16_t *, + bus_size_t); + void (*bs_rr_s_4)(bus_space_handle_t, bus_size_t, uint32_t *, + bus_size_t); + void (*bs_rr_s_8)(bus_space_handle_t, bus_size_t, uint64_t *, + bus_size_t); + + /* write */ + void (*bs_w_1)(bus_space_handle_t, bus_size_t, uint8_t); + void (*bs_w_2)(bus_space_handle_t, bus_size_t, uint16_t); + void (*bs_w_4)(bus_space_handle_t, bus_size_t, uint32_t); + void (*bs_w_8)(bus_space_handle_t, bus_size_t, uint64_t); + + void (*bs_w_s_2)(bus_space_handle_t, bus_size_t, uint16_t); + void (*bs_w_s_4)(bus_space_handle_t, bus_size_t, uint32_t); + void (*bs_w_s_8)(bus_space_handle_t, bus_size_t, uint64_t); + + /* write multiple */ + void (*bs_wm_1)(bus_space_handle_t, bus_size_t, + const uint8_t *, bus_size_t); + void (*bs_wm_2)(bus_space_handle_t, bus_size_t, + const uint16_t *, bus_size_t); + void (*bs_wm_4)(bus_space_handle_t, bus_size_t, + const uint32_t *, bus_size_t); + void (*bs_wm_8)(bus_space_handle_t, bus_size_t, + const uint64_t *, bus_size_t); + + void (*bs_wm_s_2)(bus_space_handle_t, bus_size_t, + const uint16_t *, bus_size_t); + void (*bs_wm_s_4)(bus_space_handle_t, bus_size_t, + const uint32_t *, bus_size_t); + void (*bs_wm_s_8)(bus_space_handle_t, bus_size_t, + const uint64_t *, bus_size_t); + + /* write region */ + void (*bs_wr_1)(bus_space_handle_t, bus_size_t, + const uint8_t *, bus_size_t); + void (*bs_wr_2)(bus_space_handle_t, bus_size_t, + const uint16_t *, bus_size_t); + void (*bs_wr_4)(bus_space_handle_t, bus_size_t, + const uint32_t *, bus_size_t); + void (*bs_wr_8)(bus_space_handle_t, bus_size_t, + const uint64_t *, bus_size_t); + + void (*bs_wr_s_2)(bus_space_handle_t, bus_size_t, + const uint16_t *, bus_size_t); + void (*bs_wr_s_4)(bus_space_handle_t, bus_size_t, + const uint32_t *, bus_size_t); + void (*bs_wr_s_8)(bus_space_handle_t, bus_size_t, + const uint64_t *, bus_size_t); + + /* set multiple */ + void (*bs_sm_1)(bus_space_handle_t, bus_size_t, uint8_t, + bus_size_t); + void (*bs_sm_2)(bus_space_handle_t, bus_size_t, uint16_t, + bus_size_t); + void (*bs_sm_4)(bus_space_handle_t, bus_size_t, uint32_t, + bus_size_t); + void (*bs_sm_8)(bus_space_handle_t, bus_size_t, uint64_t, + bus_size_t); + + void (*bs_sm_s_2)(bus_space_handle_t, bus_size_t, uint16_t, + bus_size_t); + void (*bs_sm_s_4)(bus_space_handle_t, bus_size_t, uint32_t, + bus_size_t); + void (*bs_sm_s_8)(bus_space_handle_t, bus_size_t, uint64_t, + bus_size_t); + + /* set region */ + void (*bs_sr_1)(bus_space_handle_t, bus_size_t, uint8_t, + bus_size_t); + void (*bs_sr_2)(bus_space_handle_t, bus_size_t, uint16_t, + bus_size_t); + void (*bs_sr_4)(bus_space_handle_t, bus_size_t, uint32_t, + bus_size_t); + void (*bs_sr_8)(bus_space_handle_t, bus_size_t, uint64_t, + bus_size_t); + + void (*bs_sr_s_2)(bus_space_handle_t, bus_size_t, uint16_t, + bus_size_t); + void (*bs_sr_s_4)(bus_space_handle_t, bus_size_t, uint32_t, + bus_size_t); + void (*bs_sr_s_8)(bus_space_handle_t, bus_size_t, uint64_t, + bus_size_t); + + /* copy region */ + void (*bs_cr_1)(bus_space_handle_t, bus_size_t, + bus_space_handle_t, bus_size_t, bus_size_t); + void (*bs_cr_2)(bus_space_handle_t, bus_size_t, + bus_space_handle_t, bus_size_t, bus_size_t); + void (*bs_cr_4)(bus_space_handle_t, bus_size_t, + bus_space_handle_t, bus_size_t, bus_size_t); + void (*bs_cr_8)(bus_space_handle_t, bus_size_t, + bus_space_handle_t, bus_size_t, bus_size_t); + + void (*bs_cr_s_2)(bus_space_handle_t, bus_size_t, + bus_space_handle_t, bus_size_t, bus_size_t); + void (*bs_cr_s_4)(bus_space_handle_t, bus_size_t, + bus_space_handle_t, bus_size_t, bus_size_t); + void (*bs_cr_s_8)(bus_space_handle_t, bus_size_t, + bus_space_handle_t, bus_size_t, bus_size_t); +}; + +extern struct bus_space bs_be_tag; +extern struct bus_space bs_le_tag; + +#define __bs_c(a,b) __CONCAT(a,b) +#define __bs_opname(op,size) __bs_c(__bs_c(__bs_c(bs_,op),_),size) + +#define __bs_rs(sz, t, h, o) \ + (*(t)->__bs_opname(r,sz))(h, o) +#define __bs_ws(sz, t, h, o, v) \ + (*(t)->__bs_opname(w,sz))(h, o, v) +#define __bs_nonsingle(type, sz, t, h, o, a, c) \ + (*(t)->__bs_opname(type,sz))(h, o, a, c) +#define __bs_set(type, sz, t, h, o, v, c) \ + (*(t)->__bs_opname(type,sz))(h, o, v, c) +#define __bs_copy(sz, t, h1, o1, h2, o2, cnt) \ + (*(t)->__bs_opname(c,sz))(h1, o1, h2, o2, cnt) + +/* + * Mapping and unmapping operations. + */ +#define bus_space_map(t, a, s, c, hp) (*(t)->bs_map)(a, s, c, hp) +#define bus_space_unmap(t, h, s) (*(t)->bs_unmap)(h, s) +#define bus_space_subregion(t, h, o, s, hp) (*(t)->bs_subregion)(h, o, s, hp) + +/* + * Allocation and deallocation operations. + */ +#define bus_space_alloc(t, rs, re, s, a, b, c, ap, hp) \ + (*(t)->bs_alloc)(rs, re, s, a, b, c, ap, hp) +#define bus_space_free(t, h, s) \ + (*(t)->bs_free)(h, s) + +/* + * Bus barrier operations. + */ +#define bus_space_barrier(t, h, o, l, f) (*(t)->bs_barrier)(h, o, l, f) + +/* + * Bus read (single) operations. + */ +#define bus_space_read_1(t, h, o) __bs_rs(1,t,h,o) +#define bus_space_read_2(t, h, o) __bs_rs(2,t,h,o) +#define bus_space_read_4(t, h, o) __bs_rs(4,t,h,o) +#define bus_space_read_8(t, h, o) __bs_rs(8,t,h,o) + +#define bus_space_read_stream_1 bus_space_read_1 +#define bus_space_read_stream_2(t, h, o) __bs_rs(s_2,t,h,o) +#define bus_space_read_stream_4(t, h, o) __bs_rs(s_4,t,h,o) +#define bus_space_read_stream_8(t, h, o) __bs_rs(s_8,t,h,o) + +/* + * Bus read multiple operations. + */ +#define bus_space_read_multi_1(t, h, o, a, c) \ + __bs_nonsingle(rm,1,(t),(h),(o),(a),(c)) +#define bus_space_read_multi_2(t, h, o, a, c) \ + __bs_nonsingle(rm,2,(t),(h),(o),(a),(c)) +#define bus_space_read_multi_4(t, h, o, a, c) \ + __bs_nonsingle(rm,4,(t),(h),(o),(a),(c)) +#define bus_space_read_multi_8(t, h, o, a, c) \ + __bs_nonsingle(rm,8,(t),(h),(o),(a),(c)) + +#define bus_space_read_multi_stream_1 bus_space_read_multi_1 +#define bus_space_read_multi_stream_2(t, h, o, a, c) \ + __bs_nonsingle(rm,s_2,(t),(h),(o),(a),(c)) +#define bus_space_read_multi_stream_4(t, h, o, a, c) \ + __bs_nonsingle(rm,s_4,(t),(h),(o),(a),(c)) +#define bus_space_read_multi_stream_8(t, h, o, a, c) \ + __bs_nonsingle(rm,s_8,(t),(h),(o),(a),(c)) + +/* + * Bus read region operations. + */ +#define bus_space_read_region_1(t, h, o, a, c) \ + __bs_nonsingle(rr,1,(t),(h),(o),(a),(c)) +#define bus_space_read_region_2(t, h, o, a, c) \ + __bs_nonsingle(rr,2,(t),(h),(o),(a),(c)) +#define bus_space_read_region_4(t, h, o, a, c) \ + __bs_nonsingle(rr,4,(t),(h),(o),(a),(c)) +#define bus_space_read_region_8(t, h, o, a, c) \ + __bs_nonsingle(rr,8,(t),(h),(o),(a),(c)) + +#define bus_space_read_region_stream_1 bus_space_read_region_1 +#define bus_space_read_region_stream_2(t, h, o, a, c) \ + __bs_nonsingle(rr,s_2,(t),(h),(o),(a),(c)) +#define bus_space_read_region_stream_4(t, h, o, a, c) \ + __bs_nonsingle(rr,s_4,(t),(h),(o),(a),(c)) +#define bus_space_read_region_stream_8(t, h, o, a, c) \ + __bs_nonsingle(rr,s_8,(t),(h),(o),(a),(c)) + +/* + * Bus write (single) operations. + */ +#define bus_space_write_1(t, h, o, v) __bs_ws(1,(t),(h),(o),(v)) +#define bus_space_write_2(t, h, o, v) __bs_ws(2,(t),(h),(o),(v)) +#define bus_space_write_4(t, h, o, v) __bs_ws(4,(t),(h),(o),(v)) +#define bus_space_write_8(t, h, o, v) __bs_ws(8,(t),(h),(o),(v)) + +#define bus_space_write_stream_1 bus_space_write_1 +#define bus_space_write_stream_2(t, h, o, v) __bs_ws(s_2,(t),(h),(o),(v)) +#define bus_space_write_stream_4(t, h, o, v) __bs_ws(s_4,(t),(h),(o),(v)) +#define bus_space_write_stream_8(t, h, o, v) __bs_ws(s_8,(t),(h),(o),(v)) + +/* + * Bus write multiple operations. + */ +#define bus_space_write_multi_1(t, h, o, a, c) \ + __bs_nonsingle(wm,1,(t),(h),(o),(a),(c)) +#define bus_space_write_multi_2(t, h, o, a, c) \ + __bs_nonsingle(wm,2,(t),(h),(o),(a),(c)) +#define bus_space_write_multi_4(t, h, o, a, c) \ + __bs_nonsingle(wm,4,(t),(h),(o),(a),(c)) +#define bus_space_write_multi_8(t, h, o, a, c) \ + __bs_nonsingle(wm,8,(t),(h),(o),(a),(c)) + +#define bus_space_write_multi_stream_1 bus_space_write_multi_1 +#define bus_space_write_multi_stream_2(t, h, o, a, c) \ + __bs_nonsingle(wm,s_2,(t),(h),(o),(a),(c)) +#define bus_space_write_multi_stream_4(t, h, o, a, c) \ + __bs_nonsingle(wm,s_4,(t),(h),(o),(a),(c)) +#define bus_space_write_multi_stream_8(t, h, o, a, c) \ + __bs_nonsingle(wm,s_8,(t),(h),(o),(a),(c)) + +/* + * Bus write region operations. + */ +#define bus_space_write_region_1(t, h, o, a, c) \ + __bs_nonsingle(wr,1,(t),(h),(o),(a),(c)) +#define bus_space_write_region_2(t, h, o, a, c) \ + __bs_nonsingle(wr,2,(t),(h),(o),(a),(c)) +#define bus_space_write_region_4(t, h, o, a, c) \ + __bs_nonsingle(wr,4,(t),(h),(o),(a),(c)) +#define bus_space_write_region_8(t, h, o, a, c) \ + __bs_nonsingle(wr,8,(t),(h),(o),(a),(c)) + +#define bus_space_write_region_stream_1 bus_space_write_region_1 +#define bus_space_write_region_stream_2(t, h, o, a, c) \ + __bs_nonsingle(wr,s_2,(t),(h),(o),(a),(c)) +#define bus_space_write_region_stream_4(t, h, o, a, c) \ + __bs_nonsingle(wr,s_4,(t),(h),(o),(a),(c)) +#define bus_space_write_region_stream_8(t, h, o, a, c) \ + __bs_nonsingle(wr,s_8,(t),(h),(o),(a),(c)) + +/* + * Set multiple operations. + */ +#define bus_space_set_multi_1(t, h, o, v, c) \ + __bs_set(sm,1,(t),(h),(o),(v),(c)) +#define bus_space_set_multi_2(t, h, o, v, c) \ + __bs_set(sm,2,(t),(h),(o),(v),(c)) +#define bus_space_set_multi_4(t, h, o, v, c) \ + __bs_set(sm,4,(t),(h),(o),(v),(c)) +#define bus_space_set_multi_8(t, h, o, v, c) \ + __bs_set(sm,8,(t),(h),(o),(v),(c)) + +#define bus_space_set_multi_stream_1 bus_space_set_multi_1 +#define bus_space_set_multi_stream_2(t, h, o, v, c) \ + __bs_set(sm,s_2,(t),(h),(o),(v),(c)) +#define bus_space_set_multi_stream_4(t, h, o, v, c) \ + __bs_set(sm,s_4,(t),(h),(o),(v),(c)) +#define bus_space_set_multi_stream_8(t, h, o, v, c) \ + __bs_set(sm,s_8,(t),(h),(o),(v),(c)) + +/* + * Set region operations. + */ +#define bus_space_set_region_1(t, h, o, v, c) \ + __bs_set(sr,1,(t),(h),(o),(v),(c)) +#define bus_space_set_region_2(t, h, o, v, c) \ + __bs_set(sr,2,(t),(h),(o),(v),(c)) +#define bus_space_set_region_4(t, h, o, v, c) \ + __bs_set(sr,4,(t),(h),(o),(v),(c)) +#define bus_space_set_region_8(t, h, o, v, c) \ + __bs_set(sr,8,(t),(h),(o),(v),(c)) + +#define bus_space_set_region_stream_1 bus_space_set_region_1 +#define bus_space_set_region_stream_2(t, h, o, v, c) \ + __bs_set(sr,s_2,(t),(h),(o),(v),(c)) +#define bus_space_set_region_stream_4(t, h, o, v, c) \ + __bs_set(sr,s_4,(t),(h),(o),(v),(c)) +#define bus_space_set_region_stream_8(t, h, o, v, c) \ + __bs_set(sr,s_8,(t),(h),(o),(v),(c)) + +#if 0 +/* + * Copy operations. + */ +#define bus_space_copy_region_1(t, h1, o1, h2, o2, c) \ + __bs_copy(1, t, h1, o1, h2, o2, c) +#define bus_space_copy_region_2(t, h1, o1, h2, o2, c) \ + __bs_copy(2, t, h1, o1, h2, o2, c) +#define bus_space_copy_region_4(t, h1, o1, h2, o2, c) \ + __bs_copy(4, t, h1, o1, h2, o2, c) +#define bus_space_copy_region_8(t, h1, o1, h2, o2, c) \ + __bs_copy(8, t, h1, o1, h2, o2, c) + +#define bus_space_copy_region_stream_1 bus_space_copy_region_1 +#define bus_space_copy_region_stream_2(t, h1, o1, h2, o2, c) \ + __bs_copy(s_2, t, h1, o1, h2, o2, c) +#define bus_space_copy_region_stream_4(t, h1, o1, h2, o2, c) \ + __bs_copy(s_4, t, h1, o1, h2, o2, c) +#define bus_space_copy_region_stream_8(t, h1, o1, h2, o2, c) \ + __bs_copy(s_8, t, h1, o1, h2, o2, c) +#endif + +#define BUS_PEEK_FUNC(width, type) \ + static inline int \ + bus_space_peek_##width(bus_space_tag_t tag, \ + bus_space_handle_t hnd, bus_size_t offset, type *value) \ + { \ + type tmp; \ + tmp = bus_space_read_##width(tag, hnd, offset); \ + *value = (type)tmp; \ + return (0); \ + } +BUS_PEEK_FUNC(1, uint8_t) +BUS_PEEK_FUNC(2, uint16_t) +BUS_PEEK_FUNC(4, uint32_t) +BUS_PEEK_FUNC(8, uint64_t) + +#define BUS_POKE_FUNC(width, type) \ + static inline int \ + bus_space_poke_##width(bus_space_tag_t tag, \ + bus_space_handle_t hnd, bus_size_t offset, type value) \ + { \ + bus_space_write_##width(tag, hnd, offset, value); \ + return (0); \ + } +BUS_POKE_FUNC(1, uint8_t) +BUS_POKE_FUNC(2, uint16_t) +BUS_POKE_FUNC(4, uint32_t) +BUS_POKE_FUNC(8, uint64_t) + +#include <machine/bus_dma.h> + +#endif /* _MACHINE_BUS_H_ */ diff --git a/sys/powerpc/include/bus_dma.h b/sys/powerpc/include/bus_dma.h new file mode 100644 index 000000000000..09bc7b15e94e --- /dev/null +++ b/sys/powerpc/include/bus_dma.h @@ -0,0 +1,37 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2005 Scott Long + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _POWERPC_BUS_DMA_H_ +#define _POWERPC_BUS_DMA_H_ + +#include <sys/bus_dma.h> +#include <sys/bus_dma_internal.h> + +int bus_dma_tag_set_iommu(bus_dma_tag_t, device_t iommu, void *cookie); + +#endif /* _POWERPC_BUS_DMA_H_ */ diff --git a/sys/powerpc/include/clock.h b/sys/powerpc/include/clock.h new file mode 100644 index 000000000000..9f2d692fefe8 --- /dev/null +++ b/sys/powerpc/include/clock.h @@ -0,0 +1,18 @@ +/*- + * Kernel interface to machine-dependent clock driver. + * Garrett Wollman, September 1994. + * This file is in the public domain. + */ + +#ifndef _MACHINE_CLOCK_H_ +#define _MACHINE_CLOCK_H_ + +#ifdef _KERNEL + +struct trapframe; + +void decr_intr(struct trapframe *); + +#endif + +#endif /* !_MACHINE_CLOCK_H_ */ diff --git a/sys/powerpc/include/counter.h b/sys/powerpc/include/counter.h new file mode 100644 index 000000000000..90e6400ad562 --- /dev/null +++ b/sys/powerpc/include/counter.h @@ -0,0 +1,164 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2012, 2013 Konstantin Belousov <kib@FreeBSD.org> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef __MACHINE_COUNTER_H__ +#define __MACHINE_COUNTER_H__ + +#include <sys/pcpu.h> +#ifdef INVARIANTS +#include <sys/proc.h> +#endif + +#define EARLY_COUNTER &__pcpu[0].pc_early_dummy_counter + +#ifdef __powerpc64__ + +#define counter_enter() do {} while (0) +#define counter_exit() do {} while (0) + +#ifdef IN_SUBR_COUNTER_C +static inline uint64_t +counter_u64_read_one(uint64_t *p, int cpu) +{ + + return (*(uint64_t *)((char *)p + UMA_PCPU_ALLOC_SIZE * cpu)); +} + +static inline uint64_t +counter_u64_fetch_inline(uint64_t *p) +{ + uint64_t r; + int i; + + r = 0; + CPU_FOREACH(i) + r += counter_u64_read_one((uint64_t *)p, i); + + return (r); +} + +static void +counter_u64_zero_one_cpu(void *arg) +{ + + *((uint64_t *)((char *)arg + UMA_PCPU_ALLOC_SIZE * + PCPU_GET(cpuid))) = 0; +} + +static inline void +counter_u64_zero_inline(counter_u64_t c) +{ + + smp_rendezvous(smp_no_rendezvous_barrier, counter_u64_zero_one_cpu, + smp_no_rendezvous_barrier, c); +} +#endif + +#define counter_u64_add_protected(c, i) counter_u64_add(c, i) + +static inline void +counter_u64_add(counter_u64_t c, int64_t inc) +{ + uint64_t ccpu, old; + + __asm __volatile("\n" + "1:\n\t" + "mfsprg %0, 0\n\t" + "ldarx %1, %0, %2\n\t" + "add %1, %1, %3\n\t" + "stdcx. %1, %0, %2\n\t" + "bne- 1b" + : "=&b" (ccpu), "=&r" (old) + : "r" ((char *)c - (char *)&__pcpu[0]), "r" (inc) + : "cr0", "memory"); +} + +#else /* !64bit */ + +#include <sys/systm.h> + +#define counter_enter() critical_enter() +#define counter_exit() critical_exit() + +#ifdef IN_SUBR_COUNTER_C +/* XXXKIB non-atomic 64bit read */ +static inline uint64_t +counter_u64_read_one(uint64_t *p, int cpu) +{ + + return (*(uint64_t *)((char *)p + UMA_PCPU_ALLOC_SIZE * cpu)); +} + +static inline uint64_t +counter_u64_fetch_inline(uint64_t *p) +{ + uint64_t r; + int i; + + r = 0; + for (i = 0; i < mp_ncpus; i++) + r += counter_u64_read_one((uint64_t *)p, i); + + return (r); +} + +/* XXXKIB non-atomic 64bit store, might interrupt increment */ +static void +counter_u64_zero_one_cpu(void *arg) +{ + + *((uint64_t *)((char *)arg + UMA_PCPU_ALLOC_SIZE * + PCPU_GET(cpuid))) = 0; +} + +static inline void +counter_u64_zero_inline(counter_u64_t c) +{ + + smp_rendezvous(smp_no_rendezvous_barrier, counter_u64_zero_one_cpu, + smp_no_rendezvous_barrier, c); +} +#endif + +#define counter_u64_add_protected(c, inc) do { \ + CRITICAL_ASSERT(curthread); \ + *(uint64_t *)zpcpu_get(c) += (inc); \ +} while (0) + +static inline void +counter_u64_add(counter_u64_t c, int64_t inc) +{ + + counter_enter(); + counter_u64_add_protected(c, inc); + counter_exit(); +} + +#endif /* 64bit */ + +#endif /* ! __MACHINE_COUNTER_H__ */ diff --git a/sys/powerpc/include/cpu.h b/sys/powerpc/include/cpu.h new file mode 100644 index 000000000000..35b32566484c --- /dev/null +++ b/sys/powerpc/include/cpu.h @@ -0,0 +1,157 @@ +/*- + * SPDX-License-Identifier: BSD-4-Clause + * + * Copyright (C) 1995-1997 Wolfgang Solfrank. + * Copyright (C) 1995-1997 TooLs GmbH. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by TooLs GmbH. + * 4. The name of TooLs GmbH may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $NetBSD: cpu.h,v 1.11 2000/05/26 21:19:53 thorpej Exp $ + */ + +#ifndef _MACHINE_CPU_H_ +#define _MACHINE_CPU_H_ + +#include <machine/frame.h> +#include <machine/pcb.h> +#include <machine/psl.h> + +/* + * CPU Feature Attributes + * + * These are defined in the PowerPC ELF ABI for the AT_HWCAP vector, + * and are exported to userland via the machdep.cpu_features + * sysctl. + */ + +extern u_long cpu_features; +extern u_long cpu_features2; + +#define PPC_FEATURE_32 0x80000000 /* Always true */ +#define PPC_FEATURE_64 0x40000000 /* Defined on a 64-bit CPU */ +#define PPC_FEATURE_601_INSTR 0x20000000 /* Defined on a 64-bit CPU */ +#define PPC_FEATURE_HAS_ALTIVEC 0x10000000 +#define PPC_FEATURE_HAS_FPU 0x08000000 +#define PPC_FEATURE_HAS_MMU 0x04000000 +#define PPC_FEATURE_UNIFIED_CACHE 0x01000000 +#define PPC_FEATURE_HAS_SPE 0x00800000 +#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000 +#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000 +#define PPC_FEATURE_NO_TB 0x00100000 +#define PPC_FEATURE_POWER4 0x00080000 +#define PPC_FEATURE_POWER5 0x00040000 +#define PPC_FEATURE_POWER5_PLUS 0x00020000 +#define PPC_FEATURE_CELL 0x00010000 +#define PPC_FEATURE_BOOKE 0x00008000 +#define PPC_FEATURE_SMT 0x00004000 +#define PPC_FEATURE_ICACHE_SNOOP 0x00002000 +#define PPC_FEATURE_ARCH_2_05 0x00001000 +#define PPC_FEATURE_HAS_DFP 0x00000400 +#define PPC_FEATURE_POWER6_EXT 0x00000200 +#define PPC_FEATURE_ARCH_2_06 0x00000100 +#define PPC_FEATURE_HAS_VSX 0x00000080 +#define PPC_FEATURE_TRUE_LE 0x00000002 +#define PPC_FEATURE_PPC_LE 0x00000001 + +#define PPC_FEATURE2_ARCH_2_07 0x80000000 +#define PPC_FEATURE2_HTM 0x40000000 +#define PPC_FEATURE2_DSCR 0x20000000 +#define PPC_FEATURE2_EBB 0x10000000 +#define PPC_FEATURE2_ISEL 0x08000000 +#define PPC_FEATURE2_TAR 0x04000000 +#define PPC_FEATURE2_HAS_VEC_CRYPTO 0x02000000 +#define PPC_FEATURE2_HTM_NOSC 0x01000000 +#define PPC_FEATURE2_ARCH_3_00 0x00800000 +#define PPC_FEATURE2_HAS_IEEE128 0x00400000 +#define PPC_FEATURE2_DARN 0x00200000 +#define PPC_FEATURE2_SCV 0x00100000 +#define PPC_FEATURE2_HTM_NOSUSPEND 0x00080000 +#define PPC_FEATURE2_ARCH_3_1 0x00040000 +#define PPC_FEATURE2_MMA 0x00020000 + +#define PPC_FEATURE_BITMASK \ + "\20" \ + "\040PPC32\037PPC64\036PPC601\035ALTIVEC\034FPU\033MMU\031UNIFIEDCACHE" \ + "\030SPE\027SPESFP\026DPESFP\025NOTB\024POWER4\023POWER5\022P5PLUS\021CELL"\ + "\020BOOKE\017SMT\016ISNOOP\015ARCH205\013DFP\011ARCH206\010VSX"\ + "\002TRUELE\001PPCLE" +#define PPC_FEATURE2_BITMASK \ + "\20" \ + "\040ARCH207\037HTM\036DSCR\034ISEL\033TAR\032VCRYPTO\031HTMNOSC" \ + "\030ARCH300\027IEEE128\026DARN\025SCV\024HTMNOSUSP" + +#define TRAPF_USERMODE(frame) (((frame)->srr1 & PSL_PR) != 0) +#define TRAPF_PC(frame) ((frame)->srr0) + +/* + * CTL_MACHDEP definitions. + */ +#define CPU_CACHELINE 1 + +static __inline u_int64_t +get_cyclecount(void) +{ + u_int32_t _upper, _lower; + u_int64_t _time; + + __asm __volatile( + "mftb %0\n" + "mftbu %1" + : "=r" (_lower), "=r" (_upper)); + + _time = (u_int64_t)_upper; + _time = (_time << 32) + _lower; + return (_time); +} + +#define cpu_getstack(td) ((td)->td_frame->fixreg[1]) +#define cpu_spinwait() __asm __volatile("or 27,27,27") /* yield */ +#define cpu_lock_delay() DELAY(1) + +extern char btext[]; +extern char etext[]; + +struct thread; + +#ifdef __powerpc64__ +extern void enter_idle_powerx(void); +extern uint64_t can_wakeup; +extern register_t lpcr; +#endif + +void cpu_halt(void); +void cpu_reset(void); +void flush_disable_caches(void); +void fork_trampoline(void); +int cpu_machine_check(struct thread *, struct trapframe *, int *); + + +#ifndef __powerpc64__ +void mpc745x_sleep(void); +#endif + +#endif /* _MACHINE_CPU_H_ */ diff --git a/sys/powerpc/include/cpufunc.h b/sys/powerpc/include/cpufunc.h new file mode 100644 index 000000000000..19a7ae01df0c --- /dev/null +++ b/sys/powerpc/include/cpufunc.h @@ -0,0 +1,298 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 1998 Doug Rabson + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _MACHINE_CPUFUNC_H_ +#define _MACHINE_CPUFUNC_H_ + +#ifdef _KERNEL + +#include <sys/types.h> + +#include <machine/psl.h> +#include <machine/spr.h> + +struct thread; + +#ifdef KDB +void breakpoint(void); +#else +static __inline void +breakpoint(void) +{ + + return; +} +#endif + +/* CPU register mangling inlines */ + +static __inline void +mtmsr(register_t value) +{ + + __asm __volatile ("mtmsr %0; isync" :: "r"(value)); +} + +#ifdef __powerpc64__ +static __inline void +mtmsrd(register_t value) +{ + + __asm __volatile ("mtmsrd %0; isync" :: "r"(value)); +} +#endif + +static __inline register_t +mfmsr(void) +{ + register_t value; + + __asm __volatile ("mfmsr %0" : "=r"(value)); + + return (value); +} + +#ifndef __powerpc64__ +static __inline void +mtsrin(vm_offset_t va, register_t value) +{ + + __asm __volatile ("mtsrin %0,%1; isync" :: "r"(value), "r"(va)); +} + +static __inline register_t +mfsrin(vm_offset_t va) +{ + register_t value; + + __asm __volatile ("mfsrin %0,%1" : "=r"(value) : "r"(va)); + + return (value); +} +#endif + +static __inline register_t +mfctrl(void) +{ + register_t value; + + __asm __volatile ("mfspr %0,136" : "=r"(value)); + + return (value); +} + +static __inline void +mtdec(register_t value) +{ + + __asm __volatile ("mtdec %0" :: "r"(value)); +} + +static __inline register_t +mfdec(void) +{ + register_t value; + + __asm __volatile ("mfdec %0" : "=r"(value)); + + return (value); +} + +static __inline uint32_t +mfpvr(void) +{ + uint32_t value; + + __asm __volatile ("mfpvr %0" : "=r"(value)); + + return (value); +} + +static __inline u_quad_t +mftb(void) +{ + u_quad_t tb; + #ifdef __powerpc64__ + __asm __volatile ("mftb %0" : "=r"(tb)); + #else + uint32_t *tbup = (uint32_t *)&tb; + uint32_t *tblp = tbup + 1; + + do { + *tbup = mfspr(TBR_TBU); + *tblp = mfspr(TBR_TBL); + } while (*tbup != mfspr(TBR_TBU)); + #endif + + return (tb); +} + +static __inline void +mttb(u_quad_t time) +{ + + mtspr(TBR_TBWL, 0); + mtspr(TBR_TBWU, (uint32_t)(time >> 32)); + mtspr(TBR_TBWL, (uint32_t)(time & 0xffffffff)); +} + +static __inline register_t +mffs(void) +{ + uint64_t value; + + __asm __volatile ("mffs 0; stfd 0,0(%0)" + :: "b"(&value)); + + return ((register_t)value); +} + +static __inline void +mtfsf(uint64_t value) +{ + + __asm __volatile ("lfd 0,0(%0); mtfsf 0xff,0" + :: "b"(&value)); +} + +static __inline void +eieio(void) +{ + + __asm __volatile ("eieio" : : : "memory"); +} + +static __inline void +isync(void) +{ + + __asm __volatile ("isync" : : : "memory"); +} + +static __inline void +powerpc_sync(void) +{ + + __asm __volatile ("sync" : : : "memory"); +} + +static __inline int +cntlzd(uint64_t word) +{ + uint64_t result; + /* cntlzd %0, %1 */ + __asm __volatile(".long 0x7c000074 | (%1 << 21) | (%0 << 16)" : + "=r"(result) : "r"(word)); + + return (int)result; +} + +static __inline int +cnttzd(uint64_t word) +{ + uint64_t result; + /* cnttzd %0, %1 */ + __asm __volatile(".long 0x7c000474 | (%1 << 21) | (%0 << 16)" : + "=r"(result) : "r"(word)); + + return (int)result; +} + +static __inline void +ptesync(void) +{ + __asm __volatile("ptesync"); +} + +static __inline register_t +intr_disable(void) +{ + register_t msr; + + msr = mfmsr(); + mtmsr(msr & ~PSL_EE); + return (msr); +} + +static __inline void +intr_restore(register_t msr) +{ + + mtmsr(msr); +} + +static __inline struct pcpu * +get_pcpu(void) +{ + struct pcpu *ret; + + __asm __volatile("mfsprg %0, 0" : "=r"(ret)); + + return (ret); +} + +/* "NOP" operations to signify priorities to the kernel. */ +static __inline void +nop_prio_vlow(void) +{ + __asm __volatile("or 31,31,31"); +} + +static __inline void +nop_prio_low(void) +{ + __asm __volatile("or 1,1,1"); +} + +static __inline void +nop_prio_mlow(void) +{ + __asm __volatile("or 6,6,6"); +} + +static __inline void +nop_prio_medium(void) +{ + __asm __volatile("or 2,2,2"); +} + +static __inline void +nop_prio_mhigh(void) +{ + __asm __volatile("or 5,5,5"); +} + +static __inline void +nop_prio_high(void) +{ + __asm __volatile("or 3,3,3"); +} + +#endif /* _KERNEL */ + +#endif /* !_MACHINE_CPUFUNC_H_ */ diff --git a/sys/powerpc/include/db_machdep.h b/sys/powerpc/include/db_machdep.h new file mode 100644 index 000000000000..369fd9e9ddd6 --- /dev/null +++ b/sys/powerpc/include/db_machdep.h @@ -0,0 +1,87 @@ +/*- + * Mach Operating System + * Copyright (c) 1992 Carnegie Mellon University + * All Rights Reserved. + * + * Permission to use, copy, modify and distribute this software and its + * documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR + * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie Mellon + * the rights to redistribute these changes. + * + * $OpenBSD: db_machdep.h,v 1.2 1997/03/21 00:48:48 niklas Exp $ + * $NetBSD: db_machdep.h,v 1.4.22.1 2000/08/05 11:10:43 wiz Exp $ + */ + +/* + * Machine-dependent defines for new kernel debugger. + */ +#ifndef _POWERPC_DB_MACHDEP_H_ +#define _POWERPC_DB_MACHDEP_H_ + +#include <vm/vm_param.h> +#include <machine/elf.h> + +#define DB_ELF_SYMBOLS +#define DB_ELFSIZE __ELF_WORD_SIZE + +typedef vm_offset_t db_addr_t; /* address - unsigned */ +typedef intptr_t db_expr_t; /* expression - signed */ + +#define PC_REGS(regs) ((db_addr_t)kdb_thrctx->pcb_lr) + +#define BKPT_INST 0x7C810808 /* breakpoint instruction */ + +#define BKPT_SIZE (4) /* size of breakpoint inst */ +#define BKPT_SET(inst) (BKPT_INST) + +#define db_clear_single_step kdb_cpu_clear_singlestep +#define db_set_single_step kdb_cpu_set_singlestep + +#if 0 +#define SR_SINGLESTEP 0x400 +#define db_clear_single_step(regs) ((regs)->msr &= ~SR_SINGLESTEP) +#define db_set_single_step(regs) ((regs)->msr |= SR_SINGLESTEP) +#endif + +#define T_BREAKPOINT 0xffff +#define IS_BREAKPOINT_TRAP(type, code) ((type) == T_BREAKPOINT) + +#define T_WATCHPOINT 0xeeee +#ifdef T_WATCHPOINT +#define IS_WATCHPOINT_TRAP(type, code) ((type) == T_WATCHPOINT) +#else +#define IS_WATCHPOINT_TRAP(type, code) 0 +#endif + +#define M_RTS 0xfc0007fe +#define I_RTS 0x4c000020 +#define M_BC 0xfc000000 +#define I_BC 0x40000000 +#define M_B 0xfc000000 +#define I_B 0x50000000 +#define M_RFI 0xfc0007fe +#define I_RFI 0x4c000064 + +#define inst_trap_return(ins) (((ins)&M_RFI) == I_RFI) +#define inst_return(ins) (((ins)&M_RTS) == I_RTS) +#define inst_call(ins) (((ins)&M_BC ) == I_BC || \ + ((ins)&M_B ) == I_B ) +#define inst_load(ins) 0 +#define inst_store(ins) 0 + +#endif /* _POWERPC_DB_MACHDEP_H_ */ diff --git a/sys/powerpc/include/dbdma.h b/sys/powerpc/include/dbdma.h new file mode 100644 index 000000000000..b6401b1d12e2 --- /dev/null +++ b/sys/powerpc/include/dbdma.h @@ -0,0 +1,153 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2008 Nathan Whitehorn + * All rights reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _MACHINE_DBDMA_H_ +#define _MACHINE_DBDMA_H_ + +#include <sys/param.h> +#include <machine/bus.h> + +/* + * Apple's DBDMA (Descriptor-based DMA) interface is a common DMA engine + * used by a variety of custom Apple ASICs. It is described in the CHRP + * specification and in the book Macintosh Technology in the Common + * Hardware Reference Platform, copyright 1995 Apple Computer. + */ + +/* DBDMA Command Values */ + +enum { + DBDMA_OUTPUT_MORE = 0, + DBDMA_OUTPUT_LAST = 1, + DBDMA_INPUT_MORE = 2, + DBDMA_INPUT_LAST = 3, + + DBDMA_STORE_QUAD = 4, + DBDMA_LOAD_QUAD = 5, + DBDMA_NOP = 6, + DBDMA_STOP = 7 +}; + +/* These codes are for the interrupt, branch, and wait flags */ + +enum { + DBDMA_NEVER = 0, + DBDMA_COND_TRUE = 1, + DBDMA_COND_FALSE = 2, + DBDMA_ALWAYS = 3 +}; + +/* Channel status bits */ +#define DBDMA_STATUS_RUN (0x01 << 15) +#define DBDMA_STATUS_PAUSE (0x01 << 14) +#define DBDMA_STATUS_FLUSH (0x01 << 13) +#define DBDMA_STATUS_WAKE (0x01 << 12) +#define DBDMA_STATUS_DEAD (0x01 << 11) +#define DBDMA_STATUS_ACTIVE (0x01 << 10) + +/* Set by hardware if a branch was taken */ +#define DBDMA_STATUS_BRANCH 8 + +struct dbdma_command; +typedef struct dbdma_command dbdma_command_t; +struct dbdma_channel; +typedef struct dbdma_channel dbdma_channel_t; + +int dbdma_allocate_channel(struct resource *dbdma_regs, u_int offset, + bus_dma_tag_t parent_dma, int slots, dbdma_channel_t **chan); + +int dbdma_resize_channel(dbdma_channel_t *chan, int newslots); +int dbdma_free_channel(dbdma_channel_t *chan); + +void dbdma_run(dbdma_channel_t *chan); +void dbdma_stop(dbdma_channel_t *chan); +void dbdma_reset(dbdma_channel_t *chan); +void dbdma_set_current_cmd(dbdma_channel_t *chan, int slot); + +void dbdma_pause(dbdma_channel_t *chan); +void dbdma_wake(dbdma_channel_t *chan); + +/* + * DBDMA uses a 16 bit channel control register to describe the current + * state of DMA on the channel. The high-order bits (8-15) contain information + * on the run state and are listed in the DBDMA_STATUS_* constants above. These + * are manipulated with the dbdma_run/stop/reset() routines above. + * + * The low order bits (0-7) are device dependent status bits. These can be set + * and read by both hardware and software. The mask is the set of bits to + * modify; if mask is 0x03 and value is 0, the lowest order 2 bits will be + * zeroed. + */ + +uint16_t dbdma_get_chan_status(dbdma_channel_t *chan); + +uint8_t dbdma_get_device_status(dbdma_channel_t *chan); +void dbdma_set_device_status(dbdma_channel_t *chan, uint8_t mask, + uint8_t value); + +/* + * Each DBDMA command word has the current channel status register and the + * number of residual bytes (requested - actually transferred) written to it + * at time of command completion. + */ + +uint16_t dbdma_get_cmd_status(dbdma_channel_t *chan, int slot); +uint16_t dbdma_get_residuals(dbdma_channel_t *chan, int slot); + +void dbdma_clear_cmd_status(dbdma_channel_t *chan, int slot); + +/* + * The interrupt/branch/wait selector let you specify a set of values + * of the device dependent status bits that will cause intterupt/branch/wait + * conditions to be taken if the flags for these are set to one of the + * DBDMA_COND_* values. + * + * The condition is considered true if (status & mask) == value. + */ + +void dbdma_set_interrupt_selector(dbdma_channel_t *chan, uint8_t mask, + uint8_t value); +void dbdma_set_branch_selector(dbdma_channel_t *chan, uint8_t mask, + uint8_t value); +void dbdma_set_wait_selector(dbdma_channel_t *chan, uint8_t mask, + uint8_t value); + +void dbdma_insert_command(dbdma_channel_t *chan, int slot, int command, + int stream, bus_addr_t data, size_t count, uint8_t interrupt, + uint8_t branch, uint8_t wait, uint32_t branch_slot); + +void dbdma_insert_stop(dbdma_channel_t *chan, int slot); +void dbdma_insert_nop(dbdma_channel_t *chan, int slot); +void dbdma_insert_branch(dbdma_channel_t *chan, int slot, int to_slot); + +void dbdma_sync_commands(dbdma_channel_t *chan, bus_dmasync_op_t op); + +void dbdma_save_state(dbdma_channel_t *chan); +void dbdma_restore_state(dbdma_channel_t *chan); + +#endif /* _MACHINE_DBDMA_H_ */ diff --git a/sys/powerpc/include/dump.h b/sys/powerpc/include/dump.h new file mode 100644 index 000000000000..ebaf8c6dde0f --- /dev/null +++ b/sys/powerpc/include/dump.h @@ -0,0 +1,73 @@ +/*- + * Copyright (c) 2014 EMC Corp. + * Author: Conrad Meyer <conrad.meyer@isilon.com> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _MACHINE_DUMP_H_ +#define _MACHINE_DUMP_H_ + +#define KERNELDUMP_ARCH_VERSION KERNELDUMP_POWERPC_VERSION +#define EM_VALUE ELF_ARCH /* Defined in powerpc/include/elf.h */ +#define DUMPSYS_MD_PA_NPAIRS (PHYS_AVAIL_SZ + 1) +#define DUMPSYS_NUM_AUX_HDRS 0 + +/* How often to check the dump progress bar? */ +#define DUMPSYS_PB_CHECK_BITS 20 /* Every 1MB */ + +void dumpsys_pa_init(void); +void dumpsys_unmap_chunk(vm_paddr_t, size_t, void *); +size_t dumpsys_scan_pmap(struct bitset *); +void *dumpsys_dump_pmap_init(unsigned blkpgs); +void *dumpsys_dump_pmap(void *ctx, void *buf, u_long *nbytes); + +static inline struct dump_pa * +dumpsys_pa_next(struct dump_pa *p) +{ + + return (dumpsys_gen_pa_next(p)); +} + +static inline void +dumpsys_wbinv_all(void) +{ + + dumpsys_gen_wbinv_all(); +} + +static inline int +dumpsys_write_aux_headers(struct dumperinfo *di) +{ + + return (dumpsys_gen_write_aux_headers(di)); +} + +static inline int +dumpsys(struct dumperinfo *di) +{ + + return (dumpsys_generic(di)); +} + +#endif /* !_MACHINE_DUMP_H_ */ diff --git a/sys/powerpc/include/efi.h b/sys/powerpc/include/efi.h new file mode 100644 index 000000000000..394e696bdd98 --- /dev/null +++ b/sys/powerpc/include/efi.h @@ -0,0 +1,12 @@ +/*- + * This file is in the public domain since it's just boilerplate. + */ + +#ifndef __POWERPC_INCLUDE_EFI_H_ +#define __POWERPC_INCLUDE_EFI_H_ + +#define EFIABI_ATTR + +/* Note: we don't actually support this on powerpc */ + +#endif /* __POWERPC_INCLUDE_EFI_H_ */ diff --git a/sys/powerpc/include/elf.h b/sys/powerpc/include/elf.h new file mode 100644 index 000000000000..bcfa793540d2 --- /dev/null +++ b/sys/powerpc/include/elf.h @@ -0,0 +1,146 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2001 David E. O'Brien + * Copyright (c) 1996-1997 John D. Polstra. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _MACHINE_ELF_H_ +#define _MACHINE_ELF_H_ 1 + +/* + * EABI ELF definitions for the PowerPC architecture. + * See "PowerPC Embedded Application Binary Interface, 32-Bit Impliementation" + * [ppc-eabi-1995-01.pdf] for details. + */ + +#ifndef __ELF_WORD_SIZE +#ifdef __powerpc64__ +#define __ELF_WORD_SIZE 64 /* Used by <sys/elf_generic.h> */ +#else +#define __ELF_WORD_SIZE 32 /* Used by <sys/elf_generic.h> */ +#endif +#endif + +#include <sys/elf32.h> /* Definitions common to all 32 bit architectures. */ +#include <sys/elf64.h> /* Definitions common to all 64 bit architectures. */ +#include <sys/elf_generic.h> + +#if __ELF_WORD_SIZE == 64 +#define ELF_ARCH EM_PPC64 +#define ELF_MACHINE_OK(x) ((x) == EM_PPC64) +#else +#define ELF_ARCH EM_PPC +#define ELF_ARCH32 EM_PPC +#define ELF_MACHINE_OK(x) ((x) == EM_PPC) +#endif + +/* + * Auxiliary vector entries for passing information to the interpreter. + * + * The PowerPC supplement to the SVR4 ABI specification names this "auxv_t", + * but POSIX lays claim to all symbols ending with "_t". + */ + +typedef struct { /* Auxiliary vector entry on initial stack */ + int a_type; /* Entry type. */ + union { +#ifdef __powerpc64__ + int a_val; /* Integer value */ +#else + long a_val; /* Integer value. */ + void *a_ptr; /* Address. */ + void (*a_fcn)(void); /* Function pointer (not used). */ +#endif + } a_un; +} Elf32_Auxinfo; + +typedef struct { /* Auxiliary vector entry on initial stack */ + long a_type; /* Entry type. */ + union { + long a_val; /* Integer value. */ + void *a_ptr; /* Address. */ + void (*a_fcn)(void); /* Function pointer (not used). */ + } a_un; +} Elf64_Auxinfo; + +__ElfType(Auxinfo); + +/* + * Relocation types. + */ + +#define R_PPC_COUNT 37 /* Count of defined relocation types. */ + + /* Count of defined relocation types. */ +#define R_PPC_EMB_COUNT (R_PPC_EMB_RELSDA - R_PPC_EMB_NADDR32 + 1) + +/* Define "machine" characteristics */ +#if BYTE_ORDER == LITTLE_ENDIAN +#define ELF_TARG_DATA ELFDATA2LSB +#else +#define ELF_TARG_DATA ELFDATA2MSB +#endif +#if __ELF_WORD_SIZE == 64 +#define ELF_TARG_CLASS ELFCLASS64 +#define ELF_TARG_MACH EM_PPC64 +#define ELF_TARG_VER 1 +#else +#define ELF_TARG_CLASS ELFCLASS32 +#define ELF_TARG_MACH EM_PPC +#define ELF_TARG_VER 1 +#endif + +#define ET_DYN_LOAD_ADDR 0x01010000 + +#define AT_OLD_NULL AT_NULL +#define AT_OLD_IGNORE AT_IGNORE +#define AT_OLD_EXECFD AT_EXECFD +#define AT_OLD_PHDR AT_PHDR +#define AT_OLD_PHENT AT_PHENT +#define AT_OLD_PHNUM AT_PHNUM +#define AT_OLD_PAGESZ AT_PAGESZ +#define AT_OLD_BASE AT_BASE +#define AT_OLD_FLAGS AT_FLAGS +#define AT_OLD_ENTRY AT_ENTRY +#define AT_OLD_NOTELF AT_NOTELF +#define AT_OLD_UID AT_UID +#define AT_OLD_EUID AT_EUID +#define AT_OLD_EXECPATH 13 +#define AT_OLD_CANARY 14 +#define AT_OLD_CANARYLEN 15 +#define AT_OLD_OSRELDATE 16 +#define AT_OLD_NCPUS 17 +#define AT_OLD_PAGESIZES 18 +#define AT_OLD_PAGESIZESLEN 19 +#define AT_OLD_STACKPROT 21 +#define AT_OLD_TIMEKEEP AT_TIMEKEEP +#define AT_OLD_EHDRFLAGS AT_EHDRFLAGS +#define AT_OLD_HWCAP AT_HWCAP +#define AT_OLD_HWCAP2 AT_HWCAP2 + +#define AT_OLD_COUNT 27 /* Count of defined aux entry types. */ + +#endif /* !_MACHINE_ELF_H_ */ diff --git a/sys/powerpc/include/endian.h b/sys/powerpc/include/endian.h new file mode 100644 index 000000000000..90f53540256a --- /dev/null +++ b/sys/powerpc/include/endian.h @@ -0,0 +1,38 @@ +/*- + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 1987, 1991, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _MACHINE_ENDIAN_H_ +#define _MACHINE_ENDIAN_H_ + +#include <sys/_types.h> +#include <sys/_endian.h> + +#endif /* !_MACHINE_ENDIAN_H_ */ diff --git a/sys/powerpc/include/exec.h b/sys/powerpc/include/exec.h new file mode 100644 index 000000000000..cb06d086dbd0 --- /dev/null +++ b/sys/powerpc/include/exec.h @@ -0,0 +1,37 @@ +/*- + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2001 David E. O'Brien + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY JOHN BIRRELL AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _MACHINE_EXEC_H_ +#define _MACHINE_EXEC_H_ + +#define __LDPGSZ 4096 + +#endif /* !_MACHINE_EXEC_H_ */ diff --git a/sys/powerpc/include/float.h b/sys/powerpc/include/float.h new file mode 100644 index 000000000000..58ecbcfed74e --- /dev/null +++ b/sys/powerpc/include/float.h @@ -0,0 +1,98 @@ +/*- + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 1989 Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * from: FreeBSD: src/sys/i386/include/float.h,v 1.8 1999/08/28 00:44:11 + */ + +#ifndef _MACHINE_FLOAT_H_ +#define _MACHINE_FLOAT_H_ 1 + +#include <sys/cdefs.h> + +#ifndef _SOFT_FLOAT +__BEGIN_DECLS +extern int __flt_rounds(void); +__END_DECLS +#define FLT_ROUNDS __flt_rounds() +#else +#define FLT_ROUNDS (-1) +#endif + +#define FLT_RADIX 2 /* b */ +#if __ISO_C_VISIBLE >= 1999 +#define FLT_EVAL_METHOD 0 +#define DECIMAL_DIG 17 /* max precision in decimal digits */ +#endif + +#define FLT_MANT_DIG 24 /* p */ +#define FLT_EPSILON 1.19209290E-07F /* b**(1-p) */ +#define FLT_DIG 6 /* floor((p-1)*log10(b))+(b == 10) */ +#define FLT_MIN_EXP (-125) /* emin */ +#define FLT_MIN 1.17549435E-38F /* b**(emin-1) */ +#define FLT_MIN_10_EXP (-37) /* ceil(log10(b**(emin-1))) */ +#define FLT_MAX_EXP 128 /* emax */ +#define FLT_MAX 3.40282347E+38F /* (1-b**(-p))*b**emax */ +#define FLT_MAX_10_EXP 38 /* floor(log10((1-b**(-p))*b**emax)) */ +#if __ISO_C_VISIBLE >= 2011 +#define FLT_TRUE_MIN 1.40129846E-45F /* b**(emin-p) */ +#define FLT_DECIMAL_DIG 9 /* ceil(1+p*log10(b)) */ +#define FLT_HAS_SUBNORM 1 +#endif /* __ISO_C_VISIBLE >= 2011 */ + +#define DBL_MANT_DIG 53 +#define DBL_EPSILON 2.2204460492503131E-16 +#define DBL_DIG 15 +#define DBL_MIN_EXP (-1021) +#define DBL_MIN 2.2250738585072014E-308 +#define DBL_MIN_10_EXP (-307) +#define DBL_MAX_EXP 1024 +#define DBL_MAX 1.7976931348623157E+308 +#define DBL_MAX_10_EXP 308 +#if __ISO_C_VISIBLE >= 2011 +#define DBL_TRUE_MIN 4.9406564584124654E-324 +#define DBL_DECIMAL_DIG 17 +#define DBL_HAS_SUBNORM 1 +#endif /* __ISO_C_VISIBLE >= 2011 */ + +#define LDBL_MANT_DIG DBL_MANT_DIG +#define LDBL_EPSILON ((long double)DBL_EPSILON) +#define LDBL_DIG DBL_DIG +#define LDBL_MIN_EXP DBL_MIN_EXP +#define LDBL_MIN ((long double)DBL_MIN) +#define LDBL_MIN_10_EXP DBL_MIN_10_EXP +#define LDBL_MAX_EXP DBL_MAX_EXP +#define LDBL_MAX ((long double)DBL_MAX) +#define LDBL_MAX_10_EXP DBL_MAX_10_EXP +#if __ISO_C_VISIBLE >= 2011 +#define LDBL_TRUE_MIN ((long double)DBL_TRUE_MIN) +#define LDBL_DECIMAL_DIG DBL_DECIMAL_DIG +#define LDBL_HAS_SUBNORM DBL_HAS_SUBNORM +#endif /* __ISO_C_VISIBLE >= 2011 */ + +#endif /* _MACHINE_FLOAT_H_ */ diff --git a/sys/powerpc/include/floatingpoint.h b/sys/powerpc/include/floatingpoint.h new file mode 100644 index 000000000000..9d6558c0539c --- /dev/null +++ b/sys/powerpc/include/floatingpoint.h @@ -0,0 +1,37 @@ +/*- + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2004 Suleiman Souhlal <refugee@segfaulted.com> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY DAVID O'BRIEN AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _FLOATINGPOINT_H_ +#define _FLOATINGPOINT_H_ + +#include <machine/ieeefp.h> + +#endif /* !_FLOATINGPOINT_H_ */ diff --git a/sys/powerpc/include/fpu.h b/sys/powerpc/include/fpu.h new file mode 100644 index 000000000000..aa5640ea31fb --- /dev/null +++ b/sys/powerpc/include/fpu.h @@ -0,0 +1,102 @@ +/*- + * SPDX-License-Identifier: BSD-4-Clause + * + * Copyright (C) 1996 Wolfgang Solfrank. + * Copyright (C) 1996 TooLs GmbH. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by TooLs GmbH. + * 4. The name of TooLs GmbH may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $NetBSD: fpu.h,v 1.2 1999/12/07 15:14:56 danw Exp $ + */ + +#ifndef _MACHINE_FPU_H_ +#define _MACHINE_FPU_H_ + +#define FPSCR_FX 0x80000000 +#define FPSCR_FEX 0x40000000 +#define FPSCR_VX 0x20000000 +#define FPSCR_OX 0x10000000 +#define FPSCR_UX 0x08000000 +#define FPSCR_ZX 0x04000000 +#define FPSCR_XX 0x02000000 +#define FPSCR_VXSNAN 0x01000000 +#define FPSCR_VXISI 0x00800000 +#define FPSCR_VXIDI 0x00400000 +#define FPSCR_VXZDZ 0x00200000 +#define FPSCR_VXIMZ 0x00100000 +#define FPSCR_VXVC 0x00080000 +#define FPSCR_FR 0x00040000 +#define FPSCR_FI 0x00020000 +#define FPSCR_FPRF 0x0001f000 +#define FPSCR_C 0x00010000 +#define FPSCR_FPCC 0x0000f000 +#define FPSCR_FL 0x00008000 +#define FPSCR_FG 0x00004000 +#define FPSCR_FE 0x00002000 +#define FPSCR_FU 0x00001000 +#define FPSCR_VXSOFT 0x00000400 +#define FPSCR_VXSQRT 0x00000200 +#define FPSCR_VXCVI 0x00000100 +#define FPSCR_VE 0x00000080 +#define FPSCR_OE 0x00000040 +#define FPSCR_UE 0x00000020 +#define FPSCR_ZE 0x00000010 +#define FPSCR_XE 0x00000008 +#define FPSCR_NI 0x00000004 +#define FPSCR_RN 0x00000003 + +#ifdef _KERNEL + +void enable_fpu(struct thread *); +void save_fpu(struct thread *); +void save_fpu_nodrop(struct thread *); +void cleanup_fpscr(void); +u_int get_fpu_exception(struct thread *); +void enable_fpu_kern(void); +void disable_fpu(struct thread *td); + +/* + * Flags for fpu_kern_alloc_ctx(), fpu_kern_enter() and fpu_kern_thread(). + */ +#define FPU_KERN_NORMAL 0x0000 +#define FPU_KERN_NOWAIT 0x0001 +#define FPU_KERN_KTHR 0x0002 +#define FPU_KERN_NOCTX 0x0004 + +struct fpu_kern_ctx; + +struct fpu_kern_ctx *fpu_kern_alloc_ctx(u_int flags); +void fpu_kern_free_ctx(struct fpu_kern_ctx *ctx); +void fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, + u_int flags); +int fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx); +int fpu_kern_thread(u_int flags); +int is_fpu_kern_thread(u_int flags); + +#endif /* _KERNEL */ + +#endif /* _MACHINE_FPU_H_ */ diff --git a/sys/powerpc/include/frame.h b/sys/powerpc/include/frame.h new file mode 100644 index 000000000000..0841477d5fee --- /dev/null +++ b/sys/powerpc/include/frame.h @@ -0,0 +1,114 @@ +/*- + * SPDX-License-Identifier: BSD-4-Clause + * + * Copyright (C) 1995, 1996 Wolfgang Solfrank. + * Copyright (C) 1995, 1996 TooLs GmbH. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by TooLs GmbH. + * 4. The name of TooLs GmbH may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $NetBSD: frame.h,v 1.2 1999/01/10 10:13:15 tsubai Exp $ + */ + +#ifndef _MACHINE_FRAME_H_ +#define _MACHINE_FRAME_H_ + +#include <sys/types.h> + +/* + * We have to save all registers on every trap, because + * 1. user could attach this process every time + * 2. we must be able to restore all user registers in case of fork + * Actually, we do not save the fp registers on trap, since + * these are not used by the kernel. They are saved only when switching + * between processes using the FPU. + * + * Change ordering to cluster together these register_t's. XXX + */ +struct trapframe { + register_t fixreg[32]; + register_t lr; + register_t cr; + register_t xer; + register_t ctr; + register_t srr0; + register_t srr1; + register_t exc; + register_t dar; /* DAR/DEAR filled in on DSI traps */ + union { + struct { + /* dsisr only filled on a DSI trap */ + register_t dsisr; + } aim; + struct { + register_t esr; + register_t dbcr0; + } booke; + } cpu; +}; + +/* + * FRAMELEN is the size of the stack region used by the low-level trap + * handler. It is the size of its data (trapframe) plus the callframe + * header (sizeof(struct callframe) - 3 register widths). It must also + * be 16-byte aligned. + */ +#define FRAMELEN roundup(sizeof(struct trapframe) + \ + sizeof(struct callframe) - 3*sizeof(register_t), 16) +#define trapframe(td) ((td)->td_frame) + +/* + * Call frame for PowerPC used during fork. + */ +#ifdef __powerpc64__ +struct callframe { + register_t cf_dummy_fp; /* dummy frame pointer */ + register_t cf_cr; + register_t cf_lr; + register_t cf_compiler; + register_t cf_linkeditor; + register_t cf_toc; + register_t cf_func; + register_t cf_arg0; + register_t cf_arg1; + register_t _padding; /* Maintain 16-byte alignment */ +}; +#else +struct callframe { + register_t cf_dummy_fp; /* dummy frame pointer */ + register_t cf_lr; /* space for link register save */ + register_t cf_func; + register_t cf_arg0; + register_t cf_arg1; + register_t _padding; /* Maintain 16-byte alignment */ +}; +#endif + +/* Definitions for syscalls */ +#define FIRSTARG 3 /* first arg in reg 3 */ +#define NARGREG 8 /* 8 args in regs */ + +#endif /* _MACHINE_FRAME_H_ */ diff --git a/sys/powerpc/include/gdb_machdep.h b/sys/powerpc/include/gdb_machdep.h new file mode 100644 index 000000000000..c37dc7a8ee3a --- /dev/null +++ b/sys/powerpc/include/gdb_machdep.h @@ -0,0 +1,140 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2006 Marcel Moolenaar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _MACHINE_GDB_MACHDEP_H_ +#define _MACHINE_GDB_MACHDEP_H_ + +#ifdef BOOKE +#define PPC_GDB_NREGS0 1 +#define PPC_GDB_NREGS4 (70 + 1) +#define PPC_GDB_NREGS8 (1 + 32) +#define PPC_GDB_NREGS16 0 + +#else +/* + * 0 - 32*GPR(4/8) + * 32 - 32*FPR(8) + * 64 - PC, PS (4/8) + * 66 - CR (4) + * 67 - LR, CTR (4/8) + * 69 - XER, FPSCR (4) + * 71 - 32*VR(16) + * 103 - VSCR, VRSAVE (4) + */ + +#define PPC_REGNUM_R0 0 +#define PPC_REGNUM_R31 (PPC_REGNUM_R0 + 31) +#define PPC_REGNUM_FR0 32 +#define PPC_REGNUM_FR31 (PPC_REGNUM_FR0 + 31) +#define PPC_REGNUM_PC 64 +#define PPC_REGNUM_PS 65 +#define PPC_REGNUM_CR 66 +#define PPC_REGNUM_LR 67 +#define PPC_REGNUM_CTR 68 +#define PPC_REGNUM_XER 69 +#define PPC_REGNUM_FPSCR 70 +#define PPC_REGNUM_VR0 71 +#define PPC_REGNUM_VR31 (PPC_REGNUM_VR0 + 31) + +#define PPC_GDB_NREGS0 0 + +#ifdef __powerpc64__ +#define PPC_GDB_NREGS4 5 +#define PPC_GDB_NREGS8 (64 + 4) +#else +#define PPC_GDB_NREGS4 (32 + 7 + 2) +#define PPC_GDB_NREGS8 32 +#endif + +#define PPC_GDB_NREGS16 32 +#endif + +#define GDB_NREGS (PPC_GDB_NREGS0 + PPC_GDB_NREGS4 + \ + PPC_GDB_NREGS8 + PPC_GDB_NREGS16) +#define GDB_REG_PC 64 + +#define GDB_BUFSZ (PPC_GDB_NREGS4 * 8 + \ + PPC_GDB_NREGS8 * 16 + \ + PPC_GDB_NREGS16 * 32) + +static __inline size_t +gdb_cpu_regsz(int regnum) +{ + +#ifdef BOOKE + if (regnum == 70) + return (0); + if (regnum == 71 || regnum >= 73) + return (8); +#else +#ifdef __powerpc64__ + if ((regnum >= PPC_REGNUM_R0 && regnum <= PPC_REGNUM_PS) || + regnum == PPC_REGNUM_LR || regnum == PPC_REGNUM_CTR) + return (8); +#else + if (regnum >= PPC_REGNUM_FR0 && regnum <= PPC_REGNUM_FR31) + return (8); +#endif + if (regnum >= PPC_REGNUM_VR0 && regnum <= PPC_REGNUM_VR31) + return (16); +#endif + return (4); +} + +static __inline int +gdb_cpu_query(void) +{ + + return (0); +} + +static __inline void * +gdb_begin_write(void) +{ + + return (NULL); +} + +static __inline void +gdb_end_write(void *arg __unused) +{ + +} + +static __inline void +gdb_cpu_stop_reason(int type __unused, int code __unused) +{ + +} + +void *gdb_cpu_getreg(int, size_t *); +void gdb_cpu_setreg(int, void *); +int gdb_cpu_signal(int, int); +void gdb_cpu_do_offsets(void); + +#endif /* !_MACHINE_GDB_MACHDEP_H_ */ diff --git a/sys/powerpc/include/hid.h b/sys/powerpc/include/hid.h new file mode 100644 index 000000000000..090dd687d635 --- /dev/null +++ b/sys/powerpc/include/hid.h @@ -0,0 +1,223 @@ +/*- + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2000 Tsubai Masanari. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $NetBSD: hid.h,v 1.2 2001/08/22 21:05:25 matt Exp $ + */ + +#ifndef _POWERPC_HID_H_ +#define _POWERPC_HID_H_ + +/* Hardware Implementation Dependent registers for the PowerPC */ +#define HID0_RADIX 0x0080000000000000 /* Enable Radix page tables (POWER9) */ + +#define HID0_EMCP 0x80000000 /* Enable machine check pin */ +#define HID0_DBP 0x40000000 /* Disable 60x bus parity generation */ +#define HID0_EBA 0x20000000 /* Enable 60x bus address parity checking */ +#define HID0_EBD 0x10000000 /* Enable 60x bus data parity checking */ +#define HID0_BCLK 0x08000000 /* CLK_OUT clock type selection */ +#define HID0_EICE 0x04000000 /* Enable ICE output */ +#define HID0_ECLK 0x02000000 /* CLK_OUT clock type selection */ +#define HID0_PAR 0x01000000 /* Disable precharge of ARTRY */ +#define HID0_STEN 0x01000000 /* Software table search enable (7450) */ +#define HID0_DEEPNAP 0x01000000 /* Enable deep nap mode (970) */ +#define HID0_HBATEN 0x00800000 /* High BAT enable (74[45][578]) */ +#define HID0_DOZE 0x00800000 /* Enable doze mode */ +#define HID0_NAP 0x00400000 /* Enable nap mode */ +#define HID0_SLEEP 0x00200000 /* Enable sleep mode */ +#define HID0_DPM 0x00100000 /* Enable Dynamic power management */ +#define HID0_RISEG 0x00080000 /* Read I-SEG */ +#define HID0_TG 0x00040000 /* Timebase Granularity (OEA64) */ +#define HID0_BHTCLR 0x00040000 /* Clear branch history table (7450) */ +#define HID0_EIEC 0x00040000 /* Enable internal error checking */ +#define HID0_XAEN 0x00020000 /* Enable eXtended Addressing (7450) */ +#define HID0_NHR 0x00010000 /* Not hard reset */ +#define HID0_ICE 0x00008000 /* Enable i-cache */ +#define HID0_DCE 0x00004000 /* Enable d-cache */ +#define HID0_ILOCK 0x00002000 /* i-cache lock */ +#define HID0_DLOCK 0x00001000 /* d-cache lock */ +#define HID0_ICFI 0x00000800 /* i-cache flush invalidate */ +#define HID0_DCFI 0x00000400 /* d-cache flush invalidate */ +#define HID0_SPD 0x00000200 /* Disable speculative cache access */ +#define HID0_XBSEN 0x00000100 /* Extended BAT block-size enable (7457) */ +#define HID0_IFEM 0x00000100 /* Enable M-bit for I-fetch */ +#define HID0_XBSEN 0x00000100 /* Extended BAT block size enable (7455+)*/ +#define HID0_SGE 0x00000080 /* Enable store gathering */ +#define HID0_DCFA 0x00000040 /* Data cache flush assist */ +#define HID0_BTIC 0x00000020 /* Enable BTIC */ +#define HID0_LRSTK 0x00000010 /* Link register stack enable (7450) */ +#define HID0_ABE 0x00000008 /* Enable address broadcast */ +#define HID0_FOLD 0x00000008 /* Branch folding enable (7450) */ +#define HID0_BHT 0x00000004 /* Enable branch history table */ +#define HID0_NOPTI 0x00000001 /* No-op the dcbt(st) */ + +#define HID0_AIM_TBEN 0x04000000 /* Time base enable (7450) */ + +#define HID0_E500_TBEN 0x00004000 /* Time Base and decr. enable */ +#define HID0_E500_SEL_TBCLK 0x00002000 /* Select Time Base clock */ +#define HID0_E500_MAS7UPDEN 0x00000080 /* Enable MAS7 update (e500v2) */ + +#define HID0_E500MC_L2MMU_MHD 0x40000000 /* L2MMU Multiple Hit Detection */ + +#define HID0_BITMASK \ + "\20" \ + "\040EMCP\037DBP\036EBA\035EBD\034BCLK\033EICE\032ECLK\031PAR" \ + "\030DOZE\027NAP\026SLEEP\025DPM\024RISEG\023EIEC\022res\021NHR" \ + "\020ICE\017DCE\016ILOCK\015DLOCK\014ICFI\013DCFI\012SPD\011IFEM" \ + "\010SGE\007DCFA\006BTIC\005FBIOB\004ABE\003BHT\002NOPDST\001NOPTI" + +#define HID0_7450_BITMASK \ + "\20" \ + "\040EMCP\037b1\036b2\035b3\034b4\033TBEN\032b6\031STEN" \ + "\030HBATEN\027NAP\026SLEEP\025DPM\024b12\023BHTCLR\022XAEN\021NHR" \ + "\020ICE\017DCE\016ILOCK\015DLOCK\014ICFI\013DCFI\012SPD\011XBSEN" \ + "\010SGE\007b25\006BTIC\005LRSTK\004FOLD\003BHT\002NOPDST\001NOPTI" + +#define HID0_E500_BITMASK \ + "\20" \ + "\040EMCP\037b1\036b2\035b3\034b4\033b5\032b6\031b7" \ + "\030DOZE\027NAP\026SLEEP\025b11\024b12\023b13\022b14\021b15" \ + "\020b16\017TBEN\016SEL_TBCLK\015b19\014b20\013b21\012b22\011b23" \ + "\010EN_MAS7_UPDATE\007DCFA\006b26\005b27\004b28\003b29\002b30\001NOPTI" + +#define HID0_970_BITMASK \ + "\20" \ + "\040ONEPPC\037SINGLE\036ISYNCSC\035SERGP\031DEEPNAP\030DOZE" \ + "\027NAP\025DPM\023TG\022HANGDETECT\021NHR\020INORDER" \ + "\016TBCTRL\015TBEN\012CIABREN\011HDICEEN\001ENATTN" + +#define HID0_E500MC_BITMASK \ + "\20" \ + "\040EMCP\037EN_L2MMU_MHD\036b2\035b3\034b4\033b5\032b6\031b7" \ + "\030b8\027b9\026b10\025b11\024b12\023b13\022b14\021b15" \ + "\020b16\017b17\016b18\015b19\014b20\013b21\012b22\011b23" \ + "\010EN_MAS7_UPDATE\007DCFA\006b26\005CIGLSO\004b28\003b29\002b30\001NOPTI" + +#define HID0_E5500_BITMASK \ + "\20" \ + "\040EMCP\037EN_L2MMU_MHD\036b2\035b3\034b4\033b5\032b6\031b7" \ + "\030b8\027b9\026b10\025b11\024b12\023b13\022b14\021b15" \ + "\020b16\017b17\016b18\015b19\014b20\013b21\012b22\011b23" \ + "\010b24\007DCFA\006b26\005CIGLSO\004b28\003b29\002b30\001NOPTI" + +/* + * HID0 bit definitions per cpu model + * + * bit 603 604 750 7400 7410 7450 7457 e500 + * 0 EMCP EMCP EMCP EMCP EMCP - - EMCP + * 1 - ECP DBP - - - - - + * 2 EBA EBA EBA EBA EDA - - - + * 3 EBD EBD EBD EBD EBD - - - + * 4 SBCLK - BCLK BCKL BCLK - - - + * 5 EICE - - - - TBEN TBEN - + * 6 ECLK - ECLK ECLK ECLK - - - + * 7 PAR PAR PAR PAR PAR STEN STEN - + * 8 DOZE - DOZE DOZE DOZE - HBATEN DOZE + * 9 NAP - NAP NAP NAP NAP NAP NAP + * 10 SLEEP - SLEEP SLEEP SLEEP SLEEP SLEEP SLEEP + * 11 DPM - DPM DPM DPM DPM DPM - + * 12 RISEG - - RISEG - - - - + * 13 - - - EIEC EIEC BHTCLR BHTCLR - + * 14 - - - - - XAEN XAEN - + * 15 - NHR NHR NHR NHR NHR NHR - + * 16 ICE ICE ICE ICE ICE ICE ICE - + * 17 DCE DCE DCE DCE DCE DCE DCE TBEN + * 18 ILOCK ILOCK ILOCK ILOCK ILOCK ILOCK ILOCK SEL_TBCLK + * 19 DLOCK DLOCK DLOCK DLOCK DLOCK DLOCK DLOCK - + * 20 ICFI ICFI ICFI ICFI ICFI ICFI ICFI - + * 21 DCFI DCFI DCFI DCFI DCFI DCFI DCFI - + * 22 - - SPD SPD SPG SPD SPD - + * 23 - - IFEM IFTT IFTT - XBSEN - + * 24 - SIE SGE SGE SGE SGE SGE EN_MAS7_UPDATE + * 25 - - DCFA DCFA DCFA - - DCFA + * 26 - - BTIC BTIC BTIC BTIC BTIC - + * 27 FBIOB - - - - LRSTK LRSTK - + * 28 - - ABE - - FOLD FOLD - + * 29 - BHT BHT BHT BHT BHT BHT - + * 30 - - - NOPDST NOPDST NOPDST NOPDST - + * 31 NOOPTI - NOOPTI NOPTI NOPTI NOPTI NOPTI NOPTI + * + * bit e500mc e5500 + * 0 EMCP EMCP + * 1 EN_L2MMU_MHD EN_L2MMU_MHD + * 2 - - + * 3 - - + * 4 - - + * 5 - - + * 6 - - + * 7 - - + * 8 - - + * 9 - - + * 10 - - + * 11 - - + * 12 - - + * 13 - - + * 14 - - + * 15 - - + * 16 - - + * 17 - - + * 18 - - + * 19 - - + * 20 - - + * 21 - - + * 22 - - + * 23 - - + * 24 EN_MAS7_UPDATE - + * 25 DCFA DCFA + * 26 - - + * 27 CIGLSO CIGLSO + * 28 - - + * 29 - - + * 30 - - + * 31 NOPTI NOPTI + * + * 604: ECP = Enable cache parity checking + * 604: SIE = Serial instruction execution disable + * 7450: TBEN = Time Base Enable + * 7450: STEN = Software table lookup enable + * 7450: BHTCLR = Branch history clear + * 7450: XAEN = Extended Addressing Enabled + * 7450: LRSTK = Link Register Stack Enable + * 7450: FOLD = Branch folding enable + * 7457: HBATEN = High BAT Enable + * 7457: XBSEN = Extended BAT Block Size Enable + */ + +#define HID1_E500_ABE 0x00001000 /* Address broadcast enable */ +#define HID1_E500_ASTME 0x00002000 /* Address bus streaming mode enable */ +#define HID1_E500_RFXE 0x00020000 /* Read fault exception enable */ + +#define HID0_E500_DEFAULT_SET (HID0_EMCP | HID0_E500_TBEN | \ + HID0_E500_MAS7UPDEN) +#define HID1_E500_DEFAULT_SET (HID1_E500_ABE | HID1_E500_ASTME) +#define HID0_E500MC_DEFAULT_SET (HID0_EMCP | HID0_E500MC_L2MMU_MHD | \ + HID0_E500_MAS7UPDEN) +#define HID0_E5500_DEFAULT_SET (HID0_EMCP | HID0_E500MC_L2MMU_MHD) + +#define HID5_970_DCBZ_SIZE_HI 0x00000080UL /* dcbz does a 32-byte store */ +#define HID4_970_DISABLE_LG_PG 0x00000004ULL /* disables large pages */ + +#endif /* _POWERPC_HID_H_ */ diff --git a/sys/powerpc/include/ieee.h b/sys/powerpc/include/ieee.h new file mode 100644 index 000000000000..4fcb78728d15 --- /dev/null +++ b/sys/powerpc/include/ieee.h @@ -0,0 +1,141 @@ +/*- + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * + * This software was developed by the Computer Systems Engineering group + * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and + * contributed to Berkeley. + * + * All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Lawrence Berkeley Laboratory. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * from: NetBSD: ieee.h,v 1.1.1.1 1998/06/20 04:58:51 eeh Exp + */ + +#ifndef _MACHINE_IEEE_H_ +#define _MACHINE_IEEE_H_ + +/* + * ieee.h defines the machine-dependent layout of the machine's IEEE + * floating point. It does *not* define (yet?) any of the rounding + * mode bits, exceptions, and so forth. + */ + +/* + * Define the number of bits in each fraction and exponent. + * + * k k+1 + * Note that 1.0 x 2 == 0.1 x 2 and that denorms are represented + * + * (-exp_bias+1) + * as fractions that look like 0.fffff x 2 . This means that + * + * -126 + * the number 0.10000 x 2 , for instance, is the same as the normalized + * + * -127 -128 + * float 1.0 x 2 . Thus, to represent 2 , we need one leading zero + * + * -129 + * in the fraction; to represent 2 , we need two, and so on. This + * + * (-exp_bias-fracbits+1) + * implies that the smallest denormalized number is 2 + * + * for whichever format we are talking about: for single precision, for + * + * -126 -149 + * instance, we get .00000000000000000000001 x 2 , or 1.0 x 2 , and + * + * -149 == -127 - 23 + 1. + */ +#define SNG_EXPBITS 8 +#define SNG_FRACBITS 23 + +#define DBL_EXPBITS 11 +#define DBL_FRACBITS 52 + +#ifdef notyet +#define E80_EXPBITS 15 +#define E80_FRACBITS 64 +#endif + +#define EXT_EXPBITS 15 +#define EXT_FRACBITS 112 + +struct ieee_single { + u_int sng_sign:1; + u_int sng_exp:8; + u_int sng_frac:23; +}; + +struct ieee_double { + u_int dbl_sign:1; + u_int dbl_exp:11; + u_int dbl_frach:20; + u_int dbl_fracl; +}; + +struct ieee_ext { + u_int ext_sign:1; + u_int ext_exp:15; + u_int ext_frach:16; + u_int ext_frachm; + u_int ext_fraclm; + u_int ext_fracl; +}; + +/* + * Floats whose exponent is in [1..INFNAN) (of whatever type) are + * `normal'. Floats whose exponent is INFNAN are either Inf or NaN. + * Floats whose exponent is zero are either zero (iff all fraction + * bits are zero) or subnormal values. + * + * A NaN is a `signalling NaN' if its QUIETNAN bit is clear in its + * high fraction; if the bit is set, it is a `quiet NaN'. + */ +#define SNG_EXP_INFNAN 255 +#define DBL_EXP_INFNAN 2047 +#define EXT_EXP_INFNAN 32767 + +#if 0 +#define SNG_QUIETNAN (1 << 22) +#define DBL_QUIETNAN (1 << 19) +#define EXT_QUIETNAN (1 << 15) +#endif + +/* + * Exponent biases. + */ +#define SNG_EXP_BIAS 127 +#define DBL_EXP_BIAS 1023 +#define EXT_EXP_BIAS 16383 + +#endif diff --git a/sys/powerpc/include/ieeefp.h b/sys/powerpc/include/ieeefp.h new file mode 100644 index 000000000000..3aa92ff4522b --- /dev/null +++ b/sys/powerpc/include/ieeefp.h @@ -0,0 +1,42 @@ +/* - + * Written by J.T. Conklin, Apr 6, 1995 + * Public domain. + * $NetBSD: ieeefp.h,v 1.2 1999/07/07 01:52:26 danw Exp $ + */ + +#ifndef _MACHINE_IEEEFP_H_ +#define _MACHINE_IEEEFP_H_ + +/* Deprecated historical FPU control interface */ + +typedef int fp_except_t; +#ifdef __SPE__ +#define FP_X_OFL 0x01 /* overflow exception */ +#define FP_X_UFL 0x02 /* underflow exception */ +#define FP_X_DZ 0x04 /* divide-by-zero exception */ +#define FP_X_INV 0x08 /* invalid operation exception */ +#define FP_X_IMP 0x10 /* imprecise (loss of precision) */ +#else +#define FP_X_IMP 0x01 /* imprecise (loss of precision) */ +#define FP_X_DZ 0x02 /* divide-by-zero exception */ +#define FP_X_UFL 0x04 /* underflow exception */ +#define FP_X_OFL 0x08 /* overflow exception */ +#define FP_X_INV 0x10 /* invalid operation exception */ +#endif + +typedef enum { + FP_RN=0, /* round to nearest representable number */ + FP_RZ=1, /* round to zero (truncate) */ + FP_RP=2, /* round toward positive infinity */ + FP_RM=3 /* round toward negative infinity */ +} fp_rnd_t; + +__BEGIN_DECLS +extern fp_rnd_t fpgetround(void); +extern fp_rnd_t fpsetround(fp_rnd_t); +extern fp_except_t fpgetmask(void); +extern fp_except_t fpsetmask(fp_except_t); +extern fp_except_t fpgetsticky(void); +__END_DECLS + +#endif /* _MACHINE_IEEEFP_H_ */ diff --git a/sys/powerpc/include/ifunc.h b/sys/powerpc/include/ifunc.h new file mode 100644 index 000000000000..eac6019b07d7 --- /dev/null +++ b/sys/powerpc/include/ifunc.h @@ -0,0 +1,58 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2019 Brandon Bergren <bdragon@FreeBSD.org> + * Copyright (c) 2015-2018 The FreeBSD Foundation. All rights reserved. + * + * Part of this software was developed by + * Konstantin Belousov <kib@FreeBSD.org> + * under sponsorship from the FreeBSD Foundation. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef __POWERPC_IFUNC_H +#define __POWERPC_IFUNC_H + +#include <sys/types.h> + +#define DEFINE_IFUNC(qual, ret_type, name, args) \ + static ret_type (*name##_resolver(void))args __used; \ + qual ret_type name args __attribute__((ifunc(#name "_resolver"))); \ + static ret_type (*name##_resolver(void))args + +#define DEFINE_UIFUNC(qual, ret_type, name, args) \ + static ret_type (*name##_resolver(register_t, register_t, \ + register_t, register_t, register_t, register_t, register_t, \ + register_t))args __used; \ + qual ret_type name args __attribute__((ifunc(#name "_resolver"))); \ + static ret_type (*name##_resolver( \ + register_t cpu_features, \ + register_t cpu_features2, \ + register_t arg3 __unused, \ + register_t arg4 __unused, \ + register_t arg5 __unused, \ + register_t arg6 __unused, \ + register_t arg7 __unused, \ + register_t arg8 __unused))args + +#endif diff --git a/sys/powerpc/include/in_cksum.h b/sys/powerpc/include/in_cksum.h new file mode 100644 index 000000000000..7b649011f7d9 --- /dev/null +++ b/sys/powerpc/include/in_cksum.h @@ -0,0 +1,49 @@ +/*- + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from tahoe: in_cksum.c 1.2 86/01/05 + * from: Id: in_cksum.c,v 1.8 1995/12/03 18:35:19 bde Exp + */ + +#ifndef _MACHINE_IN_CKSUM_H_ +#define _MACHINE_IN_CKSUM_H_ 1 + +#define in_cksum(m, len) in_cksum_skip(m, len, 0) + +#ifdef _KERNEL +#if defined(IPVERSION) && (IPVERSION == 4) +u_int in_cksum_hdr(const struct ip *ip); +#endif +u_short in_addword(u_short sum, u_short b); +u_short in_pseudo(u_int sum, u_int b, u_int c); +u_short in_cksum_skip(struct mbuf *m, int len, int skip); +#endif + +#endif /* _MACHINE_IN_CKSUM_H_ */ diff --git a/sys/powerpc/include/intr_machdep.h b/sys/powerpc/include/intr_machdep.h new file mode 100644 index 000000000000..e46e2b5f9ba9 --- /dev/null +++ b/sys/powerpc/include/intr_machdep.h @@ -0,0 +1,64 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (C) 2002 Benno Rice. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _MACHINE_INTR_MACHDEP_H_ +#define _MACHINE_INTR_MACHDEP_H_ + +#define INTR_VECTORS 256 + +#define MAX_PICS 32 +#define MAP_IRQ(node, pin) powerpc_get_irq(node, pin) + +/* + * Default base address for MSI messages on PowerPC + */ +#define MSI_INTEL_ADDR_BASE 0xfee00000 + +extern device_t root_pic; + +struct trapframe; + +driver_filter_t powerpc_ipi_handler; + +void intrcnt_add(const char *name, u_long **countp); + +u_int powerpc_register_pic(device_t, uint32_t, u_int, u_int, u_int); +u_int powerpc_get_irq(uint32_t, u_int); + +void powerpc_dispatch_intr(u_int, struct trapframe *); +int powerpc_enable_intr(void); +int powerpc_setup_intr(const char *, u_int, driver_filter_t, driver_intr_t, + void *, enum intr_type, void **, int); +int powerpc_teardown_intr(void *); +int powerpc_bind_intr(u_int irq, u_char cpu); +int powerpc_config_intr(int, enum intr_trigger, enum intr_polarity); +int powerpc_fw_config_intr(int irq, int sense_code); + +void powerpc_intr_mask(u_int irq); +void powerpc_intr_unmask(u_int irq); + +#endif /* _MACHINE_INTR_MACHDEP_H_ */ diff --git a/sys/powerpc/include/kdb.h b/sys/powerpc/include/kdb.h new file mode 100644 index 000000000000..ccc9e473605f --- /dev/null +++ b/sys/powerpc/include/kdb.h @@ -0,0 +1,67 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2004 Marcel Moolenaar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _MACHINE_KDB_H_ +#define _MACHINE_KDB_H_ + +#include <machine/cpufunc.h> +#include <machine/frame.h> +#include <machine/md_var.h> +#include <machine/psl.h> +#include <machine/spr.h> + +void kdb_cpu_clear_singlestep(void); +void kdb_cpu_set_singlestep(void); + +static __inline void +kdb_cpu_sync_icache(unsigned char *addr, size_t size) +{ + + __syncicache(addr, size); +} + +static __inline void +kdb_cpu_trap(int vector, int _) +{ +} + +static __inline int +kdb_cpu_set_watchpoint(vm_offset_t addr, vm_size_t size, int access) +{ + + return (ENXIO); +} + +static __inline int +kdb_cpu_clr_watchpoint(vm_offset_t addr, vm_size_t size) +{ + + return (0); +} + +#endif /* _MACHINE_KDB_H_ */ diff --git a/sys/powerpc/include/kexec.h b/sys/powerpc/include/kexec.h new file mode 100644 index 000000000000..a57c50926696 --- /dev/null +++ b/sys/powerpc/include/kexec.h @@ -0,0 +1,38 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2025 Juniper Networks, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _POWERPC_KEXEC_H_ +#define _POWERPC_KEXEC_H_ + +int +kexec_load_md(struct kexec_image *image) +{ + return (ENOSYS); +} + +#define kexec_reboot_md(x) do {} while (0) +#endif /* _POWERPC_KEXEC_H_ */ diff --git a/sys/powerpc/include/limits.h b/sys/powerpc/include/limits.h new file mode 100644 index 000000000000..72dc3a64c23d --- /dev/null +++ b/sys/powerpc/include/limits.h @@ -0,0 +1,39 @@ +/*- + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 1988, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _MACHINE_LIMITS_H_ +#define _MACHINE_LIMITS_H_ + +#warning "machine/limits.h is deprecated. Include sys/limits.h instead." + +#include <sys/limits.h> + +#endif /* !_MACHINE_LIMITS_H_ */ diff --git a/sys/powerpc/include/machdep.h b/sys/powerpc/include/machdep.h new file mode 100644 index 000000000000..86a0694a6838 --- /dev/null +++ b/sys/powerpc/include/machdep.h @@ -0,0 +1,37 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2011-2012 Semihalf + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _POWERPC_MACHDEP_H_ +#define _POWERPC_MACHDEP_H_ + +void booke_disable_l2_cache(void); +void booke_enable_l1_cache(void); +void booke_enable_l2_cache(void); +void booke_enable_bpred(void); + +#endif /* _POWERPC_MACHDEP_H_ */ diff --git a/sys/powerpc/include/md_var.h b/sys/powerpc/include/md_var.h new file mode 100644 index 000000000000..e995f0a91b63 --- /dev/null +++ b/sys/powerpc/include/md_var.h @@ -0,0 +1,71 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 1998 Doug Rabson + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _MACHINE_MD_VAR_H_ +#define _MACHINE_MD_VAR_H_ + +/* + * Miscellaneous machine-dependent declarations. + */ + +extern char sigcode32[]; +extern int szsigcode32; + +#ifdef __powerpc64__ +extern char sigcode64[], sigcode64_elfv2[]; +extern int szsigcode64, szsigcode64_elfv2; + +struct dumperinfo; +struct minidumpstate; +int cpu_minidumpsys(struct dumperinfo *, const struct minidumpstate *); +#endif + +extern long Maxmem; + +extern vm_offset_t kstack0; +extern vm_offset_t kstack0_phys; + +extern int powerpc_pow_enabled; +extern int cacheline_size; +extern int hw_direct_map; + +void __syncicache(void *, int); + +int mem_valid(vm_offset_t addr, int len); + +void decr_init(void); +void decr_ap_init(void); +void decr_tc_init(void); + +void cpu_feature_setup(void); +void cpu_setup(u_int); + +struct trapframe; +void powerpc_interrupt(struct trapframe *); + +#endif /* !_MACHINE_MD_VAR_H_ */ diff --git a/sys/powerpc/include/memdev.h b/sys/powerpc/include/memdev.h new file mode 100644 index 000000000000..02dd5896b5b4 --- /dev/null +++ b/sys/powerpc/include/memdev.h @@ -0,0 +1,40 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2004 Mark R V Murray + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer + * in this position and unchanged. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _MACHINE_MEMDEV_H_ +#define _MACHINE_MEMDEV_H_ + +#define CDEV_MINOR_MEM 0 +#define CDEV_MINOR_KMEM 1 + +d_open_t memopen; +d_read_t memrw; +d_ioctl_t memioctl_md; +d_mmap_t memmmap; + +#endif /* _MACHINE_MEMDEV_H_ */ diff --git a/sys/powerpc/include/metadata.h b/sys/powerpc/include/metadata.h new file mode 100644 index 000000000000..6163f882e55f --- /dev/null +++ b/sys/powerpc/include/metadata.h @@ -0,0 +1,38 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2001 Jake Burkholder. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _MACHINE_METADATA_H_ +#define _MACHINE_METADATA_H_ + +#define MODINFOMD_ENVP 0x1001 +#define MODINFOMD_HOWTO 0x1002 +#define MODINFOMD_KERNEND 0x1003 +#define MODINFOMD_BOOTINFO 0x1004 +#define MODINFOMD_DTBP 0x1005 + +#endif /* !_MACHINE_METADATA_H_ */ diff --git a/sys/powerpc/include/minidump.h b/sys/powerpc/include/minidump.h new file mode 100644 index 000000000000..bef38c2cd700 --- /dev/null +++ b/sys/powerpc/include/minidump.h @@ -0,0 +1,52 @@ +/*- + * Copyright (c) 2006 Peter Wemm + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * From i386: FreeBSD: 157909 2006-04-21 04:28:43Z peter + */ + +#ifndef _MACHINE_MINIDUMP_H_ +#define _MACHINE_MINIDUMP_H_ 1 + +#define MINIDUMP_MAGIC "minidump FreeBSD/powerpc64" +#define MINIDUMP_VERSION 2 + +struct minidumphdr { + char magic[32]; + char mmu_name[32]; + uint32_t version; + uint32_t msgbufsize; + uint32_t bitmapsize; + uint32_t pmapsize; + uint64_t kernbase; + uint64_t kernend; + uint64_t dmapbase; + uint64_t dmapend; + int hw_direct_map; + uint64_t startkernel; + uint64_t endkernel; + uint32_t dumpavailsize; +}; + +#endif /* _MACHINE_MINIDUMP_H_ */ diff --git a/sys/powerpc/include/mmuvar.h b/sys/powerpc/include/mmuvar.h new file mode 100644 index 000000000000..9cf7a682ddd5 --- /dev/null +++ b/sys/powerpc/include/mmuvar.h @@ -0,0 +1,224 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2005 Peter Grehan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _MACHINE_MMUVAR_H_ +#define _MACHINE_MMUVAR_H_ + +typedef void (*pmap_bootstrap_t)(vm_offset_t, vm_offset_t); +typedef void (*pmap_cpu_bootstrap_t)(int); +typedef void (*pmap_kenter_t)(vm_offset_t, vm_paddr_t pa); +typedef void (*pmap_kenter_attr_t)(vm_offset_t, vm_paddr_t, vm_memattr_t); +typedef void (*pmap_kremove_t)(vm_offset_t); +typedef void *(*pmap_mapdev_t)(vm_paddr_t, vm_size_t); +typedef void *(*pmap_mapdev_attr_t)(vm_paddr_t, vm_size_t, vm_memattr_t); +typedef void (*pmap_unmapdev_t)(void *, vm_size_t); +typedef void (*pmap_page_set_memattr_t)(vm_page_t, vm_memattr_t); +typedef int (*pmap_change_attr_t)(vm_offset_t, vm_size_t, vm_memattr_t); +typedef int (*pmap_map_user_ptr_t)(pmap_t, volatile const void *, + void **, size_t, size_t *); +typedef int (*pmap_decode_kernel_ptr_t)(vm_offset_t, int *, vm_offset_t *); +typedef vm_paddr_t (*pmap_kextract_t)(vm_offset_t); +typedef int (*pmap_dev_direct_mapped_t)(vm_paddr_t, vm_size_t); + +typedef void (*pmap_page_array_startup_t)(long); +typedef void (*pmap_advise_t)(pmap_t, vm_offset_t, vm_offset_t, int); +typedef void (*pmap_clear_modify_t)(vm_page_t); +typedef void (*pmap_remove_write_t)(vm_page_t); +typedef void (*pmap_copy_t)(pmap_t, pmap_t, vm_offset_t, vm_size_t, vm_offset_t); +typedef void (*pmap_copy_page_t)(vm_page_t, vm_page_t); +typedef void (*pmap_copy_pages_t)(vm_page_t *, vm_offset_t, + vm_page_t *, vm_offset_t, int); +typedef int (*pmap_enter_t)(pmap_t, vm_offset_t, vm_page_t, vm_prot_t, + u_int, int8_t); +typedef void (*pmap_enter_object_t)(pmap_t, vm_offset_t, vm_offset_t, + vm_page_t, vm_prot_t); +typedef void (*pmap_enter_quick_t)(pmap_t, vm_offset_t, vm_page_t, vm_prot_t); +typedef vm_paddr_t (*pmap_extract_t)(pmap_t, vm_offset_t); +typedef vm_page_t (*pmap_extract_and_hold_t)(pmap_t, vm_offset_t, vm_prot_t); +typedef int (*pmap_growkernel_nopanic_t)(vm_offset_t); +typedef void (*pmap_init_t)(void); +typedef bool (*pmap_is_modified_t)(vm_page_t); +typedef bool (*pmap_is_prefaultable_t)(pmap_t, vm_offset_t); +typedef bool (*pmap_is_referenced_t)(vm_page_t); +typedef int (*pmap_ts_referenced_t)(vm_page_t); +typedef vm_offset_t (*pmap_map_t)(vm_offset_t *, vm_paddr_t, vm_paddr_t, int); +typedef void (*pmap_object_init_pt_t)(pmap_t, vm_offset_t, vm_object_t, + vm_pindex_t, vm_size_t); +typedef bool (*pmap_page_exists_quick_t)(pmap_t, vm_page_t); +typedef bool (*pmap_page_is_mapped_t)(vm_page_t); +typedef void (*pmap_page_init_t)(vm_page_t); +typedef int (*pmap_page_wired_mappings_t)(vm_page_t); +typedef void (*pmap_pinit0_t)(pmap_t); +typedef void (*pmap_protect_t)(pmap_t, vm_offset_t, vm_offset_t, vm_prot_t); +typedef void (*pmap_qenter_t)(vm_offset_t, vm_page_t *, int); +typedef void (*pmap_qremove_t)(vm_offset_t, int); +typedef void (*pmap_release_t)(pmap_t); +typedef void (*pmap_remove_t)(pmap_t, vm_offset_t, vm_offset_t); +typedef void (*pmap_remove_all_t)(vm_page_t); +typedef void (*pmap_remove_pages_t)(pmap_t); +typedef void (*pmap_unwire_t)(pmap_t, vm_offset_t, vm_offset_t); +typedef void (*pmap_zero_page_t)(vm_page_t); +typedef void (*pmap_zero_page_area_t)(vm_page_t, int, int); +typedef int (*pmap_mincore_t)(pmap_t, vm_offset_t, vm_paddr_t *); +typedef void (*pmap_activate_t)(struct thread *); +typedef void (*pmap_deactivate_t)(struct thread *); +typedef void (*pmap_align_superpage_t)(vm_object_t, vm_ooffset_t, + vm_offset_t *, vm_size_t); + +typedef void (*pmap_sync_icache_t)(pmap_t, vm_offset_t, vm_size_t); +typedef void (*pmap_dumpsys_map_chunk_t)(vm_paddr_t, size_t, void **); +typedef void (*pmap_dumpsys_unmap_chunk_t)(vm_paddr_t, size_t, void *); +typedef void (*pmap_dumpsys_pa_init_t)(void); +typedef size_t (*pmap_dumpsys_scan_pmap_t)(struct bitset *dump_bitset); +typedef void *(*pmap_dumpsys_dump_pmap_init_t)(unsigned); +typedef void *(*pmap_dumpsys_dump_pmap_t)(void *, void *, u_long *); +typedef vm_offset_t (*pmap_quick_enter_page_t)(vm_page_t); +typedef void (*pmap_quick_remove_page_t)(vm_offset_t); +typedef bool (*pmap_ps_enabled_t)(pmap_t); +typedef void (*pmap_tlbie_all_t)(void); +typedef void (*pmap_installer_t)(void); + +struct pmap_funcs { + pmap_installer_t install; + pmap_bootstrap_t bootstrap; + pmap_cpu_bootstrap_t cpu_bootstrap; + pmap_kenter_t kenter; + pmap_kenter_attr_t kenter_attr; + pmap_kremove_t kremove; + pmap_mapdev_t mapdev; + pmap_mapdev_attr_t mapdev_attr; + pmap_unmapdev_t unmapdev; + pmap_page_set_memattr_t page_set_memattr; + pmap_change_attr_t change_attr; + pmap_map_user_ptr_t map_user_ptr; + pmap_decode_kernel_ptr_t decode_kernel_ptr; + pmap_kextract_t kextract; + pmap_dev_direct_mapped_t dev_direct_mapped; + pmap_advise_t advise; + pmap_clear_modify_t clear_modify; + pmap_remove_write_t remove_write; + pmap_copy_t copy; + pmap_copy_page_t copy_page; + pmap_copy_pages_t copy_pages; + pmap_enter_t enter; + pmap_enter_object_t enter_object; + pmap_enter_quick_t enter_quick; + pmap_extract_t extract; + pmap_extract_and_hold_t extract_and_hold; + pmap_growkernel_nopanic_t growkernel_nopanic; + pmap_init_t init; + pmap_is_modified_t is_modified; + pmap_is_prefaultable_t is_prefaultable; + pmap_is_referenced_t is_referenced; + pmap_ts_referenced_t ts_referenced; + pmap_page_is_mapped_t page_is_mapped; + pmap_ps_enabled_t ps_enabled; + pmap_map_t map; + pmap_object_init_pt_t object_init_pt; + pmap_page_exists_quick_t page_exists_quick; + pmap_page_init_t page_init; + pmap_page_wired_mappings_t page_wired_mappings; + pmap_pinit_t pinit; + pmap_pinit0_t pinit0; + pmap_protect_t protect; + pmap_qenter_t qenter; + pmap_qremove_t qremove; + pmap_release_t release; + pmap_remove_t remove; + pmap_remove_all_t remove_all; + pmap_remove_pages_t remove_pages; + pmap_unwire_t unwire; + pmap_zero_page_t zero_page; + pmap_zero_page_area_t zero_page_area; + pmap_mincore_t mincore; + pmap_activate_t activate; + pmap_deactivate_t deactivate; + pmap_align_superpage_t align_superpage; + pmap_sync_icache_t sync_icache; + pmap_quick_enter_page_t quick_enter_page; + pmap_quick_remove_page_t quick_remove_page; + pmap_page_array_startup_t page_array_startup; + pmap_dumpsys_map_chunk_t dumpsys_map_chunk; + pmap_dumpsys_unmap_chunk_t dumpsys_unmap_chunk; + pmap_dumpsys_pa_init_t dumpsys_pa_init; + pmap_dumpsys_scan_pmap_t dumpsys_scan_pmap; + pmap_dumpsys_dump_pmap_init_t dumpsys_dump_pmap_init; + pmap_dumpsys_dump_pmap_t dumpsys_dump_pmap; + pmap_tlbie_all_t tlbie_all; + +}; +struct mmu_kobj { + const char *name; + const struct mmu_kobj *base; + const struct pmap_funcs *funcs; +}; + +typedef struct mmu_kobj *mmu_t; + +/* The currently installed pmap object. */ +extern mmu_t mmu_obj; + +/* + * Resolve a given pmap function. + * 'func' is the function name less the 'pmap_' * prefix. + */ +#define PMAP_RESOLVE_FUNC(func) \ + ({ \ + pmap_##func##_t f; \ + const struct mmu_kobj *mmu = mmu_obj; \ + do { \ + f = mmu->funcs->func; \ + if (f != NULL) break; \ + mmu = mmu->base; \ + } while (mmu != NULL); \ + f;}) + +#define MMU_DEF(name, ident, methods) \ + \ +const struct mmu_kobj name = { \ + ident, NULL, &methods \ +}; \ +DATA_SET(mmu_set, name) + +#define MMU_DEF_INHERIT(name, ident, methods, base1) \ + \ +const struct mmu_kobj name = { \ + ident, &base1, &methods, \ +}; \ +DATA_SET(mmu_set, name) + +/* + * Known MMU names + */ +#define MMU_TYPE_BOOKE "mmu_booke" /* Book-E MMU specification */ +#define MMU_TYPE_OEA "mmu_oea" /* 32-bit OEA */ +#define MMU_TYPE_G5 "mmu_g5" /* 64-bit bridge (ibm 970) */ +#define MMU_TYPE_RADIX "mmu_radix" /* 64-bit native ISA 3.0 (POWER9) radix */ +#define MMU_TYPE_8xx "mmu_8xx" /* 8xx quicc TLB */ + +#endif /* _MACHINE_MMUVAR_H_ */ diff --git a/sys/powerpc/include/ofw_machdep.h b/sys/powerpc/include/ofw_machdep.h new file mode 100644 index 000000000000..8b3f912fec8c --- /dev/null +++ b/sys/powerpc/include/ofw_machdep.h @@ -0,0 +1,57 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2001 by Thomas Moestl <tmm@FreeBSD.org>. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _MACHINE_OFW_MACHDEP_H_ +#define _MACHINE_OFW_MACHDEP_H_ + +#include <sys/types.h> +#include <sys/rman.h> +#include <sys/bus.h> +#include <dev/ofw/openfirm.h> +#include <machine/platform.h> + +struct mem_region; +struct numa_mem_region; + +typedef uint32_t cell_t; + +void OF_getetheraddr(device_t dev, u_char *addr); + +void OF_initial_setup(void *fdt_ptr, void *junk, int (*openfirm)(void *)); +bool OF_bootstrap(void); + +void OF_reboot(void); + +void ofw_mem_regions(struct mem_region *, int *, struct mem_region *, int *); +void ofw_numa_mem_regions(struct numa_mem_region *, int *); +void ofw_quiesce(void); /* Must be called before VM is up! */ +void ofw_save_trap_vec(char *); +int ofw_pcibus_get_domain(device_t dev, device_t child, int *domain); +int ofw_pcibus_get_cpus(device_t dev, device_t child, enum cpu_sets op, + size_t setsize, cpuset_t *cpuset); + +#endif /* _MACHINE_OFW_MACHDEP_H_ */ diff --git a/sys/powerpc/include/openpicreg.h b/sys/powerpc/include/openpicreg.h new file mode 100644 index 000000000000..16f0295469e2 --- /dev/null +++ b/sys/powerpc/include/openpicreg.h @@ -0,0 +1,141 @@ +/*- + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2000 Tsubai Masanari. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * from NetBSD: openpicreg.h,v 1.3 2001/08/30 03:08:52 briggs Exp + */ + +/* + * Size of OpenPIC register space + */ +#define OPENPIC_SIZE 0x40000 + +/* + * Per Processor Registers [private access] (0x00000 - 0x00fff) + */ + +/* IPI dispatch command reg */ +#define OPENPIC_IPI_DISPATCH(ipi) (0x40 + (ipi) * 0x10) + +/* current task priority reg */ +#define OPENPIC_TPR 0x80 +#define OPENPIC_TPR_MASK 0x0000000f + +#define OPENPIC_WHOAMI 0x90 + +/* interrupt acknowledge reg */ +#define OPENPIC_IACK 0xa0 + +/* end of interrupt reg */ +#define OPENPIC_EOI 0xb0 + +/* + * Global registers (0x01000-0x0ffff) + */ + +/* feature reporting reg 0 */ +#define OPENPIC_FEATURE 0x1000 +#define OPENPIC_FEATURE_VERSION_MASK 0x000000ff +#define OPENPIC_FEATURE_LAST_CPU_MASK 0x00001f00 +#define OPENPIC_FEATURE_LAST_CPU_SHIFT 8 +#define OPENPIC_FEATURE_LAST_IRQ_MASK 0x07ff0000 +#define OPENPIC_FEATURE_LAST_IRQ_SHIFT 16 + +/* global config reg 0 */ +#define OPENPIC_CONFIG 0x1020 +#define OPENPIC_CONFIG_RESET 0x80000000 +#define OPENPIC_CONFIG_8259_PASSTHRU_DISABLE 0x20000000 + +/* interrupt configuration mode (direct or serial) */ +#define OPENPIC_ICR 0x1030 +#define OPENPIC_ICR_SERIAL_MODE (1 << 27) +#define OPENPIC_ICR_SERIAL_RATIO_MASK (0x7 << 28) +#define OPENPIC_ICR_SERIAL_RATIO_SHIFT 28 + +/* vendor ID */ +#define OPENPIC_VENDOR_ID 0x1080 + +/* processor initialization reg */ +#define OPENPIC_PROC_INIT 0x1090 + +/* IPI vector/priority reg */ +#define OPENPIC_IPI_VECTOR(ipi) (0x10a0 + (ipi) * 0x10) + +/* spurious intr. vector */ +#define OPENPIC_SPURIOUS_VECTOR 0x10e0 + +/* Timer registers */ +#define OPENPIC_TIMERS 4 +#define OPENPIC_TFREQ 0x10f0 +#define OPENPIC_TCNT(t) (0x1100 + (t) * 0x40) +#define OPENPIC_TBASE(t) (0x1110 + (t) * 0x40) +#define OPENPIC_TVEC(t) (0x1120 + (t) * 0x40) +#define OPENPIC_TDST(t) (0x1130 + (t) * 0x40) + +/* + * Interrupt Source Configuration Registers (0x10000 - 0x1ffff) + */ + +/* interrupt vector/priority reg */ +#define OPENPIC_SRC_VECTOR_COUNT 64 +#ifndef OPENPIC_SRC_VECTOR +#define OPENPIC_SRC_VECTOR(irq) (0x10000 + (irq) * 0x20) +#endif +#define OPENPIC_SENSE_LEVEL 0x00400000 +#define OPENPIC_SENSE_EDGE 0x00000000 +#define OPENPIC_POLARITY_POSITIVE 0x00800000 +#define OPENPIC_POLARITY_NEGATIVE 0x00000000 +#define OPENPIC_IMASK 0x80000000 +#define OPENPIC_ACTIVITY 0x40000000 +#define OPENPIC_PRIORITY_MASK 0x000f0000 +#define OPENPIC_PRIORITY_SHIFT 16 +#define OPENPIC_VECTOR_MASK 0x000000ff + +/* interrupt destination cpu */ +#ifndef OPENPIC_IDEST +#define OPENPIC_IDEST(irq) (0x10010 + (irq) * 0x20) +#endif + +/* + * Per Processor Registers [global access] (0x20000 - 0x3ffff) + */ + +#define OPENPIC_PCPU_BASE(cpu) (0x20000 + (cpu) * 0x1000) + +#define OPENPIC_PCPU_IPI_DISPATCH(cpu, ipi) \ + (OPENPIC_PCPU_BASE(cpu) + OPENPIC_IPI_DISPATCH(ipi)) + +#define OPENPIC_PCPU_TPR(cpu) \ + (OPENPIC_PCPU_BASE(cpu) + OPENPIC_TPR) + +#define OPENPIC_PCPU_WHOAMI(cpu) \ + (OPENPIC_PCPU_BASE(cpu) + OPENPIC_WHOAMI) + +#define OPENPIC_PCPU_IACK(cpu) \ + (OPENPIC_PCPU_BASE(cpu) + OPENPIC_IACK) + +#define OPENPIC_PCPU_EOI(cpu) \ + (OPENPIC_PCPU_BASE(cpu) + OPENPIC_EOI) diff --git a/sys/powerpc/include/openpicvar.h b/sys/powerpc/include/openpicvar.h new file mode 100644 index 000000000000..12f01cb80406 --- /dev/null +++ b/sys/powerpc/include/openpicvar.h @@ -0,0 +1,87 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (C) 2002 Benno Rice. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _POWERPC_OPENPICVAR_H_ +#define _POWERPC_OPENPICVAR_H_ + +#include <sys/kobj.h> + +#define OPENPIC_DEVSTR "OpenPIC Interrupt Controller" + +#define OPENPIC_IRQMAX 256 /* h/w allows more */ + +#define OPENPIC_QUIRK_SINGLE_BIND 1 /* Bind interrupts to only 1 CPU */ +#define OPENPIC_QUIRK_HIDDEN_IRQS 2 /* May have IRQs beyond FRR[NIRQ] */ + +/* Names match the macros in openpicreg.h. */ +struct openpic_timer { + uint32_t tcnt; + uint32_t tbase; + uint32_t tvec; + uint32_t tdst; +}; + +struct openpic_softc { + device_t sc_dev; + struct resource *sc_memr; + struct resource *sc_intr; + bus_space_tag_t sc_bt; + bus_space_handle_t sc_bh; + char *sc_version; + int sc_rid; + int sc_irq; + void *sc_icookie; + u_int sc_ncpu; + u_int sc_nirq; + int sc_psim; + u_int sc_quirks; + + /* Saved states. */ + uint32_t sc_saved_config; + uint32_t sc_saved_ipis[4]; + uint32_t sc_saved_prios[4]; + struct openpic_timer sc_saved_timers[OPENPIC_TIMERS]; + uint32_t sc_saved_vectors[OPENPIC_SRC_VECTOR_COUNT]; + +}; + +/* + * Bus-independent attach i/f + */ +int openpic_common_attach(device_t, uint32_t); + +/* + * PIC interface. + */ +void openpic_config(device_t, u_int, enum intr_trigger, enum intr_polarity); +void openpic_enable(device_t, u_int, u_int, void **); +void openpic_eoi(device_t, u_int, void *); +void openpic_unmask(device_t, u_int, void *); + +DECLARE_CLASS(openpic_class); + +#endif /* _POWERPC_OPENPICVAR_H_ */ diff --git a/sys/powerpc/include/param.h b/sys/powerpc/include/param.h new file mode 100644 index 000000000000..e79e92f76ec2 --- /dev/null +++ b/sys/powerpc/include/param.h @@ -0,0 +1,150 @@ +/*- + * SPDX-License-Identifier: BSD-4-Clause + * + * Copyright (c) 2001 David E. O'Brien + * Copyright (c) 1990 The Regents of the University of California. + * All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * William Jolitz. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the University of + * California, Berkeley and its contributors. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _POWERPC_INCLUDE_PARAM_H_ +#define _POWERPC_INCLUDE_PARAM_H_ + +/* + * Machine dependent constants for PowerPC + */ + +#include <machine/_align.h> + +#ifndef MACHINE +#define MACHINE "powerpc" +#endif +#ifndef MACHINE_ARCH +#ifdef __powerpc64__ +#if defined(__LITTLE_ENDIAN__) +#define MACHINE_ARCH "powerpc64le" +#else +#define MACHINE_ARCH "powerpc64" +#endif +#else +#ifdef __SPE__ +#define MACHINE_ARCH "powerpcspe" +#else +#define MACHINE_ARCH "powerpc" +#endif +#endif +#endif +#define MID_MACHINE MID_POWERPC +#ifdef __powerpc64__ +#ifndef MACHINE_ARCH32 +#define MACHINE_ARCH32 "powerpc" +#endif +#endif + +#ifdef SMP +#ifndef MAXCPU +#define MAXCPU 256 +#endif +#else +#define MAXCPU 1 +#endif + +#ifndef MAXMEMDOM +#define MAXMEMDOM 8 +#endif + +#define ALIGNBYTES _ALIGNBYTES +#define ALIGN(p) _ALIGN(p) +/* + * ALIGNED_POINTER is a boolean macro that checks whether an address + * is valid to fetch data elements of type t from on this architecture. + * This does not reflect the optimal alignment, just the possibility + * (within reasonable limits). + */ +#define ALIGNED_POINTER(p, t) ((((uintptr_t)(p)) & (sizeof (t) - 1)) == 0) + +/* + * CACHE_LINE_SIZE is the compile-time maximum cache line size for an + * architecture. It should be used with appropriate caution. + */ +#define CACHE_LINE_SHIFT 7 +#define CACHE_LINE_SIZE (1 << CACHE_LINE_SHIFT) + +#define PAGE_SHIFT 12 +#define PAGE_SIZE (1 << PAGE_SHIFT) /* Page size */ +#define PAGE_MASK (PAGE_SIZE - 1) +#define NPTEPG (PAGE_SIZE/(sizeof (pt_entry_t))) +#define NPDEPG (PAGE_SIZE/(sizeof (pt_entry_t))) + +#define L1_PAGE_SIZE_SHIFT 39 +#define L1_PAGE_SIZE (1UL<<L1_PAGE_SIZE_SHIFT) +#define L1_PAGE_MASK (L1_PAGE_SIZE-1) + +#define L2_PAGE_SIZE_SHIFT 30 +#define L2_PAGE_SIZE (1UL<<L2_PAGE_SIZE_SHIFT) +#define L2_PAGE_MASK (L2_PAGE_SIZE-1) + +#define L3_PAGE_SIZE_SHIFT 21 +#define L3_PAGE_SIZE (1UL<<L3_PAGE_SIZE_SHIFT) +#define L3_PAGE_MASK (L3_PAGE_SIZE-1) + +#define MAXPAGESIZES 3 /* maximum number of supported page sizes */ + +#define RELOCATABLE_KERNEL 1 /* kernel may relocate during startup */ + +#ifndef KSTACK_PAGES +#ifdef __powerpc64__ +#define KSTACK_PAGES 12 /* includes pcb */ +#else +#define KSTACK_PAGES 4 /* includes pcb */ +#endif +#endif +#define KSTACK_GUARD_PAGES 1 /* pages of kstack guard; 0 disables */ +#define USPACE (kstack_pages * PAGE_SIZE) /* total size of pcb */ + +#define COPYFAULT 0x1 +#define FUSUFAULT 0x2 + +/* + * Mach derived conversion macros + */ +#define trunc_2mpage(x) ((unsigned long)(x) & ~L3_PAGE_MASK) +#define round_2mpage(x) ((((unsigned long)(x)) + L3_PAGE_MASK) & ~L3_PAGE_MASK) +#define trunc_1gpage(x) ((unsigned long)(x) & ~L2_PAGE_MASK) + +#define powerpc_btop(x) ((x) >> PAGE_SHIFT) +#define powerpc_ptob(x) ((x) << PAGE_SHIFT) + +#define btoc(x) ((vm_offset_t)(((x)+PAGE_MASK)>>PAGE_SHIFT)) + +#endif /* !_POWERPC_INCLUDE_PARAM_H_ */ diff --git a/sys/powerpc/include/pcb.h b/sys/powerpc/include/pcb.h new file mode 100644 index 000000000000..0230cf78aba7 --- /dev/null +++ b/sys/powerpc/include/pcb.h @@ -0,0 +1,129 @@ +/*- + * SPDX-License-Identifier: BSD-4-Clause + * + * Copyright (C) 1995, 1996 Wolfgang Solfrank. + * Copyright (C) 1995, 1996 TooLs GmbH. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by TooLs GmbH. + * 4. The name of TooLs GmbH may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $NetBSD: pcb.h,v 1.4 2000/06/04 11:57:17 tsubai Exp $ + */ + +#ifndef _MACHINE_PCB_H_ +#define _MACHINE_PCB_H_ + +#include <sys/endian.h> + +#include <machine/setjmp.h> + +#ifndef _STANDALONE +struct pcb { + register_t pcb_context[20]; /* non-volatile r12-r31 */ + register_t pcb_cr; /* Condition register */ + register_t pcb_sp; /* stack pointer */ + register_t pcb_toc; /* toc pointer */ + register_t pcb_lr; /* link register */ + register_t pcb_dscr; /* dscr value */ + register_t pcb_fscr; + register_t pcb_tar; + struct pmap *pcb_pm; /* pmap of our vmspace */ + jmp_buf *pcb_onfault; /* For use during + copyin/copyout */ + int pcb_flags; +#define PCB_FPU 0x1 /* Process uses FPU */ +#define PCB_FPREGS 0x2 /* Process had FPU registers initialized */ +#define PCB_VEC 0x4 /* Process uses Altivec */ +#define PCB_VSX 0x8 /* Process had VSX initialized */ +#define PCB_CDSCR 0x10 /* Process had Custom DSCR initialized */ +#define PCB_HTM 0x20 /* Process had HTM initialized */ +#define PCB_CFSCR 0x40 /* Process had FSCR updated */ +#define PCB_KERN_FPU 0x80 /* Kernel is using FPU/Vector unit */ +#define PCB_KERN_FPU_NOSAVE 0x100 /* FPU/Vec state not saved for kernel use */ +#define PCB_VECREGS 0x200 /* Process had Altivec registers initialized */ + struct fpu { + union { + uint32_t vsr[4]; + double fpr; + } fpr[32]; + double fpscr; /* FPSCR stored as double for easier access */ + } pcb_fpu; /* Floating point processor */ + unsigned int pcb_fpcpu; /* which CPU had our FPU + stuff. */ + struct vec { + uint32_t vr[32][4]; + uint32_t spare[2]; + uint32_t vrsave; + uint32_t vscr; /* aligned at vector element 3 */ + } pcb_vec __aligned(16); /* Vector processor */ + unsigned int pcb_veccpu; /* which CPU had our vector + stuff. */ + struct htm { + uint64_t tfhar; + uint64_t texasr; + uint64_t tfiar; + } pcb_htm; + + struct ebb { + uint64_t ebbhr; + uint64_t ebbrr; + uint64_t bescr; + } pcb_ebb; + + struct lmon { + uint64_t lmrr; + uint64_t lmser; + } pcb_lm; + + union { + struct { + vm_offset_t usr_segm; /* Base address */ + register_t usr_vsid; /* USER_SR segment */ + } aim; + struct { + register_t dbcr0; + } booke; + } pcb_cpu; + vm_offset_t pcb_lastill; /* Last illegal instruction */ +}; +#endif + +#ifdef _KERNEL + +struct trapframe; + +#ifndef curpcb +extern struct pcb *curpcb; +#endif + +extern struct pmap *curpm; +extern struct proc *fpuproc; + +void makectx(struct trapframe *, struct pcb *); +void savectx(struct pcb *) __returns_twice; + +#endif +#endif /* _MACHINE_PCB_H_ */ diff --git a/sys/powerpc/include/pcpu.h b/sys/powerpc/include/pcpu.h new file mode 100644 index 000000000000..21636310218c --- /dev/null +++ b/sys/powerpc/include/pcpu.h @@ -0,0 +1,174 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 1999 Luoqi Chen <luoqi@freebsd.org> + * Copyright (c) Peter Wemm <peter@netplex.com.au> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _MACHINE_PCPU_H_ +#define _MACHINE_PCPU_H_ + +#include <machine/cpufunc.h> +#include <machine/slb.h> +#include <machine/tlb.h> + +struct pmap; +struct pvo_entry; +#define CPUSAVE_LEN 9 + +#define PCPU_MD_COMMON_FIELDS \ + int pc_inside_intr; \ + struct pmap *pc_curpmap; /* current pmap */ \ + struct thread *pc_fputhread; /* current fpu user */ \ + struct thread *pc_vecthread; /* current vec user */ \ + struct thread *pc_htmthread; /* current htm user */ \ + uintptr_t pc_hwref; \ + int pc_bsp; \ + volatile int pc_awake; \ + uint32_t pc_ipimask; \ + uint32_t pc_flags; /* cpu feature flags */ \ + register_t pc_tempsave[CPUSAVE_LEN]; \ + register_t pc_disisave[CPUSAVE_LEN]; \ + register_t pc_dbsave[CPUSAVE_LEN]; \ + void *pc_restore; \ + vm_offset_t pc_qmap_addr; + +#define PCPU_MD_AIM32_FIELDS \ + struct pvo_entry *qmap_pvo; \ + struct mtx qmap_lock; \ + char __pad[128]; + +#define PCPU_MD_AIM64_FIELDS \ + struct slb slb[64]; \ + struct slb **userslb; \ + register_t slbsave[18]; \ + uint8_t slbstack[1024]; \ + struct pvo_entry *qmap_pvo; \ + struct mtx qmap_lock; \ + uint64_t opal_hmi_flags; \ + char __pad[1337]; + +#ifdef __powerpc64__ +#define PCPU_MD_AIM_FIELDS PCPU_MD_AIM64_FIELDS +#else +#define PCPU_MD_AIM_FIELDS PCPU_MD_AIM32_FIELDS +#endif + +/* CPU feature flags, can be used for cached flow control. */ +#define PC_FLAG_NOSRS 0x80000000 + +#define BOOKE_CRITSAVE_LEN (CPUSAVE_LEN + 2) +#define BOOKE_TLB_MAXNEST 4 +#define BOOKE_TLB_SAVELEN 16 +#define BOOKE_TLBSAVE_LEN (BOOKE_TLB_SAVELEN * BOOKE_TLB_MAXNEST) + +#ifdef __powerpc64__ +#define BOOKE_PCPU_PAD 901 +#else +#define BOOKE_PCPU_PAD 365 +#endif +#define PCPU_MD_BOOKE_FIELDS \ + register_t critsave[BOOKE_CRITSAVE_LEN]; \ + register_t mchksave[CPUSAVE_LEN]; \ + register_t tlbsave[BOOKE_TLBSAVE_LEN]; \ + register_t tlb_level; \ + uintptr_t *tlb_lock; \ + int tid_next; \ + char __pad[BOOKE_PCPU_PAD]; + +/* Definitions for register offsets within the exception tmp save areas */ +#define CPUSAVE_R27 0 /* where r27 gets saved */ +#define CPUSAVE_R28 1 /* where r28 gets saved */ +#define CPUSAVE_R29 2 /* where r29 gets saved */ +#define CPUSAVE_R30 3 /* where r30 gets saved */ +#define CPUSAVE_R31 4 /* where r31 gets saved */ +#define CPUSAVE_AIM_DAR 5 /* where SPR_DAR gets saved */ +#define CPUSAVE_AIM_DSISR 6 /* where SPR_DSISR gets saved */ +#define CPUSAVE_BOOKE_DEAR 5 /* where SPR_DEAR gets saved */ +#define CPUSAVE_BOOKE_ESR 6 /* where SPR_ESR gets saved */ +#define CPUSAVE_SRR0 7 /* where SRR0 gets saved */ +#define CPUSAVE_SRR1 8 /* where SRR1 gets saved */ +#define BOOKE_CRITSAVE_SRR0 9 /* where real SRR0 gets saved (critical) */ +#define BOOKE_CRITSAVE_SRR1 10 /* where real SRR0 gets saved (critical) */ + +/* Book-E TLBSAVE is more elaborate */ +#define TLBSAVE_BOOKE_LR 0 +#define TLBSAVE_BOOKE_CR 1 +#define TLBSAVE_BOOKE_SRR0 2 +#define TLBSAVE_BOOKE_SRR1 3 +#define TLBSAVE_BOOKE_R20 4 +#define TLBSAVE_BOOKE_R21 5 +#define TLBSAVE_BOOKE_R22 6 +#define TLBSAVE_BOOKE_R23 7 +#define TLBSAVE_BOOKE_R24 8 +#define TLBSAVE_BOOKE_R25 9 +#define TLBSAVE_BOOKE_R26 10 +#define TLBSAVE_BOOKE_R27 11 +#define TLBSAVE_BOOKE_R28 12 +#define TLBSAVE_BOOKE_R29 13 +#define TLBSAVE_BOOKE_R30 14 +#define TLBSAVE_BOOKE_R31 15 + +#define PCPU_MD_FIELDS \ + PCPU_MD_COMMON_FIELDS \ + union { \ + struct { \ + PCPU_MD_AIM_FIELDS \ + } pc_aim; \ + struct { \ + PCPU_MD_BOOKE_FIELDS \ + } pc_booke; \ + } + +#ifdef _KERNEL + +#define pcpup (get_pcpu()) + +static __inline __pure2 struct thread * +__curthread(void) +{ + struct thread *td; +#ifdef __powerpc64__ + __asm __volatile("mr %0,13" : "=r"(td)); +#else + __asm __volatile("mr %0,2" : "=r"(td)); +#endif + return (td); +} +#define curthread (__curthread()) + +#define PCPU_GET(member) (pcpup->pc_ ## member) + +/* + * XXX The implementation of this operation should be made atomic + * with respect to preemption. + */ +#define PCPU_ADD(member, value) (pcpup->pc_ ## member += (value)) +#define PCPU_PTR(member) (&pcpup->pc_ ## member) +#define PCPU_SET(member,value) (pcpup->pc_ ## member = (value)) + +#endif /* _KERNEL */ + +#endif /* !_MACHINE_PCPU_H_ */ diff --git a/sys/powerpc/include/pcpu_aux.h b/sys/powerpc/include/pcpu_aux.h new file mode 100644 index 000000000000..9ca9b4def502 --- /dev/null +++ b/sys/powerpc/include/pcpu_aux.h @@ -0,0 +1,50 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2019 The FreeBSD Foundation + * + * This software was developed by Konstantin Belousov <kib@FreeBSD.org> + * under sponsorship from the FreeBSD Foundation. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _MACHINE_PCPU_AUX_H_ +#define _MACHINE_PCPU_AUX_H_ + +#ifndef _KERNEL +#error "Not for userspace" +#endif + +#ifndef _SYS_PCPU_H_ +#error "Do not include machine/pcpu_aux.h directly" +#endif + +/* + * To minimize memory waste in per-cpu UMA zones, the page size should + * be a multiple of the size of struct pcpu. + */ +_Static_assert(PAGE_SIZE % sizeof(struct pcpu) == 0, "fix pcpu size"); + +extern struct pcpu __pcpu[]; + +#endif /* _MACHINE_PCPU_AUX_H_ */ diff --git a/sys/powerpc/include/pio.h b/sys/powerpc/include/pio.h new file mode 100644 index 000000000000..a7733453fa0d --- /dev/null +++ b/sys/powerpc/include/pio.h @@ -0,0 +1,304 @@ +/*- + * SPDX-License-Identifier: BSD-4-Clause + * + * Copyright (c) 1997 Per Fogelstrom, Opsycon AB and RTMX Inc, USA. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed under OpenBSD by + * Per Fogelstrom Opsycon AB for RTMX Inc, North Carolina, USA. + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $NetBSD: pio.h,v 1.1 1998/05/15 10:15:54 tsubai Exp $ + * $OpenBSD: pio.h,v 1.1 1997/10/13 10:53:47 pefo Exp $ + */ + +#ifndef _MACHINE_PIO_H_ +#define _MACHINE_PIO_H_ +/* + * I/O macros. + */ + +/* + * Use sync so that bus space operations cannot sneak out the bottom of + * mutex-protected sections (mutex release does not guarantee completion of + * accesses to caching-inhibited memory on some systems) + */ +#define powerpc_iomb() __asm __volatile("sync" : : : "memory") + +static __inline void +__outb(volatile u_int8_t *a, u_int8_t v) +{ + *a = v; + powerpc_iomb(); +} + +static __inline void +__outw(volatile u_int16_t *a, u_int16_t v) +{ + *a = v; + powerpc_iomb(); +} + +static __inline void +__outl(volatile u_int32_t *a, u_int32_t v) +{ + *a = v; + powerpc_iomb(); +} + +static __inline void +__outll(volatile u_int64_t *a, u_int64_t v) +{ + *a = v; + powerpc_iomb(); +} + +static __inline void +__outwrb(volatile u_int16_t *a, u_int16_t v) +{ + __asm__ volatile("sthbrx %0, 0, %1" :: "r"(v), "r"(a)); + powerpc_iomb(); +} + +static __inline void +__outlrb(volatile u_int32_t *a, u_int32_t v) +{ + __asm__ volatile("stwbrx %0, 0, %1" :: "r"(v), "r"(a)); + powerpc_iomb(); +} + +static __inline u_int8_t +__inb(volatile u_int8_t *a) +{ + u_int8_t _v_; + + _v_ = *a; + powerpc_iomb(); + return _v_; +} + +static __inline u_int16_t +__inw(volatile u_int16_t *a) +{ + u_int16_t _v_; + + _v_ = *a; + powerpc_iomb(); + return _v_; +} + +static __inline u_int32_t +__inl(volatile u_int32_t *a) +{ + u_int32_t _v_; + + _v_ = *a; + powerpc_iomb(); + return _v_; +} + +static __inline u_int64_t +__inll(volatile u_int64_t *a) +{ + u_int64_t _v_; + + _v_ = *a; + powerpc_iomb(); + return _v_; +} + +static __inline u_int16_t +__inwrb(volatile u_int16_t *a) +{ + u_int16_t _v_; + + __asm__ volatile("lhbrx %0, 0, %1" : "=r"(_v_) : "r"(a)); + powerpc_iomb(); + return _v_; +} + +static __inline u_int32_t +__inlrb(volatile u_int32_t *a) +{ + u_int32_t _v_; + + __asm__ volatile("lwbrx %0, 0, %1" : "=r"(_v_) : "r"(a)); + powerpc_iomb(); + return _v_; +} + +#define outb(a,v) (__outb((volatile u_int8_t *)(a), v)) +#define out8(a,v) outb(a,v) +#define outw(a,v) (__outw((volatile u_int16_t *)(a), v)) +#define out16(a,v) outw(a,v) +#define outl(a,v) (__outl((volatile u_int32_t *)(a), v)) +#define out32(a,v) outl(a,v) +#define outll(a,v) (__outll((volatile u_int64_t *)(a), v)) +#define out64(a,v) outll(a,v) +#define inb(a) (__inb((volatile u_int8_t *)(a))) +#define in8(a) inb(a) +#define inw(a) (__inw((volatile u_int16_t *)(a))) +#define in16(a) inw(a) +#define inl(a) (__inl((volatile u_int32_t *)(a))) +#define in32(a) inl(a) +#define inll(a) (__inll((volatile u_int64_t *)(a))) +#define in64(a) inll(a) + +#define out8rb(a,v) outb(a,v) +#define outwrb(a,v) (__outwrb((volatile u_int16_t *)(a), v)) +#define out16rb(a,v) outwrb(a,v) +#define outlrb(a,v) (__outlrb((volatile u_int32_t *)(a), v)) +#define out32rb(a,v) outlrb(a,v) +#define in8rb(a) inb(a) +#define inwrb(a) (__inwrb((volatile u_int16_t *)(a))) +#define in16rb(a) inwrb(a) +#define inlrb(a) (__inlrb((volatile u_int32_t *)(a))) +#define in32rb(a) inlrb(a) + +static __inline void +__outsb(volatile u_int8_t *a, const u_int8_t *s, size_t c) +{ + while (c--) + *a = *s++; + powerpc_iomb(); +} + +static __inline void +__outsw(volatile u_int16_t *a, const u_int16_t *s, size_t c) +{ + while (c--) + *a = *s++; + powerpc_iomb(); +} + +static __inline void +__outsl(volatile u_int32_t *a, const u_int32_t *s, size_t c) +{ + while (c--) + *a = *s++; + powerpc_iomb(); +} + +static __inline void +__outsll(volatile u_int64_t *a, const u_int64_t *s, size_t c) +{ + while (c--) + *a = *s++; + powerpc_iomb(); +} + +static __inline void +__outswrb(volatile u_int16_t *a, const u_int16_t *s, size_t c) +{ + while (c--) + __asm__ volatile("sthbrx %0, 0, %1" :: "r"(*s++), "r"(a)); + powerpc_iomb(); +} + +static __inline void +__outslrb(volatile u_int32_t *a, const u_int32_t *s, size_t c) +{ + while (c--) + __asm__ volatile("stwbrx %0, 0, %1" :: "r"(*s++), "r"(a)); + powerpc_iomb(); +} + +static __inline void +__insb(volatile u_int8_t *a, u_int8_t *d, size_t c) +{ + while (c--) + *d++ = *a; + powerpc_iomb(); +} + +static __inline void +__insw(volatile u_int16_t *a, u_int16_t *d, size_t c) +{ + while (c--) + *d++ = *a; + powerpc_iomb(); +} + +static __inline void +__insl(volatile u_int32_t *a, u_int32_t *d, size_t c) +{ + while (c--) + *d++ = *a; + powerpc_iomb(); +} + +static __inline void +__insll(volatile u_int64_t *a, u_int64_t *d, size_t c) +{ + while (c--) + *d++ = *a; + powerpc_iomb(); +} + +static __inline void +__inswrb(volatile u_int16_t *a, u_int16_t *d, size_t c) +{ + while (c--) + __asm__ volatile("lhbrx %0, 0, %1" : "=r"(*d++) : "r"(a)); + powerpc_iomb(); +} + +static __inline void +__inslrb(volatile u_int32_t *a, u_int32_t *d, size_t c) +{ + while (c--) + __asm__ volatile("lwbrx %0, 0, %1" : "=r"(*d++) : "r"(a)); + powerpc_iomb(); +} + +#define outsb(a,s,c) (__outsb((volatile u_int8_t *)(a), s, c)) +#define outs8(a,s,c) outsb(a,s,c) +#define outsw(a,s,c) (__outsw((volatile u_int16_t *)(a), s, c)) +#define outs16(a,s,c) outsw(a,s,c) +#define outsl(a,s,c) (__outsl((volatile u_int32_t *)(a), s, c)) +#define outs32(a,s,c) outsl(a,s,c) +#define outsll(a,s,c) (__outsll((volatile u_int64_t *)(a), s, c)) +#define outs64(a,s,c) outsll(a,s,c) +#define insb(a,d,c) (__insb((volatile u_int8_t *)(a), d, c)) +#define ins8(a,d,c) insb(a,d,c) +#define insw(a,d,c) (__insw((volatile u_int16_t *)(a), d, c)) +#define ins16(a,d,c) insw(a,d,c) +#define insl(a,d,c) (__insl((volatile u_int32_t *)(a), d, c)) +#define ins32(a,d,c) insl(a,d,c) +#define insll(a,d,c) (__insll((volatile u_int64_t *)(a), d, c)) +#define ins64(a,d,c) insll(a,d,c) + +#define outs8rb(a,s,c) outsb(a,s,c) +#define outswrb(a,s,c) (__outswrb((volatile u_int16_t *)(a), s, c)) +#define outs16rb(a,s,c) outswrb(a,s,c) +#define outslrb(a,s,c) (__outslrb((volatile u_int32_t *)(a), s, c)) +#define outs32rb(a,s,c) outslrb(a,s,c) +#define ins8rb(a,d,c) insb(a,d,c) +#define inswrb(a,d,c) (__inswrb((volatile u_int16_t *)(a), d, c)) +#define ins16rb(a,d,c) inswrb(a,d,c) +#define inslrb(a,d,c) (__inslrb((volatile u_int32_t *)(a), d, c)) +#define ins32rb(a,d,c) inslrb(a,d,c) + +#endif /*_MACHINE_PIO_H_*/ diff --git a/sys/powerpc/include/platform.h b/sys/powerpc/include/platform.h new file mode 100644 index 000000000000..67ec009a1f58 --- /dev/null +++ b/sys/powerpc/include/platform.h @@ -0,0 +1,76 @@ +/*- + * SPDX-License-Identifier: BSD-4-Clause + * + * Copyright (C) 1996 Wolfgang Solfrank. + * Copyright (C) 1996 TooLs GmbH. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by TooLs GmbH. + * 4. The name of TooLs GmbH may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $NetBSD: powerpc.h,v 1.3 2000/06/01 00:49:59 matt Exp $ + */ + +#ifndef _MACHINE_PLATFORM_H_ +#define _MACHINE_PLATFORM_H_ + +#include <machine/ofw_machdep.h> +#include <machine/smp.h> +#include <machine/pcpu.h> + +struct mem_region { + uint64_t mr_start; + uint64_t mr_size; +}; + +struct numa_mem_region { + uint64_t mr_start; + uint64_t mr_size; + uint64_t mr_domain; +}; + +/* Documentation for these functions is in platform_if.m */ + +void mem_regions(struct mem_region **, int *, struct mem_region **, int *); +void numa_mem_regions(struct numa_mem_region **, int *); +vm_offset_t platform_real_maxaddr(void); + +u_long platform_timebase_freq(struct cpuref *); + +int platform_smp_first_cpu(struct cpuref *); +int platform_smp_next_cpu(struct cpuref *); +int platform_smp_get_bsp(struct cpuref *); +int platform_smp_start_cpu(struct pcpu *); +void platform_smp_timebase_sync(u_long tb, int ap); +void platform_smp_ap_init(void); +void platform_smp_probe_threads(void); +int platform_node_numa_domain(phandle_t); + +const char *installed_platform(void); +void platform_probe_and_attach(void); + +void platform_sleep(void); + +#endif /* _MACHINE_PLATFORM_H_ */ diff --git a/sys/powerpc/include/platformvar.h b/sys/powerpc/include/platformvar.h new file mode 100644 index 000000000000..64b016972484 --- /dev/null +++ b/sys/powerpc/include/platformvar.h @@ -0,0 +1,89 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2005 Peter Grehan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _MACHINE_PLATFORMVAR_H_ +#define _MACHINE_PLATFORMVAR_H_ + +/* + * A PowerPC platform implementation is declared with a kernel object and + * an associated method table, similar to a device driver. + * + * e.g. + * + * static platform_method_t chrp_methods[] = { + * PLATFORMMETHOD(platform_probe, chrp_probe), + * PLATFORMMETHOD(platform_mem_regions, ofw_mem_regions), + * ... + * PLATFORMMETHOD(platform_smp_first_cpu, chrp_smp_first_cpu), + * { 0, 0 } + * }; + * + * static platform_def_t chrp_platform = { + * "chrp", + * chrp_methods, + * sizeof(chrp_platform_softc), // or 0 if no softc + * }; + * + * PLATFORM_DEF(chrp_platform); + */ + +#include <sys/kobj.h> + +struct platform_kobj { + /* + * A platform instance is a kernel object + */ + KOBJ_FIELDS; + + /* + * Utility elements that an instance may use + */ + struct mtx platform_mtx; /* available for instance use */ + void *platform_iptr; /* instance data pointer */ + + /* + * Opaque data that can be overlaid with an instance-private + * structure. Platform code can test that this is large enough at + * compile time with a sizeof() test againt it's softc. There + * is also a run-time test when the platform kernel object is + * registered. + */ +#define PLATFORM_OPAQUESZ 64 + u_int platform_opaque[PLATFORM_OPAQUESZ]; +}; + +typedef struct platform_kobj *platform_t; +typedef struct kobj_class platform_def_t; +#define platform_method_t kobj_method_t + +#define PLATFORMMETHOD KOBJMETHOD +#define PLATFORMMETHOD_END KOBJMETHOD_END + +#define PLATFORM_DEF(name) DATA_SET(platform_set, name) + +#endif /* _MACHINE_PLATFORMVAR_H_ */ diff --git a/sys/powerpc/include/pmap.h b/sys/powerpc/include/pmap.h new file mode 100644 index 000000000000..df07858ff7e3 --- /dev/null +++ b/sys/powerpc/include/pmap.h @@ -0,0 +1,361 @@ +/*- + * SPDX-License-Identifier: BSD-3-Clause AND BSD-4-Clause + * + * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> + * All rights reserved. + * + * Adapted for Freescale's e500 core CPUs. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/*- + * Copyright (C) 1995, 1996 Wolfgang Solfrank. + * Copyright (C) 1995, 1996 TooLs GmbH. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by TooLs GmbH. + * 4. The name of TooLs GmbH may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * from: $NetBSD: pmap.h,v 1.17 2000/03/30 16:18:24 jdolecek Exp $ + */ + +#ifndef _MACHINE_PMAP_H_ +#define _MACHINE_PMAP_H_ + +#include <sys/queue.h> +#include <sys/tree.h> +#include <sys/_cpuset.h> +#include <sys/_lock.h> +#include <sys/_mutex.h> +#include <machine/sr.h> +#include <machine/pte.h> +#include <machine/slb.h> +#include <machine/tlb.h> +#include <machine/vmparam.h> +#ifdef __powerpc64__ +#include <vm/_vm_radix.h> +#endif + +/* + * The radix page table structure is described by levels 1-4. + * See Fig 33. on p. 1002 of Power ISA v3.0B + * + * Page directories and tables must be size aligned. + */ + +/* Root page directory - 64k -- each entry covers 512GB */ +typedef uint64_t pml1_entry_t; +/* l2 page directory - 4k -- each entry covers 1GB */ +typedef uint64_t pml2_entry_t; +/* l3 page directory - 4k -- each entry covers 2MB */ +typedef uint64_t pml3_entry_t; +/* l4 page directory - 256B/4k -- each entry covers 64k/4k */ +typedef uint64_t pml4_entry_t; + +typedef uint64_t pt_entry_t; + +struct pmap; +typedef struct pmap *pmap_t; + +#define PMAP_ENTER_QUICK_LOCKED 0x10000000 + +#if !defined(NPMAPS) +#define NPMAPS 32768 +#endif /* !defined(NPMAPS) */ + +struct slbtnode; + +struct pvo_entry { + LIST_ENTRY(pvo_entry) pvo_vlink; /* Link to common virt page */ +#ifndef __powerpc64__ + LIST_ENTRY(pvo_entry) pvo_olink; /* Link to overflow entry */ +#endif + union { + RB_ENTRY(pvo_entry) pvo_plink; /* Link to pmap entries */ + SLIST_ENTRY(pvo_entry) pvo_dlink; /* Link to delete enty */ + }; + struct { +#ifndef __powerpc64__ + /* 32-bit fields */ + pte_t pte; +#endif + /* 64-bit fields */ + uintptr_t slot; + vm_paddr_t pa; + vm_prot_t prot; + } pvo_pte; + pmap_t pvo_pmap; /* Owning pmap */ + vm_offset_t pvo_vaddr; /* VA of entry */ + uint64_t pvo_vpn; /* Virtual page number */ +}; +LIST_HEAD(pvo_head, pvo_entry); +SLIST_HEAD(pvo_dlist, pvo_entry); +RB_HEAD(pvo_tree, pvo_entry); +int pvo_vaddr_compare(struct pvo_entry *, struct pvo_entry *); +RB_PROTOTYPE(pvo_tree, pvo_entry, pvo_plink, pvo_vaddr_compare); + +/* Used by 32-bit PMAP */ +#define PVO_PTEGIDX_MASK 0x007UL /* which PTEG slot */ +#define PVO_PTEGIDX_VALID 0x008UL /* slot is valid */ +/* Used by 64-bit PMAP */ +#define PVO_HID 0x008UL /* PVO entry in alternate hash*/ +/* Used by both */ +#define PVO_WIRED 0x010UL /* PVO entry is wired */ +#define PVO_MANAGED 0x020UL /* PVO entry is managed */ +#define PVO_BOOTSTRAP 0x080UL /* PVO entry allocated during + bootstrap */ +#define PVO_DEAD 0x100UL /* waiting to be deleted */ +#define PVO_LARGE 0x200UL /* large page */ +#define PVO_VADDR(pvo) ((pvo)->pvo_vaddr & ~ADDR_POFF) +#define PVO_PTEGIDX_GET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_MASK) +#define PVO_PTEGIDX_ISSET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_VALID) +#define PVO_PTEGIDX_CLR(pvo) \ + ((void)((pvo)->pvo_vaddr &= ~(PVO_PTEGIDX_VALID|PVO_PTEGIDX_MASK))) +#define PVO_PTEGIDX_SET(pvo, i) \ + ((void)((pvo)->pvo_vaddr |= (i)|PVO_PTEGIDX_VALID)) +#define PVO_VSID(pvo) ((pvo)->pvo_vpn >> 16) + +struct pmap { + struct pmap_statistics pm_stats; + struct mtx pm_mtx; + cpuset_t pm_active; + union { + struct { + #ifdef __powerpc64__ + struct slbtnode *pm_slb_tree_root; + struct slb **pm_slb; + int pm_slb_len; + #else + register_t pm_sr[16]; + #endif + + struct pmap *pmap_phys; + struct pvo_tree pmap_pvo; + }; +#ifdef __powerpc64__ + /* Radix support */ + struct { + pml1_entry_t *pm_pml1; /* KVA of root page directory */ + struct vm_radix pm_radix; /* spare page table pages */ + TAILQ_HEAD(,pv_chunk) pm_pvchunk; /* list of mappings in pmap */ + uint64_t pm_pid; /* PIDR value */ + int pm_flags; + }; +#endif + struct { + /* TID to identify this pmap entries in TLB */ + tlbtid_t pm_tid[MAXCPU]; + +#ifdef __powerpc64__ + /* + * Page table directory, + * array of pointers to page directories. + */ + pte_t ****pm_root; +#else + /* + * Page table directory, + * array of pointers to page tables. + */ + pte_t **pm_pdir; + + /* List of allocated ptbl bufs (ptbl kva regions). */ + TAILQ_HEAD(, ptbl_buf) pm_ptbl_list; +#endif + }; + } __aligned(CACHE_LINE_SIZE); +}; + +/* + * pv_entries are allocated in chunks per-process. This avoids the + * need to track per-pmap assignments. + */ +#define _NPCPV 126 +#define _NPCM howmany(_NPCPV, 64) + +#define PV_CHUNK_HEADER \ + pmap_t pc_pmap; \ + TAILQ_ENTRY(pv_chunk) pc_list; \ + uint64_t pc_map[_NPCM]; /* bitmap; 1 = free */ \ + TAILQ_ENTRY(pv_chunk) pc_lru; + +struct pv_entry { + pmap_t pv_pmap; + vm_offset_t pv_va; + TAILQ_ENTRY(pv_entry) pv_link; +}; +typedef struct pv_entry *pv_entry_t; + +struct pv_chunk_header { + PV_CHUNK_HEADER +}; +struct pv_chunk { + PV_CHUNK_HEADER + uint64_t reserved; + struct pv_entry pc_pventry[_NPCPV]; +}; + +struct md_page { + union { + struct { + volatile int32_t mdpg_attrs; + vm_memattr_t mdpg_cache_attrs; + struct pvo_head mdpg_pvoh; + int pv_gen; /* (p) */ + }; + struct { + int pv_tracked; + }; + }; + TAILQ_HEAD(, pv_entry) pv_list; /* (p) */ +}; + +#ifdef AIM +#define pmap_page_get_memattr(m) ((m)->md.mdpg_cache_attrs) +#else +#define pmap_page_get_memattr(m) VM_MEMATTR_DEFAULT +#endif /* AIM */ + +/* + * Return the VSID corresponding to a given virtual address. + * If no VSID is currently defined, it will allocate one, and add + * it to a free slot if available. + * + * NB: The PMAP MUST be locked already. + */ +uint64_t va_to_vsid(pmap_t pm, vm_offset_t va); + +/* Lock-free, non-allocating lookup routines */ +uint64_t kernel_va_to_slbv(vm_offset_t va); +struct slb *user_va_to_slb_entry(pmap_t pm, vm_offset_t va); + +uint64_t allocate_user_vsid(pmap_t pm, uint64_t esid, int large); +void free_vsid(pmap_t pm, uint64_t esid, int large); +void slb_insert_user(pmap_t pm, struct slb *slb); +void slb_insert_kernel(uint64_t slbe, uint64_t slbv); + +struct slbtnode *slb_alloc_tree(void); +void slb_free_tree(pmap_t pm); +struct slb **slb_alloc_user_cache(void); +void slb_free_user_cache(struct slb **); + +extern struct pmap kernel_pmap_store; +#define kernel_pmap (&kernel_pmap_store) + +#ifdef _KERNEL + +#define PMAP_LOCK(pmap) mtx_lock(&(pmap)->pm_mtx) +#define PMAP_LOCK_ASSERT(pmap, type) \ + mtx_assert(&(pmap)->pm_mtx, (type)) +#define PMAP_LOCK_DESTROY(pmap) mtx_destroy(&(pmap)->pm_mtx) +#define PMAP_LOCK_INIT(pmap) mtx_init(&(pmap)->pm_mtx, \ + (pmap == kernel_pmap) ? "kernelpmap" : \ + "pmap", NULL, MTX_DEF | MTX_DUPOK) +#define PMAP_LOCKED(pmap) mtx_owned(&(pmap)->pm_mtx) +#define PMAP_MTX(pmap) (&(pmap)->pm_mtx) +#define PMAP_TRYLOCK(pmap) mtx_trylock(&(pmap)->pm_mtx) +#define PMAP_UNLOCK(pmap) mtx_unlock(&(pmap)->pm_mtx) + +#define pmap_page_is_write_mapped(m) (((m)->a.flags & PGA_WRITEABLE) != 0) + +#define pmap_vm_page_alloc_check(m) + +void pmap_bootstrap(vm_offset_t, vm_offset_t); +void pmap_kenter(vm_offset_t va, vm_paddr_t pa); +void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, vm_memattr_t); +void pmap_kremove(vm_offset_t); +void *pmap_mapdev(vm_paddr_t, vm_size_t); +void *pmap_mapdev_attr(vm_paddr_t, vm_size_t, vm_memattr_t); +void pmap_unmapdev(void *, vm_size_t); +void pmap_page_set_memattr(vm_page_t, vm_memattr_t); +int pmap_change_attr(vm_offset_t, vm_size_t, vm_memattr_t); +int pmap_map_user_ptr(pmap_t pm, volatile const void *uaddr, + void **kaddr, size_t ulen, size_t *klen); +int pmap_decode_kernel_ptr(vm_offset_t addr, int *is_user, + vm_offset_t *decoded_addr); +void pmap_deactivate(struct thread *); +vm_paddr_t pmap_kextract(vm_offset_t); +int pmap_dev_direct_mapped(vm_paddr_t, vm_size_t); +bool pmap_mmu_install(char *name, int prio); +void pmap_mmu_init(void); +const char *pmap_mmu_name(void); +bool pmap_ps_enabled(pmap_t pmap); +int pmap_nofault(pmap_t pmap, vm_offset_t va, vm_prot_t flags); +bool pmap_page_is_mapped(vm_page_t m); +#define pmap_map_delete(pmap, sva, eva) pmap_remove(pmap, sva, eva) + +void pmap_page_array_startup(long count); + +#define vtophys(va) pmap_kextract((vm_offset_t)(va)) + +extern vm_offset_t virtual_avail; +extern vm_offset_t virtual_end; +extern caddr_t crashdumpmap; + +extern vm_offset_t msgbuf_phys; + +extern int pmap_bootstrapped; +extern int radix_mmu; +extern int superpages_enabled; + +#ifdef AIM +void pmap_early_io_map_init(void); +#endif +vm_offset_t pmap_early_io_map(vm_paddr_t pa, vm_size_t size); +void pmap_early_io_unmap(vm_offset_t va, vm_size_t size); +void pmap_track_page(pmap_t pmap, vm_offset_t va); +void pmap_page_print_mappings(vm_page_t m); +void pmap_tlbie_all(void); + +static inline int +pmap_vmspace_copy(pmap_t dst_pmap __unused, pmap_t src_pmap __unused) +{ + + return (0); +} + +#endif + +#endif /* !_MACHINE_PMAP_H_ */ diff --git a/sys/powerpc/include/pmc_mdep.h b/sys/powerpc/include/pmc_mdep.h new file mode 100644 index 000000000000..527fed23bfab --- /dev/null +++ b/sys/powerpc/include/pmc_mdep.h @@ -0,0 +1,95 @@ +/*- + * This file is in the public domain. + */ + +#ifndef _MACHINE_PMC_MDEP_H_ +#define _MACHINE_PMC_MDEP_H_ + +#define PMC_MDEP_CLASS_INDEX_POWERPC 1 + +union pmc_md_op_pmcallocate { + uint32_t pm_event; + uint64_t __pad[4]; +}; + +/* Logging */ +#ifdef __powerpc64__ +#define PMCLOG_READADDR PMCLOG_READ64 +#define PMCLOG_EMITADDR PMCLOG_EMIT64 +#else +#define PMCLOG_READADDR PMCLOG_READ32 +#define PMCLOG_EMITADDR PMCLOG_EMIT32 +#endif + +#define mtpmr(reg, val) \ + __asm __volatile("mtpmr %0,%1" : : "K"(reg), "r"(val)) +#define mfpmr(reg) \ + ( { register_t val; \ + __asm __volatile("mfpmr %0,%1" : "=r"(val) : "K"(reg)); \ + val; } ) + +#define PMR_PMC0 16 +#define PMR_PMC1 17 +#define PMR_PMC2 18 +#define PMR_PMC3 19 +#define PMR_PMLCa0 144 +#define PMLCax_FC 0x80000000 +#define PMLCax_FCS 0x40000000 +#define PMLCax_FCU 0x20000000 +#define PMLCax_FCM1 0x10000000 +#define PMLCax_FCM0 0x08000000 +#define PMLCax_CE 0x04000000 +#define PMLCax_EVENT(x) ((x) << 16) +#define PMLCax_FCGS1 0x00000002 +#define PMLCax_FCGS0 0x00000001 +#define PMR_PMLCa1 145 +#define PMR_PMLCa2 146 +#define PMR_PMLCa3 147 +#define PMR_PMLCb0 272 +#define PMLCbx_TRIGONCTL(x) ((x) << 28) +#define PMLCbx_TRIGOFFCTL(x) ((x) << 24) +#define PMLCbx_PMCC 0x00800000 +#define PMLCbx_PMP(x) ((x) << 13) +#define PMLCbx_TREHMUL(x) ((x) << 8) +#define PMLCbx_TRESHOLD(x) ((x) << 0) +#define PMR_PMLCb1 273 +#define PMR_PMLCb2 274 +#define PMR_PMLCb3 275 +#define PMR_PMGC0 400 +#define PMGC_FAC 0x80000000 +#define PMGC_PMIE 0x40000000 +#define PMGC_FCECE 0x20000000 +#define PMGC_TBSEL(x) ((x) << 11) +#define PMGC_TBEE 0x00000100 +#define PMR_UPMC0 0 +#define PMR_UPMC1 1 +#define PMR_UPMC2 2 +#define PMR_UPMC3 3 +#define PMR_UPMLCa0 128 +#define PMR_UPMLCa1 129 +#define PMR_UPMLCa2 130 +#define PMR_UPMLCa3 131 +#define PMR_UPMLCb0 256 +#define PMR_UPMLCb1 257 +#define PMR_UPMLCb2 258 +#define PMR_UPMLCb3 259 +#define PMR_UPMGC0 384 + +#if _KERNEL + +struct pmc_md_powerpc_pmc { + uint64_t pm_powerpc_overflowcnt; + uint32_t pm_powerpc_evsel; +}; + +union pmc_md_pmc { + struct pmc_md_powerpc_pmc pm_powerpc; +}; + +#define PMC_TRAPFRAME_TO_PC(TF) ((TF)->srr0) +#define PMC_TRAPFRAME_TO_FP(TF) ((TF)->fixreg[1]) +#define PMC_TRAPFRAME_TO_SP(TF) (0) + +#endif + +#endif /* !_MACHINE_PMC_MDEP_H_ */ diff --git a/sys/powerpc/include/proc.h b/sys/powerpc/include/proc.h new file mode 100644 index 000000000000..c8c9b6370711 --- /dev/null +++ b/sys/powerpc/include/proc.h @@ -0,0 +1,61 @@ +/*- + * SPDX-License-Identifier: BSD-4-Clause + * + * Copyright (C) 1995, 1996 Wolfgang Solfrank. + * Copyright (C) 1995, 1996 TooLs GmbH. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by TooLs GmbH. + * 4. The name of TooLs GmbH may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $NetBSD: proc.h,v 1.2 1997/04/16 22:57:48 thorpej Exp $ + */ + +#ifndef _MACHINE_PROC_H_ +#define _MACHINE_PROC_H_ + +/* + * Machine-dependent part of the proc structure + */ +struct mdthread { + int md_spinlock_count; /* (k) */ + register_t md_saved_msr; /* (k) */ +}; + +struct mdproc { + /* + * Avoid empty structs because they are undefined behavior. + */ + long md_spare; +}; + +#ifdef __powerpc64__ +#define KINFO_PROC_SIZE 1088 +#define KINFO_PROC32_SIZE 816 +#else +#define KINFO_PROC_SIZE 816 +#endif + +#endif /* !_MACHINE_PROC_H_ */ diff --git a/sys/powerpc/include/procctl.h b/sys/powerpc/include/procctl.h new file mode 100644 index 000000000000..b340002b45ee --- /dev/null +++ b/sys/powerpc/include/procctl.h @@ -0,0 +1,3 @@ +/*- + * This file is in the public domain. + */ diff --git a/sys/powerpc/include/profile.h b/sys/powerpc/include/profile.h new file mode 100644 index 000000000000..7588cc6a2ca3 --- /dev/null +++ b/sys/powerpc/include/profile.h @@ -0,0 +1,234 @@ +/*- + * SPDX-License-Identifier: MIT-CMU + * + * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. + * All rights reserved. + * + * Author: Chris G. Demetriou + * + * Permission to use, copy, modify and distribute this software and + * its documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND + * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie the + * rights to redistribute these changes. + * + * from: NetBSD: profile.h,v 1.9 1997/04/06 08:47:37 cgd Exp + * from: FreeBSD: src/sys/alpha/include/profile.h,v 1.4 1999/12/29 + */ + +#ifndef _MACHINE_PROFILE_H_ +#define _MACHINE_PROFILE_H_ + +#define _MCOUNT_DECL void __mcount + +#define FUNCTION_ALIGNMENT 4 + +typedef __ptrdiff_t fptrdiff_t; + +/* + * The mcount trampoline macro, expanded in libc/gmon/mcount.c + * + * For PowerPC SVR4 ABI profiling, the compiler will insert + * a data declaration and code sequence at the start of a routine of the form + * + * .function_mc: .data + * .align 2 + * .long 0 + * .text + * + * function: mflr %r0 + * addis %r11,%r0, .function_mc@ha + * stw %r0,4(%r1) + * addi %r0,%r11, .function_mc@l + * bl _mcount + * + * The link register is saved in the LR save word in the caller's + * stack frame, r0 is set up to point to the allocated longword, + * and control is transferred to _mcount. + * + * On return from _mcount, the routine should function as it would + * with no profiling so _mcount must restore register state to that upon + * entry. Any routine called by the _mcount trampoline will save + * callee-save registers, so _mcount must make sure it saves volatile + * registers that may have state after it returns i.e. parameter registers. + * + * The FreeBSD libc mcount routine ignores the r0 longword pointer, but + * instead requires as parameters the current PC and called PC. The current + * PC is obtained from the link register, as a result of "bl _mcount" in + * the stub, while the caller's PC is obtained from the LR save word. + * + * On return from libc mcount, the return is done indirectly with the + * ctr register rather than the link register, to allow the link register + * to be restored to what it was on entry to the profiled routine. + */ + +#if defined(__powerpc64__) + +#if !defined(_CALL_ELF) || _CALL_ELF == 1 +#define MCOUNT_PREAMBLE \ + " .align 2 \n" \ + " .globl _mcount \n" \ + " .section \".opd\",\"aw\" \n" \ + " .align 3 \n" \ + "_mcount: \n" \ + " .quad .L._mcount,.TOC.@tocbase,0\n" \ + " .previous \n" \ + " .size _mcount,24 \n" \ + " .type _mcount,@function \n" \ + " .align 4 \n" \ + ".L._mcount: \n" +#else +#define MCOUNT_PREAMBLE \ + " .globl _mcount \n" \ + " .type _mcount,@function \n" \ + " .align 4 \n" \ + "_mcount: \n" +#endif + +#define MCOUNT \ +__asm( MCOUNT_PREAMBLE \ + " stdu %r1,-(288+128)(%r1) \n" \ + " std %r3,48(%r1) \n" \ + " std %r4,56(%r1) \n" \ + " std %r5,64(%r1) \n" \ + " std %r6,72(%r1) \n" \ + " std %r7,80(%r1) \n" \ + " std %r8,88(%r1) \n" \ + " std %r9,96(%r1) \n" \ + " std %r10,104(%r1) \n" \ + " mflr %r4 \n" \ + " std %r4,112(%r1) \n" \ + " ld %r3,0(%r1) \n" \ + " ld %r3,0(%r3) \n" \ + " ld %r3,16(%r3) \n" \ + " bl __mcount \n" \ + " nop \n" \ + " ld %r4,112(%r1) \n" \ + " mtlr %r4 \n" \ + " ld %r3,48(%r1) \n" \ + " ld %r4,56(%r1) \n" \ + " ld %r5,64(%r1) \n" \ + " ld %r6,72(%r1) \n" \ + " ld %r7,80(%r1) \n" \ + " ld %r8,88(%r1) \n" \ + " ld %r9,96(%r1) \n" \ + " ld %r10,104(%r1) \n" \ + " addi %r1,%r1,(288+128) \n" \ + " blr \n"); +#else + +#ifdef PIC +#define _PLT "@plt" +#else +#define _PLT +#endif + +#define MCOUNT \ +__asm( " .globl _mcount \n" \ + " .type _mcount,@function \n" \ + " .align 4 \n" \ + "_mcount: \n" \ + " stwu %r1,-64(%r1) \n" \ + " stw %r3,16(%r1) \n" \ + " stw %r4,20(%r1) \n" \ + " stw %r5,24(%r1) \n" \ + " stw %r6,28(%r1) \n" \ + " stw %r7,32(%r1) \n" \ + " stw %r8,36(%r1) \n" \ + " stw %r9,40(%r1) \n" \ + " stw %r10,44(%r1) \n" \ + " mflr %r4 \n" \ + " stw %r4,48(%r1) \n" \ + " lwz %r3,68(%r1) \n" \ + " bl __mcount" _PLT " \n" \ + " lwz %r3,68(%r1) \n" \ + " mtlr %r3 \n" \ + " lwz %r4,48(%r1) \n" \ + " mtctr %r4 \n" \ + " lwz %r3,16(%r1) \n" \ + " lwz %r4,20(%r1) \n" \ + " lwz %r5,24(%r1) \n" \ + " lwz %r6,28(%r1) \n" \ + " lwz %r7,32(%r1) \n" \ + " lwz %r8,36(%r1) \n" \ + " lwz %r9,40(%r1) \n" \ + " lwz %r10,44(%r1) \n" \ + " addi %r1,%r1,64 \n" \ + " bctr \n" \ + "_mcount_end: \n" \ + " .size _mcount,_mcount_end-_mcount"); +#endif + +#ifdef _KERNEL +#define MCOUNT_ENTER(s) s = intr_disable() +#define MCOUNT_EXIT(s) intr_restore(s) +#define MCOUNT_DECL(s) register_t s; + +#ifndef COMPILING_LINT +#ifdef AIM +#include <machine/trap.h> +#define __PROFILE_VECTOR_BASE EXC_RST +#define __PROFILE_VECTOR_TOP (EXC_LAST + 0x100) +#endif /* AIM */ +#if defined(BOOKE) +extern char interrupt_vector_base[]; +extern char interrupt_vector_top[]; +#define __PROFILE_VECTOR_BASE (uintfptr_t)interrupt_vector_base +#define __PROFILE_VECTOR_TOP (uintfptr_t)interrupt_vector_top +#endif /* BOOKE_E500 */ + +#endif /* !COMPILING_LINT */ + +#ifndef __PROFILE_VECTOR_BASE +#define __PROFILE_VECTOR_BASE 0 +#endif +#ifndef __PROFILE_VECTOR_TOP +#define __PROFILE_VECTOR_TOP 1 +#endif + +static __inline void +powerpc_profile_interrupt(void) +{ +} + +static __inline void +powerpc_profile_userspace(void) +{ +} + +#define MCOUNT_FROMPC_USER(pc) \ + ((pc < (uintfptr_t)VM_MAXUSER_ADDRESS) ? \ + (uintfptr_t)powerpc_profile_userspace : pc) + +#define MCOUNT_FROMPC_INTR(pc) \ + ((pc >= __PROFILE_VECTOR_BASE && \ + pc < __PROFILE_VECTOR_TOP) ? \ + (uintfptr_t)powerpc_profile_interrupt : ~0U) + +void __mcount(uintfptr_t frompc, uintfptr_t selfpc); + +#else /* !_KERNEL */ + +#ifdef __powerpc64__ +typedef u_long uintfptr_t; +#else +typedef u_int uintfptr_t; +#endif + +#endif /* _KERNEL */ + +#endif /* !_MACHINE_PROFILE_H_ */ diff --git a/sys/powerpc/include/psl.h b/sys/powerpc/include/psl.h new file mode 100644 index 000000000000..86c0b3707983 --- /dev/null +++ b/sys/powerpc/include/psl.h @@ -0,0 +1,101 @@ +/*- + * SPDX-License-Identifier: BSD-4-Clause + * + * Copyright (C) 1995, 1996 Wolfgang Solfrank. + * Copyright (C) 1995, 1996 TooLs GmbH. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by TooLs GmbH. + * 4. The name of TooLs GmbH may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $NetBSD: psl.h,v 1.5 2000/11/19 19:52:37 matt Exp $ + */ + +#ifndef _MACHINE_PSL_H_ +#define _MACHINE_PSL_H_ + +/* + * Machine State Register (MSR) - All cores + */ +#define PSL_VEC 0x02000000UL /* AltiVec/SPE vector unit available */ +#define PSL_VSX 0x00800000UL /* Vector-Scalar unit available */ +#define PSL_EE 0x00008000UL /* external interrupt enable */ +#define PSL_PR 0x00004000UL /* privilege mode (1 == user) */ +#define PSL_FP 0x00002000UL /* floating point enable */ +#define PSL_ME 0x00001000UL /* machine check enable */ +#define PSL_FE0 0x00000800UL /* floating point interrupt mode 0 */ +#define PSL_FE1 0x00000100UL /* floating point interrupt mode 1 */ +#define PSL_PMM 0x00000004UL /* performance monitor mark */ +#define PSL_RI 0x00000002UL /* recoverable interrupt */ + +/* Machine State Register - Book-E cores */ +#ifdef __powerpc64__ +#define PSL_CM 0x80000000UL /* Computation Mode (64-bit) */ +#endif + +#define PSL_GS 0x10000000UL /* Guest state */ +#define PSL_UCLE 0x04000000UL /* User mode cache lock enable */ +#define PSL_WE 0x00040000UL /* Wait state enable */ +#define PSL_CE 0x00020000UL /* Critical interrupt enable */ +#define PSL_UBLE 0x00000400UL /* BTB lock enable - e500 only */ +#define PSL_DWE 0x00000400UL /* Debug Wait Enable - 440 only*/ +#define PSL_DE 0x00000200UL /* Debug interrupt enable */ +#define PSL_IS 0x00000020UL /* Instruction address space */ +#define PSL_DS 0x00000010UL /* Data address space */ + +/* Machine State Register (MSR) - AIM cores */ +#ifdef __powerpc64__ +#define PSL_SF 0x8000000000000000UL /* 64-bit addressing */ +#define PSL_HV 0x1000000000000000UL /* hyper-privileged mode */ +#endif + +#define PSL_POW 0x00040000UL /* power management */ +#define PSL_ILE 0x00010000UL /* interrupt endian mode (1 == le) */ +#define PSL_SE 0x00000400UL /* single-step trace enable */ +#define PSL_BE 0x00000200UL /* branch trace enable */ +#define PSL_IP 0x00000040UL /* interrupt prefix - 601 only */ +#define PSL_IR 0x00000020UL /* instruction address relocation */ +#define PSL_DR 0x00000010UL /* data address relocation */ +#define PSL_LE 0x00000001UL /* endian mode (1 == le) */ + +/* + * Floating-point exception modes: + */ +#define PSL_FE_DIS 0 /* none */ +#define PSL_FE_NONREC PSL_FE1 /* imprecise non-recoverable */ +#define PSL_FE_REC PSL_FE0 /* imprecise recoverable */ +#define PSL_FE_PREC (PSL_FE0 | PSL_FE1) /* precise */ +#define PSL_FE_DFLT PSL_FE_PREC /* default == precise */ + +#ifndef LOCORE +extern register_t psl_kernset; /* Default MSR values for kernel */ +extern register_t psl_userset; /* Default MSR values for userland */ +#ifdef __powerpc64__ +extern register_t psl_userset32; /* Default user MSR values for 32-bit */ +#endif +extern register_t psl_userstatic; /* Bits of SRR1 userland may not set */ +#endif + +#endif /* _MACHINE_PSL_H_ */ diff --git a/sys/powerpc/include/pte.h b/sys/powerpc/include/pte.h new file mode 100644 index 000000000000..ed926f80c879 --- /dev/null +++ b/sys/powerpc/include/pte.h @@ -0,0 +1,432 @@ +/*- + * SPDX-License-Identifier: BSD-4-Clause + * + * Copyright (C) 1995, 1996 Wolfgang Solfrank. + * Copyright (C) 1995, 1996 TooLs GmbH. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by TooLs GmbH. + * 4. The name of TooLs GmbH may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $NetBSD: pte.h,v 1.2 1998/08/31 14:43:40 tsubai Exp $ + */ + +#ifndef _MACHINE_PTE_H_ +#define _MACHINE_PTE_H_ + +#if defined(AIM) + +/* + * Page Table Entries + */ +#ifndef LOCORE + +/* 32-bit PTE */ +struct pte { + u_int32_t pte_hi; + u_int32_t pte_lo; +}; + +struct pteg { + struct pte pt[8]; +}; + +/* 64-bit (long) PTE */ +struct lpte { + u_int64_t pte_hi; + u_int64_t pte_lo; +}; + +struct lpteg { + struct lpte pt[8]; +}; + +/* Partition table entry */ +struct pate { + u_int64_t pagetab; + u_int64_t proctab; +}; + +/* Process table entry */ +struct prte { + u_int64_t proctab0; + u_int64_t proctab1; +}; + +typedef struct pte pte_t; +typedef struct lpte lpte_t; +#endif /* LOCORE */ + +/* 32-bit PTE definitions */ + +/* High word: */ +#define PTE_VALID 0x80000000 +#define PTE_VSID_SHFT 7 +#define PTE_HID 0x00000040 +#define PTE_API 0x0000003f +/* Low word: */ +#define PTE_RPGN 0xfffff000 +#define PTE_REF 0x00000100 +#define PTE_CHG 0x00000080 +#define PTE_WIMG 0x00000078 +#define PTE_W 0x00000040 +#define PTE_I 0x00000020 +#define PTE_M 0x00000010 +#define PTE_G 0x00000008 +#define PTE_PP 0x00000003 +#define PTE_SO 0x00000000 /* Super. Only (U: XX, S: RW) */ +#define PTE_SW 0x00000001 /* Super. Write-Only (U: RO, S: RW) */ +#define PTE_BW 0x00000002 /* Supervisor (U: RW, S: RW) */ +#define PTE_BR 0x00000003 /* Both Read Only (U: RO, S: RO) */ +#define PTE_RW PTE_BW +#define PTE_RO PTE_BR + +#define PTE_EXEC 0x00000200 /* pseudo bit in attrs; page is exec */ + +/* 64-bit PTE definitions */ + +/* High quadword: */ +#define LPTE_VSID_SHIFT 12 +#define LPTE_AVPN_MASK 0xFFFFFFFFFFFFFF80ULL +#define LPTE_AVA_MASK 0x3FFFFFFFFFFFFF80ULL +#define LPTE_API 0x0000000000000F80ULL +#define LPTE_SWBITS 0x0000000000000078ULL +#define LPTE_WIRED 0x0000000000000010ULL +#define LPTE_LOCKED 0x0000000000000008ULL +#define LPTE_BIG 0x0000000000000004ULL /* 4kb/16Mb page */ +#define LPTE_HID 0x0000000000000002ULL +#define LPTE_VALID 0x0000000000000001ULL + +/* Low quadword: */ +#define LP_4K_16M 0x38 /* 4KB base, 16MB actual page size */ + +#define EXTEND_PTE(x) UINT64_C(x) /* make constants 64-bit */ +#define LPTE_RPGN 0xfffffffffffff000ULL +#define LPTE_LP_MASK 0x00000000000ff000ULL +#define LPTE_LP_SHIFT 12 +#define LPTE_LP_4K_16M ((unsigned long long)(LP_4K_16M) << LPTE_LP_SHIFT) +#define LPTE_REF EXTEND_PTE( PTE_REF ) +#define LPTE_CHG EXTEND_PTE( PTE_CHG ) +#define LPTE_WIMG EXTEND_PTE( PTE_WIMG ) +#define LPTE_W EXTEND_PTE( PTE_W ) +#define LPTE_I EXTEND_PTE( PTE_I ) +#define LPTE_M EXTEND_PTE( PTE_M ) +#define LPTE_G EXTEND_PTE( PTE_G ) +#define LPTE_NOEXEC 0x0000000000000004ULL +#define LPTE_PP EXTEND_PTE( PTE_PP ) + +#define LPTE_SO EXTEND_PTE( PTE_SO ) /* Super. Only */ +#define LPTE_SW EXTEND_PTE( PTE_SW ) /* Super. Write-Only */ +#define LPTE_BW EXTEND_PTE( PTE_BW ) /* Supervisor */ +#define LPTE_BR EXTEND_PTE( PTE_BR ) /* Both Read Only */ +#define LPTE_RW LPTE_BW +#define LPTE_RO LPTE_BR + +/* HPT superpage definitions */ +#define HPT_SP_SHIFT (VM_LEVEL_0_ORDER + PAGE_SHIFT) +#define HPT_SP_SIZE (1 << HPT_SP_SHIFT) +#define HPT_SP_MASK (HPT_SP_SIZE - 1) +#define HPT_SP_PAGES (1 << VM_LEVEL_0_ORDER) + +/* POWER ISA 3.0 Radix Table Definitions */ +#define RPTE_VALID 0x8000000000000000ULL +#define RPTE_LEAF 0x4000000000000000ULL /* is a PTE: always 1 */ +#define RPTE_SW0 0x2000000000000000ULL +#define RPTE_RPN_MASK 0x00FFFFFFFFFFF000ULL +#define RPTE_RPN_SHIFT 12 +#define RPTE_SW1 0x0000000000000800ULL +#define RPTE_SW2 0x0000000000000400ULL +#define RPTE_SW3 0x0000000000000200ULL +#define RPTE_R 0x0000000000000100ULL +#define RPTE_C 0x0000000000000080ULL + +#define RPTE_MANAGED RPTE_SW1 +#define RPTE_WIRED RPTE_SW2 +#define RPTE_PROMOTED RPTE_SW3 + +#define RPTE_ATTR_MASK 0x0000000000000030ULL +#define RPTE_ATTR_MEM 0x0000000000000000ULL /* PTE M */ +#define RPTE_ATTR_SAO 0x0000000000000010ULL /* PTE WIM */ +#define RPTE_ATTR_GUARDEDIO 0x0000000000000020ULL /* PTE IMG */ +#define RPTE_ATTR_UNGUARDEDIO 0x0000000000000030ULL /* PTE IM */ + +#define RPTE_EAA_MASK 0x000000000000000FULL +#define RPTE_EAA_P 0x0000000000000008ULL /* Supervisor only */ +#define RPTE_EAA_R 0x0000000000000004ULL /* Read allowed */ +#define RPTE_EAA_W 0x0000000000000002ULL /* Write (+read) */ +#define RPTE_EAA_X 0x0000000000000001ULL /* Execute allowed */ + +#define RPDE_VALID RPTE_VALID +#define RPDE_LEAF RPTE_LEAF /* is a PTE: always 0 */ +#define RPDE_NLB_MASK 0x00FFFFFFFFFFFF00ULL +#define RPDE_NLB_SHIFT 8 +#define RPDE_NLS_MASK 0x000000000000001FULL + +#define PG_FRAME (0x000ffffffffff000ul) +#define PG_PS_FRAME (0x000fffffffe00000ul) +/* + * Extract bits from address + */ +#define ADDR_SR_SHFT 28 +#define ADDR_PIDX 0x0ffff000UL +#define ADDR_PIDX_SHFT 12 +#define ADDR_API_SHFT 22 +#define ADDR_API_SHFT64 16 +#define ADDR_POFF 0x00000fffUL + +/* + * Bits in DSISR: + */ +#define DSISR_DIRECT 0x80000000 +#define DSISR_NOTFOUND 0x40000000 +#define DSISR_PROTECT 0x08000000 +#define DSISR_INVRX 0x04000000 +#define DSISR_STORE 0x02000000 +#define DSISR_DABR 0x00400000 +#define DSISR_SEGMENT 0x00200000 +#define DSISR_EAR 0x00100000 + +/* + * Bits in SRR1 on ISI: + */ +#define ISSRR1_NOTFOUND 0x40000000 +#define ISSRR1_DIRECT 0x10000000 +#define ISSRR1_PROTECT 0x08000000 +#define ISSRR1_SEGMENT 0x00200000 + +#else /* BOOKE */ + +#include <machine/tlb.h> + +/* + * Flags for pte_remove() routine. + */ +#define PTBL_HOLD 0x00000001 /* do not unhold ptbl pages */ +#define PTBL_UNHOLD 0x00000002 /* unhold and attempt to free ptbl pages */ + +#define PTBL_HOLD_FLAG(pmap) (((pmap) == kernel_pmap) ? PTBL_HOLD : PTBL_UNHOLD) + +/* + * Page Table Entry definitions and macros. + * + * RPN need only be 32-bit because Book-E has 36-bit addresses, and the smallest + * page size is 4k (12-bit mask), so RPN can really fit into 24 bits. + */ +#ifndef LOCORE +typedef uint64_t pte_t; +#endif + +/* RPN mask, TLB0 4K pages */ +#define PTE_PA_MASK PAGE_MASK + +#if defined(BOOKE_E500) + +/* PTE bits assigned to MAS2, MAS3 flags */ +#define PTE_MAS2_SHIFT 19 +#define PTE_W (MAS2_W << PTE_MAS2_SHIFT) +#define PTE_I (MAS2_I << PTE_MAS2_SHIFT) +#define PTE_M (MAS2_M << PTE_MAS2_SHIFT) +#define PTE_G (MAS2_G << PTE_MAS2_SHIFT) +#define PTE_MAS2_MASK (MAS2_G | MAS2_M | MAS2_I | MAS2_W) + +#define PTE_MAS3_SHIFT 2 +#define PTE_UX (MAS3_UX << PTE_MAS3_SHIFT) +#define PTE_SX (MAS3_SX << PTE_MAS3_SHIFT) +#define PTE_UW (MAS3_UW << PTE_MAS3_SHIFT) +#define PTE_SW (MAS3_SW << PTE_MAS3_SHIFT) +#define PTE_UR (MAS3_UR << PTE_MAS3_SHIFT) +#define PTE_SR (MAS3_SR << PTE_MAS3_SHIFT) +#define PTE_MAS3_MASK ((MAS3_UX | MAS3_SX | MAS3_UW \ + | MAS3_SW | MAS3_UR | MAS3_SR) << PTE_MAS3_SHIFT) + +#define PTE_PS_SHIFT 8 +#define PTE_PS_4KB (2 << PTE_PS_SHIFT) + +#endif + +/* Other PTE flags */ +#define PTE_VALID 0x00000001 /* Valid */ +#define PTE_MODIFIED 0x00001000 /* Modified */ +#define PTE_WIRED 0x00002000 /* Wired */ +#define PTE_MANAGED 0x00000002 /* Managed */ +#define PTE_REFERENCED 0x00040000 /* Referenced */ + +/* + * Page Table Entry definitions and macros. + * + * We use the hardware page table entry format: + * + * 63 24 23 19 18 17 14 13 12 11 8 7 6 5 4 3 2 1 0 + * --------------------------------------------------------------- + * ARPN(12:51) WIMGE R U0:U3 SW0 C PSIZE UX SX UW SW UR SR SW1 V + * --------------------------------------------------------------- + */ + +/* PTE fields. */ +#define PTE_TSIZE_SHIFT (63-54) +#define PTE_TSIZE_MASK 0x7 +#define PTE_TSIZE_SHIFT_DIRECT (63-55) +#define PTE_TSIZE_MASK_DIRECT 0xf +#define PTE_PS_DIRECT(ps) (ps<<PTE_TSIZE_SHIFT_DIRECT) /* Direct Entry Page Size */ +#define PTE_PS(ps) (ps<<PTE_TSIZE_SHIFT) /* Page Size */ + +/* Macro argument must of pte_t type. */ +#define PTE_TSIZE(pte) (int)((*pte >> PTE_TSIZE_SHIFT) & PTE_TSIZE_MASK) +#define PTE_TSIZE_DIRECT(pte) (int)((*pte >> PTE_TSIZE_SHIFT_DIRECT) & PTE_TSIZE_MASK_DIRECT) + +/* Macro argument must of pte_t type. */ +#define PTE_ARPN_SHIFT 12 +#define PTE_FLAGS_MASK 0x00ffffff +#define PTE_RPN_FROM_PA(pa) (((pa) & ~PAGE_MASK) << PTE_ARPN_SHIFT) +#define PTE_PA(pte) ((vm_paddr_t)(*pte >> PTE_ARPN_SHIFT) & ~PAGE_MASK) +#define PTE_ISVALID(pte) ((*pte) & PTE_VALID) +#define PTE_ISWIRED(pte) ((*pte) & PTE_WIRED) +#define PTE_ISMANAGED(pte) ((*pte) & PTE_MANAGED) +#define PTE_ISMODIFIED(pte) ((*pte) & PTE_MODIFIED) +#define PTE_ISREFERENCED(pte) ((*pte) & PTE_REFERENCED) + +#endif /* BOOKE */ + +/* Book-E page table format, broken out for the generic pmap.h. */ +#ifdef __powerpc64__ + +#include <machine/tlb.h> + +/* + * The virtual address is: + * + * 4K page size + * +-----+-----------+-------+-------------+-------------+----------------+ + * | - | pg_root |pdir_l1| dir# | pte# | off in 4K page | + * +-----+-----------+-------+-------------+-------------+----------------+ + * 63 52 51 39 38 30 29 ^ 21 20 ^ 12 11 0 + * | | + * index in 1 page of pointers + * + * 1st level - Root page table + * + * pp2d consists of PG_ROOT_NENTRIES entries, each being a pointer to + * second level entity, i.e. the page table directory (pdir). + */ +#define PG_ROOT_H 51 +#define PG_ROOT_L 39 +#define PG_ROOT_SIZE (1UL << PG_ROOT_L) /* va range mapped by pp2d */ +#define PG_ROOT_SHIFT PG_ROOT_L +#define PG_ROOT_NUM (PG_ROOT_H - PG_ROOT_L + 1) +#define PG_ROOT_MASK ((1 << PG_ROOT_NUM) - 1) +#define PG_ROOT_IDX(va) ((va >> PG_ROOT_SHIFT) & PG_ROOT_MASK) +#define PG_ROOT_NENTRIES (1 << PG_ROOT_NUM) +#define PG_ROOT_ENTRY_SHIFT 3 /* log2 (sizeof(struct pte_entry **)) */ + +/* + * 2nd level - page directory directory (pdir l1) + * + * pdir consists of PDIR_NENTRIES entries, each being a pointer to + * second level entity, i.e. the actual page table (ptbl). + */ +#define PDIR_L1_H (PG_ROOT_L-1) +#define PDIR_L1_L 30 +#define PDIR_L1_NUM (PDIR_L1_H-PDIR_L1_L+1) +#define PDIR_L1_SIZE (1 << PDIR_L1_L) /* va range mapped by pdir */ +#define PDIR_L1_MASK ((1<<PDIR_L1_NUM)-1) +#define PDIR_L1_SHIFT PDIR_L1_L +#define PDIR_L1_NENTRIES (1<<PDIR_L1_NUM) +#define PDIR_L1_IDX(va) (((va) >> PDIR_L1_SHIFT) & PDIR_L1_MASK) +#define PDIR_L1_ENTRY_SHIFT 3 /* log2 (sizeof(struct pte_entry *)) */ +#define PDIR_L1_PAGES ((PDIR_L1_NENTRIES * (1<<PDIR_L1_ENTRY_SHIFT)) / PAGE_SIZE) + +/* + * 3rd level - page table directory (pdir) + * + * pdir consists of PDIR_NENTRIES entries, each being a pointer to + * second level entity, i.e. the actual page table (ptbl). + */ +#define PDIR_H (PDIR_L1_L-1) +#define PDIR_L 21 +#define PDIR_NUM (PDIR_H-PDIR_L+1) +#define PDIR_SIZE (1 << PDIR_L) /* va range mapped by pdir */ +#define PDIR_MASK ((1<<PDIR_NUM)-1) +#define PDIR_SHIFT PDIR_L +#define PDIR_NENTRIES (1<<PDIR_NUM) +#define PDIR_IDX(va) (((va) >> PDIR_SHIFT) & PDIR_MASK) +#define PDIR_ENTRY_SHIFT 3 /* log2 (sizeof(struct pte_entry *)) */ +#define PDIR_PAGES ((PDIR_NENTRIES * (1<<PDIR_ENTRY_SHIFT)) / PAGE_SIZE) + +/* + * 4th level - page table (ptbl) + * + * Page table covers PTBL_NENTRIES page table entries. Page + * table entry (pte) is 64 bit wide and defines mapping + * for a single page. + */ +#define PTBL_H (PDIR_L-1) +#define PTBL_L PAGE_SHIFT +#define PTBL_NUM (PTBL_H-PTBL_L+1) +#define PTBL_MASK ((1<<PTBL_NUM)-1) +#define PTBL_SHIFT PTBL_L +#define PTBL_SIZE PAGE_SIZE /* va range mapped by ptbl entry */ +#define PTBL_NENTRIES (1<<PTBL_NUM) +#define PTBL_IDX(va) ((va >> PTBL_SHIFT) & PTBL_MASK) +#define PTBL_ENTRY_SHIFT 3 /* log2 (sizeof (struct pte_entry)) */ +#define PTBL_PAGES ((PTBL_NENTRIES * (1<<PTBL_ENTRY_SHIFT)) / PAGE_SIZE) + +#else +/* + * 1st level - page table directory (pdir) + * + * pdir consists of 1024 entries, each being a pointer to + * second level entity, i.e. the actual page table (ptbl). + */ +#define PDIR_SHIFT 22 +#define PDIR_SIZE (1 << PDIR_SHIFT) /* va range mapped by pdir */ +#define PDIR_MASK (~(PDIR_SIZE - 1)) +#define PDIR_NENTRIES 1024 /* number of page tables in pdir */ + +/* Returns pdir entry number for given va */ +#define PDIR_IDX(va) ((va) >> PDIR_SHIFT) + +#define PDIR_ENTRY_SHIFT 2 /* entry size is 2^2 = 4 bytes */ + +/* + * 2nd level - page table (ptbl) + * + * Page table covers 1024 page table entries. Page + * table entry (pte) is 32 bit wide and defines mapping + * for a single page. + */ +#define PTBL_SHIFT PAGE_SHIFT +#define PTBL_SIZE PAGE_SIZE /* va range mapped by ptbl entry */ +#define PTBL_MASK ((PDIR_SIZE - 1) & ~((1 << PAGE_SHIFT) - 1)) +#define PTBL_NENTRIES 1024 /* number of pages mapped by ptbl */ + +/* Returns ptbl entry number for given va */ +#define PTBL_IDX(va) (((va) & PTBL_MASK) >> PTBL_SHIFT) + +/* Size of ptbl in pages, 1024 entries, each sizeof(struct pte_entry). */ +#define PTBL_PAGES 2 +#define PTBL_ENTRY_SHIFT 3 /* entry size is 2^3 = 8 bytes */ + +#endif +#endif /* _MACHINE_PTE_H_ */ diff --git a/sys/powerpc/include/ptrace.h b/sys/powerpc/include/ptrace.h new file mode 100644 index 000000000000..69c100c32572 --- /dev/null +++ b/sys/powerpc/include/ptrace.h @@ -0,0 +1,42 @@ +/*- + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 2014 Justin Hibbits + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _MACHINE_PTRACE_H_ +#define _MACHINE_PTRACE_H_ + +#define __HAVE_PTRACE_MACHDEP + +#define PT_GETVRREGS (PT_FIRSTMACH + 0) +#define PT_SETVRREGS (PT_FIRSTMACH + 1) +#define PT_GETVSRREGS (PT_FIRSTMACH + 2) +#define PT_SETVSRREGS (PT_FIRSTMACH + 3) + +#endif diff --git a/sys/powerpc/include/reg.h b/sys/powerpc/include/reg.h new file mode 100644 index 000000000000..781ee3b02289 --- /dev/null +++ b/sys/powerpc/include/reg.h @@ -0,0 +1,87 @@ +/* $NetBSD: reg.h,v 1.4 2000/06/04 09:30:44 tsubai Exp $ */ + +#ifndef _POWERPC_REG_H_ +#define _POWERPC_REG_H_ + +#include <sys/_types.h> + +/* Must match struct trapframe */ +struct reg { + __register_t fixreg[32]; + __register_t lr; + __register_t cr; + __register_t xer; + __register_t ctr; + __register_t pc; +}; + +struct fpreg { + double fpreg[32]; + double fpscr; +}; + +/* Must match pcb.pcb_vec */ +struct vmxreg { + __uint32_t vr[32][4]; + __uint32_t pad[2]; + __uint32_t vrsave; + __uint32_t vscr; +}; + +struct dbreg { + unsigned int junk; +}; + +#ifdef __LP64__ +/* Must match struct trapframe */ +struct reg32 { + __int32_t fixreg[32]; + __int32_t lr; + __int32_t cr; + __int32_t xer; + __int32_t ctr; + __int32_t pc; +}; + +struct fpreg32 { + struct fpreg data; +}; + +struct vmxreg32 { + struct vmxreg data; +}; + +struct dbreg32 { + struct dbreg data; +}; + +#define __HAVE_REG32 +#endif + +#ifdef _KERNEL +/* + * XXX these interfaces are MI, so they should be declared in a MI place. + */ +int fill_regs(struct thread *, struct reg *); +int set_regs(struct thread *, struct reg *); +int fill_fpregs(struct thread *, struct fpreg *); +int set_fpregs(struct thread *, struct fpreg *); +int fill_dbregs(struct thread *, struct dbreg *); +int set_dbregs(struct thread *, struct dbreg *); + +#ifdef COMPAT_FREEBSD32 +struct image_params; + +int fill_regs32(struct thread *, struct reg32 *); +int set_regs32(struct thread *, struct reg32 *); +void ppc32_setregs(struct thread *, struct image_params *, uintptr_t); + +#define fill_fpregs32(td, reg) fill_fpregs(td,(struct fpreg *)reg) +#define set_fpregs32(td, reg) set_fpregs(td,(struct fpreg *)reg) +#define fill_dbregs32(td, reg) fill_dbregs(td,(struct dbreg *)reg) +#define set_dbregs32(td, reg) set_dbregs(td,(struct dbreg *)reg) +#endif + +#endif + +#endif /* _POWERPC_REG_H_ */ diff --git a/sys/powerpc/include/reloc.h b/sys/powerpc/include/reloc.h new file mode 100644 index 000000000000..21c9d92f1a42 --- /dev/null +++ b/sys/powerpc/include/reloc.h @@ -0,0 +1,30 @@ +/*- + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 1998 John Birrell <jb@cimlogic.com.au>. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the author nor the names of any co-contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY JOHN BIRRELL AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ diff --git a/sys/powerpc/include/resource.h b/sys/powerpc/include/resource.h new file mode 100644 index 000000000000..e7e9493569cc --- /dev/null +++ b/sys/powerpc/include/resource.h @@ -0,0 +1,51 @@ +/*- + * Copyright 1998 Massachusetts Institute of Technology + * + * Permission to use, copy, modify, and distribute this software and + * its documentation for any purpose and without fee is hereby + * granted, provided that both the above copyright notice and this + * permission notice appear in all copies, that both the above + * copyright notice and this permission notice appear in all + * supporting documentation, and that the name of M.I.T. not be used + * in advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. M.I.T. makes + * no representations about the suitability of this software for any + * purpose. It is provided "as is" without express or implied + * warranty. + * + * THIS SOFTWARE IS PROVIDED BY M.I.T. ``AS IS''. M.I.T. DISCLAIMS + * ALL EXPRESS OR IMPLIED WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT + * SHALL M.I.T. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _MACHINE_RESOURCE_H_ +#define _MACHINE_RESOURCE_H_ 1 + +/* + * Definitions of resource types for Intel Architecture machines + * with support for legacy ISA devices and drivers. + */ + +#define SYS_RES_IRQ 1 /* interrupt lines */ +#define SYS_RES_DRQ 2 /* isa dma lines */ +#define SYS_RES_MEMORY 3 /* i/o memory */ +#define SYS_RES_IOPORT 4 /* i/o ports */ +#define PCI_RES_BUS 5 /* PCI bus numbers */ + +/* + * A powerpc-specific resource flag to request little-endian bus tags + * for a resource. + */ + +#define RF_LITTLEENDIAN RF_SPARE1 + +#endif /* !_MACHINE_RESOURCE_H_ */ diff --git a/sys/powerpc/include/rtas.h b/sys/powerpc/include/rtas.h new file mode 100644 index 000000000000..7189a4bc00bf --- /dev/null +++ b/sys/powerpc/include/rtas.h @@ -0,0 +1,59 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2011 Nathan Whitehorn + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _MACHINE_RTAS_H_ +#define _MACHINE_RTAS_H_ + +#include <sys/types.h> +#include <dev/ofw/openfirm.h> + +/* + * RTAS functions are defined by 32-bit integer tokens. These vary from + * system to system, and can be looked up from their standardized names + * using rtas_token_lookup(). If RTAS is not available, rtas_token_lookup() + * and rtas_call_method() return -1; this can be checked in advance using + * rtas_exists(). Otherwise, rtas_call_method() returns one of the RTAS + * status codes from the bottom of this file. + */ + +int rtas_exists(void); +int rtas_call_method(cell_t token, int nargs, int nreturns, ...); +cell_t rtas_token_lookup(const char *method); + +/* RTAS Status Codes: see CHRP or PAPR specification */ +#define RTAS_OK 0 +#define RTAS_HW_ERROR -1 +#define RTAS_BUSY -2 +#define RTAS_PARAM_ERROR -3 +#define RTAS_STATE_CHANGE -7 +#define RTAS_VENDOR_BEGIN 9000 +#define RTAS_EXTENDED_DELAY 9900 +#define RTAS_ISOLATION_ERROR -9000 +#define RTAS_VENDOR_ERROR_BEGIN -9004 + +#endif /* _MACHINE_RTAS_H_ */ diff --git a/sys/powerpc/include/sc_machdep.h b/sys/powerpc/include/sc_machdep.h new file mode 100644 index 000000000000..0c0b25b72da6 --- /dev/null +++ b/sys/powerpc/include/sc_machdep.h @@ -0,0 +1,71 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2003 Jake Burkholder. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _MACHINE_SC_MACHDEP_H_ +#define _MACHINE_SC_MACHDEP_H_ + +/* Color attributes for foreground text */ + +#define FG_BLACK 0x0 +#define FG_BLUE 0x1 +#define FG_GREEN 0x2 +#define FG_CYAN 0x3 +#define FG_RED 0x4 +#define FG_MAGENTA 0x5 +#define FG_BROWN 0x6 +#define FG_LIGHTGREY 0x7 /* aka white */ +#define FG_DARKGREY 0x8 +#define FG_LIGHTBLUE 0x9 +#define FG_LIGHTGREEN 0xa +#define FG_LIGHTCYAN 0xb +#define FG_LIGHTRED 0xc +#define FG_LIGHTMAGENTA 0xd +#define FG_YELLOW 0xe +#define FG_WHITE 0xf /* aka bright white */ +#define FG_BLINK 0x80 + +/* Color attributes for text background */ + +#define BG_BLACK 0x00 +#define BG_BLUE 0x10 +#define BG_GREEN 0x20 +#define BG_CYAN 0x30 +#define BG_RED 0x40 +#define BG_MAGENTA 0x50 +#define BG_BROWN 0x60 +#define BG_LIGHTGREY 0x70 +#define BG_DARKGREY 0x80 +#define BG_LIGHTBLUE 0x90 +#define BG_LIGHTGREEN 0xa0 +#define BG_LIGHTCYAN 0xb0 +#define BG_LIGHTRED 0xc0 +#define BG_LIGHTMAGENTA 0xd0 +#define BG_YELLOW 0xe0 +#define BG_WHITE 0xf0 + +#endif /* !_MACHINE_SC_MACHDEP_H_ */ diff --git a/sys/powerpc/include/sdt_machdep.h b/sys/powerpc/include/sdt_machdep.h new file mode 100644 index 000000000000..8f6c3d88ea7d --- /dev/null +++ b/sys/powerpc/include/sdt_machdep.h @@ -0,0 +1,12 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2024 Mark Johnston <markj@FreeBSD.org> + */ + +#ifndef _SYS_SDT_MACHDEP_H_ +#define _SYS_SDT_MACHDEP_H_ + +#define _SDT_ASM_PATCH_INSTR "nop" + +#endif diff --git a/sys/powerpc/include/setjmp.h b/sys/powerpc/include/setjmp.h new file mode 100644 index 000000000000..5dc463619bca --- /dev/null +++ b/sys/powerpc/include/setjmp.h @@ -0,0 +1,27 @@ +/*- + * $NetBSD: setjmp.h,v 1.3 1998/09/16 23:51:27 thorpej Exp $ + */ + +#ifndef _MACHINE_SETJMP_H_ +#define _MACHINE_SETJMP_H_ + +#include <sys/cdefs.h> + +#ifdef _KERNEL +#define _JBLEN 25 /* Kernel doesn't save FP and Altivec regs */ +#else +#define _JBLEN 100 +#endif + +/* + * jmp_buf and sigjmp_buf are encapsulated in different structs to force + * compile-time diagnostics for mismatches. The structs are the same + * internally to avoid some run-time errors for mismatches. + */ +#if __BSD_VISIBLE || __POSIX_VISIBLE || __XSI_VISIBLE +typedef struct _sigjmp_buf { long _sjb[_JBLEN + 1]; } sigjmp_buf[1]; +#endif + +typedef struct _jmp_buf { long _jb[_JBLEN + 1]; } jmp_buf[1]; + +#endif /* !_MACHINE_SETJMP_H_ */ diff --git a/sys/powerpc/include/sigframe.h b/sys/powerpc/include/sigframe.h new file mode 100644 index 000000000000..ce8cdf635376 --- /dev/null +++ b/sys/powerpc/include/sigframe.h @@ -0,0 +1,39 @@ +/*- + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 1999 Marcel Moolenaar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer + * in this position and unchanged. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _MACHINE_SIGFRAME_H_ +#define _MACHINE_SIGFRAME_H_ 1 + +struct sigframe { + ucontext_t sf_uc; + siginfo_t sf_si; +}; + +#endif /* _MACHINE_SIGFRAME_H_ */ diff --git a/sys/powerpc/include/signal.h b/sys/powerpc/include/signal.h new file mode 100644 index 000000000000..0d5bf48e7635 --- /dev/null +++ b/sys/powerpc/include/signal.h @@ -0,0 +1,54 @@ +/*- + * SPDX-License-Identifier: BSD-4-Clause + * + * Copyright (C) 1995, 1996 Wolfgang Solfrank. + * Copyright (C) 1995, 1996 TooLs GmbH. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by TooLs GmbH. + * 4. The name of TooLs GmbH may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $NetBSD: signal.h,v 1.4 1998/09/14 02:48:34 thorpej Exp $ + */ + +#ifndef _MACHINE_SIGNAL_H_ +#define _MACHINE_SIGNAL_H_ + +#include <sys/cdefs.h> + +typedef int sig_atomic_t; + +#if __BSD_VISIBLE +#include <machine/frame.h> + +struct sigcontext { + int sc_onstack; /* saved onstack flag */ + int __sc_mask13; /* saved signal mask (old style) */ + struct trapframe sc_frame; /* saved registers */ + struct __sigset sc_mask; /* saved signal mask (new style) */ +}; +#endif + +#endif /* !_MACHINE_SIGNAL_H_ */ diff --git a/sys/powerpc/include/slb.h b/sys/powerpc/include/slb.h new file mode 100644 index 000000000000..707887d197bd --- /dev/null +++ b/sys/powerpc/include/slb.h @@ -0,0 +1,92 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (C) 2009 Nathan Whitehorn + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _MACHINE_SLB_H_ +#define _MACHINE_SLB_H_ + +/* + * Bit definitions for segment lookaside buffer entries. + * + * PowerPC Microprocessor Family: The Programming Environments for 64-bit + * Microprocessors, section 7.4.2.1 + * + * Note that these bitmasks are relative to the values for one of the two + * values for slbmte, slbmfee, and slbmfev, not the internal SLB + * representation. + */ + +#define SLBV_KS 0x0000000000000800UL /* Supervisor-state prot key */ +#define SLBV_KP 0x0000000000000400UL /* User-state prot key */ +#define SLBV_N 0x0000000000000200UL /* No-execute protection */ +#define SLBV_L 0x0000000000000100UL /* Large page selector */ +#define SLBV_CLASS 0x0000000000000080UL /* Class selector */ +#define SLBV_VSID_MASK 0xfffffffffffff000UL /* Virtual segment ID mask */ +#define SLBV_VSID_SHIFT 12 + +/* + * Make a predictable 1:1 map from ESIDs to VSIDs for the kernel. Hash table + * coverage is increased by swizzling the ESID and multiplying by a prime + * number (0x13bb). + */ +#define KERNEL_VSID_BIT 0x0000001000000000UL /* Bit set in all kernel VSIDs */ +#define KERNEL_VSID(esid) ((((((uint64_t)esid << 8) | ((uint64_t)esid >> 28)) \ + * 0x13bbUL) & (KERNEL_VSID_BIT - 1)) | \ + KERNEL_VSID_BIT) + +#define SLBE_VALID 0x0000000008000000UL /* SLB entry valid */ +#define SLBE_INDEX_MASK 0x0000000000000fffUL /* SLB index mask*/ +#define SLBE_ESID_MASK 0xfffffffff0000000UL /* Effective segment ID mask */ +#define SLBE_ESID_SHIFT 28 + +/* + * SLB page sizes encoding, as present in property ibm,segment-page-sizes + * of CPU device tree node. + * + * See LoPAPR: CPU Node Properties, section C.6.1.4. + */ +#define SLB_PGSZ_4K_4K 0 + +/* Virtual real-mode VSID in LPARs */ +#define VSID_VRMA 0x1ffffff + +/* + * User segment for copyin/out + */ +#define USER_SLB_SLOT 0 +#define USER_SLB_SLBE (((USER_ADDR >> ADDR_SR_SHFT) << SLBE_ESID_SHIFT) | \ + SLBE_VALID | USER_SLB_SLOT) + +struct slb { + uint64_t slbv; + uint64_t slbe; +}; + +struct pmap; +void handle_kernel_slb_spill(int, register_t, register_t); +int handle_user_slb_spill(struct pmap *pm, vm_offset_t addr); + +#endif /* !_MACHINE_SLB_H_ */ diff --git a/sys/powerpc/include/smp.h b/sys/powerpc/include/smp.h new file mode 100644 index 000000000000..d29a576655ae --- /dev/null +++ b/sys/powerpc/include/smp.h @@ -0,0 +1,64 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2008 Marcel Moolenaar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _MACHINE_SMP_H_ +#define _MACHINE_SMP_H_ + +#ifdef _KERNEL + +#define IPI_AST 0 +#define IPI_PREEMPT 1 +#define IPI_RENDEZVOUS 2 +#define IPI_STOP 3 +#define IPI_STOP_HARD 3 +#define IPI_HARDCLOCK 4 + +#ifndef LOCORE + +#include <machine/pcb.h> +#include <sys/_cpuset.h> + +void ipi_all_but_self(int ipi); +void ipi_cpu(int cpu, u_int ipi); +void ipi_selected(cpuset_t cpus, int ipi); + +struct cpuref { + uintptr_t cr_hwref; + u_int cr_cpuid; + u_int cr_domain; +}; + +void pmap_cpu_bootstrap(int); +void cpudep_ap_early_bootstrap(void); +uintptr_t cpudep_ap_bootstrap(void); +void cpudep_ap_setup(void); +void machdep_ap_bootstrap(void); + +#endif /* !LOCORE */ +#endif /* _KERNEL */ +#endif /* !_MACHINE_SMP_H */ diff --git a/sys/powerpc/include/spr.h b/sys/powerpc/include/spr.h new file mode 100644 index 000000000000..605b1be194d9 --- /dev/null +++ b/sys/powerpc/include/spr.h @@ -0,0 +1,868 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2001 The NetBSD Foundation, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * $NetBSD: spr.h,v 1.25 2002/08/14 15:38:40 matt Exp $ + */ +#ifndef _POWERPC_SPR_H_ +#define _POWERPC_SPR_H_ + +#ifndef _LOCORE +#define mtspr(reg, val) \ + __asm __volatile("mtspr %0,%1" : : "K"(reg), "r"(val)) +#define mfspr(reg) \ + ( { register_t val; \ + __asm __volatile("mfspr %0,%1" : "=r"(val) : "K"(reg)); \ + val; } ) + +#ifndef __powerpc64__ + +/* The following routines allow manipulation of the full 64-bit width + * of SPRs on 64 bit CPUs in bridge mode */ + +#define mtspr64(reg,valhi,vallo,scratch) \ + __asm __volatile(" \ + mfmsr %0; \ + insrdi %0,%5,1,0; \ + mtmsrd %0; \ + isync; \ + \ + sld %1,%1,%4; \ + or %1,%1,%2; \ + mtspr %3,%1; \ + srd %1,%1,%4; \ + \ + clrldi %0,%0,1; \ + mtmsrd %0; \ + isync;" \ + : "=r"(scratch), "=r"(valhi) : "r"(vallo), "K"(reg), "r"(32), "r"(1)) + +#define mfspr64upper(reg,scratch) \ + ( { register_t val; \ + __asm __volatile(" \ + mfmsr %0; \ + insrdi %0,%4,1,0; \ + mtmsrd %0; \ + isync; \ + \ + mfspr %1,%2; \ + srd %1,%1,%3; \ + \ + clrldi %0,%0,1; \ + mtmsrd %0; \ + isync;" \ + : "=r"(scratch), "=r"(val) : "K"(reg), "r"(32), "r"(1)); \ + val; } ) + +#endif + +#endif /* _LOCORE */ + +/* + * Special Purpose Register declarations. + * + * The first column in the comments indicates which PowerPC + * architectures the SPR is valid on - 4 for 4xx series, + * 6 for 6xx/7xx series and 8 for 8xx and 8xxx series. + */ + +#define SPR_MQ 0x000 /* .6. 601 MQ register */ +#define SPR_XER 0x001 /* 468 Fixed Point Exception Register */ +#define SPR_DSCR 0x003 /* .6. Data Stream Control Register (Unprivileged) */ +#define SPR_RTCU_R 0x004 /* .6. 601 RTC Upper - Read */ +#define SPR_RTCL_R 0x005 /* .6. 601 RTC Lower - Read */ +#define SPR_LR 0x008 /* 468 Link Register */ +#define SPR_CTR 0x009 /* 468 Count Register */ +#define SPR_DSCRP 0x011 /* Data Stream Control Register (Privileged) */ +#define SPR_DSISR 0x012 /* .68 DSI exception source */ +#define DSISR_DIRECT 0x80000000 /* Direct-store error exception */ +#define DSISR_NOTFOUND 0x40000000 /* Translation not found */ +#define DSISR_PROTECT 0x08000000 /* Memory access not permitted */ +#define DSISR_INVRX 0x04000000 /* Reserve-indexed insn direct-store access */ +#define DSISR_STORE 0x02000000 /* Store operation */ +#define DSISR_DABR 0x00400000 /* DABR match */ +#define DSISR_SEGMENT 0x00200000 /* XXX; not in 6xx PEM */ +#define DSISR_EAR 0x00100000 /* eciwx/ecowx && EAR[E] == 0 */ +#define DSISR_MC_UE_DEFERRED 0x00008000 /* UE deferred error */ +#define DSISR_MC_UE_TABLEWALK 0x00004000 /* UE deferred error during tablewalk */ +#define DSISR_MC_DERAT_MULTIHIT 0x00000800 /* D-ERAT multi-hit */ +#define DSISR_MC_TLB_MULTIHIT 0x00000400 /* TLB multi-hit */ +#define DSISR_MC_TLBIE_ERR 0x00000200 /* TLBIE or TLBIEL programming error */ +#define DSISR_MC_SLB_PARITY 0x00000100 /* SLB parity error */ +#define DSISR_MC_SLB_MULTIHIT 0x00000080 /* SLB Multi-hit detected (D-side) */ +#define DSISR_MC_BAD_REAL_LD 0x00000040 /* Bad real address for load. */ +#define DSISR_MC_BAD_ADDR 0x00000020 /* Bad address for load or store tablewalk */ +#define SPR_DAR 0x013 /* .68 Data Address Register */ +#define SPR_RTCU_W 0x014 /* .6. 601 RTC Upper - Write */ +#define SPR_RTCL_W 0x015 /* .6. 601 RTC Lower - Write */ +#define SPR_DEC 0x016 /* .68 DECrementer register */ +#define SPR_SDR1 0x019 /* .68 Page table base address register */ +#define SPR_SRR0 0x01a /* 468 Save/Restore Register 0 */ +#define SPR_SRR1 0x01b /* 468 Save/Restore Register 1 */ +#define SRR1_ISI_PFAULT 0x40000000 /* ISI page not found */ +#define SRR1_ISI_NOEXECUTE 0x10000000 /* Memory marked no-execute */ +#define SRR1_ISI_PP 0x08000000 /* PP bits forbid access */ +#define SRR1_MCHK_DATA 0x00200000 /* Machine check data in DSISR */ +#define SRR1_MCHK_IFETCH_M 0x081c0000 /* Machine check instr fetch mask */ +#define SRR1_MCHK_IFETCH_SLBMH 0x000c0000 /* SLB multihit */ +#define SPR_CFAR 0x01c /* Come From Address Register */ +#define SPR_AMR 0x01d /* Authority Mask Register */ + +#define SPR_PID 0x030 /* 4.. Process ID */ + +#define SPR_DECAR 0x036 /* ..8 Decrementer auto reload */ +#define SPR_IAMR 0x03d /* Instr. Authority Mask Reg */ + +#define SPR_EIE 0x050 /* ..8 Exception Interrupt ??? */ +#define SPR_EID 0x051 /* ..8 Exception Interrupt ??? */ +#define SPR_NRI 0x052 /* ..8 Exception Interrupt ??? */ +#define SPR_FSCR 0x099 /* Facility Status and Control Register */ +#define FSCR_IC_MASK 0xFF00000000000000ULL /* FSCR[0:7] is Interrupt Cause */ +#define FSCR_IC_FP 0x0000000000000000ULL /* FP unavailable */ +#define FSCR_IC_VSX 0x0100000000000000ULL /* VSX unavailable */ +#define FSCR_IC_DSCR 0x0200000000000000ULL /* Access to the DSCR at SPRs 3 or 17 */ +#define FSCR_IC_PM 0x0300000000000000ULL /* Read or write access of a Performance Monitor SPR in group A */ +#define FSCR_IC_BHRB 0x0400000000000000ULL /* Execution of a BHRB Instruction */ +#define FSCR_IC_HTM 0x0500000000000000ULL /* Access to a Transactional Memory */ +/* Reserved 0x0600000000000000ULL */ +#define FSCR_IC_EBB 0x0700000000000000ULL /* Access to Event-Based Branch */ +#define FSCR_IC_TAR 0x0800000000000000ULL /* Access to Target Address Register */ +#define FSCR_IC_STOP 0x0900000000000000ULL /* Access to the 'stop' instruction in privileged non-hypervisor state */ +#define FSCR_IC_MSG 0x0A00000000000000ULL /* Access to 'msgsndp' or 'msgclrp' instructions */ +#define FSCR_IC_LM 0x0A00000000000000ULL /* Access to load monitored facility */ +#define FSCR_IC_SCV 0x0C00000000000000ULL /* Execution of a 'scv' instruction */ +#define FSCR_SCV 0x0000000000001000 /* scv instruction available */ +#define FSCR_LM 0x0000000000000800 /* Load monitored facilities available */ +#define FSCR_MSGP 0x0000000000000400 /* msgsndp and SPRs available */ +#define FSCR_TAR 0x0000000000000100 /* TAR register available */ +#define FSCR_EBB 0x0000000000000080 /* Event-based branch available */ +#define FSCR_DSCR 0x0000000000000004 /* DSCR available in PR state */ +#define SPR_UAMOR 0x09d /* User Authority Mask Override Register */ +#define SPR_DPDES 0x0b0 /* .6. Directed Privileged Doorbell Exception State Register */ +#define SPR_HFSCR 0xbe /* Hypervisor Facility Status and Control Register */ +#define HFSCR_BHRB 0x0000000000000010 /* BHRB instructions */ +#define HFSCR_PM 0x0000000000000008 /* Performance monitor SPRs */ +#define HFSCR_VECVSX 0x0000000000000002 /* Vector and VSX facilities */ +#define HFSCR_FP 0x0000000000000001 /* Floating Point facility */ +#define SPR_USPRG0 0x100 /* 4.8 User SPR General 0 */ +#define SPR_VRSAVE 0x100 /* .6. AltiVec VRSAVE */ +#define SPR_SPRG0 0x110 /* 468 SPR General 0 */ +#define SPR_SPRG1 0x111 /* 468 SPR General 1 */ +#define SPR_SPRG2 0x112 /* 468 SPR General 2 */ +#define SPR_SPRG3 0x113 /* 468 SPR General 3 */ +#define SPR_SPRG4 0x114 /* 4.8 SPR General 4 */ +#define SPR_SPRG5 0x115 /* 4.8 SPR General 5 */ +#define SPR_SPRG6 0x116 /* 4.8 SPR General 6 */ +#define SPR_SPRG7 0x117 /* 4.8 SPR General 7 */ +#define SPR_SCOMC 0x114 /* ... SCOM Address Register (970) */ +#define SPR_SCOMD 0x115 /* ... SCOM Data Register (970) */ +#define SPR_ASR 0x118 /* ... Address Space Register (PPC64) */ +#define SPR_EAR 0x11a /* .68 External Access Register */ +#define SPR_PVR 0x11f /* 468 Processor Version Register */ +#define MPC601 0x0001 +#define MPC603 0x0003 +#define MPC604 0x0004 +#define MPC602 0x0005 +#define MPC603e 0x0006 +#define MPC603ev 0x0007 +#define MPC750 0x0008 +#define MPC750CL 0x7000 /* Nintendo Wii's Broadway */ +#define MPC604ev 0x0009 +#define MPC7400 0x000c +#define MPC620 0x0014 +#define IBM403 0x0020 +#define IBM401A1 0x0021 +#define IBM401B2 0x0022 +#define IBM401C2 0x0023 +#define IBM401D2 0x0024 +#define IBM401E2 0x0025 +#define IBM401F2 0x0026 +#define IBM401G2 0x0027 +#define IBMRS64II 0x0033 +#define IBMRS64III 0x0034 +#define IBMPOWER4 0x0035 +#define IBMRS64III_2 0x0036 +#define IBMRS64IV 0x0037 +#define IBMPOWER4PLUS 0x0038 +#define IBM970 0x0039 +#define IBMPOWER5 0x003a +#define IBMPOWER5PLUS 0x003b +#define IBM970FX 0x003c +#define IBMPOWER6 0x003e +#define IBMPOWER7 0x003f +#define IBMPOWER3 0x0040 +#define IBMPOWER3PLUS 0x0041 +#define IBM970MP 0x0044 +#define IBM970GX 0x0045 +#define IBMPOWERPCA2 0x0049 +#define IBMPOWER7PLUS 0x004a +#define IBMPOWER8E 0x004b +#define IBMPOWER8NVL 0x004c +#define IBMPOWER8 0x004d +#define IBMPOWER9 0x004e +#define MPC860 0x0050 +#define IBMCELLBE 0x0070 +#define IBMPOWER10 0x0080 +#define MPC8240 0x0081 +#define IBMPOWER11 0x0082 +#define PA6T 0x0090 +#define IBM405GP 0x4011 +#define IBM405L 0x4161 +#define IBM750FX 0x7000 +#define MPC745X_P(v) ((v & 0xFFF8) == 0x8000) +#define MPC7450 0x8000 +#define MPC7455 0x8001 +#define MPC7457 0x8002 +#define MPC7447A 0x8003 +#define MPC7448 0x8004 +#define MPC7410 0x800c +#define MPC8245 0x8081 +#define FSL_E500v1 0x8020 +#define FSL_E500v2 0x8021 +#define FSL_E500mc 0x8023 +#define FSL_E5500 0x8024 +#define FSL_E6500 0x8040 +#define FSL_E300C1 0x8083 +#define FSL_E300C2 0x8084 +#define FSL_E300C3 0x8085 +#define FSL_E300C4 0x8086 + +#define LPCR_PECE_WAKESET (LPCR_PECE_EXT | LPCR_PECE_DECR | LPCR_PECE_ME) + +#define SPR_DBSR 0x130 /* ..8 Debug Status Register */ +#define DBSR_IDE 0x80000000 /* Imprecise debug event. */ +#define DBSR_UDE 0x40000000 /* Unconditional debug event. */ +#define DBSR_MRR 0x30000000 /* Most recent Reset (mask). */ +#define DBSR_ICMP 0x08000000 /* Instr. complete debug event. */ +#define DBSR_BRT 0x04000000 /* Branch taken debug event. */ +#define DBSR_IRPT 0x02000000 /* Interrupt taken debug event. */ +#define DBSR_TRAP 0x01000000 /* Trap instr. debug event. */ +#define DBSR_IAC1 0x00800000 /* Instr. address compare #1. */ +#define DBSR_IAC2 0x00400000 /* Instr. address compare #2. */ +#define DBSR_IAC3 0x00200000 /* Instr. address compare #3. */ +#define DBSR_IAC4 0x00100000 /* Instr. address compare #4. */ +#define DBSR_DAC1R 0x00080000 /* Data addr. read compare #1. */ +#define DBSR_DAC1W 0x00040000 /* Data addr. write compare #1. */ +#define DBSR_DAC2R 0x00020000 /* Data addr. read compare #2. */ +#define DBSR_DAC2W 0x00010000 /* Data addr. write compare #2. */ +#define DBSR_RET 0x00008000 /* Return debug event. */ +#define SPR_EPCR 0x133 +#define EPCR_EXTGS 0x80000000 +#define EPCR_DTLBGS 0x40000000 +#define EPCR_ITLBGS 0x20000000 +#define EPCR_DSIGS 0x10000000 +#define EPCR_ISIGS 0x08000000 +#define EPCR_DUVGS 0x04000000 +#define EPCR_ICM 0x02000000 +#define EPCR_GICMGS 0x01000000 +#define EPCR_DGTMI 0x00800000 +#define EPCR_DMIUH 0x00400000 +#define EPCR_PMGS 0x00200000 +#define SPR_DBCR0 0x134 /* ..8 Debug Control Register 0 */ +#define SPR_DBCR1 0x135 /* ..8 Debug Control Register 1 */ +#define SPR_DBCR2 0x136 /* ..8 Debug Control Register 2 */ +#define SPR_IAC1 0x138 /* ..8 Instruction Address Compare 1 */ +#define SPR_IAC2 0x139 /* ..8 Instruction Address Compare 2 */ +#define SPR_IAC3 0x13a /* ..8 Instruction Address Compare 3 */ +#define SPR_IAC4 0x13b /* ..8 Instruction Address Compare 4 */ + +#define SPR_HSRR0 0x13a +#define SPR_HSRR1 0x13b +#define SPR_DAC1 0x13c /* ..8 Data Address Compare 1 */ +#define SPR_DAC2 0x13d /* ..8 Data Address Compare 2 */ +#define SPR_DVC1 0x13e /* ..8 Data Value Compare 1 */ +#define SPR_DVC2 0x13f /* ..8 Data Value Compare 2 */ + +#define SPR_LPCR 0x13e /* .6. Logical Partitioning Control */ +#define LPCR_LPES 0x008 /* Bit 60 */ +#define LPCR_HVICE 0x002 /* Hypervisor Virtualization Interrupt (Arch 3.0) */ +#define LPCR_ILE (1ULL << 25) /* Interrupt Little-Endian (ISA 2.07) */ +#define LPCR_UPRT (1ULL << 22) /* Use Process Table (ISA 3) */ +#define LPCR_HR (1ULL << 20) /* Host Radix mode */ +#define LPCR_PECE_DRBL (1ULL << 16) /* Directed Privileged Doorbell */ +#define LPCR_PECE_HDRBL (1ULL << 15) /* Directed Hypervisor Doorbell */ +#define LPCR_PECE_EXT (1ULL << 14) /* External exceptions */ +#define LPCR_PECE_DECR (1ULL << 13) /* Decrementer exceptions */ +#define LPCR_PECE_ME (1ULL << 12) /* Machine Check and Hypervisor */ + /* Maintenance exceptions */ +#define SPR_LPID 0x13f /* .6. Logical Partitioning Control */ +#define SPR_HMER 0x150 /* Hypervisor Maintenance Exception Register */ +#define SPR_HMEER 0x151 /* Hypervisor Maintenance Exception Enable Register */ +#define SPR_AMOR 0x15d /* Authority Mask Override Register */ + +#define SPR_TIR 0x1be /* .6. Thread Identification Register */ +#define SPR_PTCR 0x1d0 /* Partition Table Control Register */ +#define SPR_SPEFSCR 0x200 /* ..8 Signal Processing Engine FSCR. */ +#define SPEFSCR_SOVH 0x80000000 +#define SPEFSCR_OVH 0x40000000 +#define SPEFSCR_FGH 0x20000000 +#define SPEFSCR_FXH 0x10000000 +#define SPEFSCR_FINVH 0x08000000 +#define SPEFSCR_FDBZH 0x04000000 +#define SPEFSCR_FUNFH 0x02000000 +#define SPEFSCR_FOVFH 0x01000000 +#define SPEFSCR_FINXS 0x00200000 +#define SPEFSCR_FINVS 0x00100000 +#define SPEFSCR_FDBZS 0x00080000 +#define SPEFSCR_FUNFS 0x00040000 +#define SPEFSCR_FOVFS 0x00020000 +#define SPEFSCR_SOV 0x00008000 +#define SPEFSCR_OV 0x00004000 +#define SPEFSCR_FG 0x00002000 +#define SPEFSCR_FX 0x00001000 +#define SPEFSCR_FINV 0x00000800 +#define SPEFSCR_FDBZ 0x00000400 +#define SPEFSCR_FUNF 0x00000200 +#define SPEFSCR_FOVF 0x00000100 +#define SPEFSCR_FINXE 0x00000040 +#define SPEFSCR_FINVE 0x00000020 +#define SPEFSCR_FDBZE 0x00000010 +#define SPEFSCR_FUNFE 0x00000008 +#define SPEFSCR_FOVFE 0x00000004 +#define SPEFSCR_FRMC_M 0x00000003 +#define SPEFSCR_DFLT (SPEFSCR_FINVE | SPEFSCR_FDBZE | \ + SPEFSCR_FUNFE | SPEFSCR_FOVFE) +#define SPR_IBAT0U 0x210 /* .6. Instruction BAT Reg 0 Upper */ +#define SPR_IBAT0L 0x211 /* .6. Instruction BAT Reg 0 Lower */ +#define SPR_IBAT1U 0x212 /* .6. Instruction BAT Reg 1 Upper */ +#define SPR_IBAT1L 0x213 /* .6. Instruction BAT Reg 1 Lower */ +#define SPR_IBAT2U 0x214 /* .6. Instruction BAT Reg 2 Upper */ +#define SPR_IBAT2L 0x215 /* .6. Instruction BAT Reg 2 Lower */ +#define SPR_IBAT3U 0x216 /* .6. Instruction BAT Reg 3 Upper */ +#define SPR_IBAT3L 0x217 /* .6. Instruction BAT Reg 3 Lower */ +#define SPR_DBAT0U 0x218 /* .6. Data BAT Reg 0 Upper */ +#define SPR_DBAT0L 0x219 /* .6. Data BAT Reg 0 Lower */ +#define SPR_DBAT1U 0x21a /* .6. Data BAT Reg 1 Upper */ +#define SPR_DBAT1L 0x21b /* .6. Data BAT Reg 1 Lower */ +#define SPR_DBAT2U 0x21c /* .6. Data BAT Reg 2 Upper */ +#define SPR_DBAT2L 0x21d /* .6. Data BAT Reg 2 Lower */ +#define SPR_DBAT3U 0x21e /* .6. Data BAT Reg 3 Upper */ +#define SPR_DBAT3L 0x21f /* .6. Data BAT Reg 3 Lower */ +#define SPR_IBAT4U 0x230 /* .6. Instruction BAT Reg 4 Upper */ +#define SPR_DBCR3 0x231 /* ..8 Debug Control Register 3 */ +#define SPR_IBAT4L 0x231 /* .6. Instruction BAT Reg 4 Lower */ +#define SPR_IBAT5U 0x232 /* .6. Instruction BAT Reg 5 Upper */ +#define SPR_IBAT5L 0x233 /* .6. Instruction BAT Reg 5 Lower */ +#define SPR_DBCR4 0x233 /* ..8 Debug Control Register 4 */ +#define SPR_IBAT6U 0x234 /* .6. Instruction BAT Reg 6 Upper */ +#define SPR_DBCR5 0x234 /* ..8 Debug Control Register 5 */ +#define SPR_IBAT6L 0x235 /* .6. Instruction BAT Reg 6 Lower */ +#define SPR_IAC5 0x235 /* ..8 Instruction Address Compare 5 */ +#define SPR_IBAT7U 0x236 /* .6. Instruction BAT Reg 7 Upper */ +#define SPR_IAC6 0x236 /* ..8 Instruction Address Compare 6 */ +#define SPR_IBAT7L 0x237 /* .6. Instruction BAT Reg 7 Lower */ +#define SPR_IAC7 0x237 /* ..8 Instruction Address Compare 7 */ +#define SPR_DBAT4U 0x238 /* .6. Data BAT Reg 4 Upper */ +#define SPR_IAC8 0x238 /* ..8 Instruction Address Compare 8 */ +#define SPR_DBAT4L 0x239 /* .6. Data BAT Reg 4 Lower */ +#define SPR_DBAT5U 0x23a /* .6. Data BAT Reg 5 Upper */ +#define SPR_DBAT5L 0x23b /* .6. Data BAT Reg 5 Lower */ +#define SPR_DBAT6U 0x23c /* .6. Data BAT Reg 6 Upper */ +#define SPR_DBAT6L 0x23d /* .6. Data BAT Reg 6 Lower */ +#define SPR_DBAT7U 0x23e /* .6. Data BAT Reg 7 Upper */ +#define SPR_DBAT7L 0x23f /* .6. Data BAT Reg 7 Lower */ +#define SPR_DBCR6 0x25b /* ..8 Debug Control Register 6 */ +#define SPR_SPRG8 0x25c /* ..8 SPR General 8 */ + +#define SPR_MMCRA 0x312 /* ... Monitor Mode Control Register A */ +#define SPR_PMC1 0x313 /* ... PMC 1 */ +#define SPR_PMC2 0x314 /* ... PMC 2 */ +#define SPR_PMC3 0x315 /* ... PMC 3 */ +#define SPR_PMC4 0x316 /* ... PMC 4 */ +#define SPR_PMC5 0x317 /* ... PMC 5 */ +#define SPR_PMC6 0x318 /* ... PMC 6 */ +#define SPR_PMC7 0x319 /* ... PMC 7 */ +#define SPR_PMC8 0x31a /* ... PMC 8 */ + +#define SPR_MMCR0 0x31b /* ... Monitor Mode Control Register 0 */ +#define SPR_MMCR0_FC 0x80000000 /* Freeze counters */ +#define SPR_MMCR0_FCS 0x40000000 /* Freeze counters in supervisor mode */ +#define SPR_MMCR0_FCP 0x20000000 /* Freeze counters in user mode */ +#define SPR_MMCR0_FCM1 0x10000000 /* Freeze counters when mark=1 */ +#define SPR_MMCR0_FCM0 0x08000000 /* Freeze counters when mark=0 */ +#define SPR_MMCR0_PMXE 0x04000000 /* Enable PM interrupt */ +#define SPR_MMCR0_PMAE 0x04000000 /* PM Alert Enable */ +#define SPR_MMCR0_FCECE 0x02000000 /* Freeze counters after event */ +#define SPR_MMCR0_TBSEL_15 0x01800000 /* Count bit 15 of TBL */ +#define SPR_MMCR0_TBSEL_19 0x01000000 /* Count bit 19 of TBL */ +#define SPR_MMCR0_TBSEL_23 0x00800000 /* Count bit 23 of TBL */ +#define SPR_MMCR0_TBSEL_31 0x00000000 /* Count bit 31 of TBL */ +#define SPR_MMCR0_TBEE 0x00400000 /* Time-base event enable */ +#define SPR_MMCR0_THRESHOLD(x) ((x) << 16) /* Threshold value */ +#define SPR_MMCR0_PMC1CE 0x00008000 /* PMC1 condition enable */ +#define SPR_MMCR0_PMCNCE 0x00004000 /* PMCn condition enable */ +#define SPR_MMCR0_TRIGGER 0x00002000 /* Trigger */ +#define SPR_MMCR0_PMAO 0x00000080 /* PM Alert Occurred */ +#define SPR_MMCR0_FCPC 0x00001000 /* Freeze Counters in Problem State Cond. */ +#define SPR_MMCR0_FC56 0x00000010 /* Freeze Counters 5-6 */ +#define SPR_MMCR0_PMC1SEL(x) ((x) << 8) /* PMC1 selector (970) */ +#define SPR_MMCR0_PMC2SEL(x) ((x) << 1) /* PMC2 selector (970) */ +#define SPR_MMCR0_74XX_PMC1SEL(x) (((x) & 0x3f) << 6) /* PMC1 selector */ +#define SPR_MMCR0_74XX_PMC2SEL(x) (((x) & 0x3f) << 0) /* PMC2 selector */ + +#define SPR_MMCR1 0x31e /* ... Monitor Mode Control Register 1 */ +#define SPR_MMCR1_PMC3SEL(x) (((x) & 0x1f) << 27) /* PMC 3 selector */ +#define SPR_MMCR1_PMC4SEL(x) (((x) & 0x1f) << 22) /* PMC 4 selector */ +#define SPR_MMCR1_PMC5SEL(x) (((x) & 0x1f) << 17) /* PMC 5 selector */ +#define SPR_MMCR1_PMC6SEL(x) (((x) & 0x1f) << 12) /* PMC 6 selector */ +#define SPR_MMCR1_74XX_PMC6SEL(x) (((x) & 0x3f) << 11) /* PMC 6 selector */ +#define SPR_MMCR1_PMC7SEL(x) (((x) & 0x1f) << 7) /* PMC 7 selector */ +#define SPR_MMCR1_PMC8SEL(x) (((x) & 0x1f) << 2) /* PMC 8 selector */ +#define SPR_MMCR1_P8_PMCSEL_ALL 0xffffffff +#define SPR_MMCR1_P8_PMCNSEL_MASK(n) (0xffUL << ((3-(n))*8)) +#define SPR_MMCR1_P8_PMCNSEL(n, v) ((unsigned long)(v) << ((3-(n))*8)) + +#define SPR_MMCR2 0x311 +#define SPR_MMCR2_CNBIT(n, bit) ((bit) << (((5 - (n)) * 9) + 10)) +#define SPR_MMCR2_FCNS(n) SPR_MMCR2_CNBIT(n, 0x100ULL) +#define SPR_MMCR2_FCNP0(n) SPR_MMCR2_CNBIT(n, 0x080ULL) +#define SPR_MMCR2_FCNP1(n) SPR_MMCR2_CNBIT(n, 0x040ULL) +#define SPR_MMCR2_FCNM1(n) SPR_MMCR2_CNBIT(n, 0x020ULL) +#define SPR_MMCR2_FCNM0(n) SPR_MMCR2_CNBIT(n, 0x010ULL) +#define SPR_MMCR2_FCNWAIT(n) SPR_MMCR2_CNBIT(n, 0x008ULL) +#define SPR_MMCR2_FCNH(n) SPR_MMCR2_CNBIT(n, 0x004ULL) +/* Freeze Counter N in Hypervisor/Supervisor/Problem states */ +#define SPR_MMCR2_FCNHSP(n) \ + (SPR_MMCR2_FCNS(n) | SPR_MMCR2_FCNP0(n) | \ + SPR_MMCR2_FCNP1(n) | SPR_MMCR2_FCNH(n)) + +#define SPR_M_TWB 0x31c /* ..8 MMU tablewalk base */ +#define M_TWB_L1TB 0xfffff000 /* level-1 translation base */ +#define M_TWB_L1INDX 0x00000ffc /* level-1 index */ +#define SPR_MD_TWC 0x31d /* ..8 DMMU tablewalk control */ +#define SPR_MD_RPN 0x31e /* ..8 DMMU real (phys) page number */ +#define SPR_MD_TW 0x31f /* ..8 MMU tablewalk scratch */ +#define SPR_BESCRS 0x320 /* .6. Branch Event Status and Control Set Register */ +#define SPR_BESCRSU 0x321 /* .6. Branch Event Status and Control Set Register (upper 32-bit) */ +#define SPR_BESCRR 0x322 /* .6. Branch Event Status and Control Reset Register */ +#define SPR_BESCRRU 0x323 /* .6. Branch Event Status and Control Register (upper 32-bit) */ +#define SPR_EBBHR 0x324 /* .6. Event-based Branch Handler Register */ +#define SPR_EBBRR 0x325 /* .6. Event-based Branch Return Register */ +#define SPR_BESCR 0x326 /* .6. Branch Event Status and Control Register */ +#define SPR_LMRR 0x32d /* .6. Load Monitored Region Register */ +#define SPR_LMSER 0x32e /* .6. Load Monitored Section Enable Register */ +#define SPR_TAR 0x32f /* .6. Branch Target Address Register */ +#define SPR_MI_CAM 0x330 /* ..8 IMMU CAM entry read */ +#define SPR_MI_RAM0 0x331 /* ..8 IMMU RAM entry read reg 0 */ +#define SPR_MI_RAM1 0x332 /* ..8 IMMU RAM entry read reg 1 */ +#define SPR_MD_CAM 0x338 /* ..8 IMMU CAM entry read */ +#define SPR_MD_RAM0 0x339 /* ..8 IMMU RAM entry read reg 0 */ +#define SPR_MD_RAM1 0x33a /* ..8 IMMU RAM entry read reg 1 */ +#define SPR_PSSCR 0x357 /* Processor Stop Status and Control Register (ISA 3.0) */ +#define PSSCR_PLS_S 60 +#define PSSCR_PLS_M (0xf << PSSCR_PLS_S) +#define PSSCR_SD (1 << 22) +#define PSSCR_ESL (1 << 21) +#define PSSCR_EC (1 << 20) +#define PSSCR_PSLL_S 16 +#define PSSCR_PSLL_M (0xf << PSSCR_PSLL_S) +#define PSSCR_TR_S 8 +#define PSSCR_TR_M (0x3 << PSSCR_TR_S) +#define PSSCR_MTL_S 4 +#define PSSCR_MTL_M (0xf << PSSCR_MTL_S) +#define PSSCR_RL_S 0 +#define PSSCR_RL_M (0xf << PSSCR_RL_S) +#define SPR_PMCR 0x374 /* Processor Management Control Register */ +#define SPR_UMMCR2 0x3a0 /* .6. User Monitor Mode Control Register 2 */ +#define SPR_UMMCR0 0x3a8 /* .6. User Monitor Mode Control Register 0 */ +#define SPR_USIA 0x3ab /* .6. User Sampled Instruction Address */ +#define SPR_UMMCR1 0x3ac /* .6. User Monitor Mode Control Register 1 */ +#define SPR_MMCR2_74XX 0x3b0 /* .6. Monitor Mode Control Register 2 */ +#define SPR_MMCR2_74XX_THRESHMULT_32 0x80000000 /* Multiply MMCR0 threshold by 32 */ +#define SPR_MMCR2_74XX_THRESHMULT_2 0x00000000 /* Multiply MMCR0 threshold by 2 */ +#define SPR_PMC5_74XX 0x3b1 /* .6. Performance Counter Register 5 */ +#define SPR_PMC6_74XX 0x3b2 /* .6. Performance Counter Register 6 */ +#define SPR_MMCR0_74XX 0x3b8 /* .6. Monitor Mode Control Register 0 */ +#define SPR_PMC1_74XX 0x3b9 /* .6. Performance Counter Register 1 */ +#define SPR_PMC2_74XX 0x3ba /* .6. Performance Counter Register 2 */ +#define SPR_SIA 0x3bb /* .6. Sampled Instruction Address */ +#define SPR_MMCR1_74XX 0x3bc /* .6. Monitor Mode Control Register 2 */ + +#define SPR_PMC3_74XX 0x3bd /* .6. Performance Counter Register 3 */ +#define SPR_PMC4_74XX 0x3be /* .6. Performance Counter Register 4 */ +#define SPR_DMISS 0x3d0 /* .68 Data TLB Miss Address Register */ +#define SPR_DCMP 0x3d1 /* .68 Data TLB Compare Register */ +#define SPR_HASH1 0x3d2 /* .68 Primary Hash Address Register */ +#define SPR_HASH2 0x3d3 /* .68 Secondary Hash Address Register */ +#define SPR_IMISS 0x3d4 /* .68 Instruction TLB Miss Address Register */ +#define SPR_TLBMISS 0x3d4 /* .6. TLB Miss Address Register */ +#define SPR_DEAR 0x03d /* ..8 Data Exception Address Register */ +#define SPR_ICMP 0x3d5 /* .68 Instruction TLB Compare Register */ +#define SPR_PTEHI 0x3d5 /* .6. Instruction TLB Compare Register */ +#define SPR_RPA 0x3d6 /* .68 Required Physical Address Register */ +#define SPR_PTELO 0x3d6 /* .6. Required Physical Address Register */ + +#define SPR_TSR 0x150 /* ..8 Timer Status Register */ +#define SPR_TCR 0x154 /* ..8 Timer Control Register */ + +#define TSR_ENW 0x80000000 /* Enable Next Watchdog */ +#define TSR_WIS 0x40000000 /* Watchdog Interrupt Status */ +#define TSR_WRS_MASK 0x30000000 /* Watchdog Reset Status */ +#define TSR_WRS_NONE 0x00000000 /* No watchdog reset has occurred */ +#define TSR_WRS_CORE 0x10000000 /* Core reset was forced by the watchdog */ +#define TSR_WRS_CHIP 0x20000000 /* Chip reset was forced by the watchdog */ +#define TSR_WRS_SYSTEM 0x30000000 /* System reset was forced by the watchdog */ +#define TSR_PIS 0x08000000 /* PIT Interrupt Status */ +#define TSR_DIS 0x08000000 /* Decrementer Interrupt Status */ +#define TSR_FIS 0x04000000 /* FIT Interrupt Status */ + +#define TCR_WP_MASK 0xc0000000 /* Watchdog Period mask */ +#define TCR_WP_2_17 0x00000000 /* 2**17 clocks */ +#define TCR_WP_2_21 0x40000000 /* 2**21 clocks */ +#define TCR_WP_2_25 0x80000000 /* 2**25 clocks */ +#define TCR_WP_2_29 0xc0000000 /* 2**29 clocks */ +#define TCR_WRC_MASK 0x30000000 /* Watchdog Reset Control mask */ +#define TCR_WRC_NONE 0x00000000 /* No watchdog reset */ +#define TCR_WRC_CORE 0x10000000 /* Core reset */ +#define TCR_WRC_CHIP 0x20000000 /* Chip reset */ +#define TCR_WRC_SYSTEM 0x30000000 /* System reset */ +#define TCR_WIE 0x08000000 /* Watchdog Interrupt Enable */ +#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ +#define TCR_DIE 0x04000000 /* Pecrementer Interrupt Enable */ +#define TCR_FP_MASK 0x03000000 /* FIT Period */ +#define TCR_FP_2_9 0x00000000 /* 2**9 clocks */ +#define TCR_FP_2_13 0x01000000 /* 2**13 clocks */ +#define TCR_FP_2_17 0x02000000 /* 2**17 clocks */ +#define TCR_FP_2_21 0x03000000 /* 2**21 clocks */ +#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ +#define TCR_ARE 0x00400000 /* Auto Reload Enable */ + +#define SPR_HID0 0x3f0 /* ..8 Hardware Implementation Register 0 */ +#define SPR_HID1 0x3f1 /* ..8 Hardware Implementation Register 1 */ +#define SPR_HID2 0x3f3 /* ..8 Hardware Implementation Register 2 */ +#define SPR_HID4 0x3f4 /* ..8 Hardware Implementation Register 4 */ +#define SPR_HID5 0x3f6 /* ..8 Hardware Implementation Register 5 */ +#define SPR_HID6 0x3f9 /* ..8 Hardware Implementation Register 6 */ + +#define SPR_CELL_TSRL 0x380 /* ... Cell BE Thread Status Register */ +#define SPR_CELL_TSCR 0x399 /* ... Cell BE Thread Switch Register */ + +#if defined(AIM) +#define SPR_PIR 0x3ff /* .6. Processor Identification Register */ +#elif defined(BOOKE) +#define SPR_PIR 0x11e /* ..8 Processor Identification Register */ +#endif + +#define DBCR0_EDM 0x80000000 /* External Debug Mode */ +#define DBCR0_IDM 0x40000000 /* Internal Debug Mode */ +#define DBCR0_RST_MASK 0x30000000 /* ReSeT */ +#define DBCR0_RST_NONE 0x00000000 /* No action */ +#define DBCR0_RST_CORE 0x10000000 /* Core reset */ +#define DBCR0_RST_CHIP 0x20000000 /* Chip reset */ +#define DBCR0_RST_SYSTEM 0x30000000 /* System reset */ +#define DBCR0_IC 0x08000000 /* Instruction Completion debug event */ +#define DBCR0_BT 0x04000000 /* Branch Taken debug event */ +#define DBCR0_EDE 0x02000000 /* Exception Debug Event */ +#define DBCR0_TDE 0x01000000 /* Trap Debug Event */ +#define DBCR0_IA1 0x00800000 /* IAC (Instruction Address Compare) 1 debug event */ +#define DBCR0_IA2 0x00400000 /* IAC 2 debug event */ +#define DBCR0_IA12 0x00200000 /* Instruction Address Range Compare 1-2 */ +#define DBCR0_IA12X 0x00100000 /* IA12 eXclusive */ +#define DBCR0_IA3 0x00080000 /* IAC 3 debug event */ +#define DBCR0_IA4 0x00040000 /* IAC 4 debug event */ +#define DBCR0_IA34 0x00020000 /* Instruction Address Range Compare 3-4 */ +#define DBCR0_IA34X 0x00010000 /* IA34 eXclusive */ +#define DBCR0_IA12T 0x00008000 /* Instruction Address Range Compare 1-2 range Toggle */ +#define DBCR0_IA34T 0x00004000 /* Instruction Address Range Compare 3-4 range Toggle */ +#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ + +#define SPR_IABR 0x3f2 /* ..8 Instruction Address Breakpoint Register 0 */ +#define SPR_DABR 0x3f5 /* .6. Data Address Breakpoint Register */ +#define SPR_MSSCR0 0x3f6 /* .6. Memory SubSystem Control Register */ +#define MSSCR0_SHDEN 0x80000000 /* 0: Shared-state enable */ +#define MSSCR0_SHDPEN3 0x40000000 /* 1: ~SHD[01] signal enable in MEI mode */ +#define MSSCR0_L1INTVEN 0x38000000 /* 2-4: L1 data cache ~HIT intervention enable */ +#define MSSCR0_L2INTVEN 0x07000000 /* 5-7: L2 data cache ~HIT intervention enable*/ +#define MSSCR0_DL1HWF 0x00800000 /* 8: L1 data cache hardware flush */ +#define MSSCR0_MBO 0x00400000 /* 9: must be one */ +#define MSSCR0_EMODE 0x00200000 /* 10: MPX bus mode (read-only) */ +#define MSSCR0_ABD 0x00100000 /* 11: address bus driven (read-only) */ +#define MSSCR0_MBZ 0x000fffff /* 12-31: must be zero */ +#define MSSCR0_L2PFE 0x00000003 /* 30-31: L2 prefetch enable */ +#define SPR_MSSSR0 0x3f7 /* .6. Memory Subsystem Status Register (MPC745x) */ +#define MSSSR0_L2TAG 0x00040000 /* 13: L2 tag parity error */ +#define MSSSR0_L2DAT 0x00020000 /* 14: L2 data parity error */ +#define MSSSR0_L3TAG 0x00010000 /* 15: L3 tag parity error */ +#define MSSSR0_L3DAT 0x00008000 /* 16: L3 data parity error */ +#define MSSSR0_APE 0x00004000 /* 17: Address parity error */ +#define MSSSR0_DPE 0x00002000 /* 18: Data parity error */ +#define MSSSR0_TEA 0x00001000 /* 19: Bus transfer error acknowledge */ +#define SPR_LDSTCR 0x3f8 /* .6. Load/Store Control Register */ +#define SPR_L2PM 0x3f8 /* .6. L2 Private Memory Control Register */ +#define SPR_L2CR 0x3f9 /* .6. L2 Control Register */ +#define L2CR_L2E 0x80000000 /* 0: L2 enable */ +#define L2CR_L2PE 0x40000000 /* 1: L2 data parity enable */ +#define L2CR_L2SIZ 0x30000000 /* 2-3: L2 size */ +#define L2SIZ_2M 0x00000000 +#define L2SIZ_256K 0x10000000 +#define L2SIZ_512K 0x20000000 +#define L2SIZ_1M 0x30000000 +#define L2CR_L2CLK 0x0e000000 /* 4-6: L2 clock ratio */ +#define L2CLK_DIS 0x00000000 /* disable L2 clock */ +#define L2CLK_10 0x02000000 /* core clock / 1 */ +#define L2CLK_15 0x04000000 /* / 1.5 */ +#define L2CLK_20 0x08000000 /* / 2 */ +#define L2CLK_25 0x0a000000 /* / 2.5 */ +#define L2CLK_30 0x0c000000 /* / 3 */ +#define L2CR_L2RAM 0x01800000 /* 7-8: L2 RAM type */ +#define L2RAM_FLOWTHRU_BURST 0x00000000 +#define L2RAM_PIPELINE_BURST 0x01000000 +#define L2RAM_PIPELINE_LATE 0x01800000 +#define L2CR_L2DO 0x00400000 /* 9: L2 data-only. + Setting this bit disables instruction + caching. */ +#define L2CR_L2I 0x00200000 /* 10: L2 global invalidate. */ +#define L2CR_L2IO_7450 0x00010000 /* 11: L2 instruction-only (MPC745x). */ +#define L2CR_L2CTL 0x00100000 /* 11: L2 RAM control (ZZ enable). + Enables automatic operation of the + L2ZZ (low-power mode) signal. */ +#define L2CR_L2WT 0x00080000 /* 12: L2 write-through. */ +#define L2CR_L2TS 0x00040000 /* 13: L2 test support. */ +#define L2CR_L2OH 0x00030000 /* 14-15: L2 output hold. */ +#define L2CR_L2DO_7450 0x00010000 /* 15: L2 data-only (MPC745x). */ +#define L2CR_L2SL 0x00008000 /* 16: L2 DLL slow. */ +#define L2CR_L2DF 0x00004000 /* 17: L2 differential clock. */ +#define L2CR_L2BYP 0x00002000 /* 18: L2 DLL bypass. */ +#define L2CR_L2FA 0x00001000 /* 19: L2 flush assist (for software flush). */ +#define L2CR_L2HWF 0x00000800 /* 20: L2 hardware flush. */ +#define L2CR_L2IO 0x00000400 /* 21: L2 instruction-only. */ +#define L2CR_L2CLKSTP 0x00000200 /* 22: L2 clock stop. */ +#define L2CR_L2DRO 0x00000100 /* 23: L2DLL rollover checkstop enable. */ +#define L2CR_L2IP 0x00000001 /* 31: L2 global invalidate in */ + /* progress (read only). */ +#define SPR_L3CR 0x3fa /* .6. L3 Control Register */ +#define L3CR_L3E 0x80000000 /* 0: L3 enable */ +#define L3CR_L3PE 0x40000000 /* 1: L3 data parity enable */ +#define L3CR_L3APE 0x20000000 +#define L3CR_L3SIZ 0x10000000 /* 3: L3 size (0=1MB, 1=2MB) */ +#define L3CR_L3CLKEN 0x08000000 /* 4: Enables L3_CLK[0:1] */ +#define L3CR_L3CLK 0x03800000 +#define L3CR_L3IO 0x00400000 +#define L3CR_L3CLKEXT 0x00200000 +#define L3CR_L3CKSPEXT 0x00100000 +#define L3CR_L3OH1 0x00080000 +#define L3CR_L3SPO 0x00040000 +#define L3CR_L3CKSP 0x00030000 +#define L3CR_L3PSP 0x0000e000 +#define L3CR_L3REP 0x00001000 +#define L3CR_L3HWF 0x00000800 +#define L3CR_L3I 0x00000400 /* 21: L3 global invalidate */ +#define L3CR_L3RT 0x00000300 +#define L3CR_L3NIRCA 0x00000080 +#define L3CR_L3DO 0x00000040 +#define L3CR_PMEN 0x00000004 +#define L3CR_PMSIZ 0x00000003 + +#define SPR_THRM1 0x3fc /* .6. Thermal Management Register */ +#define SPR_THRM2 0x3fd /* .6. Thermal Management Register */ +#define SPR_THRM_TIN 0x80000000 /* Thermal interrupt bit (RO) */ +#define SPR_THRM_TIV 0x40000000 /* Thermal interrupt valid (RO) */ +#define SPR_THRM_THRESHOLD(x) ((x) << 23) /* Thermal sensor threshold */ +#define SPR_THRM_TID 0x00000004 /* Thermal interrupt direction */ +#define SPR_THRM_TIE 0x00000002 /* Thermal interrupt enable */ +#define SPR_THRM_VALID 0x00000001 /* Valid bit */ +#define SPR_THRM3 0x3fe /* .6. Thermal Management Register */ +#define SPR_THRM_TIMER(x) ((x) << 1) /* Sampling interval timer */ +#define SPR_THRM_ENABLE 0x00000001 /* TAU Enable */ +#define SPR_FPECR 0x3fe /* .6. Floating-Point Exception Cause Register */ + +/* Time Base Register declarations */ +#define TBR_TBL 0x10c /* 468 Time Base Lower - read */ +#define TBR_TBU 0x10d /* 468 Time Base Upper - read */ +#define TBR_TBWL 0x11c /* 468 Time Base Lower - supervisor, write */ +#define TBR_TBWU 0x11d /* 468 Time Base Upper - supervisor, write */ + +/* Performance counter declarations */ +#define PMC_OVERFLOW 0x80000000 /* Counter has overflowed */ + +/* The first five countable [non-]events are common to many PMC's */ +#define PMCN_NONE 0 /* Count nothing */ +#define PMCN_CYCLES 1 /* Processor cycles */ +#define PMCN_ICOMP 2 /* Instructions completed */ +#define PMCN_TBLTRANS 3 /* TBL bit transitions */ +#define PCMN_IDISPATCH 4 /* Instructions dispatched */ + +/* Similar things for the 970 PMC direct counters */ +#define PMC970N_NONE 0x8 /* Count nothing */ +#define PMC970N_CYCLES 0xf /* Processor cycles */ +#define PMC970N_ICOMP 0x9 /* Instructions completed */ + +#if defined(BOOKE) + +#define SPR_MCARU 0x239 /* ..8 Machine Check Address register upper bits */ +#define SPR_MCSR 0x23c /* ..8 Machine Check Syndrome register */ +#define MCSR_MCP 0x80000000 /* Machine check input signal to core */ +#define MCSR_L2MMU_MHIT 0x08000000 /* L2 MMU simultaneous hit */ +#define MCSR_NMI 0x00100000 /* Non-maskable interrupt */ +#define MCSR_MAV 0x00080000 /* MCAR address valid */ +#define MCSR_MEA 0x00040000 /* MCAR effective address */ +#define MCSR_IF 0x00010000 /* Instruction fetch error report */ +#define MCSR_LD 0x00008000 /* Load instruction error report */ +#define MCSR_ST 0x00004000 /* Store instruction error report */ +#define MCSR_LDG 0x00002000 /* Guarded load instruction error report */ +#define MCSR_TLBSYNC 0x00000002 /* Simultaneous TLBSYNC detected */ +#define SPR_MCAR 0x23d /* ..8 Machine Check Address register */ + +#define SPR_ESR 0x003e /* ..8 Exception Syndrome Register */ +#define ESR_PIL 0x08000000 /* Program interrupt - illegal */ +#define ESR_PPR 0x04000000 /* Program interrupt - privileged */ +#define ESR_PTR 0x02000000 /* Program interrupt - trap */ +#define ESR_ST 0x00800000 /* Store operation */ +#define ESR_DLK 0x00200000 /* Data storage, D cache locking */ +#define ESR_ILK 0x00100000 /* Data storage, I cache locking */ +#define ESR_BO 0x00020000 /* Data/instruction storage, byte ordering */ +#define ESR_SPE 0x00000080 /* SPE exception bit */ + +#define SPR_CSRR0 0x03a /* ..8 58 Critical SRR0 */ +#define SPR_CSRR1 0x03b /* ..8 59 Critical SRR1 */ +#define SPR_MCSRR0 0x23a /* ..8 570 Machine check SRR0 */ +#define SPR_MCSRR1 0x23b /* ..8 571 Machine check SRR1 */ +#define SPR_DSRR0 0x23e /* ..8 574 Debug SRR0<E.ED> */ +#define SPR_DSRR1 0x23f /* ..8 575 Debug SRR1<E.ED> */ + +#define SPR_MMUCSR0 0x3f4 /* ..8 1012 MMU Control and Status Register 0 */ +#define MMUCSR0_L2TLB0_FI 0x04 /* TLB0 flash invalidate */ +#define MMUCSR0_L2TLB1_FI 0x02 /* TLB1 flash invalidate */ + +#define SPR_SVR 0x3ff /* ..8 1023 System Version Register */ +#define SVR_MPC8533 0x8034 +#define SVR_MPC8533E 0x803c +#define SVR_MPC8541 0x8072 +#define SVR_MPC8541E 0x807a +#define SVR_MPC8548 0x8031 +#define SVR_MPC8548E 0x8039 +#define SVR_MPC8555 0x8071 +#define SVR_MPC8555E 0x8079 +#define SVR_MPC8572 0x80e0 +#define SVR_MPC8572E 0x80e8 +#define SVR_P1011 0x80e5 +#define SVR_P1011E 0x80ed +#define SVR_P1013 0x80e7 +#define SVR_P1013E 0x80ef +#define SVR_P1020 0x80e4 +#define SVR_P1020E 0x80ec +#define SVR_P1022 0x80e6 +#define SVR_P1022E 0x80ee +#define SVR_P2010 0x80e3 +#define SVR_P2010E 0x80eb +#define SVR_P2020 0x80e2 +#define SVR_P2020E 0x80ea +#define SVR_P2041 0x8210 +#define SVR_P2041E 0x8218 +#define SVR_P3041 0x8211 +#define SVR_P3041E 0x8219 +#define SVR_P4040 0x8200 +#define SVR_P4040E 0x8208 +#define SVR_P4080 0x8201 +#define SVR_P4080E 0x8209 +#define SVR_P5010 0x8221 +#define SVR_P5010E 0x8229 +#define SVR_P5020 0x8220 +#define SVR_P5020E 0x8228 +#define SVR_P5021 0x8205 +#define SVR_P5021E 0x820d +#define SVR_P5040 0x8204 +#define SVR_P5040E 0x820c +#define SVR_VER(svr) (((svr) >> 16) & 0xffff) + +#define SPR_PID0 0x030 /* ..8 Process ID Register 0 */ +#define SPR_PID1 0x279 /* ..8 Process ID Register 1 */ +#define SPR_PID2 0x27a /* ..8 Process ID Register 2 */ + +#define SPR_TLB0CFG 0x2B0 /* ..8 TLB 0 Config Register */ +#define SPR_TLB1CFG 0x2B1 /* ..8 TLB 1 Config Register */ +#define TLBCFG_ASSOC_MASK 0xff000000 /* Associativity of TLB */ +#define TLBCFG_ASSOC_SHIFT 24 +#define TLBCFG_NENTRY_MASK 0x00000fff /* Number of entries in TLB */ + +#define SPR_IVPR 0x03f /* ..8 Interrupt Vector Prefix Register */ +#define SPR_IVOR0 0x190 /* ..8 Critical input */ +#define SPR_IVOR1 0x191 /* ..8 Machine check */ +#define SPR_IVOR2 0x192 +#define SPR_IVOR3 0x193 +#define SPR_IVOR4 0x194 +#define SPR_IVOR5 0x195 +#define SPR_IVOR6 0x196 +#define SPR_IVOR7 0x197 +#define SPR_IVOR8 0x198 +#define SPR_IVOR9 0x199 +#define SPR_IVOR10 0x19a +#define SPR_IVOR11 0x19b +#define SPR_IVOR12 0x19c +#define SPR_IVOR13 0x19d +#define SPR_IVOR14 0x19e +#define SPR_IVOR15 0x19f +#define SPR_IVOR32 0x210 +#define SPR_IVOR33 0x211 +#define SPR_IVOR34 0x212 +#define SPR_IVOR35 0x213 + +#define SPR_MAS0 0x270 /* ..8 MMU Assist Register 0 Book-E/e500 */ +#define SPR_MAS1 0x271 /* ..8 MMU Assist Register 1 Book-E/e500 */ +#define SPR_MAS2 0x272 /* ..8 MMU Assist Register 2 Book-E/e500 */ +#define SPR_MAS3 0x273 /* ..8 MMU Assist Register 3 Book-E/e500 */ +#define SPR_MAS4 0x274 /* ..8 MMU Assist Register 4 Book-E/e500 */ +#define SPR_MAS5 0x275 /* ..8 MMU Assist Register 5 Book-E */ +#define SPR_MAS6 0x276 /* ..8 MMU Assist Register 6 Book-E/e500 */ +#define SPR_MAS7 0x3B0 /* ..8 MMU Assist Register 7 Book-E/e500 */ +#define SPR_MAS8 0x155 /* ..8 MMU Assist Register 8 Book-E/e500 */ + +#define SPR_L1CFG0 0x203 /* ..8 L1 cache configuration register 0 */ +#define SPR_L1CFG1 0x204 /* ..8 L1 cache configuration register 1 */ + +#define SPR_CCR1 0x378 +#define CCR1_L2COBE 0x00000040 + +#define DCR_L2DCDCRAI 0x0000 /* L2 D-Cache DCR Address Pointer */ +#define DCR_L2DCDCRDI 0x0001 /* L2 D-Cache DCR Data Indirect */ +#define DCR_L2CR0 0x00 /* L2 Cache Configuration Register 0 */ +#define L2CR0_AS 0x30000000 + +#define SPR_L1CSR0 0x3F2 /* ..8 L1 Cache Control and Status Register 0 */ +#define L1CSR0_DCPE 0x00010000 /* Data Cache Parity Enable */ +#define L1CSR0_DCLFR 0x00000100 /* Data Cache Lock Bits Flash Reset */ +#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ +#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ +#define SPR_L1CSR1 0x3F3 /* ..8 L1 Cache Control and Status Register 1 */ +#define L1CSR1_ICPE 0x00010000 /* Instruction Cache Parity Enable */ +#define L1CSR1_ICUL 0x00000400 /* Instr Cache Unable to Lock */ +#define L1CSR1_ICLFR 0x00000100 /* Instruction Cache Lock Bits Flash Reset */ +#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ +#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ + +#define SPR_L2CFG0 0x207 /* ..8 L2 Configuration Register 0 */ +#define SPR_L2CSR0 0x3F9 /* ..8 L2 Cache Control and Status Register 0 */ +#define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */ +#define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity Enable */ +#define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */ +#define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flags Clear */ + +#define SPR_BUCSR 0x3F5 /* ..8 Branch Unit Control and Status Register */ +#define BUCSR_BPEN 0x00000001 /* Branch Prediction Enable */ +#define BUCSR_BBFI 0x00000200 /* Branch Buffer Flash Invalidate */ + +#endif /* BOOKE */ +#endif /* !_POWERPC_SPR_H_ */ diff --git a/sys/powerpc/include/sr.h b/sys/powerpc/include/sr.h new file mode 100644 index 000000000000..d5fa2610d4e4 --- /dev/null +++ b/sys/powerpc/include/sr.h @@ -0,0 +1,62 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (C) 2002 Benno Rice. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _MACHINE_SR_H_ +#define _MACHINE_SR_H_ + +/* + * Bit definitions for segment registers. + * + * PowerPC Microprocessor Family: The Programming Environments for 32-bit + * Microprocessors, section 2.3.5 + */ + +#define SR_TYPE 0x80000000 /* Type selector */ +#define SR_KS 0x40000000 /* Supervisor-state protection key */ +#define SR_KP 0x20000000 /* User-state protection key */ +#define SR_N 0x10000000 /* No-execute protection */ +#define SR_VSID_MASK 0x00ffffff /* Virtual Segment ID mask */ + +/* Kernel segment register usage */ +#define USER_SR 12 +#define KERNEL_SR 13 +#define KERNEL2_SR 14 +#define KERNEL3_SR 15 +#define KERNEL_VSIDBITS 0xfffffUL +#define KERNEL_SEGMENT (0xfffff0 + KERNEL_SR) +#define KERNEL2_SEGMENT (0xfffff0 + KERNEL2_SR) +#define EMPTY_SEGMENT 0xfffff0 +#ifdef __powerpc64__ +#define USER_ADDR 0xc00ffffff0000000UL +#else +#define USER_ADDR ((uintptr_t)USER_SR << ADDR_SR_SHFT) +#endif +#define SEGMENT_LENGTH 0x10000000UL +#define SEGMENT_INVMASK 0x0fffffffUL +#define SEGMENT_MASK ~SEGMENT_INVMASK + +#endif /* !_MACHINE_SR_H_ */ diff --git a/sys/powerpc/include/stack.h b/sys/powerpc/include/stack.h new file mode 100644 index 000000000000..2904c36fe208 --- /dev/null +++ b/sys/powerpc/include/stack.h @@ -0,0 +1,54 @@ +/*- + * Mach Operating System + * Copyright (c) 1992 Carnegie Mellon University + * All Rights Reserved. + * + * Permission to use, copy, modify and distribute this software and its + * documentation is hereby granted, provided that both the copyright + * notice and this permission notice appear in all copies of the + * software, derivative works or modified versions, and any portions + * thereof, and that both notices appear in supporting documentation. + * + * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" + * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR + * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. + * + * Carnegie Mellon requests users of this software to return to + * + * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU + * School of Computer Science + * Carnegie Mellon University + * Pittsburgh PA 15213-3890 + * + * any improvements or extensions that they make and grant Carnegie Mellon + * the rights to redistribute these changes. + */ + +#ifndef _MACHINE_STACK_H_ +#define _MACHINE_STACK_H_ + +extern int trapexit[]; +extern int asttrapexit[]; +extern int end[]; + +#ifdef _SYS_PROC_H_ + +#include <machine/pcb.h> + +/* Get the current kernel thread stack usage. */ +#define GET_STACK_USAGE(total, used) do { \ + struct thread *td = curthread; \ + (total) = td->td_kstack_pages * PAGE_SIZE - sizeof(struct pcb); \ + (used) = td->td_kstack + (total) - (vm_offset_t)&td; \ +} while (0) + +static __inline bool +kstack_contains(struct thread *td, vm_offset_t va, size_t len) +{ + return (va >= td->td_kstack && va + len >= va && + va + len <= td->td_kstack + td->td_kstack_pages * PAGE_SIZE - + sizeof(struct pcb)); +} +#endif /* _SYS_PROC_H_ */ + +#endif /* !_MACHINE_STACK_H_ */ diff --git a/sys/powerpc/include/stdarg.h b/sys/powerpc/include/stdarg.h new file mode 100644 index 000000000000..aba008ef3774 --- /dev/null +++ b/sys/powerpc/include/stdarg.h @@ -0,0 +1,37 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2017 Poul-Henning Kamp. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _MACHINE_STDARG_H_ +#define _MACHINE_STDARG_H_ + +#include <sys/_stdarg.h> + +#ifndef va_start + #error this file needs to be ported to your compiler +#endif + +#endif /* !_MACHINE_STDARG_H_ */ diff --git a/sys/powerpc/include/sysarch.h b/sys/powerpc/include/sysarch.h new file mode 100644 index 000000000000..13f53f9406d9 --- /dev/null +++ b/sys/powerpc/include/sysarch.h @@ -0,0 +1,43 @@ +/*- + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (c) 1993 The Regents of the University of California. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _MACHINE_SYSARCH_H_ +#define _MACHINE_SYSARCH_H_ + +#ifndef _KERNEL +#include <sys/cdefs.h> + +__BEGIN_DECLS +int sysarch(int, void *); +__END_DECLS +#endif + +#endif /* !_MACHINE_SYSARCH_H_ */ diff --git a/sys/powerpc/include/tlb.h b/sys/powerpc/include/tlb.h new file mode 100644 index 000000000000..0a4463e0b928 --- /dev/null +++ b/sys/powerpc/include/tlb.h @@ -0,0 +1,181 @@ +/*- + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright (C) 2006-2012 Semihalf. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _MACHINE_TLB_H_ +#define _MACHINE_TLB_H_ + +#if defined(BOOKE_E500) + +/* PowerPC E500 MAS registers */ +#define MAS0_TLBSEL(x) ((x << 28) & 0x10000000) +#define MAS0_ESEL(x) ((x << 16) & 0x003F0000) + +#define MAS0_TLBSEL1 0x10000000 +#define MAS0_TLBSEL0 0x00000000 +#define MAS0_ESEL_TLB1MASK 0x000F0000 +#define MAS0_ESEL_TLB0MASK 0x00030000 +#define MAS0_ESEL_SHIFT 16 +#define MAS0_NV_MASK 0x00000003 +#define MAS0_NV_SHIFT 0 + +#define MAS1_VALID 0x80000000 +#define MAS1_IPROT 0x40000000 +#define MAS1_TID_MASK 0x00FF0000 +#define MAS1_TID_SHIFT 16 +#define MAS1_TS_MASK 0x00001000 +#define MAS1_TS_SHIFT 12 +#define MAS1_TSIZE_MASK 0x00000F00 +#define MAS1_TSIZE_SHIFT 8 + +#define TLB_SIZE_4K 1 +#define TLB_SIZE_16K 2 +#define TLB_SIZE_64K 3 +#define TLB_SIZE_256K 4 +#define TLB_SIZE_1M 5 +#define TLB_SIZE_4M 6 +#define TLB_SIZE_16M 7 +#define TLB_SIZE_64M 8 +#define TLB_SIZE_256M 9 +#define TLB_SIZE_1G 10 +#define TLB_SIZE_4G 11 + +#ifdef __powerpc64__ +#define MAS2_EPN_MASK 0xFFFFFFFFFFFFF000UL +#else +#define MAS2_EPN_MASK 0xFFFFF000 +#endif +#define MAS2_EPN_SHIFT 12 +#define MAS2_X0 0x00000040 +#define MAS2_X1 0x00000020 +#define MAS2_W 0x00000010 +#define MAS2_I 0x00000008 +#define MAS2_M 0x00000004 +#define MAS2_G 0x00000002 +#define MAS2_E 0x00000001 +#define MAS2_WIMGE_MASK 0x0000007F + +#define MAS3_RPN 0xFFFFF000 +#define MAS3_RPN_SHIFT 12 +#define MAS3_U0 0x00000200 +#define MAS3_U1 0x00000100 +#define MAS3_U2 0x00000080 +#define MAS3_U3 0x00000040 +#define MAS3_UX 0x00000020 +#define MAS3_SX 0x00000010 +#define MAS3_UW 0x00000008 +#define MAS3_SW 0x00000004 +#define MAS3_UR 0x00000002 +#define MAS3_SR 0x00000001 + +#define MAS4_TLBSELD1 0x10000000 +#define MAS4_TLBSELD0 0x00000000 +#define MAS4_TIDSELD_MASK 0x00030000 +#define MAS4_TIDSELD_SHIFT 16 +#define MAS4_TSIZED_MASK 0x00000F00 +#define MAS4_TSIZED_SHIFT 8 +#define MAS4_X0D 0x00000040 +#define MAS4_X1D 0x00000020 +#define MAS4_WD 0x00000010 +#define MAS4_ID 0x00000008 +#define MAS4_MD 0x00000004 +#define MAS4_GD 0x00000002 +#define MAS4_ED 0x00000001 + +#define MAS6_SPID0_MASK 0x00FF0000 +#define MAS6_SPID0_SHIFT 16 +#define MAS6_SAS 0x00000001 + +#define MAS7_RPN 0x0000000F + +#define MAS1_GETTID(mas1) (((mas1) & MAS1_TID_MASK) >> MAS1_TID_SHIFT) + +#define MAS2_TLB0_ENTRY_IDX_MASK 0x0007f000 +#define MAS2_TLB0_ENTRY_IDX_SHIFT 12 + +/* + * Maximum number of TLB1 entries used for a permanent mapping of kernel + * region (kernel image plus statically allocated data). + */ +#define KERNEL_REGION_MAX_TLB_ENTRIES 4 + +/* + * Use MAS2_X0 to mark entries which will be copied + * to AP CPUs during SMP bootstrap. As result entries + * marked with _TLB_ENTRY_SHARED will be shared by all CPUs. + */ +#define _TLB_ENTRY_SHARED (MAS2_X0) /* XXX under SMP? */ +#define _TLB_ENTRY_IO (MAS2_I | MAS2_G) +#define _TLB_ENTRY_MEM (MAS2_M) + +#define TLB1_MAX_ENTRIES 64 + +#if !defined(LOCORE) +typedef struct tlb_entry { + vm_paddr_t phys; + vm_offset_t virt; + vm_size_t size; + uint32_t mas1; +#ifdef __powerpc64__ + uint64_t mas2; +#else + uint32_t mas2; +#endif + uint32_t mas3; + uint32_t mas7; +} tlb_entry_t; + +void tlb1_inval_entry(unsigned int); +void tlb1_init(void); +#endif /* !LOCORE */ + +#endif /* BOOKE_E500 */ + +#define TID_KERNEL 0 /* TLB TID to use for kernel (shared) translations */ +#define TID_KRESERVED 1 /* Number of TIDs reserved for kernel */ +#define TID_URESERVED 0 /* Number of TIDs reserved for user */ +#define TID_MIN (TID_KRESERVED + TID_URESERVED) +#define TID_MAX 255 +#define TID_NONE -1 + +#define TLB_UNLOCKED 0 + +#if !defined(LOCORE) + +typedef int tlbtid_t; + +struct pmap; + +void tlb_lock(uintptr_t *); +void tlb_unlock(uintptr_t *); +void tlb1_ap_prep(void); +int tlb1_set_entry(vm_offset_t, vm_paddr_t, vm_size_t, uint32_t); + +#endif /* !LOCORE */ + +#endif /* _MACHINE_TLB_H_ */ diff --git a/sys/powerpc/include/tls.h b/sys/powerpc/include/tls.h new file mode 100644 index 000000000000..745a83a910c4 --- /dev/null +++ b/sys/powerpc/include/tls.h @@ -0,0 +1,66 @@ +/*- + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright 2004 by Peter Grehan. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _MACHINE_TLS_H_ +#define _MACHINE_TLS_H_ + +#include <sys/_tls_variant_i.h> + +#define TLS_DTV_OFFSET 0x8000 +#define TLS_TCB_ALIGN TLS_TCB_SIZE +#define TLS_TP_OFFSET 0x7000 + +static __inline void +_tcb_set(struct tcb *tcb) +{ +#ifdef __powerpc64__ + __asm __volatile("mr 13,%0" :: + "r" ((uint8_t *)tcb + TLS_TP_OFFSET + TLS_TCB_SIZE)); +#else + __asm __volatile("mr 2,%0" :: + "r" ((uint8_t *)tcb + TLS_TP_OFFSET + TLS_TCB_SIZE)); +#endif +} + +static __inline struct tcb * +_tcb_get(void) +{ + struct tcb *tcb; + +#ifdef __powerpc64__ + __asm __volatile("addi %0,13,%1" : "=r" (tcb) : + "i" (-(TLS_TP_OFFSET + TLS_TCB_SIZE))); +#else + __asm __volatile("addi %0,2,%1" : "=r" (tcb) : + "i" (-(TLS_TP_OFFSET + TLS_TCB_SIZE))); +#endif + return (tcb); +} + +#endif /* !_MACHINE_TLS_H_ */ diff --git a/sys/powerpc/include/trap.h b/sys/powerpc/include/trap.h new file mode 100644 index 000000000000..c7ee81102121 --- /dev/null +++ b/sys/powerpc/include/trap.h @@ -0,0 +1,160 @@ +/*- + * SPDX-License-Identifier: BSD-4-Clause + * + * Copyright (C) 1995, 1996 Wolfgang Solfrank. + * Copyright (C) 1995, 1996 TooLs GmbH. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by TooLs GmbH. + * 4. The name of TooLs GmbH may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $NetBSD: trap.h,v 1.7 2002/02/22 13:51:40 kleink Exp $ + */ + +#ifndef _POWERPC_TRAP_H_ +#define _POWERPC_TRAP_H_ + +#define EXC_RSVD 0x0000 /* Reserved */ +#define EXC_RST 0x0100 /* Reset; all but IBM4xx */ +#define EXC_MCHK 0x0200 /* Machine Check */ +#define EXC_DSI 0x0300 /* Data Storage Interrupt */ +#define EXC_DSE 0x0380 /* Data Segment Interrupt */ +#define EXC_ISI 0x0400 /* Instruction Storage Interrupt */ +#define EXC_ISE 0x0480 /* Instruction Segment Interrupt */ +#define EXC_EXI 0x0500 /* External Interrupt */ +#define EXC_ALI 0x0600 /* Alignment Interrupt */ +#define EXC_PGM 0x0700 /* Program Interrupt */ +#define EXC_FPU 0x0800 /* Floating-point Unavailable */ +#define EXC_DECR 0x0900 /* Decrementer Interrupt */ +#define EXC_SC 0x0c00 /* System Call */ +#define EXC_TRC 0x0d00 /* Trace */ +#define EXC_FPA 0x0e00 /* Floating-point Assist */ + +/* The following is only available on the 601: */ +#define EXC_RUNMODETRC 0x2000 /* Run Mode/Trace Exception */ + +/* The following are only available on 970(G5): */ +#define EXC_VECAST_G5 0x1700 /* AltiVec Assist */ + +/* The following are only available on 7400(G4): */ +#define EXC_VEC 0x0f20 /* AltiVec Unavailable */ +#define EXC_VECAST_G4 0x1600 /* AltiVec Assist */ + +/* The following are only available on 604/750/7400: */ +#define EXC_PERF 0x0f00 /* Performance Monitoring */ +#define EXC_BPT 0x1300 /* Instruction Breakpoint */ +#define EXC_SMI 0x1400 /* System Managment Interrupt */ + +/* The following are only available on 750/7400: */ +#define EXC_THRM 0x1700 /* Thermal Management Interrupt */ + +/* And these are only on the 603: */ +#define EXC_IMISS 0x1000 /* Instruction translation miss */ +#define EXC_DLMISS 0x1100 /* Data load translation miss */ +#define EXC_DSMISS 0x1200 /* Data store translation miss */ + +/* Power ISA 2.06+: */ +#define EXC_HDSI 0x0e00 /* Hypervisor Data Storage */ +#define EXC_HISI 0x0e20 /* Hypervisor Instruction Storage */ +#define EXC_HEA 0x0e40 /* Hypervisor Emulation Assistance */ +#define EXC_HMI 0x0e60 /* Hypervisor Maintenance */ +#define EXC_VSX 0x0f40 /* VSX Unavailable */ + +/* Power ISA 2.07+: */ +#define EXC_FAC 0x0f60 /* Facility Unavailable */ +#define EXC_HFAC 0x0f80 /* Hypervisor Facility Unavailable */ + +/* Power ISA 3.0+: */ +#define EXC_HVI 0x0ea0 /* Hypervisor Virtualization */ + +/* The following are available on 4xx and 85xx */ +#define EXC_CRIT 0x0100 /* Critical Input Interrupt */ +#define EXC_PIT 0x1000 /* Programmable Interval Timer */ +#define EXC_FIT 0x1010 /* Fixed Interval Timer */ +#define EXC_WDOG 0x1020 /* Watchdog Timer */ +#define EXC_DTMISS 0x1100 /* Data TLB Miss */ +#define EXC_ITMISS 0x1200 /* Instruction TLB Miss */ +#define EXC_APU 0x1300 /* Auxiliary Processing Unit */ +#define EXC_DEBUG 0x2f10 /* Debug trap */ +#define EXC_VECAST_E 0x2f20 /* Altivec Assist (Book-E) */ +#define EXC_SPFPD 0x2f30 /* SPE Floating-point Data */ +#define EXC_SPFPR 0x2f40 /* SPE Floating-point Round */ + +/* POWER8 */ +#define EXC_SOFT_PATCH 0x1500 /* POWER8 Soft Patch Exception */ + +#define EXC_LAST 0x2f00 /* Last possible exception vector */ + +#define EXC_AST 0x3000 /* Fake AST vector */ + +/* Trap was in user mode */ +#define EXC_USER 0x10000 + +/* + * EXC_ALI sets bits in the DSISR and DAR to provide enough + * information to recover from the unaligned access without needing to + * parse the offending instruction. This includes certain bits of the + * opcode, and information about what registers are used. The opcode + * indicator values below come from Appendix F of Book III of "The + * PowerPC Architecture". + */ + +#define EXC_ALI_OPCODE_INDICATOR(dsisr) ((dsisr >> 10) & 0x7f) +#define EXC_ALI_LFD 0x09 +#define EXC_ALI_STFD 0x0b + +/* Macros to extract register information */ +#define EXC_ALI_RST(dsisr) ((dsisr >> 5) & 0x1f) /* source or target */ +#define EXC_ALI_RA(dsisr) (dsisr & 0x1f) +#define EXC_ALI_INST_RST(instr) ((instr >> 21) & 0x1f) + +/* + * SRR1 bits for program exception traps. These identify what caused + * the program exception. See section 6.5.9 of the Power ISA Version + * 2.05. + */ + +#define EXC_PGM_FPENABLED (1UL << 20) +#define EXC_PGM_ILLEGAL (1UL << 19) +#define EXC_PGM_PRIV (1UL << 18) +#define EXC_PGM_TRAP (1UL << 17) + +/* DTrace trap opcode. */ +#define EXC_DTRACE 0x7ffff808 + +/* Magic pointer to store TOC base and other info for trap handlers on ppc64 */ +#define TRAP_ENTRY 0x1e8 +#define TRAP_GENTRAP 0x1f0 +#define TRAP_TOCBASE 0x1f8 + +#ifndef LOCORE +struct trapframe; +struct thread; +extern int (*hmi_handler)(struct trapframe *); +void trap(struct trapframe *); +int ppc_instr_emulate(struct trapframe *, struct thread *); +#endif + +#endif /* _POWERPC_TRAP_H_ */ diff --git a/sys/powerpc/include/ucontext.h b/sys/powerpc/include/ucontext.h new file mode 100644 index 000000000000..dc87edd578bc --- /dev/null +++ b/sys/powerpc/include/ucontext.h @@ -0,0 +1,93 @@ +/*- + * SPDX-License-Identifier: BSD-4-Clause + * + * Copyright (C) 1995, 1996 Wolfgang Solfrank. + * Copyright (C) 1995, 1996 TooLs GmbH. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by TooLs GmbH. + * 4. The name of TooLs GmbH may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $NetBSD: signal.h,v 1.4 1998/09/14 02:48:34 thorpej Exp $ + */ + +#ifndef _MACHINE_UCONTEXT_H_ +#define _MACHINE_UCONTEXT_H_ + +typedef struct __mcontext { + int mc_vers; + int mc_flags; +#define _MC_FP_VALID 0x01 +#define _MC_AV_VALID 0x02 +#define _MC_VS_VALID 0x04 + int mc_onstack; /* saved onstack flag */ + int mc_len; /* sizeof(__mcontext) */ + __uint64_t mc_avec[32*2]; /* vector register file */ + __uint32_t mc_av[2]; + __register_t mc_frame[42]; + __uint64_t mc_fpreg[33]; + __uint64_t mc_vsxfpreg[32]; /* low-order half of VSR0-31 */ +} mcontext_t __aligned(16); + +#if defined(_KERNEL) && defined(__powerpc64__) +typedef struct __mcontext32 { + int mc_vers; + int mc_flags; +#define _MC_FP_VALID 0x01 +#define _MC_AV_VALID 0x02 +#define _MC_VS_VALID 0x04 + int mc_onstack; /* saved onstack flag */ + int mc_len; /* sizeof(__mcontext) */ + uint64_t mc_avec[32*2]; /* vector register file */ + uint32_t mc_av[2]; + uint32_t mc_frame[42]; + uint64_t mc_fpreg[33]; + uint64_t mc_vsxfpreg[32]; /* low-order half of VSR0-31 */ +} mcontext32_t __aligned(16); +#endif + +/* GPRs and supervisor-level regs */ +#define mc_gpr mc_frame +#define mc_lr mc_frame[32] +#define mc_cr mc_frame[33] +#define mc_xer mc_frame[34] +#define mc_ctr mc_frame[35] +#define mc_srr0 mc_frame[36] +#define mc_srr1 mc_frame[37] +#define mc_exc mc_frame[38] +#define mc_dar mc_frame[39] +#define mc_dsisr mc_frame[40] + +/* floating-point state */ +#define mc_fpscr mc_fpreg[32] + +/* altivec state */ +#define mc_vscr mc_av[0] +#define mc_vrsave mc_av[1] + +#define _MC_VERSION 0x1 +#define _MC_VERSION_KSE 0xee /* partial ucontext for libpthread */ + +#endif /* !_MACHINE_UCONTEXT_H_ */ diff --git a/sys/powerpc/include/vdso.h b/sys/powerpc/include/vdso.h new file mode 100644 index 000000000000..afe3e0a314d9 --- /dev/null +++ b/sys/powerpc/include/vdso.h @@ -0,0 +1,43 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright 2012 Konstantin Belousov <kib@FreeBSD.ORG>. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _POWERPC_VDSO_H +#define _POWERPC_VDSO_H + +#define VDSO_TIMEHANDS_MD \ + uint32_t th_res[8]; + +#define VDSO_TH_ALGO_PPC_TB VDSO_TH_ALGO_1 + +#ifdef _KERNEL +#ifdef COMPAT_FREEBSD32 + +#define VDSO_TIMEHANDS_MD32 VDSO_TIMEHANDS_MD + +#endif +#endif +#endif diff --git a/sys/powerpc/include/vm.h b/sys/powerpc/include/vm.h new file mode 100644 index 000000000000..5c99cda51257 --- /dev/null +++ b/sys/powerpc/include/vm.h @@ -0,0 +1,45 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2009 Alan L. Cox <alc@cs.rice.edu> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _MACHINE_VM_H_ +#define _MACHINE_VM_H_ + +#include <machine/pte.h> + +/* Memory attributes. */ +#define VM_MEMATTR_DEFAULT 0 +#define VM_MEMATTR_UNCACHEABLE 0x01 +#define VM_MEMATTR_CACHEABLE 0x02 +#define VM_MEMATTR_WRITE_COMBINING 0x04 +#define VM_MEMATTR_WRITE_BACK 0x08 +#define VM_MEMATTR_WRITE_THROUGH 0x10 +#define VM_MEMATTR_PREFETCHABLE 0x20 + +#define VM_MEMATTR_DEVICE VM_MEMATTR_DEFAULT + +#endif /* !_MACHINE_VM_H_ */ diff --git a/sys/powerpc/include/vmparam.h b/sys/powerpc/include/vmparam.h new file mode 100644 index 000000000000..67fce74ade55 --- /dev/null +++ b/sys/powerpc/include/vmparam.h @@ -0,0 +1,327 @@ +/*- + * SPDX-License-Identifier: BSD-4-Clause + * + * Copyright (C) 1995, 1996 Wolfgang Solfrank. + * Copyright (C) 1995, 1996 TooLs GmbH. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by TooLs GmbH. + * 4. The name of TooLs GmbH may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $NetBSD: vmparam.h,v 1.11 2000/02/11 19:25:16 thorpej Exp $ + */ + +#ifndef _MACHINE_VMPARAM_H_ +#define _MACHINE_VMPARAM_H_ + +#ifndef LOCORE +#include <machine/md_var.h> +#endif + +#define USRSTACK SHAREDPAGE + +#ifndef MAXTSIZ +#define MAXTSIZ (1*1024*1024*1024) /* max text size */ +#endif + +#ifndef DFLDSIZ +#define DFLDSIZ (128*1024*1024) /* default data size */ +#endif + +#ifndef MAXDSIZ +#ifdef __powerpc64__ +#define MAXDSIZ (32UL*1024*1024*1024) /* max data size */ +#else +#define MAXDSIZ (1*1024*1024*1024) /* max data size */ +#endif +#endif + +#ifndef DFLSSIZ +#define DFLSSIZ (8*1024*1024) /* default stack size */ +#endif + +#ifndef MAXSSIZ +#ifdef __powerpc64__ +#define MAXSSIZ (512*1024*1024) /* max stack size */ +#else +#define MAXSSIZ (64*1024*1024) /* max stack size */ +#endif +#endif + +#ifdef AIM +#define VM_MAXUSER_ADDRESS32 0xfffff000 +#else +#define VM_MAXUSER_ADDRESS32 0x7ffff000 +#endif + +/* + * Would like to have MAX addresses = 0, but this doesn't (currently) work + */ +#ifdef __powerpc64__ +/* + * Virtual addresses of things. Derived from the page directory and + * page table indexes from pmap.h for precision. + * + * kernel map should be able to start at 0xc008000000000000 - + * but at least the functional simulator doesn't like it + * + * 0x0000000000000000 - 0x000fffffffffffff user map + * 0xc000000000000000 - 0xc007ffffffffffff direct map + * 0xc008000000000000 - 0xc00fffffffffffff kernel map + * + */ +#define VM_MIN_ADDRESS 0x0000000000000000 +#define VM_MAXUSER_ADDRESS 0x000fffffc0000000 +#define VM_MAX_ADDRESS 0xc00fffffffffffff +#define VM_MIN_KERNEL_ADDRESS 0xc008000000000000 +#define VM_MAX_KERNEL_ADDRESS 0xc0080007ffffffff +#define VM_MAX_SAFE_KERNEL_ADDRESS VM_MAX_KERNEL_ADDRESS +#else +#define VM_MIN_ADDRESS 0 +#define VM_MAXUSER_ADDRESS VM_MAXUSER_ADDRESS32 +#define VM_MAX_ADDRESS 0xffffffff +#endif + +#define SHAREDPAGE (VM_MAXUSER_ADDRESS - PAGE_SIZE) + +#define FREEBSD32_SHAREDPAGE (VM_MAXUSER_ADDRESS32 - PAGE_SIZE) +#define FREEBSD32_USRSTACK FREEBSD32_SHAREDPAGE + +#define KERNBASE 0x00100100 /* start of kernel virtual */ + +#define UMA_MD_SMALL_ALLOC + +#ifdef AIM +#ifndef __powerpc64__ +#define VM_MIN_KERNEL_ADDRESS ((vm_offset_t)KERNEL_SR << ADDR_SR_SHFT) +#define VM_MAX_SAFE_KERNEL_ADDRESS (VM_MIN_KERNEL_ADDRESS + 2*SEGMENT_LENGTH -1) +#define VM_MAX_KERNEL_ADDRESS (VM_MIN_KERNEL_ADDRESS + 3*SEGMENT_LENGTH - 1) +#endif + +/* + * Use the direct-mapped BAT registers for UMA small allocs. This + * takes pressure off the small amount of available KVA. + */ +#define UMA_USE_DMAP + +#else /* Book-E */ + +/* Use the direct map for UMA small allocs on powerpc64. */ +#ifdef __powerpc64__ +#define UMA_USE_DMAP +#else +#define VM_MIN_KERNEL_ADDRESS 0xc0000000 +#define VM_MAX_KERNEL_ADDRESS 0xffffefff +#define VM_MAX_SAFE_KERNEL_ADDRESS VM_MAX_KERNEL_ADDRESS +#endif + +#endif /* AIM/E500 */ + +#if !defined(LOCORE) +struct pmap_physseg { + struct pv_entry *pvent; + char *attrs; +}; +#endif + +#ifdef __powerpc64__ +#define VM_PHYSSEG_MAX 63 /* 1? */ +#else +#define VM_PHYSSEG_MAX 16 /* 1? */ +#endif + +#define PHYS_AVAIL_SZ 256 /* Allows up to 16GB Ram on pSeries with + * logical memory block size of 64MB. + * For more Ram increase the lmb or this value. + */ + +/* XXX This is non-sensical. Phys avail should hold contiguous regions. */ +#define PHYS_AVAIL_ENTRIES PHYS_AVAIL_SZ + +/* + * The physical address space is densely populated on 32-bit systems, + * but may not be on 64-bit ones. + */ +#ifdef __powerpc64__ +#define VM_PHYSSEG_SPARSE +#else +#define VM_PHYSSEG_DENSE +#endif + +/* + * Create two free page pools: VM_FREEPOOL_DEFAULT is the default pool + * from which physical pages are allocated and VM_FREEPOOL_DIRECT is + * the pool from which physical pages for small UMA objects are + * allocated. + */ +#define VM_NFREEPOOL 2 +#define VM_FREEPOOL_DEFAULT 0 +#define VM_FREEPOOL_DIRECT 1 + +/* + * Create one free page list. + */ +#define VM_NFREELIST 1 +#define VM_FREELIST_DEFAULT 0 + +#ifdef __powerpc64__ +/* The largest allocation size is 16MB. */ +#define VM_NFREEORDER 13 +#else +/* The largest allocation size is 4MB. */ +#define VM_NFREEORDER 11 +#endif + +#ifndef VM_NRESERVLEVEL +#ifdef __powerpc64__ +/* Enable superpage reservations: 1 level. */ +#define VM_NRESERVLEVEL 1 +#else +/* Disable superpage reservations. */ +#define VM_NRESERVLEVEL 0 +#endif +#endif + +#ifndef VM_LEVEL_0_ORDER +/* Level 0 reservations consist of 512 (RPT) or 4096 (HPT) pages. */ +#define VM_LEVEL_0_ORDER vm_level_0_order +#ifndef __ASSEMBLER__ +extern int vm_level_0_order; +#endif +#endif + +#ifndef VM_LEVEL_0_ORDER_MAX +#define VM_LEVEL_0_ORDER_MAX 12 +#endif + +#ifndef VM_INITIAL_PAGEIN +#define VM_INITIAL_PAGEIN 16 +#endif + +#ifndef SGROWSIZ +#define SGROWSIZ (128UL*1024) /* amount to grow stack */ +#endif + +/* + * How many physical pages per kmem arena virtual page. + */ +#ifndef VM_KMEM_SIZE_SCALE +#define VM_KMEM_SIZE_SCALE (3) +#endif + +/* + * Optional floor (in bytes) on the size of the kmem arena. + */ +#ifndef VM_KMEM_SIZE_MIN +#define VM_KMEM_SIZE_MIN (12 * 1024 * 1024) +#endif + +/* + * Optional ceiling (in bytes) on the size of the kmem arena: 40% of the + * usable KVA space. + */ +#ifndef VM_KMEM_SIZE_MAX +#define VM_KMEM_SIZE_MAX ((VM_MAX_SAFE_KERNEL_ADDRESS - \ + VM_MIN_KERNEL_ADDRESS + 1) * 2 / 5) +#endif + +#ifdef __powerpc64__ +#define ZERO_REGION_SIZE (2 * 1024 * 1024) /* 2MB */ +#else +#define ZERO_REGION_SIZE (64 * 1024) /* 64KB */ +#endif + +/* + * On 32-bit OEA, the only purpose for which sf_buf is used is to implement + * an opaque pointer required by the machine-independent parts of the kernel. + * That pointer references the vm_page that is "mapped" by the sf_buf. The + * actual mapping is provided by the direct virtual-to-physical mapping. + * + * On OEA64 and Book-E, we need to do something a little more complicated. Use + * the runtime-detected hw_direct_map to pick between the two cases. Our + * friends in vm_machdep.c will do the same to ensure nothing gets confused. + */ +#define SFBUF +#define SFBUF_NOMD + +/* + * We (usually) have a direct map of all physical memory, so provide + * a macro to use to get the kernel VA address for a given PA. Check the + * value of PMAP_HAS_PMAP before using. + */ +#ifndef LOCORE +#ifdef __powerpc64__ +#define DMAP_BASE_ADDRESS 0xc000000000000000UL +#define DMAP_MIN_ADDRESS DMAP_BASE_ADDRESS +#define DMAP_MAX_ADDRESS 0xc007ffffffffffffUL +#else +#define DMAP_BASE_ADDRESS 0x00000000UL +#define DMAP_MAX_ADDRESS 0xbfffffffUL +#endif +#endif + +#if defined(__powerpc64__) || defined(BOOKE) +/* + * powerpc64 and Book-E will provide their own page array allocators. + * + * On AIM, this will allocate a single virtual array, with pages from the + * correct memory domains. + * On Book-E this will let us put the array in TLB1, removing the need for TLB + * thrashing. + * + * VM_MIN_KERNEL_ADDRESS is just a dummy. It will get set by the MMU driver. + */ +#define PA_MIN_ADDRESS VM_MIN_KERNEL_ADDRESS +#define PMAP_HAS_PAGE_ARRAY 1 +#endif + +#if defined(__powerpc64__) +/* + * Need a page dump array for minidump. + */ +#define MINIDUMP_PAGE_TRACKING 1 +#define MINIDUMP_STARTUP_PAGE_TRACKING 1 +#else +/* + * No minidump with 32-bit powerpc. + */ +#define MINIDUMP_PAGE_TRACKING 0 +#define MINIDUMP_STARTUP_PAGE_TRACKING 0 +#endif + +#define PMAP_HAS_DMAP (hw_direct_map) +#define PHYS_TO_DMAP(x) ({ \ + KASSERT(hw_direct_map, ("Direct map not provided by PMAP")); \ + (x) | DMAP_BASE_ADDRESS; }) +#define DMAP_TO_PHYS(x) ({ \ + KASSERT(hw_direct_map, ("Direct map not provided by PMAP")); \ + (x) &~ DMAP_BASE_ADDRESS; }) + +/* + * No non-transparent large page support in the pmap. + */ +#define PMAP_HAS_LARGEPAGES 0 + +#endif /* _MACHINE_VMPARAM_H_ */ |