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-rw-r--r--sys/riscv/include/kexec.h39
-rw-r--r--sys/riscv/riscv/fpe.c66
-rw-r--r--sys/riscv/vmm/vmm.c4
-rw-r--r--sys/riscv/vmm/vmm_aplic.c10
-rw-r--r--sys/riscv/vmm/vmm_aplic.h1
5 files changed, 72 insertions, 48 deletions
diff --git a/sys/riscv/include/kexec.h b/sys/riscv/include/kexec.h
new file mode 100644
index 000000000000..5fb6fd321989
--- /dev/null
+++ b/sys/riscv/include/kexec.h
@@ -0,0 +1,39 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2025 Juniper Networks, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _RISCV_KEXEC_H_
+#define _RISCV_KEXEC_H_
+
+int
+kexec_load_md(struct kexec_image *image)
+{
+ return (ENOSYS);
+}
+
+#define kexec_reboot_md(x) do {} while (0)
+#endif /* _RISCV_KEXEC_H_ */
diff --git a/sys/riscv/riscv/fpe.c b/sys/riscv/riscv/fpe.c
index b6c66e5e4f09..63103a794a8e 100644
--- a/sys/riscv/riscv/fpe.c
+++ b/sys/riscv/riscv/fpe.c
@@ -69,39 +69,39 @@ fpe_store(struct fpreg *regs)
__asm __volatile(
"frcsr %0 \n"
- "fsd f0, (16 * 0)(%1)\n"
- "fsd f1, (16 * 1)(%1)\n"
- "fsd f2, (16 * 2)(%1)\n"
- "fsd f3, (16 * 3)(%1)\n"
- "fsd f4, (16 * 4)(%1)\n"
- "fsd f5, (16 * 5)(%1)\n"
- "fsd f6, (16 * 6)(%1)\n"
- "fsd f7, (16 * 7)(%1)\n"
- "fsd f8, (16 * 8)(%1)\n"
- "fsd f9, (16 * 9)(%1)\n"
- "fsd f10, (16 * 10)(%1)\n"
- "fsd f11, (16 * 11)(%1)\n"
- "fsd f12, (16 * 12)(%1)\n"
- "fsd f13, (16 * 13)(%1)\n"
- "fsd f14, (16 * 14)(%1)\n"
- "fsd f15, (16 * 15)(%1)\n"
- "fsd f16, (16 * 16)(%1)\n"
- "fsd f17, (16 * 17)(%1)\n"
- "fsd f18, (16 * 18)(%1)\n"
- "fsd f19, (16 * 19)(%1)\n"
- "fsd f20, (16 * 20)(%1)\n"
- "fsd f21, (16 * 21)(%1)\n"
- "fsd f22, (16 * 22)(%1)\n"
- "fsd f23, (16 * 23)(%1)\n"
- "fsd f24, (16 * 24)(%1)\n"
- "fsd f25, (16 * 25)(%1)\n"
- "fsd f26, (16 * 26)(%1)\n"
- "fsd f27, (16 * 27)(%1)\n"
- "fsd f28, (16 * 28)(%1)\n"
- "fsd f29, (16 * 29)(%1)\n"
- "fsd f30, (16 * 30)(%1)\n"
- "fsd f31, (16 * 31)(%1)\n"
- : "=&r"(fcsr), "=r"(fp_x), "=m"(*fp_x));
+ "fsd f0, (16 * 0)(%2)\n"
+ "fsd f1, (16 * 1)(%2)\n"
+ "fsd f2, (16 * 2)(%2)\n"
+ "fsd f3, (16 * 3)(%2)\n"
+ "fsd f4, (16 * 4)(%2)\n"
+ "fsd f5, (16 * 5)(%2)\n"
+ "fsd f6, (16 * 6)(%2)\n"
+ "fsd f7, (16 * 7)(%2)\n"
+ "fsd f8, (16 * 8)(%2)\n"
+ "fsd f9, (16 * 9)(%2)\n"
+ "fsd f10, (16 * 10)(%2)\n"
+ "fsd f11, (16 * 11)(%2)\n"
+ "fsd f12, (16 * 12)(%2)\n"
+ "fsd f13, (16 * 13)(%2)\n"
+ "fsd f14, (16 * 14)(%2)\n"
+ "fsd f15, (16 * 15)(%2)\n"
+ "fsd f16, (16 * 16)(%2)\n"
+ "fsd f17, (16 * 17)(%2)\n"
+ "fsd f18, (16 * 18)(%2)\n"
+ "fsd f19, (16 * 19)(%2)\n"
+ "fsd f20, (16 * 20)(%2)\n"
+ "fsd f21, (16 * 21)(%2)\n"
+ "fsd f22, (16 * 22)(%2)\n"
+ "fsd f23, (16 * 23)(%2)\n"
+ "fsd f24, (16 * 24)(%2)\n"
+ "fsd f25, (16 * 25)(%2)\n"
+ "fsd f26, (16 * 26)(%2)\n"
+ "fsd f27, (16 * 27)(%2)\n"
+ "fsd f28, (16 * 28)(%2)\n"
+ "fsd f29, (16 * 29)(%2)\n"
+ "fsd f30, (16 * 30)(%2)\n"
+ "fsd f31, (16 * 31)(%2)\n"
+ : "=&r"(fcsr), "=m"(*fp_x) : "r"(fp_x));
regs->fp_fcsr = fcsr;
}
diff --git a/sys/riscv/vmm/vmm.c b/sys/riscv/vmm/vmm.c
index 24b4be89af48..a9eb9d144336 100644
--- a/sys/riscv/vmm/vmm.c
+++ b/sys/riscv/vmm/vmm.c
@@ -319,10 +319,6 @@ vm_alloc_vcpu(struct vm *vm, int vcpuid)
if (vcpuid < 0 || vcpuid >= vm_get_maxcpus(vm))
return (NULL);
- /* Some interrupt controllers may have a CPU limit */
- if (vcpuid >= aplic_max_cpu_count(vm->cookie))
- return (NULL);
-
vcpu = (struct vcpu *)
atomic_load_acq_ptr((uintptr_t *)&vm->vcpu[vcpuid]);
if (__predict_true(vcpu != NULL))
diff --git a/sys/riscv/vmm/vmm_aplic.c b/sys/riscv/vmm/vmm_aplic.c
index 4df41f2de1a5..74cb4fef4273 100644
--- a/sys/riscv/vmm/vmm_aplic.c
+++ b/sys/riscv/vmm/vmm_aplic.c
@@ -577,13 +577,3 @@ aplic_sync_hwstate(struct hypctx *hypctx)
{
}
-
-int
-aplic_max_cpu_count(struct hyp *hyp)
-{
- int16_t max_count;
-
- max_count = vm_get_maxcpus(hyp->vm);
-
- return (max_count);
-}
diff --git a/sys/riscv/vmm/vmm_aplic.h b/sys/riscv/vmm/vmm_aplic.h
index 49510221b419..96018fe9adda 100644
--- a/sys/riscv/vmm/vmm_aplic.h
+++ b/sys/riscv/vmm/vmm_aplic.h
@@ -49,6 +49,5 @@ void aplic_cpuinit(struct hypctx *hypctx);
void aplic_cpucleanup(struct hypctx *hypctx);
void aplic_flush_hwstate(struct hypctx *hypctx);
void aplic_sync_hwstate(struct hypctx *hypctx);
-int aplic_max_cpu_count(struct hyp *hyp);
#endif /* !_VMM_APLIC_H_ */