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-rw-r--r--sys/riscv/conf/std.allwinner3
-rw-r--r--sys/riscv/conf/std.starfive3
-rw-r--r--sys/riscv/include/kexec.h39
-rw-r--r--sys/riscv/riscv/fpe.c66
-rw-r--r--sys/riscv/vmm/vmm.c5
-rw-r--r--sys/riscv/vmm/vmm_dev_machdep.c37
6 files changed, 105 insertions, 48 deletions
diff --git a/sys/riscv/conf/std.allwinner b/sys/riscv/conf/std.allwinner
index 34fe195b01ba..ecd789f39963 100644
--- a/sys/riscv/conf/std.allwinner
+++ b/sys/riscv/conf/std.allwinner
@@ -17,4 +17,7 @@ device awg # Allwinner EMAC Gigabit Ethernet
device musb # Mentor Graphics USB OTG controller
+# DTBs
+makeoptions MODULES_EXTRA+="dtb/allwinner"
+
files "../allwinner/files.allwinner"
diff --git a/sys/riscv/conf/std.starfive b/sys/riscv/conf/std.starfive
index 9bdb1af9e79c..6a0e56cc84bd 100644
--- a/sys/riscv/conf/std.starfive
+++ b/sys/riscv/conf/std.starfive
@@ -10,4 +10,7 @@ device eqos
device dwmmc
device dwmmc_starfive
+# DTBs
+makeoptions MODULES_EXTRA+="dtb/starfive"
+
files "../starfive/files.starfive"
diff --git a/sys/riscv/include/kexec.h b/sys/riscv/include/kexec.h
new file mode 100644
index 000000000000..5fb6fd321989
--- /dev/null
+++ b/sys/riscv/include/kexec.h
@@ -0,0 +1,39 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2025 Juniper Networks, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _RISCV_KEXEC_H_
+#define _RISCV_KEXEC_H_
+
+int
+kexec_load_md(struct kexec_image *image)
+{
+ return (ENOSYS);
+}
+
+#define kexec_reboot_md(x) do {} while (0)
+#endif /* _RISCV_KEXEC_H_ */
diff --git a/sys/riscv/riscv/fpe.c b/sys/riscv/riscv/fpe.c
index b6c66e5e4f09..63103a794a8e 100644
--- a/sys/riscv/riscv/fpe.c
+++ b/sys/riscv/riscv/fpe.c
@@ -69,39 +69,39 @@ fpe_store(struct fpreg *regs)
__asm __volatile(
"frcsr %0 \n"
- "fsd f0, (16 * 0)(%1)\n"
- "fsd f1, (16 * 1)(%1)\n"
- "fsd f2, (16 * 2)(%1)\n"
- "fsd f3, (16 * 3)(%1)\n"
- "fsd f4, (16 * 4)(%1)\n"
- "fsd f5, (16 * 5)(%1)\n"
- "fsd f6, (16 * 6)(%1)\n"
- "fsd f7, (16 * 7)(%1)\n"
- "fsd f8, (16 * 8)(%1)\n"
- "fsd f9, (16 * 9)(%1)\n"
- "fsd f10, (16 * 10)(%1)\n"
- "fsd f11, (16 * 11)(%1)\n"
- "fsd f12, (16 * 12)(%1)\n"
- "fsd f13, (16 * 13)(%1)\n"
- "fsd f14, (16 * 14)(%1)\n"
- "fsd f15, (16 * 15)(%1)\n"
- "fsd f16, (16 * 16)(%1)\n"
- "fsd f17, (16 * 17)(%1)\n"
- "fsd f18, (16 * 18)(%1)\n"
- "fsd f19, (16 * 19)(%1)\n"
- "fsd f20, (16 * 20)(%1)\n"
- "fsd f21, (16 * 21)(%1)\n"
- "fsd f22, (16 * 22)(%1)\n"
- "fsd f23, (16 * 23)(%1)\n"
- "fsd f24, (16 * 24)(%1)\n"
- "fsd f25, (16 * 25)(%1)\n"
- "fsd f26, (16 * 26)(%1)\n"
- "fsd f27, (16 * 27)(%1)\n"
- "fsd f28, (16 * 28)(%1)\n"
- "fsd f29, (16 * 29)(%1)\n"
- "fsd f30, (16 * 30)(%1)\n"
- "fsd f31, (16 * 31)(%1)\n"
- : "=&r"(fcsr), "=r"(fp_x), "=m"(*fp_x));
+ "fsd f0, (16 * 0)(%2)\n"
+ "fsd f1, (16 * 1)(%2)\n"
+ "fsd f2, (16 * 2)(%2)\n"
+ "fsd f3, (16 * 3)(%2)\n"
+ "fsd f4, (16 * 4)(%2)\n"
+ "fsd f5, (16 * 5)(%2)\n"
+ "fsd f6, (16 * 6)(%2)\n"
+ "fsd f7, (16 * 7)(%2)\n"
+ "fsd f8, (16 * 8)(%2)\n"
+ "fsd f9, (16 * 9)(%2)\n"
+ "fsd f10, (16 * 10)(%2)\n"
+ "fsd f11, (16 * 11)(%2)\n"
+ "fsd f12, (16 * 12)(%2)\n"
+ "fsd f13, (16 * 13)(%2)\n"
+ "fsd f14, (16 * 14)(%2)\n"
+ "fsd f15, (16 * 15)(%2)\n"
+ "fsd f16, (16 * 16)(%2)\n"
+ "fsd f17, (16 * 17)(%2)\n"
+ "fsd f18, (16 * 18)(%2)\n"
+ "fsd f19, (16 * 19)(%2)\n"
+ "fsd f20, (16 * 20)(%2)\n"
+ "fsd f21, (16 * 21)(%2)\n"
+ "fsd f22, (16 * 22)(%2)\n"
+ "fsd f23, (16 * 23)(%2)\n"
+ "fsd f24, (16 * 24)(%2)\n"
+ "fsd f25, (16 * 25)(%2)\n"
+ "fsd f26, (16 * 26)(%2)\n"
+ "fsd f27, (16 * 27)(%2)\n"
+ "fsd f28, (16 * 28)(%2)\n"
+ "fsd f29, (16 * 29)(%2)\n"
+ "fsd f30, (16 * 30)(%2)\n"
+ "fsd f31, (16 * 31)(%2)\n"
+ : "=&r"(fcsr), "=m"(*fp_x) : "r"(fp_x));
regs->fp_fcsr = fcsr;
}
diff --git a/sys/riscv/vmm/vmm.c b/sys/riscv/vmm/vmm.c
index 4c9b1fa53f7a..24b4be89af48 100644
--- a/sys/riscv/vmm/vmm.c
+++ b/sys/riscv/vmm/vmm.c
@@ -954,8 +954,7 @@ vcpu_get_state(struct vcpu *vcpu, int *hostcpu)
int
vm_get_register(struct vcpu *vcpu, int reg, uint64_t *retval)
{
-
- if (reg >= VM_REG_LAST)
+ if (reg < 0 || reg >= VM_REG_LAST)
return (EINVAL);
return (vmmops_getreg(vcpu->cookie, reg, retval));
@@ -966,7 +965,7 @@ vm_set_register(struct vcpu *vcpu, int reg, uint64_t val)
{
int error;
- if (reg >= VM_REG_LAST)
+ if (reg < 0 || reg >= VM_REG_LAST)
return (EINVAL);
error = vmmops_setreg(vcpu->cookie, reg, val);
if (error || reg != VM_REG_GUEST_SEPC)
diff --git a/sys/riscv/vmm/vmm_dev_machdep.c b/sys/riscv/vmm/vmm_dev_machdep.c
index ba15d8dcd79e..c736b10dc9c0 100644
--- a/sys/riscv/vmm/vmm_dev_machdep.c
+++ b/sys/riscv/vmm/vmm_dev_machdep.c
@@ -67,18 +67,13 @@ int
vmmdev_machdep_ioctl(struct vm *vm, struct vcpu *vcpu, u_long cmd, caddr_t data,
int fflag, struct thread *td)
{
- struct vm_run *vmrun;
- struct vm_aplic_descr *aplic;
- struct vm_irq *vi;
- struct vm_exception *vmexc;
- struct vm_gla2gpa *gg;
- struct vm_msi *vmsi;
int error;
error = 0;
switch (cmd) {
case VM_RUN: {
struct vm_exit *vme;
+ struct vm_run *vmrun;
vmrun = (struct vm_run *)data;
vme = vm_exitinfo(vcpu);
@@ -90,34 +85,52 @@ vmmdev_machdep_ioctl(struct vm *vm, struct vcpu *vcpu, u_long cmd, caddr_t data,
error = copyout(vme, vmrun->vm_exit, sizeof(*vme));
break;
}
- case VM_INJECT_EXCEPTION:
+ case VM_INJECT_EXCEPTION: {
+ struct vm_exception *vmexc;
+
vmexc = (struct vm_exception *)data;
error = vm_inject_exception(vcpu, vmexc->scause);
break;
- case VM_GLA2GPA_NOFAULT:
+ }
+ case VM_GLA2GPA_NOFAULT: {
+ struct vm_gla2gpa *gg;
+
gg = (struct vm_gla2gpa *)data;
error = vm_gla2gpa_nofault(vcpu, &gg->paging, gg->gla,
gg->prot, &gg->gpa, &gg->fault);
KASSERT(error == 0 || error == EFAULT,
("%s: vm_gla2gpa unknown error %d", __func__, error));
break;
- case VM_ATTACH_APLIC:
+ }
+ case VM_ATTACH_APLIC: {
+ struct vm_aplic_descr *aplic;
+
aplic = (struct vm_aplic_descr *)data;
error = vm_attach_aplic(vm, aplic);
break;
- case VM_RAISE_MSI:
+ }
+ case VM_RAISE_MSI: {
+ struct vm_msi *vmsi;
+
vmsi = (struct vm_msi *)data;
error = vm_raise_msi(vm, vmsi->msg, vmsi->addr, vmsi->bus,
vmsi->slot, vmsi->func);
break;
- case VM_ASSERT_IRQ:
+ }
+ case VM_ASSERT_IRQ: {
+ struct vm_irq *vi;
+
vi = (struct vm_irq *)data;
error = vm_assert_irq(vm, vi->irq);
break;
- case VM_DEASSERT_IRQ:
+ }
+ case VM_DEASSERT_IRQ: {
+ struct vm_irq *vi;
+
vi = (struct vm_irq *)data;
error = vm_deassert_irq(vm, vi->irq);
break;
+ }
default:
error = ENOTTY;
break;
generated by cgit v1.2.3 (git 2.25.1) at 2025-10-31 12:46:55 +0000