diff options
Diffstat (limited to 'sys')
| -rw-r--r-- | sys/amd64/amd64/identcpu.c | 2 | ||||
| -rw-r--r-- | sys/amd64/include/specialreg.h | 165 | ||||
| -rw-r--r-- | sys/i386/i386/identcpu.c | 2 | ||||
| -rw-r--r-- | sys/i386/include/specialreg.h | 223 |
4 files changed, 197 insertions, 195 deletions
diff --git a/sys/amd64/amd64/identcpu.c b/sys/amd64/amd64/identcpu.c index 6b055e4ed73a..dec01882de28 100644 --- a/sys/amd64/amd64/identcpu.c +++ b/sys/amd64/amd64/identcpu.c @@ -312,7 +312,7 @@ printcpuinfo(void) "\006<b5>" "\007<b6>" "\010<b7>" - "\011<b8>" + "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */ "\012<b9>" "\013<b10>" "\014<b11>" diff --git a/sys/amd64/include/specialreg.h b/sys/amd64/include/specialreg.h index a4e656af528a..5c5908f365db 100644 --- a/sys/amd64/include/specialreg.h +++ b/sys/amd64/include/specialreg.h @@ -112,35 +112,36 @@ #define CPUID_IA64 0x40000000 #define CPUID_PBE 0x80000000 -#define CPUID2_SSE3 0x00000001 -#define CPUID2_MON 0x00000008 -#define CPUID2_DS_CPL 0x00000010 -#define CPUID2_VMX 0x00000020 -#define CPUID2_EST 0x00000080 -#define CPUID2_TM2 0x00000100 -#define CPUID2_SSSE3 0x00000200 -#define CPUID2_CNXTID 0x00000400 -#define CPUID2_CX16 0x00002000 -#define CPUID2_XTPR 0x00004000 +#define CPUID2_SSE3 0x00000001 +#define CPUID2_MON 0x00000008 +#define CPUID2_DS_CPL 0x00000010 +#define CPUID2_VMX 0x00000020 +#define CPUID2_EST 0x00000080 +#define CPUID2_TM2 0x00000100 +#define CPUID2_SSSE3 0x00000200 +#define CPUID2_CNXTID 0x00000400 +#define CPUID2_CX16 0x00002000 +#define CPUID2_XTPR 0x00004000 /* * Important bits in the AMD extended cpuid flags */ -#define AMDID_SYSCALL 0x00000800 -#define AMDID_MP 0x00080000 -#define AMDID_NX 0x00100000 -#define AMDID_EXT_MMX 0x00400000 -#define AMDID_FFXSR 0x01000000 -#define AMDID_RDTSCP 0x08000000 -#define AMDID_LM 0x20000000 -#define AMDID_EXT_3DNOW 0x40000000 -#define AMDID_3DNOW 0x80000000 +#define AMDID_SYSCALL 0x00000800 +#define AMDID_MP 0x00080000 +#define AMDID_NX 0x00100000 +#define AMDID_EXT_MMX 0x00400000 +#define AMDID_FFXSR 0x01000000 +#define AMDID_RDTSCP 0x08000000 +#define AMDID_LM 0x20000000 +#define AMDID_EXT_3DNOW 0x40000000 +#define AMDID_3DNOW 0x80000000 -#define AMDID2_LAHF 0x00000001 -#define AMDID2_CMP 0x00000002 -#define AMDID2_SVM 0x00000004 -#define AMDID2_EXT_APIC 0x00000008 -#define AMDID2_CR8 0x00000010 +#define AMDID2_LAHF 0x00000001 +#define AMDID2_CMP 0x00000002 +#define AMDID2_SVM 0x00000004 +#define AMDID2_EXT_APIC 0x00000008 +#define AMDID2_CR8 0x00000010 +#define AMDID2_PREFETCH 0x00000100 /* * CPUID instruction 1 ebx info @@ -153,29 +154,29 @@ /* * AMD extended function 8000_0008h ecx info */ -#define AMDID_CMP_CORES 0x000000ff +#define AMDID_CMP_CORES 0x000000ff /* * Model-specific registers for the i386 family */ -#define MSR_P5_MC_ADDR 0x000 -#define MSR_P5_MC_TYPE 0x001 -#define MSR_TSC 0x010 +#define MSR_P5_MC_ADDR 0x000 +#define MSR_P5_MC_TYPE 0x001 +#define MSR_TSC 0x010 #define MSR_P5_CESR 0x011 #define MSR_P5_CTR0 0x012 #define MSR_P5_CTR1 0x013 #define MSR_IA32_PLATFORM_ID 0x017 -#define MSR_APICBASE 0x01b -#define MSR_EBL_CR_POWERON 0x02a +#define MSR_APICBASE 0x01b +#define MSR_EBL_CR_POWERON 0x02a #define MSR_TEST_CTL 0x033 -#define MSR_BIOS_UPDT_TRIG 0x079 +#define MSR_BIOS_UPDT_TRIG 0x079 #define MSR_BBL_CR_D0 0x088 #define MSR_BBL_CR_D1 0x089 #define MSR_BBL_CR_D2 0x08a -#define MSR_BIOS_SIGN 0x08b -#define MSR_PERFCTR0 0x0c1 -#define MSR_PERFCTR1 0x0c2 -#define MSR_MTRRcap 0x0fe +#define MSR_BIOS_SIGN 0x08b +#define MSR_PERFCTR0 0x0c1 +#define MSR_PERFCTR1 0x0c2 +#define MSR_MTRRcap 0x0fe #define MSR_BBL_CR_ADDR 0x116 #define MSR_BBL_CR_DECC 0x118 #define MSR_BBL_CR_CTL 0x119 @@ -185,47 +186,47 @@ #define MSR_SYSENTER_CS_MSR 0x174 #define MSR_SYSENTER_ESP_MSR 0x175 #define MSR_SYSENTER_EIP_MSR 0x176 -#define MSR_MCG_CAP 0x179 -#define MSR_MCG_STATUS 0x17a -#define MSR_MCG_CTL 0x17b -#define MSR_EVNTSEL0 0x186 -#define MSR_EVNTSEL1 0x187 -#define MSR_THERM_CONTROL 0x19a -#define MSR_THERM_INTERRUPT 0x19b -#define MSR_THERM_STATUS 0x19c +#define MSR_MCG_CAP 0x179 +#define MSR_MCG_STATUS 0x17a +#define MSR_MCG_CTL 0x17b +#define MSR_EVNTSEL0 0x186 +#define MSR_EVNTSEL1 0x187 +#define MSR_THERM_CONTROL 0x19a +#define MSR_THERM_INTERRUPT 0x19b +#define MSR_THERM_STATUS 0x19c #define MSR_IA32_MISC_ENABLE 0x1a0 -#define MSR_DEBUGCTLMSR 0x1d9 -#define MSR_LASTBRANCHFROMIP 0x1db -#define MSR_LASTBRANCHTOIP 0x1dc -#define MSR_LASTINTFROMIP 0x1dd -#define MSR_LASTINTTOIP 0x1de -#define MSR_ROB_CR_BKUPTMPDR6 0x1e0 -#define MSR_MTRRVarBase 0x200 -#define MSR_MTRR64kBase 0x250 -#define MSR_MTRR16kBase 0x258 -#define MSR_MTRR4kBase 0x268 -#define MSR_PAT 0x277 -#define MSR_MTRRdefType 0x2ff -#define MSR_MC0_CTL 0x400 -#define MSR_MC0_STATUS 0x401 -#define MSR_MC0_ADDR 0x402 -#define MSR_MC0_MISC 0x403 -#define MSR_MC1_CTL 0x404 -#define MSR_MC1_STATUS 0x405 -#define MSR_MC1_ADDR 0x406 -#define MSR_MC1_MISC 0x407 -#define MSR_MC2_CTL 0x408 -#define MSR_MC2_STATUS 0x409 -#define MSR_MC2_ADDR 0x40a -#define MSR_MC2_MISC 0x40b -#define MSR_MC3_CTL 0x40c -#define MSR_MC3_STATUS 0x40d -#define MSR_MC3_ADDR 0x40e -#define MSR_MC3_MISC 0x40f -#define MSR_MC4_CTL 0x410 -#define MSR_MC4_STATUS 0x411 -#define MSR_MC4_ADDR 0x412 -#define MSR_MC4_MISC 0x413 +#define MSR_DEBUGCTLMSR 0x1d9 +#define MSR_LASTBRANCHFROMIP 0x1db +#define MSR_LASTBRANCHTOIP 0x1dc +#define MSR_LASTINTFROMIP 0x1dd +#define MSR_LASTINTTOIP 0x1de +#define MSR_ROB_CR_BKUPTMPDR6 0x1e0 +#define MSR_MTRRVarBase 0x200 +#define MSR_MTRR64kBase 0x250 +#define MSR_MTRR16kBase 0x258 +#define MSR_MTRR4kBase 0x268 +#define MSR_PAT 0x277 +#define MSR_MTRRdefType 0x2ff +#define MSR_MC0_CTL 0x400 +#define MSR_MC0_STATUS 0x401 +#define MSR_MC0_ADDR 0x402 +#define MSR_MC0_MISC 0x403 +#define MSR_MC1_CTL 0x404 +#define MSR_MC1_STATUS 0x405 +#define MSR_MC1_ADDR 0x406 +#define MSR_MC1_MISC 0x407 +#define MSR_MC2_CTL 0x408 +#define MSR_MC2_STATUS 0x409 +#define MSR_MC2_ADDR 0x40a +#define MSR_MC2_MISC 0x40b +#define MSR_MC3_CTL 0x40c +#define MSR_MC3_STATUS 0x40d +#define MSR_MC3_ADDR 0x40e +#define MSR_MC3_MISC 0x40f +#define MSR_MC4_CTL 0x410 +#define MSR_MC4_STATUS 0x411 +#define MSR_MC4_ADDR 0x412 +#define MSR_MC4_MISC 0x413 /* * Constants related to MSR's. @@ -250,9 +251,9 @@ /* * Constants related to MTRRs */ -#define MTRR_N64K 8 /* numbers of fixed-size entries */ -#define MTRR_N16K 16 -#define MTRR_N4K 64 +#define MTRR_N64K 8 /* numbers of fixed-size entries */ +#define MTRR_N16K 16 +#define MTRR_N4K 64 /* Performance Control Register (5x86 only). */ #define PCR0 0x20 @@ -349,11 +350,11 @@ #define RCR6 0xe2 #define RCR7 0xe3 -#define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ -#define RCR_RCE 0x01 /* Enables caching for ARR7. */ -#define RCR_WWO 0x02 /* Weak write ordering. */ +#define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ +#define RCR_RCE 0x01 /* Enables caching for ARR7. */ +#define RCR_WWO 0x02 /* Weak write ordering. */ #define RCR_WL 0x04 /* Weak locking. */ -#define RCR_WG 0x08 /* Write gathering. */ +#define RCR_WG 0x08 /* Write gathering. */ #define RCR_WT 0x10 /* Write-through. */ #define RCR_NLB 0x20 /* LBA# pin is not asserted. */ diff --git a/sys/i386/i386/identcpu.c b/sys/i386/i386/identcpu.c index e5021590cc50..2c023b86fcd9 100644 --- a/sys/i386/i386/identcpu.c +++ b/sys/i386/i386/identcpu.c @@ -832,7 +832,7 @@ via_common: "\006<b5>" "\007<b6>" "\010<b7>" - "\011<b8>" + "\011Prefetch" /* 3DNow! Prefetch/PrefetchW */ "\012<b9>" "\013<b10>" "\014<b11>" diff --git a/sys/i386/include/specialreg.h b/sys/i386/include/specialreg.h index 52e9abeb93e1..2789ca231015 100644 --- a/sys/i386/include/specialreg.h +++ b/sys/i386/include/specialreg.h @@ -104,35 +104,36 @@ #define CPUID_IA64 0x40000000 #define CPUID_PBE 0x80000000 -#define CPUID2_SSE3 0x00000001 -#define CPUID2_MON 0x00000008 -#define CPUID2_DS_CPL 0x00000010 -#define CPUID2_VMX 0x00000020 -#define CPUID2_EST 0x00000080 -#define CPUID2_TM2 0x00000100 -#define CPUID2_SSSE3 0x00000200 -#define CPUID2_CNXTID 0x00000400 -#define CPUID2_CX16 0x00002000 -#define CPUID2_XTPR 0x00004000 +#define CPUID2_SSE3 0x00000001 +#define CPUID2_MON 0x00000008 +#define CPUID2_DS_CPL 0x00000010 +#define CPUID2_VMX 0x00000020 +#define CPUID2_EST 0x00000080 +#define CPUID2_TM2 0x00000100 +#define CPUID2_SSSE3 0x00000200 +#define CPUID2_CNXTID 0x00000400 +#define CPUID2_CX16 0x00002000 +#define CPUID2_XTPR 0x00004000 /* * Important bits in the AMD extended cpuid flags */ -#define AMDID_SYSCALL 0x00000800 -#define AMDID_MP 0x00080000 -#define AMDID_NX 0x00100000 -#define AMDID_EXT_MMX 0x00400000 -#define AMDID_FFXSR 0x01000000 -#define AMDID_RDTSCP 0x08000000 -#define AMDID_LM 0x20000000 -#define AMDID_EXT_3DNOW 0x40000000 -#define AMDID_3DNOW 0x80000000 +#define AMDID_SYSCALL 0x00000800 +#define AMDID_MP 0x00080000 +#define AMDID_NX 0x00100000 +#define AMDID_EXT_MMX 0x00400000 +#define AMDID_FFXSR 0x01000000 +#define AMDID_RDTSCP 0x08000000 +#define AMDID_LM 0x20000000 +#define AMDID_EXT_3DNOW 0x40000000 +#define AMDID_3DNOW 0x80000000 -#define AMDID2_LAHF 0x00000001 -#define AMDID2_CMP 0x00000002 -#define AMDID2_SVM 0x00000004 -#define AMDID2_EXT_APIC 0x00000008 -#define AMDID2_CR8 0x00000010 +#define AMDID2_LAHF 0x00000001 +#define AMDID2_CMP 0x00000002 +#define AMDID2_SVM 0x00000004 +#define AMDID2_EXT_APIC 0x00000008 +#define AMDID2_CR8 0x00000010 +#define AMDID2_PREFETCH 0x00000100 /* * CPUID instruction 1 ebx info @@ -145,29 +146,29 @@ /* * AMD extended function 8000_0008h ecx info */ -#define AMDID_CMP_CORES 0x000000ff +#define AMDID_CMP_CORES 0x000000ff /* * Model-specific registers for the i386 family */ -#define MSR_P5_MC_ADDR 0x000 -#define MSR_P5_MC_TYPE 0x001 -#define MSR_TSC 0x010 +#define MSR_P5_MC_ADDR 0x000 +#define MSR_P5_MC_TYPE 0x001 +#define MSR_TSC 0x010 #define MSR_P5_CESR 0x011 #define MSR_P5_CTR0 0x012 #define MSR_P5_CTR1 0x013 #define MSR_IA32_PLATFORM_ID 0x017 -#define MSR_APICBASE 0x01b -#define MSR_EBL_CR_POWERON 0x02a +#define MSR_APICBASE 0x01b +#define MSR_EBL_CR_POWERON 0x02a #define MSR_TEST_CTL 0x033 -#define MSR_BIOS_UPDT_TRIG 0x079 +#define MSR_BIOS_UPDT_TRIG 0x079 #define MSR_BBL_CR_D0 0x088 #define MSR_BBL_CR_D1 0x089 #define MSR_BBL_CR_D2 0x08a -#define MSR_BIOS_SIGN 0x08b -#define MSR_PERFCTR0 0x0c1 -#define MSR_PERFCTR1 0x0c2 -#define MSR_MTRRcap 0x0fe +#define MSR_BIOS_SIGN 0x08b +#define MSR_PERFCTR0 0x0c1 +#define MSR_PERFCTR1 0x0c2 +#define MSR_MTRRcap 0x0fe #define MSR_BBL_CR_ADDR 0x116 #define MSR_BBL_CR_DECC 0x118 #define MSR_BBL_CR_CTL 0x119 @@ -177,47 +178,47 @@ #define MSR_SYSENTER_CS_MSR 0x174 #define MSR_SYSENTER_ESP_MSR 0x175 #define MSR_SYSENTER_EIP_MSR 0x176 -#define MSR_MCG_CAP 0x179 -#define MSR_MCG_STATUS 0x17a -#define MSR_MCG_CTL 0x17b -#define MSR_EVNTSEL0 0x186 -#define MSR_EVNTSEL1 0x187 -#define MSR_THERM_CONTROL 0x19a -#define MSR_THERM_INTERRUPT 0x19b -#define MSR_THERM_STATUS 0x19c +#define MSR_MCG_CAP 0x179 +#define MSR_MCG_STATUS 0x17a +#define MSR_MCG_CTL 0x17b +#define MSR_EVNTSEL0 0x186 +#define MSR_EVNTSEL1 0x187 +#define MSR_THERM_CONTROL 0x19a +#define MSR_THERM_INTERRUPT 0x19b +#define MSR_THERM_STATUS 0x19c #define MSR_IA32_MISC_ENABLE 0x1a0 -#define MSR_DEBUGCTLMSR 0x1d9 -#define MSR_LASTBRANCHFROMIP 0x1db -#define MSR_LASTBRANCHTOIP 0x1dc -#define MSR_LASTINTFROMIP 0x1dd -#define MSR_LASTINTTOIP 0x1de -#define MSR_ROB_CR_BKUPTMPDR6 0x1e0 -#define MSR_MTRRVarBase 0x200 -#define MSR_MTRR64kBase 0x250 -#define MSR_MTRR16kBase 0x258 -#define MSR_MTRR4kBase 0x268 -#define MSR_PAT 0x277 -#define MSR_MTRRdefType 0x2ff -#define MSR_MC0_CTL 0x400 -#define MSR_MC0_STATUS 0x401 -#define MSR_MC0_ADDR 0x402 -#define MSR_MC0_MISC 0x403 -#define MSR_MC1_CTL 0x404 -#define MSR_MC1_STATUS 0x405 -#define MSR_MC1_ADDR 0x406 -#define MSR_MC1_MISC 0x407 -#define MSR_MC2_CTL 0x408 -#define MSR_MC2_STATUS 0x409 -#define MSR_MC2_ADDR 0x40a -#define MSR_MC2_MISC 0x40b -#define MSR_MC3_CTL 0x40c -#define MSR_MC3_STATUS 0x40d -#define MSR_MC3_ADDR 0x40e -#define MSR_MC3_MISC 0x40f -#define MSR_MC4_CTL 0x410 -#define MSR_MC4_STATUS 0x411 -#define MSR_MC4_ADDR 0x412 -#define MSR_MC4_MISC 0x413 +#define MSR_DEBUGCTLMSR 0x1d9 +#define MSR_LASTBRANCHFROMIP 0x1db +#define MSR_LASTBRANCHTOIP 0x1dc +#define MSR_LASTINTFROMIP 0x1dd +#define MSR_LASTINTTOIP 0x1de +#define MSR_ROB_CR_BKUPTMPDR6 0x1e0 +#define MSR_MTRRVarBase 0x200 +#define MSR_MTRR64kBase 0x250 +#define MSR_MTRR16kBase 0x258 +#define MSR_MTRR4kBase 0x268 +#define MSR_PAT 0x277 +#define MSR_MTRRdefType 0x2ff +#define MSR_MC0_CTL 0x400 +#define MSR_MC0_STATUS 0x401 +#define MSR_MC0_ADDR 0x402 +#define MSR_MC0_MISC 0x403 +#define MSR_MC1_CTL 0x404 +#define MSR_MC1_STATUS 0x405 +#define MSR_MC1_ADDR 0x406 +#define MSR_MC1_MISC 0x407 +#define MSR_MC2_CTL 0x408 +#define MSR_MC2_STATUS 0x409 +#define MSR_MC2_ADDR 0x40a +#define MSR_MC2_MISC 0x40b +#define MSR_MC3_CTL 0x40c +#define MSR_MC3_STATUS 0x40d +#define MSR_MC3_ADDR 0x40e +#define MSR_MC3_MISC 0x40f +#define MSR_MC4_CTL 0x410 +#define MSR_MC4_STATUS 0x411 +#define MSR_MC4_ADDR 0x412 +#define MSR_MC4_MISC 0x413 /* * Constants related to MSR's. @@ -242,9 +243,9 @@ /* * Constants related to MTRRs */ -#define MTRR_N64K 8 /* numbers of fixed-size entries */ -#define MTRR_N16K 16 -#define MTRR_N4K 64 +#define MTRR_N64K 8 /* numbers of fixed-size entries */ +#define MTRR_N16K 16 +#define MTRR_N4K 64 /* * Cyrix configuration registers, accessible as IO ports. @@ -277,7 +278,7 @@ #define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */ #define CCR2_WT1 0x10 /* WT region 1 */ #define CCR2_WPR1 0x10 /* Write-protect region 1 */ -#define CCR2_BARB 0x20 /* Flushes write-back cache when entering +#define CCR2_BARB 0x20 /* Flushes write-back cache when entering hold state. */ #define CCR2_BWRT 0x40 /* Enables burst write cycles */ #define CCR2_USE_SUSP 0x80 /* Enables suspend pins */ @@ -404,11 +405,11 @@ #define RCR6 0xe2 #define RCR7 0xe3 -#define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ -#define RCR_RCE 0x01 /* Enables caching for ARR7. */ -#define RCR_WWO 0x02 /* Weak write ordering. */ +#define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ +#define RCR_RCE 0x01 /* Enables caching for ARR7. */ +#define RCR_WWO 0x02 /* Weak write ordering. */ #define RCR_WL 0x04 /* Weak locking. */ -#define RCR_WG 0x08 /* Write gathering. */ +#define RCR_WG 0x08 /* Write gathering. */ #define RCR_WT 0x10 /* Write-through. */ #define RCR_NLB 0x20 /* LBA# pin is not asserted. */ @@ -418,40 +419,40 @@ #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ /* VIA ACE crypto featureset: for via_feature_rng */ -#define VIA_HAS_RNG 1 /* cpu has RNG */ +#define VIA_HAS_RNG 1 /* cpu has RNG */ /* VIA ACE crypto featureset: for via_feature_xcrypt */ -#define VIA_HAS_AES 1 /* cpu has AES */ -#define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ -#define VIA_HAS_MM 4 /* cpu has RSA instructions */ -#define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ +#define VIA_HAS_AES 1 /* cpu has AES */ +#define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ +#define VIA_HAS_MM 4 /* cpu has RSA instructions */ +#define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ /* Centaur Extended Feature flags */ -#define VIA_CPUID_HAS_RNG 0x000004 -#define VIA_CPUID_DO_RNG 0x000008 -#define VIA_CPUID_HAS_ACE 0x000040 -#define VIA_CPUID_DO_ACE 0x000080 -#define VIA_CPUID_HAS_ACE2 0x000100 -#define VIA_CPUID_DO_ACE2 0x000200 -#define VIA_CPUID_HAS_PHE 0x000400 -#define VIA_CPUID_DO_PHE 0x000800 -#define VIA_CPUID_HAS_PMM 0x001000 -#define VIA_CPUID_DO_PMM 0x002000 +#define VIA_CPUID_HAS_RNG 0x000004 +#define VIA_CPUID_DO_RNG 0x000008 +#define VIA_CPUID_HAS_ACE 0x000040 +#define VIA_CPUID_DO_ACE 0x000080 +#define VIA_CPUID_HAS_ACE2 0x000100 +#define VIA_CPUID_DO_ACE2 0x000200 +#define VIA_CPUID_HAS_PHE 0x000400 +#define VIA_CPUID_DO_PHE 0x000800 +#define VIA_CPUID_HAS_PMM 0x001000 +#define VIA_CPUID_DO_PMM 0x002000 /* VIA ACE xcrypt-* instruction context control options */ -#define VIA_CRYPT_CWLO_ROUND_M 0x0000000f -#define VIA_CRYPT_CWLO_ALG_M 0x00000070 -#define VIA_CRYPT_CWLO_ALG_AES 0x00000000 -#define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080 -#define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000 -#define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080 -#define VIA_CRYPT_CWLO_NORMAL 0x00000000 -#define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100 -#define VIA_CRYPT_CWLO_ENCRYPT 0x00000000 -#define VIA_CRYPT_CWLO_DECRYPT 0x00000200 -#define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */ -#define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */ -#define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */ +#define VIA_CRYPT_CWLO_ROUND_M 0x0000000f +#define VIA_CRYPT_CWLO_ALG_M 0x00000070 +#define VIA_CRYPT_CWLO_ALG_AES 0x00000000 +#define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080 +#define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000 +#define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080 +#define VIA_CRYPT_CWLO_NORMAL 0x00000000 +#define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100 +#define VIA_CRYPT_CWLO_ENCRYPT 0x00000000 +#define VIA_CRYPT_CWLO_DECRYPT 0x00000200 +#define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */ +#define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */ +#define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */ #ifndef LOCORE static __inline u_char |