diff options
Diffstat (limited to 'test/CodeGen/Mips')
66 files changed, 2822 insertions, 179 deletions
diff --git a/test/CodeGen/Mips/Fast-ISel/br1.ll b/test/CodeGen/Mips/Fast-ISel/br1.ll new file mode 100644 index 000000000000..579a77f88fef --- /dev/null +++ b/test/CodeGen/Mips/Fast-ISel/br1.ll @@ -0,0 +1,34 @@ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \ +; RUN: < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \ +; RUN: < %s | FileCheck %s + +@b = global i32 1, align 4 +@i = global i32 0, align 4 +@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 + +; Function Attrs: nounwind +define void @br() #0 { +entry: + %0 = load i32* @b, align 4 + %tobool = icmp eq i32 %0, 0 + br i1 %tobool, label %if.end, label %if.then + +if.then: ; preds = %entry + store i32 6754, i32* @i, align 4 + br label %if.end + +if.end: ; preds = %entry, %if.then + ret void +; FIXME: This instruction is redundant. +; CHECK: xor $[[REG1:[0-9]+]], ${{[0-9]+}}, $zero +; CHECK: sltiu $[[REG2:[0-9]+]], $[[REG1]], 1 +; CHECK: bgtz $[[REG2]], $BB[[BL:[0-9]+_[0-9]+]] +; CHECK: nop +; CHECK: addiu ${{[0-9]+}}, $zero, 6754 +; CHECK: sw ${{[0-9]+}}, 0(${{[0-9]+}}) +; CHECK: $BB[[BL]]: + +} + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/Mips/Fast-ISel/callabi.ll b/test/CodeGen/Mips/Fast-ISel/callabi.ll new file mode 100644 index 000000000000..e76d7a74bd0e --- /dev/null +++ b/test/CodeGen/Mips/Fast-ISel/callabi.ll @@ -0,0 +1,477 @@ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \ +; RUN: < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \ +; RUN: < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \ +; RUN: < %s | FileCheck %s -check-prefix=mips32r2 +; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \ +; RUN: < %s | FileCheck %s -check-prefix=mips32 +; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \ +; RUN: < %s | FileCheck %s -check-prefix=CHECK2 +; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \ +; RUN: < %s | FileCheck %s -check-prefix=CHECK2 + + +@c1 = global i8 -45, align 1 +@uc1 = global i8 27, align 1 +@s1 = global i16 -1789, align 2 +@us1 = global i16 1256, align 2 + +; Function Attrs: nounwind +define void @cxi() #0 { +entry: +; CHECK-LABEL: cxi + call void @xi(i32 10) +; CHECK-DAG: addiu $4, $zero, 10 +; CHECK-DAG: lw $25, %got(xi)(${{[0-9]+}}) +; CHECK: jalr $25 + + ret void +} + +declare void @xi(i32) #1 + +; Function Attrs: nounwind +define void @cxii() #0 { +entry: +; CHECK-LABEL: cxii + call void @xii(i32 746, i32 892) +; CHECK-DAG: addiu $4, $zero, 746 +; CHECK-DAG: addiu $5, $zero, 892 +; CHECK-DAG: lw $25, %got(xii)(${{[0-9]+}}) +; CHECK: jalr $25 + + ret void +} + +declare void @xii(i32, i32) #1 + +; Function Attrs: nounwind +define void @cxiii() #0 { +entry: +; CHECK-LABEL: cxiii + call void @xiii(i32 88, i32 44, i32 11) +; CHECK-DAG: addiu $4, $zero, 88 +; CHECK-DAG: addiu $5, $zero, 44 +; CHECK-DAG: addiu $6, $zero, 11 +; CHECK-DAG: lw $25, %got(xiii)(${{[0-9]+}}) +; CHECK: jalr $25 + ret void +} + +declare void @xiii(i32, i32, i32) #1 + +; Function Attrs: nounwind +define void @cxiiii() #0 { +entry: +; CHECK-LABEL: cxiiii + call void @xiiii(i32 167, i32 320, i32 97, i32 14) +; CHECK-DAG: addiu $4, $zero, 167 +; CHECK-DAG: addiu $5, $zero, 320 +; CHECK-DAG: addiu $6, $zero, 97 +; CHECK-DAG: addiu $7, $zero, 14 +; CHECK-DAG: lw $25, %got(xiiii)(${{[0-9]+}}) +; CHECK: jalr $25 + + ret void +} + +declare void @xiiii(i32, i32, i32, i32) #1 + +; Function Attrs: nounwind +define void @cxiiiiconv() #0 { +entry: +; CHECK-LABEL: cxiiiiconv +; mips32r2-LABEL: cxiiiiconv +; mips32-LABEL: cxiiiiconv + %0 = load i8* @c1, align 1 + %conv = sext i8 %0 to i32 + %1 = load i8* @uc1, align 1 + %conv1 = zext i8 %1 to i32 + %2 = load i16* @s1, align 2 + %conv2 = sext i16 %2 to i32 + %3 = load i16* @us1, align 2 + %conv3 = zext i16 %3 to i32 + call void @xiiii(i32 %conv, i32 %conv1, i32 %conv2, i32 %conv3) +; CHECK: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} +; mips32r2: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} +; mips32: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} +; mips32r2-DAG: lw $[[REG_C1_ADDR:[0-9]+]], %got(c1)($[[REG_GP]]) +; mips32r2-DAG: lbu $[[REG_C1:[0-9]+]], 0($[[REG_C1_ADDR]]) +; mips32r2-DAG seb $3, $[[REG_C1]] +; mips32-DAG: lw $[[REG_C1_ADDR:[0-9]+]], %got(c1)($[[REG_GP]]) +; mips32-DAG: lbu $[[REG_C1:[0-9]+]], 0($[[REG_C1_ADDR]]) +; mips32-DAG: sll $[[REG_C1_1:[0-9]+]], $[[REG_C1]], 24 +; mips32-DAG: sra $4, $[[REG_C1_1]], 24 +; CHECK-DAG: lw $[[REG_UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]]) +; CHECK-DAG: lbu $[[REG_UC1:[0-9]+]], 0($[[REG_UC1_ADDR]]) +; FIXME andi is superfulous +; CHECK-DAG: andi $5, $[[REG_UC1]], 255 +; mips32r2-DAG: lw $[[REG_S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]]) +; mips32r2-DAG: lhu $[[REG_S1:[0-9]+]], 0($[[REG_S1_ADDR]]) +; mips32r2-DAG: seh $6, $[[REG_S1]] +; mips32-DAG: lw $[[REG_S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]]) +; mips32-DAG: lhu $[[REG_S1:[0-9]+]], 0($[[REG_S1_ADDR]]) +; mips32-DAG: sll $[[REG_S1_1:[0-9]+]], $[[REG_S1]], 16 +; mips32-DAG: sra $6, $[[REG_S1_1]], 16 +; CHECK-DAG: lw $[[REG_US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]]) +; CHECK-DAG: lhu $[[REG_US1:[0-9]+]], 0($[[REG_US1_ADDR]]) +; FIXME andi is superfulous +; CHECK-DAG: andi $7, $[[REG_US1]], 65535 +; mips32r2: jalr $25 +; mips32r2: jalr $25 +; CHECK: jalr $25 + ret void +} + +; Function Attrs: nounwind +define void @cxf() #0 { +entry: +; CHECK-LABEL: cxf + call void @xf(float 0x40BBC85560000000) +; CHECK: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} +; CHECK: lui $[[REG_FPCONST_1:[0-9]+]], 17886 +; CHECK: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 17067 +; CHECK: mtc1 $[[REG_FPCONST]], $f12 +; CHECK: lw $25, %got(xf)($[[REG_GP]]) +; CHECK: jalr $25 + ret void +} + +declare void @xf(float) #1 + +; Function Attrs: nounwind +define void @cxff() #0 { +entry: +; CHECK-LABEL: cxff + call void @xff(float 0x3FF74A6CA0000000, float 0x401A2C0840000000) +; CHECK: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} +; CHECK-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16314 +; CHECK-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 21349 +; CHECK-DAG: mtc1 $[[REG_FPCONST]], $f12 +; CHECK-DAG: lui $[[REG_FPCONST_2:[0-9]+]], 16593 +; CHECK-DAG: ori $[[REG_FPCONST_3:[0-9]+]], $[[REG_FPCONST_2]], 24642 +; CHECK-DAG: mtc1 $[[REG_FPCONST_3]], $f14 +; CHECK: lw $25, %got(xff)($[[REG_GP]]) +; CHECK: jalr $25 + ret void +} + +declare void @xff(float, float) #1 + +; Function Attrs: nounwind +define void @cxfi() #0 { +entry: +; CHECK-LABEL: cxfi + call void @xfi(float 0x4013906240000000, i32 102) +; CHECK: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} +; CHECK-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16540 +; CHECK-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 33554 +; CHECK-DAG: mtc1 $[[REG_FPCONST]], $f12 +; CHECK-DAG: addiu $5, $zero, 102 +; CHECK: lw $25, %got(xfi)($[[REG_GP]]) +; CHECK: jalr $25 + + ret void +} + +declare void @xfi(float, i32) #1 + +; Function Attrs: nounwind +define void @cxfii() #0 { +entry: +; CHECK-LABEL: cxfii + call void @xfii(float 0x405EC7EE00000000, i32 9993, i32 10922) +; CHECK: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} +; CHECK-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 17142 +; CHECK-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 16240 +; CHECK-DAG: mtc1 $[[REG_FPCONST]], $f12 +; CHECK-DAG: addiu $5, $zero, 9993 +; CHECK-DAG: addiu $6, $zero, 10922 +; CHECK: lw $25, %got(xfii)($[[REG_GP]]) +; CHECK: jalr $25 + ret void +} + +declare void @xfii(float, i32, i32) #1 + +; Function Attrs: nounwind +define void @cxfiii() #0 { +entry: +; CHECK-LABEL: cxfiii + call void @xfiii(float 0x405C072B20000000, i32 3948, i32 89011, i32 111222) +; CHECK: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} +; CHECK-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 17120 +; CHECK-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 14681 +; CHECK-DAG: mtc1 $[[REG_FPCONST]], $f12 +; CHECK-DAG: addiu $5, $zero, 3948 +; CHECK-DAG: lui $[[REG_I_1:[0-9]+]], 1 +; CHECK-DAG: ori $6, $[[REG_I_1]], 23475 +; CHECK-DAG: lui $[[REG_I_2:[0-9]+]], 1 +; CHECK-DAG: ori $7, $[[REG_I_2]], 45686 +; CHECK: lw $25, %got(xfiii)($[[REG_GP]]) +; CHECK: jalr $25 + ret void +} + +declare void @xfiii(float, i32, i32, i32) #1 + +; Function Attrs: nounwind +define void @cxd() #0 { +entry: +; mips32r2-LABEL: cxd: +; mips32-LABEL: cxd: + call void @xd(double 5.994560e+02) +; mips32: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} +; mips32-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16514 +; mips32-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 48037 +; mips32-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 58195 +; mips32-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 63439 +; mips32-DAG: mtc1 $[[REG_FPCONST_4]], $f12 +; mips32-DAG: mtc1 $[[REG_FPCONST_2]], $f13 +; mips32-DAG: lw $25, %got(xd)($[[REG_GP]]) +; mips32: jalr $25 +; mips32r2: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} +; mips32r2-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16514 +; mips32r2-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 48037 +; mips32r2-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 58195 +; mips32r2-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 63439 +; mips32r2-DAG: mtc1 $[[REG_FPCONST_4]], $f12 +; mips32r2-DAG: mthc1 $[[REG_FPCONST_2]], $f12 +; mips32r2-DAG: lw $25, %got(xd)($[[REG_GP]]) +; mips32r2 : jalr $25 + ret void +} + +declare void @xd(double) #1 + +; Function Attrs: nounwind +define void @cxdd() #0 { +; mips32r2-LABEL: cxdd: +; mips32-LABEL: cxdd: +entry: + call void @xdd(double 1.234980e+03, double 0x40F5B331F7CED917) +; mips32: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} +; mips32-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16531 +; mips32-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 19435 +; mips32-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 34078 +; mips32-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 47186 +; mips32-DAG: mtc1 $[[REG_FPCONST_4]], $f12 +; mips32-DAG: mtc1 $[[REG_FPCONST_2]], $f13 +; mips32-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16629 +; mips32-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 45873 +; mips32-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 63438 +; mips32-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 55575 +; mips32-DAG: mtc1 $[[REG_FPCONST_4]], $f14 +; mips32-DAG: mtc1 $[[REG_FPCONST_2]], $f15 +; mips32-DAG: lw $25, %got(xdd)($[[REG_GP]]) +; mips32: jalr $25 +; mips32r2: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} +; mips32r2-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16531 +; mips32r2-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 19435 +; mips32r2-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 34078 +; mips32r2-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 47186 +; mips32r2-DAG: mtc1 $[[REG_FPCONST_4]], $f12 +; mips32r2-DAG: mthc1 $[[REG_FPCONST_2]], $f12 +; mips32r2-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16629 +; mips32r2-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 45873 +; mips32r2-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 63438 +; mips32r2-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 55575 +; mips32r2-DAG: mtc1 $[[REG_FPCONST_4]], $f14 +; mips32r2-DAG: mthc1 $[[REG_FPCONST_2]], $f14 +; mips32r2-DAG: lw $25, %got(xdd)($[[REG_GP]]) +; mips32r2 : jalr $25 + ret void +} + +declare void @xdd(double, double) #1 + +; Function Attrs: nounwind +define void @cxif() #0 { +entry: +; CHECK-LABEL: cxif: + call void @xif(i32 345, float 0x407BCE5A20000000) +; CHECK-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} +; CHECK-DAG: addiu $4, $zero, 345 +; CHECK-DAG: lui $[[REGF_1:[0-9]+]], 17374 +; CHECK-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 29393 +; CHECK-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]] +; CHECK-DAG: mfc1 $5, $f[[REGF_3]] +; CHECK-DAG: lw $25, %got(xif)($[[REG_GP]]) +; CHECK: jalr $25 + + ret void +} + +declare void @xif(i32, float) #1 + +; Function Attrs: nounwind +define void @cxiff() #0 { +entry: +; CHECK-LABEL: cxiff: +; CHECK2-LABEL: cxiff: + call void @xiff(i32 12239, float 0x408EDB3340000000, float 0x4013FFE5C0000000) +; We need to do the two floating point parameters in a separate +; check because we can't control the ordering of parts of the sequence +;; +; CHECK: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} +; CHECK: addiu $4, $zero, 12239 +; CHECK2: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} +; CHECK2: addiu $4, $zero, 12239 +; CHECK: lui $[[REGF_1:[0-9]+]], 17526 +; CHECK: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 55706 +; CHECK: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]] +; CHECK: mfc1 $5, $f[[REGF_3]] +; CHECK2: lui $[[REGF2_1:[0-9]+]], 16543 +; CHECK2: ori $[[REGF2_2:[0-9]+]], $[[REGF2_1]], 65326 +; CHECK2: mtc1 $[[REGF2_2]], $f[[REGF2_3:[0-9]+]] +; CHECK2: mfc1 $6, $f[[REGF2_3]] +; CHECK: lw $25, %got(xiff)($[[REG_GP]]) +; CHECK2: lw $25, %got(xiff)($[[REG_GP]]) +; CHECK: jalr $25 +; CHECK2: jalr $25 + ret void +} + +declare void @xiff(i32, float, float) #1 + +; Function Attrs: nounwind +define void @cxifi() #0 { +entry: +; CHECK: cxifi: + call void @xifi(i32 887, float 0x402277CEE0000000, i32 888) +; CHECK-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} +; CHECK-DAG: addiu $4, $zero, 887 +; CHECK-DAG: lui $[[REGF_1:[0-9]+]], 16659 +; CHECK-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 48759 +; CHECK-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]] +; CHECK-DAG: mfc1 $5, $f[[REGF_3]] +; CHECk-DAG: addiu $6, $zero, 888 +; CHECK-DAG: lw $25, %got(xifi)($[[REG_GP]]) +; CHECK: jalr $25 + + ret void +} + +declare void @xifi(i32, float, i32) #1 + +; Function Attrs: nounwind +define void @cxifif() #0 { +entry: +; CHECK: cxifif: +; CHECK2: cxifif: + call void @xifif(i32 67774, float 0x408EE0FBE0000000, i32 9991, float 0x40B15C8CC0000000) +; CHECK-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} +; CHECK-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} +; CHECK-DAG: lui $[[REGI:[0-9]+]], 1 +; CHECK-DAG: ori $4, $[[REGI]], 2238 +; CHECK-DAG: lui $[[REGF_1:[0-9]+]], 17527 +; CHECK-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 2015 +; CHECK-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]] +; CHECK-DAG: mfc1 $5, $f[[REGF_3]] +; CHECk-DAG: addiu $6, $zero, 888 +; CHECK2: lui $[[REGF2_1:[0-9]+]], 17802 +; CHECK2: ori $[[REGF2_2:[0-9]+]], $[[REGF2_1]], 58470 +; CHECK2: mtc1 $[[REGF2_2]], $f[[REGF2_3:[0-9]+]] +; CHECK2: mfc1 $7, $f[[REGF2_3]] +; CHECK: lw $25, %got(xifif)($[[REG_GP]]) +; CHECK2: lw $25, %got(xifif)($[[REG_GP]]) +; CHECK2: jalr $25 +; CHECK: jalr $25 + + ret void +} + +declare void @xifif(i32, float, i32, float) #1 + +; Function Attrs: nounwind +define void @cxiffi() #0 { +entry: +; CHECK-label: cxiffi: +; CHECK2-label: cxiffi: + call void @xiffi(i32 45, float 0x3FF6666660000000, float 0x408F333340000000, i32 234) +; CHECK-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} +; CHECK-DAG: addiu $4, $zero, 45 +; CHECK2-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} +; CHECK2-DAG: addiu $4, $zero, 45 +; CHECK-DAG: lui $[[REGF_1:[0-9]+]], 16307 +; CHECK-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 13107 +; CHECK-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]] +; CHECK-DAG: mfc1 $5, $f[[REGF_3]] +; CHECK2: lui $[[REGF2_1:[0-9]+]], 17529 +; CHECK2: ori $[[REGF2_2:[0-9]+]], $[[REGF2_1]], 39322 +; CHECK2: mtc1 $[[REGF2_2]], $f[[REGF2_3:[0-9]+]] +; CHECK2: mfc1 $6, $f[[REGF2_3]] +; CHECK-DAG: lw $25, %got(xiffi)($[[REG_GP]]) +; CHECK-DAG: addiu $7, $zero, 234 +; CHECK2-DAG: lw $25, %got(xiffi)($[[REG_GP]]) +; CHECK: jalr $25 +; CHECK2: jalr $25 + + ret void +} + +declare void @xiffi(i32, float, float, i32) #1 + +; Function Attrs: nounwind +define void @cxifii() #0 { +entry: +; CHECK-DAG: cxifii: + call void @xifii(i32 12239, float 0x408EDB3340000000, i32 998877, i32 1234) +; CHECK-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}} +; CHECK-DAG: addiu $4, $zero, 12239 +; CHECK-DAG: lui $[[REGF_1:[0-9]+]], 17526 +; CHECK-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 55706 +; CHECK-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]] +; CHECK-DAG: mfc1 $5, $f[[REGF_3]] +; CHECK-DAG: lui $[[REGI2:[0-9]+]], 15 +; CHECK-DAG: ori $6, $[[REGI2]], 15837 +; CHECk-DAG: addiu $7, $zero, 1234 +; CHECK-DAG: lw $25, %got(xifii)($[[REG_GP]]) +; CHECK: jalr $25 + ret void +} + +declare void @xifii(i32, float, i32, i32) #1 + +; FIXME: this function will not pass yet. +; Function Attrs: nounwind +; define void @cxfid() #0 { +;entry: +; call void @xfid(float 0x4013B851E0000000, i32 811123, double 0x40934BFF487FCB92) +; ret void +;} + +declare void @xfid(float, i32, double) #1 + +; Function Attrs: nounwind +define void @g() #0 { +entry: + call void @cxi() + call void @cxii() + call void @cxiii() + call void @cxiiii() + call void @cxiiiiconv() + call void @cxf() + call void @cxff() + call void @cxd() + call void @cxfi() + call void @cxfii() + call void @cxfiii() + call void @cxdd() + call void @cxif() + call void @cxiff() + call void @cxifi() + call void @cxifii() + call void @cxifif() + call void @cxiffi() + ret void +} + + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } + +!llvm.ident = !{!0} + +!0 = !{!"clang version 3.6.0 (gitosis@dmz-portal.mips.com:clang 43992fe7b17de5553ac06d323cb80cc6723a9ae3) (gitosis@dmz-portal.mips.com:llvm.git 0834e6839eb170197c81bb02e916258d1527e312)"} diff --git a/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll b/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll new file mode 100644 index 000000000000..c72b1e70c718 --- /dev/null +++ b/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll @@ -0,0 +1,254 @@ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \ +; RUN: < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \ +; RUN: < %s | FileCheck %s + +@f1 = common global float 0.000000e+00, align 4 +@f2 = common global float 0.000000e+00, align 4 +@b1 = common global i32 0, align 4 +@d1 = common global double 0.000000e+00, align 8 +@d2 = common global double 0.000000e+00, align 8 + +; Function Attrs: nounwind +define void @feq1() { +entry: + %0 = load float* @f1, align 4 + %1 = load float* @f2, align 4 + %cmp = fcmp oeq float %0, %1 +; CHECK-LABEL: feq1: +; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}}) +; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}}) +; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]]) +; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]]) +; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 +; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 +; CHECK: c.eq.s $f[[REG_F1]], $f[[REG_F2]] +; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0 + + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @b1, align 4 + ret void +} + +; Function Attrs: nounwind +define void @fne1() { +entry: + %0 = load float* @f1, align 4 + %1 = load float* @f2, align 4 + %cmp = fcmp une float %0, %1 +; CHECK-LABEL: fne1: +; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}}) +; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}}) +; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]]) +; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]]) +; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 +; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 +; CHECK: c.eq.s $f[[REG_F1]], $f[[REG_F2]] +; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0 + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @b1, align 4 + ret void +} + +; Function Attrs: nounwind +define void @flt1() { +entry: + %0 = load float* @f1, align 4 + %1 = load float* @f2, align 4 + %cmp = fcmp olt float %0, %1 +; CHECK-LABEL: flt1: +; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}}) +; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}}) +; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]]) +; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]]) +; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 +; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 +; CHECK: c.olt.s $f[[REG_F1]], $f[[REG_F2]] +; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0 + + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @b1, align 4 + ret void +} + +; Function Attrs: nounwind +define void @fgt1() { +entry: + %0 = load float* @f1, align 4 + %1 = load float* @f2, align 4 + %cmp = fcmp ogt float %0, %1 +; CHECK-LABEL: fgt1: +; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}}) +; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}}) +; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]]) +; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]]) +; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 +; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 +; CHECK: c.ule.s $f[[REG_F1]], $f[[REG_F2]] +; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0 + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @b1, align 4 + ret void +} + +; Function Attrs: nounwind +define void @fle1() { +entry: + %0 = load float* @f1, align 4 + %1 = load float* @f2, align 4 + %cmp = fcmp ole float %0, %1 +; CHECK-LABEL: fle1: +; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}}) +; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}}) +; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]]) +; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]]) +; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 +; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 +; CHECK: c.ole.s $f[[REG_F1]], $f[[REG_F2]] +; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0 + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @b1, align 4 + ret void +} + +; Function Attrs: nounwind +define void @fge1() { +entry: + %0 = load float* @f1, align 4 + %1 = load float* @f2, align 4 + %cmp = fcmp oge float %0, %1 +; CHECK-LABEL: fge1: +; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}}) +; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}}) +; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]]) +; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]]) +; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 +; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 +; CHECK: c.ult.s $f[[REG_F1]], $f[[REG_F2]] +; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0 + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @b1, align 4 + ret void +} + +; Function Attrs: nounwind +define void @deq1() { +entry: + %0 = load double* @d1, align 8 + %1 = load double* @d2, align 8 + %cmp = fcmp oeq double %0, %1 +; CHECK-LABEL: deq1: +; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}}) +; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}}) +; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]]) +; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]]) +; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 +; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 +; CHECK: c.eq.d $f[[REG_D1]], $f[[REG_D2]] +; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0 + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @b1, align 4 + ret void +} + +; Function Attrs: nounwind +define void @dne1() { +entry: + %0 = load double* @d1, align 8 + %1 = load double* @d2, align 8 + %cmp = fcmp une double %0, %1 +; CHECK-LABEL: dne1: +; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}}) +; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}}) +; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]]) +; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]]) +; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 +; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 +; CHECK: c.eq.d $f[[REG_D1]], $f[[REG_D2]] +; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0 + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @b1, align 4 + ret void +} + +; Function Attrs: nounwind +define void @dlt1() { +entry: + %0 = load double* @d1, align 8 + %1 = load double* @d2, align 8 + %cmp = fcmp olt double %0, %1 +; CHECK-LABEL: dlt1: +; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}}) +; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}}) +; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]]) +; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]]) +; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 +; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 +; CHECK: c.olt.d $f[[REG_D1]], $f[[REG_D2]] +; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0 + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @b1, align 4 + ret void +} + +; Function Attrs: nounwind +define void @dgt1() { +entry: + %0 = load double* @d1, align 8 + %1 = load double* @d2, align 8 + %cmp = fcmp ogt double %0, %1 +; CHECK-LABEL: dgt1: +; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}}) +; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}}) +; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]]) +; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]]) +; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 +; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 +; CHECK: c.ule.d $f[[REG_D1]], $f[[REG_D2]] +; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0 + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @b1, align 4 + ret void +} + +; Function Attrs: nounwind +define void @dle1() { +entry: + %0 = load double* @d1, align 8 + %1 = load double* @d2, align 8 + %cmp = fcmp ole double %0, %1 +; CHECK-LABEL: dle1: +; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}}) +; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}}) +; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]]) +; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]]) +; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 +; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 +; CHECK: c.ole.d $f[[REG_D1]], $f[[REG_D2]] +; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0 + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @b1, align 4 + ret void +} + +; Function Attrs: nounwind +define void @dge1() { +entry: + %0 = load double* @d1, align 8 + %1 = load double* @d2, align 8 + %cmp = fcmp oge double %0, %1 +; CHECK-LABEL: dge1: +; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}}) +; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}}) +; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]]) +; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]]) +; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 +; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 +; CHECK: c.ult.d $f[[REG_D1]], $f[[REG_D2]] +; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0 + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @b1, align 4 + ret void +} + + diff --git a/test/CodeGen/Mips/Fast-ISel/fpext.ll b/test/CodeGen/Mips/Fast-ISel/fpext.ll new file mode 100644 index 000000000000..98aca756c58f --- /dev/null +++ b/test/CodeGen/Mips/Fast-ISel/fpext.ll @@ -0,0 +1,21 @@ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \ +; RUN: < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \ +; RUN: < %s | FileCheck %s + +@f = global float 0x40147E6B80000000, align 4 +@d_f = common global double 0.000000e+00, align 8 +@.str = private unnamed_addr constant [6 x i8] c"%f \0A\00", align 1 + +; Function Attrs: nounwind +define void @dv() #0 { +entry: + %0 = load float* @f, align 4 + %conv = fpext float %0 to double +; CHECK: cvt.d.s $f{{[0-9]+}}, $f{{[0-9]+}} + store double %conv, double* @d_f, align 8 + ret void +} + + +attributes #1 = { nounwind } diff --git a/test/CodeGen/Mips/Fast-ISel/fpintconv.ll b/test/CodeGen/Mips/Fast-ISel/fpintconv.ll new file mode 100644 index 000000000000..846726a868b3 --- /dev/null +++ b/test/CodeGen/Mips/Fast-ISel/fpintconv.ll @@ -0,0 +1,35 @@ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \ +; RUN: < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \ +; RUN: < %s | FileCheck %s + + +@f = global float 0x40D6E83280000000, align 4 +@d = global double 0x4132D68780000000, align 8 +@i_f = common global i32 0, align 4 +@i_d = common global i32 0, align 4 +@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 + +; Function Attrs: nounwind +define void @ifv() { +entry: +; CHECK-LABEL: .ent ifv + %0 = load float* @f, align 4 + %conv = fptosi float %0 to i32 +; CHECK: trunc.w.s $f[[REG:[0-9]+]], $f{{[0-9]+}} +; CHECK: mfc1 ${{[0-9]+}}, $f[[REG]] + store i32 %conv, i32* @i_f, align 4 + ret void +} + +; Function Attrs: nounwind +define void @idv() { +entry: +; CHECK-LABEL: .ent idv + %0 = load double* @d, align 8 + %conv = fptosi double %0 to i32 +; CHECK: trunc.w.d $f[[REG:[0-9]+]], $f{{[0-9]+}} +; CHECK: mfc1 ${{[0-9]+}}, $f[[REG]] + store i32 %conv, i32* @i_d, align 4 + ret void +} diff --git a/test/CodeGen/Mips/Fast-ISel/fptrunc.ll b/test/CodeGen/Mips/Fast-ISel/fptrunc.ll new file mode 100644 index 000000000000..d843dee5a8c9 --- /dev/null +++ b/test/CodeGen/Mips/Fast-ISel/fptrunc.ll @@ -0,0 +1,20 @@ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \ +; RUN: < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \ +; RUN: < %s | FileCheck %s + +@d = global double 0x40147E6B74DF0446, align 8 +@f = common global float 0.000000e+00, align 4 +@.str = private unnamed_addr constant [6 x i8] c"%f \0A\00", align 1 + +; Function Attrs: nounwind +define void @fv() #0 { +entry: + %0 = load double* @d, align 8 + %conv = fptrunc double %0 to float +; CHECK: cvt.s.d $f{{[0-9]+}}, $f{{[0-9]+}} + store float %conv, float* @f, align 4 + ret void +} + +attributes #1 = { nounwind } diff --git a/test/CodeGen/Mips/Fast-ISel/icmpa.ll b/test/CodeGen/Mips/Fast-ISel/icmpa.ll new file mode 100644 index 000000000000..bd41a2911dc4 --- /dev/null +++ b/test/CodeGen/Mips/Fast-ISel/icmpa.ll @@ -0,0 +1,210 @@ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \ +; RUN: < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \ +; RUN: < %s | FileCheck %s + +@c = global i32 4, align 4 +@d = global i32 9, align 4 +@uc = global i32 4, align 4 +@ud = global i32 9, align 4 +@b1 = common global i32 0, align 4 + +; Function Attrs: nounwind +define void @eq() { +entry: +; CHECK-LABEL: .ent eq + + %0 = load i32* @c, align 4 + %1 = load i32* @d, align 4 + %cmp = icmp eq i32 %0, %1 + %conv = zext i1 %cmp to i32 +; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}}) +; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}}) +; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]]) +; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]]) +; CHECK: xor $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]] +; CHECK: sltiu $[[REG2:[0-9]+]], $[[REG1]], 1 +; FIXME: This instruction is redundant. The sltiu can only produce 0 and 1. +; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1 + + store i32 %conv, i32* @b1, align 4 + ret void +} + +; Function Attrs: nounwind +define void @ne() { +entry: +; CHECK-LABEL: .ent ne + %0 = load i32* @c, align 4 + %1 = load i32* @d, align 4 + %cmp = icmp ne i32 %0, %1 + %conv = zext i1 %cmp to i32 +; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}}) +; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}}) +; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]]) +; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]]) +; CHECK: xor $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]] +; CHECK: sltu $[[REG2:[0-9]+]], $zero, $[[REG1]] +; FIXME: This instruction is redundant. The sltu can only produce 0 and 1. +; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1 + + store i32 %conv, i32* @b1, align 4 + ret void +} + +; Function Attrs: nounwind +define void @ugt() { +entry: +; CHECK-LABEL: .ent ugt + %0 = load i32* @uc, align 4 + %1 = load i32* @ud, align 4 + %cmp = icmp ugt i32 %0, %1 + %conv = zext i1 %cmp to i32 +; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}}) +; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}}) +; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]]) +; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]]) +; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UD]], $[[REG_UC]] +; FIXME: This instruction is redundant. The sltu can only produce 0 and 1. +; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1 + + store i32 %conv, i32* @b1, align 4 + ret void +} + +; Function Attrs: nounwind +define void @ult() { +entry: +; CHECK-LABEL: .ent ult + %0 = load i32* @uc, align 4 + %1 = load i32* @ud, align 4 + %cmp = icmp ult i32 %0, %1 + %conv = zext i1 %cmp to i32 +; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}}) +; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}}) +; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]]) +; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]]) +; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UC]], $[[REG_UD]] +; FIXME: This instruction is redundant. The sltu can only produce 0 and 1. +; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1 + store i32 %conv, i32* @b1, align 4 + ret void +} + +; Function Attrs: nounwind +define void @uge() { +entry: +; CHECK-LABEL: .ent uge + %0 = load i32* @uc, align 4 + %1 = load i32* @ud, align 4 + %cmp = icmp uge i32 %0, %1 + %conv = zext i1 %cmp to i32 +; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}}) +; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}}) +; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]]) +; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]]) +; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UC]], $[[REG_UD]] +; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1 +; FIXME: This instruction is redundant. The sltu can only produce 0 and 1. +; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1 + store i32 %conv, i32* @b1, align 4 + ret void +} + +; Function Attrs: nounwind +define void @ule() { +entry: +; CHECK-LABEL: .ent ule + %0 = load i32* @uc, align 4 + %1 = load i32* @ud, align 4 + %cmp = icmp ule i32 %0, %1 + %conv = zext i1 %cmp to i32 +; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}}) +; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}}) +; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]]) +; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]]) +; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UD]], $[[REG_UC]] +; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1 +; FIXME: This instruction is redundant. The sltu can only produce 0 and 1. +; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1 + store i32 %conv, i32* @b1, align 4 + ret void +} + +; Function Attrs: nounwind +define void @sgt() { +entry: +; CHECK-LABEL: .ent sgt + %0 = load i32* @c, align 4 + %1 = load i32* @d, align 4 + %cmp = icmp sgt i32 %0, %1 + %conv = zext i1 %cmp to i32 +; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}}) +; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}}) +; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]]) +; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]]) +; CHECK: slt $[[REG1:[0-9]+]], $[[REG_D]], $[[REG_C]] +; FIXME: This instruction is redundant. The slt can only produce 0 and 1. +; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1 + store i32 %conv, i32* @b1, align 4 + ret void +} + +; Function Attrs: nounwind +define void @slt() { +entry: +; CHECK-LABEL: .ent slt + %0 = load i32* @c, align 4 + %1 = load i32* @d, align 4 + %cmp = icmp slt i32 %0, %1 + %conv = zext i1 %cmp to i32 +; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}}) +; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}}) +; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]]) +; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]]) +; CHECK: slt $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]] +; FIXME: This instruction is redundant. The slt can only produce 0 and 1. +; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1 + store i32 %conv, i32* @b1, align 4 + ret void +} + +; Function Attrs: nounwind +define void @sge() { +entry: +; CHECK-LABEL: .ent sge + %0 = load i32* @c, align 4 + %1 = load i32* @d, align 4 + %cmp = icmp sge i32 %0, %1 + %conv = zext i1 %cmp to i32 + store i32 %conv, i32* @b1, align 4 +; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}}) +; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}}) +; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]]) +; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]]) +; CHECK: slt $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]] +; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1 +; FIXME: This instruction is redundant. The slt can only produce 0 and 1. +; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1 + ret void +} + +; Function Attrs: nounwind +define void @sle() { +entry: +; CHECK-LABEL: .ent sle + %0 = load i32* @c, align 4 + %1 = load i32* @d, align 4 + %cmp = icmp sle i32 %0, %1 + %conv = zext i1 %cmp to i32 +; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}}) +; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}}) +; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]]) +; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]]) +; CHECK: slt $[[REG1:[0-9]+]], $[[REG_D]], $[[REG_C]] +; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1 +; FIXME: This instruction is redundant. The slt can only produce 0 and 1. +; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1 + store i32 %conv, i32* @b1, align 4 + ret void +} diff --git a/test/CodeGen/Mips/Fast-ISel/loadstore2.ll b/test/CodeGen/Mips/Fast-ISel/loadstore2.ll index f113a0eb1d54..d84478b9c5a9 100644 --- a/test/CodeGen/Mips/Fast-ISel/loadstore2.ll +++ b/test/CodeGen/Mips/Fast-ISel/loadstore2.ll @@ -6,6 +6,8 @@ target triple = "mips--linux-gnu" @c1 = common global i8 0, align 1 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \ +; RUN: < %s | FileCheck %s @s2 = common global i16 0, align 2 @s1 = common global i16 0, align 2 diff --git a/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll b/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll new file mode 100644 index 000000000000..f7f2c6481b3c --- /dev/null +++ b/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll @@ -0,0 +1,179 @@ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \ +; RUN: < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \ +; RUN: < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \ +; RUN: < %s | FileCheck %s -check-prefix=mips32r2 +; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \ +; RUN: < %s | FileCheck %s -check-prefix=mips32 + +@b2 = global i8 0, align 1 +@b1 = global i8 1, align 1 +@uc1 = global i8 0, align 1 +@uc2 = global i8 -1, align 1 +@sc1 = global i8 -128, align 1 +@sc2 = global i8 127, align 1 +@ss1 = global i16 -32768, align 2 +@ss2 = global i16 32767, align 2 +@us1 = global i16 0, align 2 +@us2 = global i16 -1, align 2 +@ssi = global i16 0, align 2 +@ssj = global i16 0, align 2 +@i = global i32 0, align 4 +@j = global i32 0, align 4 +@.str = private unnamed_addr constant [4 x i8] c"%i\0A\00", align 1 +@.str1 = private unnamed_addr constant [7 x i8] c"%i %i\0A\00", align 1 + +; Function Attrs: nounwind +define void @_Z3b_iv() { +entry: +; CHECK-LABEL: .ent _Z3b_iv + %0 = load i8* @b1, align 1 + %tobool = trunc i8 %0 to i1 + %frombool = zext i1 %tobool to i8 + store i8 %frombool, i8* @b2, align 1 + %1 = load i8* @b2, align 1 + %tobool1 = trunc i8 %1 to i1 + %conv = zext i1 %tobool1 to i32 + store i32 %conv, i32* @i, align 4 +; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) +; CHECK: andi $[[REG2:[0-9]+]], $[[REG1]], 1 +; CHECK: sb $[[REG2]], 0(${{[0-9]+}}) + + + + ret void +; CHECK: .end _Z3b_iv +} + +; Function Attrs: nounwind +define void @_Z4uc_iv() { +entry: +; CHECK-LABEL: .ent _Z4uc_iv + + %0 = load i8* @uc1, align 1 + %conv = zext i8 %0 to i32 + store i32 %conv, i32* @i, align 4 + %1 = load i8* @uc2, align 1 + %conv1 = zext i8 %1 to i32 +; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) +; CHECK: andi ${{[0-9]+}}, $[[REG1]], 255 + + store i32 %conv1, i32* @j, align 4 + ret void +; CHECK: .end _Z4uc_iv + +} + +; Function Attrs: nounwind +define void @_Z4sc_iv() { +entry: +; mips32r2-LABEL: .ent _Z4sc_iv +; mips32-LABEL: .ent _Z4sc_iv + + %0 = load i8* @sc1, align 1 + %conv = sext i8 %0 to i32 + store i32 %conv, i32* @i, align 4 + %1 = load i8* @sc2, align 1 + %conv1 = sext i8 %1 to i32 + store i32 %conv1, i32* @j, align 4 +; mips32r2: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) +; mips32r2: seb ${{[0-9]+}}, $[[REG1]] +; mips32: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) +; mips32: sll $[[REG2:[0-9]+]], $[[REG1]], 24 +; mips32: sra ${{[0-9]+}}, $[[REG2]], 24 + + ret void +; CHECK: .end _Z4sc_iv +} + +; Function Attrs: nounwind +define void @_Z4us_iv() { +entry: +; CHECK-LABEL: .ent _Z4us_iv + %0 = load i16* @us1, align 2 + %conv = zext i16 %0 to i32 + store i32 %conv, i32* @i, align 4 + %1 = load i16* @us2, align 2 + %conv1 = zext i16 %1 to i32 + store i32 %conv1, i32* @j, align 4 + ret void +; CHECK: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) +; CHECK: andi ${{[0-9]+}}, $[[REG1]], 65535 +; CHECK: .end _Z4us_iv +} + +; Function Attrs: nounwind +define void @_Z4ss_iv() { +entry: +; mips32r2-LABEL: .ent _Z4ss_iv +; mips32=LABEL: .ent _Z4ss_iv + + %0 = load i16* @ss1, align 2 + %conv = sext i16 %0 to i32 + store i32 %conv, i32* @i, align 4 + %1 = load i16* @ss2, align 2 + %conv1 = sext i16 %1 to i32 + store i32 %conv1, i32* @j, align 4 +; mips32r2: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) +; mips32r2: seh ${{[0-9]+}}, $[[REG1]] +; mips32: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) +; mips32: sll $[[REG2:[0-9]+]], $[[REG1]], 16 +; mips32: sra ${{[0-9]+}}, $[[REG2]], 16 + + ret void +; CHECK: .end _Z4ss_iv +} + +; Function Attrs: nounwind +define void @_Z4b_ssv() { +entry: +; CHECK-LABEL: .ent _Z4b_ssv + %0 = load i8* @b2, align 1 + %tobool = trunc i8 %0 to i1 + %conv = zext i1 %tobool to i16 + store i16 %conv, i16* @ssi, align 2 + ret void +; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) +; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1 +; CHECK: .end _Z4b_ssv +} + +; Function Attrs: nounwind +define void @_Z5uc_ssv() { +entry: +; CHECK-LABEL: .ent _Z5uc_ssv + %0 = load i8* @uc1, align 1 + %conv = zext i8 %0 to i16 + store i16 %conv, i16* @ssi, align 2 + %1 = load i8* @uc2, align 1 + %conv1 = zext i8 %1 to i16 +; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) +; CHECK: andi ${{[0-9]+}}, $[[REG1]], 255 + + store i16 %conv1, i16* @ssj, align 2 + ret void +; CHECK: .end _Z5uc_ssv +} + +; Function Attrs: nounwind +define void @_Z5sc_ssv() { +entry: +; mips32r2-LABEL: .ent _Z5sc_ssv +; mips32-LABEL: .ent _Z5sc_ssv + %0 = load i8* @sc1, align 1 + %conv = sext i8 %0 to i16 + store i16 %conv, i16* @ssi, align 2 + %1 = load i8* @sc2, align 1 + %conv1 = sext i8 %1 to i16 + store i16 %conv1, i16* @ssj, align 2 +; mips32r2: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) +; mips32r2: seb ${{[0-9]+}}, $[[REG1]] +; mips32: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}}) +; mips32: sll $[[REG2:[0-9]+]], $[[REG1]], 24 +; mips32: sra ${{[0-9]+}}, $[[REG2]], 24 + + ret void +; CHECK: .end _Z5sc_ssv +} + diff --git a/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll b/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll new file mode 100644 index 000000000000..93cf4c15a2f5 --- /dev/null +++ b/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll @@ -0,0 +1,21 @@ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \ +; RUN: < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \ +; RUN: < %s | FileCheck %s + +@.str = private unnamed_addr constant [6 x i8] c"hello\00", align 1 +@s = common global i8* null, align 4 + +; Function Attrs: nounwind +define void @foo() #0 { +entry: + store i8* getelementptr inbounds ([6 x i8]* @.str, i32 0, i32 0), i8** @s, align 4 + ret void +; CHECK: .ent foo +; CHECK: lw $[[REG1:[0-9]+]], %got($.str)(${{[0-9]+}}) +; CHECK: addiu ${{[0-9]+}}, $[[REG1]], %lo($.str) + +} + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } + diff --git a/test/CodeGen/Mips/Fast-ISel/nullvoid.ll b/test/CodeGen/Mips/Fast-ISel/nullvoid.ll index eeaff878bf54..c847561d0278 100644 --- a/test/CodeGen/Mips/Fast-ISel/nullvoid.ll +++ b/test/CodeGen/Mips/Fast-ISel/nullvoid.ll @@ -1,5 +1,7 @@ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \ +; RUN: < %s | FileCheck %s ; Function Attrs: nounwind define void @foo() { diff --git a/test/CodeGen/Mips/Fast-ISel/shift.ll b/test/CodeGen/Mips/Fast-ISel/shift.ll new file mode 100644 index 000000000000..18fd5ac32d22 --- /dev/null +++ b/test/CodeGen/Mips/Fast-ISel/shift.ll @@ -0,0 +1,24 @@ +; RUN: llc -march=mipsel -mcpu=mips32r2 -O1 -fast-isel=true -mips-fast-isel -filetype=obj %s -o - \ +; RUN: | llvm-objdump -arch mipsel -mcpu=mips32r2 -d - | FileCheck %s + +; This test checks that encoding for srl is correct when fast-isel for mips32r2 is used. + +%struct.s = type { [4 x i8], i32 } + +define i32 @main() nounwind uwtable { +entry: + %foo = alloca %struct.s, align 4 + %0 = bitcast %struct.s* %foo to i32* + %bf.load = load i32* %0, align 4 + %bf.lshr = lshr i32 %bf.load, 2 + %cmp = icmp ne i32 %bf.lshr, 2 + br i1 %cmp, label %if.then, label %if.end + +if.then: + unreachable + +if.end: + ret i32 0 +} + +; CHECK: srl ${{[0-9]+}}, ${{[0-9]+}}, {{[0-9]+}} diff --git a/test/CodeGen/Mips/Fast-ISel/simplestore.ll b/test/CodeGen/Mips/Fast-ISel/simplestore.ll index 5d52481dfdf3..83e3f3f24274 100644 --- a/test/CodeGen/Mips/Fast-ISel/simplestore.ll +++ b/test/CodeGen/Mips/Fast-ISel/simplestore.ll @@ -1,5 +1,7 @@ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \ +; RUN: < %s | FileCheck %s @abcd = external global i32 diff --git a/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll b/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll index 6759c01c774b..74723ae1beeb 100644 --- a/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll +++ b/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll @@ -1,5 +1,11 @@ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \ +; RUN: < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \ ; RUN: < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \ +; RUN: < %s | FileCheck %s -check-prefix=mips32r2 +; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \ +; RUN: < %s | FileCheck %s -check-prefix=mips32 @f = common global float 0.000000e+00, align 4 @de = common global double 0.000000e+00, align 8 @@ -23,15 +29,25 @@ entry: define void @d1() #0 { entry: store double 1.234567e+00, double* @de, align 8 -; CHECK: .ent d1 -; CHECK: lui $[[REG1a:[0-9]+]], 16371 -; CHECK: ori $[[REG2a:[0-9]+]], $[[REG1a]], 49353 -; CHECK: lui $[[REG1b:[0-9]+]], 21403 -; CHECK: ori $[[REG2b:[0-9]+]], $[[REG1b]], 34951 -; CHECK: mtc1 $[[REG2b]], $f[[REG3:[0-9]+]] -; CHECK: mthc1 $[[REG2a]], $f[[REG3]] -; CHECK: sdc1 $f[[REG3]], 0(${{[0-9]+}}) -; CHECK: .end d1 +; mip32r2: .ent d1 +; mips32r2: lui $[[REG1a:[0-9]+]], 16371 +; mips32r2: ori $[[REG2a:[0-9]+]], $[[REG1a]], 49353 +; mips32r2: lui $[[REG1b:[0-9]+]], 21403 +; mips32r2: ori $[[REG2b:[0-9]+]], $[[REG1b]], 34951 +; mips32r2: mtc1 $[[REG2b]], $f[[REG3:[0-9]+]] +; mips32r2: mthc1 $[[REG2a]], $f[[REG3]] +; mips32r2: sdc1 $f[[REG3]], 0(${{[0-9]+}}) +; mips32r2: .end d1 +; mips32: .ent d1 +; mips32: lui $[[REG1a:[0-9]+]], 16371 +; mips32: ori $[[REG2a:[0-9]+]], $[[REG1a]], 49353 +; mips32: lui $[[REG1b:[0-9]+]], 21403 +; mips32: ori $[[REG2b:[0-9]+]], $[[REG1b]], 34951 +; mips32: mtc1 $[[REG2b]], $f[[REG3:[0-9]+]] +; mips32: mtc1 $[[REG2a]], $f{{[0-9]+}} +; mips32: sdc1 $f[[REG3]], 0(${{[0-9]+}}) +; mips32: .end d1 + ret void } diff --git a/test/CodeGen/Mips/Fast-ISel/simplestorei.ll b/test/CodeGen/Mips/Fast-ISel/simplestorei.ll index 7d2c8e73c352..128e1de9cad0 100644 --- a/test/CodeGen/Mips/Fast-ISel/simplestorei.ll +++ b/test/CodeGen/Mips/Fast-ISel/simplestorei.ll @@ -1,5 +1,7 @@ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \ +; RUN: < %s | FileCheck %s @ijk = external global i32 diff --git a/test/CodeGen/Mips/atomic.ll b/test/CodeGen/Mips/atomic.ll index 78fd8296178e..ccfeb00967e3 100644 --- a/test/CodeGen/Mips/atomic.ll +++ b/test/CodeGen/Mips/atomic.ll @@ -1,14 +1,15 @@ -; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EL -; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips4 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EL -; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EL -; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL +; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS +; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS +; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS +; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips4 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS +; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS +; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS +; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS +; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r2 -mattr=micromips < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=MICROMIPS ; Keep one big-endian check so that we don't reduce testing, but don't add more ; since endianness doesn't affect the body of the atomic operations. -; RUN: llc -march=mips --disable-machine-licm -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EB +; RUN: llc -march=mips --disable-machine-licm -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EB -check-prefix=NOT-MICROMIPS @x = common global i32 0, align 4 @@ -26,7 +27,8 @@ entry: ; ALL: ll $[[R1:[0-9]+]], 0($[[R0]]) ; ALL: addu $[[R2:[0-9]+]], $[[R1]], $4 ; ALL: sc $[[R2]], 0($[[R0]]) -; ALL: beqz $[[R2]], $[[BB0]] +; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]] +; MICROMIPS: beqzc $[[R2]], $[[BB0]] } define i32 @AtomicLoadNand32(i32 signext %incr) nounwind { @@ -44,7 +46,8 @@ entry: ; ALL: and $[[R3:[0-9]+]], $[[R1]], $4 ; ALL: nor $[[R2:[0-9]+]], $zero, $[[R3]] ; ALL: sc $[[R2]], 0($[[R0]]) -; ALL: beqz $[[R2]], $[[BB0]] +; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]] +; MICROMIPS: beqzc $[[R2]], $[[BB0]] } define i32 @AtomicSwap32(i32 signext %newval) nounwind { @@ -63,7 +66,8 @@ entry: ; ALL: $[[BB0:[A-Z_0-9]+]]: ; ALL: ll ${{[0-9]+}}, 0($[[R0]]) ; ALL: sc $[[R2:[0-9]+]], 0($[[R0]]) -; ALL: beqz $[[R2]], $[[BB0]] +; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]] +; MICROMIPS: beqzc $[[R2]], $[[BB0]] } define i32 @AtomicCmpSwap32(i32 signext %oldval, i32 signext %newval) nounwind { @@ -84,7 +88,8 @@ entry: ; ALL: ll $2, 0($[[R0]]) ; ALL: bne $2, $4, $[[BB1:[A-Z_0-9]+]] ; ALL: sc $[[R2:[0-9]+]], 0($[[R0]]) -; ALL: beqz $[[R2]], $[[BB0]] +; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]] +; MICROMIPS: beqzc $[[R2]], $[[BB0]] ; ALL: $[[BB1]]: } @@ -120,7 +125,8 @@ entry: ; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]] ; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]] ; ALL: sc $[[R14]], 0($[[R2]]) -; ALL: beqz $[[R14]], $[[BB0]] +; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]] +; MICROMIPS: beqzc $[[R14]], $[[BB0]] ; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]] ; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]] @@ -159,7 +165,8 @@ entry: ; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]] ; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]] ; ALL: sc $[[R14]], 0($[[R2]]) -; ALL: beqz $[[R14]], $[[BB0]] +; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]] +; MICROMIPS: beqzc $[[R14]], $[[BB0]] ; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]] ; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]] @@ -199,7 +206,8 @@ entry: ; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]] ; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]] ; ALL: sc $[[R14]], 0($[[R2]]) -; ALL: beqz $[[R14]], $[[BB0]] +; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]] +; MICROMIPS: beqzc $[[R14]], $[[BB0]] ; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]] ; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]] @@ -237,7 +245,8 @@ entry: ; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]] ; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R18]] ; ALL: sc $[[R14]], 0($[[R2]]) -; ALL: beqz $[[R14]], $[[BB0]] +; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]] +; MICROMIPS: beqzc $[[R14]], $[[BB0]] ; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]] ; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]] @@ -282,7 +291,8 @@ entry: ; ALL: and $[[R15:[0-9]+]], $[[R13]], $[[R8]] ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R12]] ; ALL: sc $[[R16]], 0($[[R2]]) -; ALL: beqz $[[R16]], $[[BB0]] +; NOT-MICROMIPS: beqz $[[R16]], $[[BB0]] +; MICROMIPS: beqzc $[[R16]], $[[BB0]] ; ALL: $[[BB1]]: ; ALL: srlv $[[R17:[0-9]+]], $[[R14]], $[[R5]] @@ -322,7 +332,8 @@ entry: ; ALL: and $[[R15:[0-9]+]], $[[R13]], $[[R8]] ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R12]] ; ALL: sc $[[R16]], 0($[[R2]]) -; ALL: beqz $[[R16]], $[[BB0]] +; NOT-MICROMIPS: beqz $[[R16]], $[[BB0]] +; MICROMIPS: beqzc $[[R16]], $[[BB0]] ; ALL: $[[BB1]]: ; ALL: srlv $[[R17:[0-9]+]], $[[R14]], $[[R5]] @@ -367,7 +378,8 @@ entry: ; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]] ; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]] ; ALL: sc $[[R14]], 0($[[R2]]) -; ALL: beqz $[[R14]], $[[BB0]] +; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]] +; MICROMIPS: beqzc $[[R14]], $[[BB0]] ; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]] ; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]] @@ -430,5 +442,6 @@ entry: ; ALL: ll $[[R1:[0-9]+]], 0($[[PTR]]) ; ALL: addu $[[R2:[0-9]+]], $[[R1]], $4 ; ALL: sc $[[R2]], 0($[[PTR]]) -; ALL: beqz $[[R2]], $[[BB0]] +; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]] +; MICROMIPS: beqzc $[[R2]], $[[BB0]] } diff --git a/test/CodeGen/Mips/brsize3.ll b/test/CodeGen/Mips/brsize3.ll index 7b1f44001a9a..3620868bb2f6 100644 --- a/test/CodeGen/Mips/brsize3.ll +++ b/test/CodeGen/Mips/brsize3.ll @@ -30,4 +30,4 @@ x: ; preds = %x, %entry attributes #0 = { noreturn nounwind optsize "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" } attributes #1 = { nounwind } -!1 = metadata !{i32 45} +!1 = !{i32 45} diff --git a/test/CodeGen/Mips/brsize3a.ll b/test/CodeGen/Mips/brsize3a.ll index 6382fa228e19..f05e21191925 100644 --- a/test/CodeGen/Mips/brsize3a.ll +++ b/test/CodeGen/Mips/brsize3a.ll @@ -23,4 +23,4 @@ x: ; preds = %x, %entry attributes #0 = { noreturn nounwind optsize "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" } attributes #1 = { nounwind } -!1 = metadata !{i32 45} +!1 = !{i32 45} diff --git a/test/CodeGen/Mips/ci2.ll b/test/CodeGen/Mips/ci2.ll index 7187f0c75888..e2068fdf14e1 100644 --- a/test/CodeGen/Mips/ci2.ll +++ b/test/CodeGen/Mips/ci2.ll @@ -36,4 +36,4 @@ if.end: ; preds = %if.else, %if.then attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind } -!1 = metadata !{i32 103} +!1 = !{i32 103} diff --git a/test/CodeGen/Mips/cmov.ll b/test/CodeGen/Mips/cmov.ll index e548049ab346..b12c2df97c19 100755 --- a/test/CodeGen/Mips/cmov.ll +++ b/test/CodeGen/Mips/cmov.ll @@ -757,24 +757,9 @@ define i32 @slti6(i32 signext %a) nounwind readnone { ; ALL-LABEL: slti6: -; 32-CMOV-DAG: slti [[R1:\$[0-9]+]], $4, 7 -; 32-CMOV-DAG: xori [[R1]], [[R1]], 1 -; 32-CMOV-DAG: addiu [[R2:\$[0-9]+]], [[R1]], 3 -; 32-CMOV-NOT: movn - -; 32-CMP-DAG: slti [[R1:\$[0-9]+]], $4, 7 -; 32-CMP-DAG: xori [[R1]], [[R1]], 1 -; 32-CMP-DAG: addiu [[R2:\$[0-9]+]], [[R1]], 3 -; 32-CMP-NOT: seleqz -; 32-CMP-NOT: selnez - -; 64-CMOV-DAG: slti [[R1:\$[0-9]+]], $4, 7 -; 64-CMOV-DAG: xori [[R1]], [[R1]], 1 -; 64-CMOV-DAG: addiu [[R2:\$[0-9]+]], [[R1]], 3 -; 64-CMOV-NOT: movn - -; 64-CMP-DAG: slti [[R1:\$[0-9]+]], $4, 7 -; 64-CMP-DAG: xori [[R1]], [[R1]], 1 -; 64-CMP-DAG: addiu [[R2:\$[0-9]+]], [[R1]], 3 -; 64-CMP-NOT: seleqz -; 64-CMP-NOT: selnez +; ALL-DAG: addiu [[R1:\$[0-9]+]], $zero, 6 +; ALL-DAG: slt [[R1]], [[R1]], $4 +; ALL-DAG: addiu [[R2:\$[0-9]+]], [[R1]], 3 +; ALL-NOT: movn +; ALL-NOT: seleqz +; ALL-NOT: selnez diff --git a/test/CodeGen/Mips/const1.ll b/test/CodeGen/Mips/const1.ll index cb2bacaf17a5..f32ce244cf40 100644 --- a/test/CodeGen/Mips/const1.ll +++ b/test/CodeGen/Mips/const1.ll @@ -32,4 +32,4 @@ attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"= !llvm.ident = !{!0} -!0 = metadata !{metadata !"clang version 3.4 (gitosis@dmz-portal.mips.com:clang.git b754974ec32ab712ea7d8b52cd8037b24e7d6ed3) (gitosis@dmz-portal.mips.com:llvm.git 8e211187b501bc73edb938fde0019c9a20bcffd5)"} +!0 = !{!"clang version 3.4 (gitosis@dmz-portal.mips.com:clang.git b754974ec32ab712ea7d8b52cd8037b24e7d6ed3) (gitosis@dmz-portal.mips.com:llvm.git 8e211187b501bc73edb938fde0019c9a20bcffd5)"} diff --git a/test/CodeGen/Mips/const4a.ll b/test/CodeGen/Mips/const4a.ll index b4c509fcd8c0..ac6795b2c833 100644 --- a/test/CodeGen/Mips/const4a.ll +++ b/test/CodeGen/Mips/const4a.ll @@ -177,4 +177,4 @@ attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "n !llvm.ident = !{!0} -!0 = metadata !{metadata !"clang version 3.4 (gitosis@dmz-portal.mips.com:clang.git b310439121c875937d78cc49cc969bc1197fc025) (gitosis@dmz-portal.mips.com:llvm.git 7fc0ca9656ebec8dad61f72f5a5ddfb232c070fd)"} +!0 = !{!"clang version 3.4 (gitosis@dmz-portal.mips.com:clang.git b310439121c875937d78cc49cc969bc1197fc025) (gitosis@dmz-portal.mips.com:llvm.git 7fc0ca9656ebec8dad61f72f5a5ddfb232c070fd)"} diff --git a/test/CodeGen/Mips/const6.ll b/test/CodeGen/Mips/const6.ll index 3f02ab907e1e..c26e02f2ebba 100644 --- a/test/CodeGen/Mips/const6.ll +++ b/test/CodeGen/Mips/const6.ll @@ -159,6 +159,6 @@ attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "n !llvm.ident = !{!0} -!0 = metadata !{metadata !"clang version 3.4 (gitosis@dmz-portal.mips.com:clang.git b310439121c875937d78cc49cc969bc1197fc025) (gitosis@dmz-portal.mips.com:llvm.git 7fc0ca9656ebec8dad61f72f5a5ddfb232c070fd)"} +!0 = !{!"clang version 3.4 (gitosis@dmz-portal.mips.com:clang.git b310439121c875937d78cc49cc969bc1197fc025) (gitosis@dmz-portal.mips.com:llvm.git 7fc0ca9656ebec8dad61f72f5a5ddfb232c070fd)"} diff --git a/test/CodeGen/Mips/const6a.ll b/test/CodeGen/Mips/const6a.ll index d34239058734..aff1357c3a8f 100644 --- a/test/CodeGen/Mips/const6a.ll +++ b/test/CodeGen/Mips/const6a.ll @@ -26,4 +26,4 @@ entry: attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" } attributes #1 = { nounwind } -!1 = metadata !{i32 121} +!1 = !{i32 121} diff --git a/test/CodeGen/Mips/ctlz-v.ll b/test/CodeGen/Mips/ctlz-v.ll new file mode 100644 index 000000000000..3d580e5771f4 --- /dev/null +++ b/test/CodeGen/Mips/ctlz-v.ll @@ -0,0 +1,19 @@ +; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=MIPS32 +; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=MIPS64 + +declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1) + +define <2 x i32> @ctlzv2i32(<2 x i32> %x) { +entry: +; MIPS32: clz $2, $4 +; MIPS32: clz $3, $5 + +; MIPS64-DAG: sll $[[A0:[0-9]+]], $4, 0 +; MIPS64-DAG: clz $2, $[[A0]] +; MIPS64-DAG: sll $[[A1:[0-9]+]], $5, 0 +; MIPS64-DAG: clz $3, $[[A1]] + + %ret = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %x, i1 true) + ret <2 x i32> %ret +} + diff --git a/test/CodeGen/Mips/cttz-v.ll b/test/CodeGen/Mips/cttz-v.ll new file mode 100644 index 000000000000..85f69f9a17d9 --- /dev/null +++ b/test/CodeGen/Mips/cttz-v.ll @@ -0,0 +1,39 @@ +; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=MIPS32 +; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=MIPS64 + +declare <2 x i32> @llvm.cttz.v2i32(<2 x i32>, i1) + +define <2 x i32> @cttzv2i32(<2 x i32> %x) { +entry: +; MIPS32-DAG: addiu $[[R0:[0-9]+]], $4, -1 +; MIPS32-DAG: not $[[R1:[0-9]+]], $4 +; MIPS32-DAG: and $[[R2:[0-9]+]], $[[R1]], $[[R0]] +; MIPS32-DAG: clz $[[R3:[0-9]+]], $[[R2]] +; MIPS32-DAG: addiu $[[R4:[0-9]+]], $zero, 32 +; MIPS32-DAG: subu $2, $[[R4]], $[[R3]] +; MIPS32-DAG: addiu $[[R5:[0-9]+]], $5, -1 +; MIPS32-DAG: not $[[R6:[0-9]+]], $5 +; MIPS32-DAG: and $[[R7:[0-9]+]], $[[R6]], $[[R5]] +; MIPS32-DAG: clz $[[R8:[0-9]+]], $[[R7]] +; MIPS32-DAG: jr $ra +; MIPS32-DAG: subu $3, $[[R4]], $[[R8]] + +; MIPS64-DAG: sll $[[A0:[0-9]+]], $4, 0 +; MIPS64-DAG: addiu $[[R0:[0-9]+]], $[[A0]], -1 +; MIPS64-DAG: not $[[R1:[0-9]+]], $[[A0]] +; MIPS64-DAG: and $[[R2:[0-9]+]], $[[R1]], $[[R0]] +; MIPS64-DAG: clz $[[R3:[0-9]+]], $[[R2]] +; MIPS64-DAG: addiu $[[R4:[0-9]+]], $zero, 32 +; MIPS64-DAG: subu $2, $[[R4]], $[[R3]] +; MIPS64-DAG: sll $[[A1:[0-9]+]], $5, 0 +; MIPS64-DAG: addiu $[[R5:[0-9]+]], $[[A1]], -1 +; MIPS64-DAG: not $[[R6:[0-9]+]], $[[A1]] +; MIPS64-DAG: and $[[R7:[0-9]+]], $[[R6]], $[[R5]] +; MIPS64-DAG: clz $[[R8:[0-9]+]], $[[R7]] +; MIPS64-DAG: jr $ra +; MIPS64-DAG: subu $3, $[[R4]], $[[R8]] + + %ret = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %x, i1 true) + ret <2 x i32> %ret +} + diff --git a/test/CodeGen/Mips/fp16instrinsmc.ll b/test/CodeGen/Mips/fp16instrinsmc.ll index 7ced36c016f7..84d3814ee8b8 100644 --- a/test/CodeGen/Mips/fp16instrinsmc.ll +++ b/test/CodeGen/Mips/fp16instrinsmc.ll @@ -385,7 +385,7 @@ entry: ; Function Attrs: nounwind declare double @exp2(double) #0 -attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind readnone "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" } attributes #2 = { nounwind readnone } attributes #3 = { nounwind } diff --git a/test/CodeGen/Mips/fptr2.ll b/test/CodeGen/Mips/fptr2.ll deleted file mode 100644 index c8b5e0d1771e..000000000000 --- a/test/CodeGen/Mips/fptr2.ll +++ /dev/null @@ -1,20 +0,0 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=static16 - -; Function Attrs: nounwind -define double @my_mul(double %a, double %b) #0 { -entry: - %a.addr = alloca double, align 8 - %b.addr = alloca double, align 8 - store double %a, double* %a.addr, align 8 - store double %b, double* %b.addr, align 8 - %0 = load double* %a.addr, align 8 - %1 = load double* %b.addr, align 8 - %mul = fmul double %0, %1 - ret double %mul -} - -; static16: .ent __fn_stub_my_mul -; static16: .set reorder -; static16-NEXT: #NO_APP -; static16: .end __fn_stub_my_mul -attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" } diff --git a/test/CodeGen/Mips/gpreg-lazy-binding.ll b/test/CodeGen/Mips/gpreg-lazy-binding.ll index 88e596b3bb0d..3a636d82533f 100644 --- a/test/CodeGen/Mips/gpreg-lazy-binding.ll +++ b/test/CodeGen/Mips/gpreg-lazy-binding.ll @@ -25,3 +25,11 @@ entry: ret void } +define void @no_lazy(void (i32)* %pf) { + +; CHECK-LABEL: no_lazy +; CHECK-NOT: gp_disp + + tail call void %pf(i32 1) + ret void +} diff --git a/test/CodeGen/Mips/hfptrcall.ll b/test/CodeGen/Mips/hfptrcall.ll index 9df8d900693c..683952d0e4ec 100644 --- a/test/CodeGen/Mips/hfptrcall.ll +++ b/test/CodeGen/Mips/hfptrcall.ll @@ -118,8 +118,8 @@ entry: declare i32 @printf(i8*, ...) #1 -attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="true" } -attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="true" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/Mips/init-array.ll b/test/CodeGen/Mips/init-array.ll index f96ce2647289..1ca182dae7a5 100644 --- a/test/CodeGen/Mips/init-array.ll +++ b/test/CodeGen/Mips/init-array.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple mipsel-unknown-linux -use-init-array < %s | FileCheck %s +; RUN: llc -mtriple mipsel-unknown-linux < %s | FileCheck %s target triple = "mipsel-unknown-linux" diff --git a/test/CodeGen/Mips/inlineasm-assembler-directives.ll b/test/CodeGen/Mips/inlineasm-assembler-directives.ll new file mode 100644 index 000000000000..e4a6d1e26c69 --- /dev/null +++ b/test/CodeGen/Mips/inlineasm-assembler-directives.ll @@ -0,0 +1,23 @@ +; RUN: llc -march=mips < %s | FileCheck %s + +; Check for the emission of appropriate assembler directives before and +; after the inline assembly code. +define void @f() nounwind { +entry: +; CHECK: #APP +; CHECK-NEXT: .set push +; CHECK-NEXT: .set at +; CHECK-NEXT: .set macro +; CHECK-NEXT: .set reorder +; CHECK: addi $9, ${{[2-9][0-9]?}}, 8 +; CHECK: subi ${{[2-9][0-9]?}}, $9, 6 +; CHECK: .set pop +; CHECK-NEXT: #NO_APP + %a = alloca i32, align 4 + %b = alloca i32, align 4 + store i32 20, i32* %a, align 4 + %0 = load i32* %a, align 4 + %1 = call i32 asm sideeffect "addi $$9, $1, 8\0A\09subi $0, $$9, 6", "=r,r,~{$1}"(i32 %0) + store i32 %1, i32* %b, align 4 + ret void +} diff --git a/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll b/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll index a67ddce222ae..41991d07a4fe 100644 --- a/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll +++ b/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll @@ -32,10 +32,10 @@ entry: ; Now l with 1024: make sure register lo is picked. We do this by checking the instruction ; after the inline expression for a mflo to pull the value out of lo. -; CHECK: #APP -; CHECK-NEXT: mtlo ${{[0-9]+}} +; CHECK: #APP +; CHECK: mtlo ${{[0-9]+}} ; CHECK-NEXT: madd ${{[0-9]+}},${{[0-9]+}} -; CHECK-NEXT: #NO_APP +; CHECK: #NO_APP ; CHECK-NEXT: mflo ${{[0-9]+}} %bosco = alloca i32, align 4 call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1,$2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounwind diff --git a/test/CodeGen/Mips/inlineasmmemop.ll b/test/CodeGen/Mips/inlineasmmemop.ll index a08a0243b8b9..5518520c5491 100644 --- a/test/CodeGen/Mips/inlineasmmemop.ll +++ b/test/CodeGen/Mips/inlineasmmemop.ll @@ -5,6 +5,7 @@ define i32 @f1(i32 %x) nounwind { entry: +; CHECK-LABEL: f1: ; CHECK: addiu $[[T0:[0-9]+]], $sp ; CHECK: #APP ; CHECK: sw $4, 0($[[T0]]) @@ -22,42 +23,26 @@ entry: ret i32 %0 } -; "D": Second word of double word. This works for any memory element +; CHECK-LABEL: main: +; "D": Second word of a double word. This works for any memory element ; double or single. ; CHECK: #APP -; CHECK-NEXT: lw ${{[0-9]+}},4(${{[0-9]+}}); -; CHECK-NEXT: #NO_APP +; CHECK: lw ${{[0-9]+}},4(${{[0-9]+}}); +; CHECK: #NO_APP -; No "D": First word of double word. This works for any memory element +; No "D": First word of a double word. This works for any memory element ; double or single. ; CHECK: #APP -; CHECK-NEXT: lw ${{[0-9]+}},0(${{[0-9]+}}); -; CHECK-NEXT: #NO_APP - -;int b[8] = {0,1,2,3,4,5,6,7}; -;int main() -;{ -; int i; -; -; // The first word. Notice, no 'D' -; { asm ( -; "lw %0,%1;\n" -; : "=r" (i) : "m" (*(b+4)));} -; -; // The second word -; { asm ( -; "lw %0,%D1;\n" -; : "=r" (i) "m" (*(b+4)));} -;} +; CHECK: lw ${{[0-9]+}},0(${{[0-9]+}}); +; CHECK: #NO_APP @b = common global [20 x i32] zeroinitializer, align 4 define void @main() { entry: +; Second word: tail call void asm sideeffect " lw $0,${1:D};", "r,*m,~{$11}"(i32 undef, i32* getelementptr inbounds ([20 x i32]* @b, i32 0, i32 3)) +; First word. Notice, no 'D': tail call void asm sideeffect " lw $0,${1};", "r,*m,~{$11}"(i32 undef, i32* getelementptr inbounds ([20 x i32]* @b, i32 0, i32 3)) ret void } - -attributes #0 = { nounwind } - diff --git a/test/CodeGen/Mips/lcb2.ll b/test/CodeGen/Mips/lcb2.ll index 715584b6797d..59b96e64e95e 100644 --- a/test/CodeGen/Mips/lcb2.ll +++ b/test/CodeGen/Mips/lcb2.ll @@ -120,14 +120,14 @@ attributes #1 = { nounwind } !llvm.ident = !{!0} -!0 = metadata !{metadata !"clang version 3.5 (gitosis@dmz-portal.mips.com:clang.git ed197d08c90d82e1119774e10920e6f7a841c8ec) (gitosis@dmz-portal.mips.com:llvm.git b9235a363fa2dddb26ac01cbaed58efbc9eff392)"} -!1 = metadata !{metadata !2, metadata !2, i64 0} -!2 = metadata !{metadata !"int", metadata !3, i64 0} -!3 = metadata !{metadata !"omnipotent char", metadata !4, i64 0} -!4 = metadata !{metadata !"Simple C/C++ TBAA"} -!5 = metadata !{i32 59} -!6 = metadata !{i32 156} -!7 = metadata !{i32 210} -!8 = metadata !{i32 299} -!9 = metadata !{i32 340} -!10 = metadata !{i32 412} +!0 = !{!"clang version 3.5 (gitosis@dmz-portal.mips.com:clang.git ed197d08c90d82e1119774e10920e6f7a841c8ec) (gitosis@dmz-portal.mips.com:llvm.git b9235a363fa2dddb26ac01cbaed58efbc9eff392)"} +!1 = !{!2, !2, i64 0} +!2 = !{!"int", !3, i64 0} +!3 = !{!"omnipotent char", !4, i64 0} +!4 = !{!"Simple C/C++ TBAA"} +!5 = !{i32 59} +!6 = !{i32 156} +!7 = !{i32 210} +!8 = !{i32 299} +!9 = !{i32 340} +!10 = !{i32 412} diff --git a/test/CodeGen/Mips/lcb3c.ll b/test/CodeGen/Mips/lcb3c.ll index 72a0b8cf5cea..eb8329145421 100644 --- a/test/CodeGen/Mips/lcb3c.ll +++ b/test/CodeGen/Mips/lcb3c.ll @@ -55,5 +55,5 @@ attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"= attributes #1 = { nounwind } -!1 = metadata !{i32 65} -!2 = metadata !{i32 167} +!1 = !{i32 65} +!2 = !{i32 167} diff --git a/test/CodeGen/Mips/lcb4a.ll b/test/CodeGen/Mips/lcb4a.ll index e37feca78179..fbcadd2552f8 100644 --- a/test/CodeGen/Mips/lcb4a.ll +++ b/test/CodeGen/Mips/lcb4a.ll @@ -59,11 +59,11 @@ attributes #0 = { nounwind optsize "less-precise-fpmad"="false" "no-frame-pointe attributes #1 = { nounwind } -!1 = metadata !{metadata !2, metadata !2, i64 0} -!2 = metadata !{metadata !"int", metadata !3, i64 0} -!3 = metadata !{metadata !"omnipotent char", metadata !4, i64 0} -!4 = metadata !{metadata !"Simple C/C++ TBAA"} -!5 = metadata !{i32 58} -!6 = metadata !{i32 108} -!7 = metadata !{i32 190} -!8 = metadata !{i32 243} +!1 = !{!2, !2, i64 0} +!2 = !{!"int", !3, i64 0} +!3 = !{!"omnipotent char", !4, i64 0} +!4 = !{!"Simple C/C++ TBAA"} +!5 = !{i32 58} +!6 = !{i32 108} +!7 = !{i32 190} +!8 = !{i32 243} diff --git a/test/CodeGen/Mips/lcb5.ll b/test/CodeGen/Mips/lcb5.ll index 0a89c804945f..b2a8d1d33ef6 100644 --- a/test/CodeGen/Mips/lcb5.ll +++ b/test/CodeGen/Mips/lcb5.ll @@ -220,21 +220,21 @@ attributes #0 = { nounwind optsize "less-precise-fpmad"="false" "no-frame-pointe attributes #1 = { nounwind } -!1 = metadata !{metadata !2, metadata !2, i64 0} -!2 = metadata !{metadata !"int", metadata !3, i64 0} -!3 = metadata !{metadata !"omnipotent char", metadata !4, i64 0} -!4 = metadata !{metadata !"Simple C/C++ TBAA"} -!5 = metadata !{i32 57} -!6 = metadata !{i32 107} -!7 = metadata !{i32 188} -!8 = metadata !{i32 241} -!9 = metadata !{i32 338} -!10 = metadata !{i32 391} -!11 = metadata !{i32 477} -!12 = metadata !{i32 533} -!13 = metadata !{i32 621} -!14 = metadata !{i32 663} -!15 = metadata !{i32 747} -!16 = metadata !{i32 792} -!17 = metadata !{i32 867} -!18 = metadata !{i32 953} +!1 = !{!2, !2, i64 0} +!2 = !{!"int", !3, i64 0} +!3 = !{!"omnipotent char", !4, i64 0} +!4 = !{!"Simple C/C++ TBAA"} +!5 = !{i32 57} +!6 = !{i32 107} +!7 = !{i32 188} +!8 = !{i32 241} +!9 = !{i32 338} +!10 = !{i32 391} +!11 = !{i32 477} +!12 = !{i32 533} +!13 = !{i32 621} +!14 = !{i32 663} +!15 = !{i32 747} +!16 = !{i32 792} +!17 = !{i32 867} +!18 = !{i32 953} diff --git a/test/CodeGen/Mips/llvm-ir/mul.ll b/test/CodeGen/Mips/llvm-ir/mul.ll new file mode 100644 index 000000000000..167412407cdc --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/mul.ll @@ -0,0 +1,181 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=M2 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=32R1-R2 -check-prefix=32R1 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=32R1-R2 -check-prefix=32R2 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=32R6 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=M4 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=64R1-R2 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=64R1-R2 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=64R6 + +define signext i1 @mul_i1(i1 signext %a, i1 signext %b) { +entry: +; ALL-LABEL: mul_i1: + + ; M2: mult $4, $5 + ; M2: mflo $[[T0:[0-9]+]] + ; M2: sll $[[T0]], $[[T0]], 31 + ; M2: sra $2, $[[T0]], 31 + + ; 32R1-R2: mul $[[T0:[0-9]+]], $4, $5 + ; 32R1-R2: sll $[[T0]], $[[T0]], 31 + ; 32R1-R2: sra $2, $[[T0]], 31 + + ; 32R6: mul $[[T0:[0-9]+]], $4, $5 + ; 32R6: sll $[[T0]], $[[T0]], 31 + ; 32R6: sra $2, $[[T0]], 31 + + ; M4: mult $4, $5 + ; M4: mflo $[[T0:[0-9]+]] + ; M4: sll $[[T0]], $[[T0]], 31 + ; M4: sra $2, $[[T0]], 31 + + ; 64R1-R2: mul $[[T0:[0-9]+]], $4, $5 + ; 64R1-R2: sll $[[T0]], $[[T0]], 31 + ; 64R1-R2: sra $2, $[[T0]], 31 + + ; 64R6: mul $[[T0:[0-9]+]], $4, $5 + ; 64R6: sll $[[T0]], $[[T0]], 31 + ; 64R6: sra $2, $[[T0]], 31 + + %r = mul i1 %a, %b + ret i1 %r +} + +define signext i8 @mul_i8(i8 signext %a, i8 signext %b) { +entry: +; ALL-LABEL: mul_i8: + + ; M2: mult $4, $5 + ; M2: mflo $[[T0:[0-9]+]] + ; M2: sll $[[T0]], $[[T0]], 24 + ; M2: sra $2, $[[T0]], 24 + + ; 32R1: mul $[[T0:[0-9]+]], $4, $5 + ; 32R1: sll $[[T0]], $[[T0]], 24 + ; 32R1: sra $2, $[[T0]], 24 + + ; 32R2: mul $[[T0:[0-9]+]], $4, $5 + ; 32R2: seb $2, $[[T0]] + + ; 32R6: mul $[[T0:[0-9]+]], $4, $5 + ; 32R6: seb $2, $[[T0]] + + ; M4: mult $4, $5 + ; M4: mflo $[[T0:[0-9]+]] + ; M4: sll $[[T0]], $[[T0]], 24 + ; M4: sra $2, $[[T0]], 24 + + ; 64R1: mul $[[T0:[0-9]+]], $4, $5 + ; 64R1: sll $[[T0]], $[[T0]], 24 + ; 64R1: sra $2, $[[T0]], 24 + + ; 64R2: mul $[[T0:[0-9]+]], $4, $5 + ; 64R2: seb $2, $[[T0]] + + ; 64R6: mul $[[T0:[0-9]+]], $4, $5 + ; 64R6: seb $2, $[[T0]] + %r = mul i8 %a, %b + ret i8 %r +} + +define signext i16 @mul_i16(i16 signext %a, i16 signext %b) { +entry: +; ALL-LABEL: mul_i16: + + ; M2: mult $4, $5 + ; M2: mflo $[[T0:[0-9]+]] + ; M2: sll $[[T0]], $[[T0]], 16 + ; M2: sra $2, $[[T0]], 16 + + ; 32R1: mul $[[T0:[0-9]+]], $4, $5 + ; 32R1: sll $[[T0]], $[[T0]], 16 + ; 32R1: sra $2, $[[T0]], 16 + + ; 32R2: mul $[[T0:[0-9]+]], $4, $5 + ; 32R2: seh $2, $[[T0]] + + ; 32R6: mul $[[T0:[0-9]+]], $4, $5 + ; 32R6: seh $2, $[[T0]] + + ; M4: mult $4, $5 + ; M4: mflo $[[T0:[0-9]+]] + ; M4: sll $[[T0]], $[[T0]], 16 + ; M4: sra $2, $[[T0]], 16 + + ; 64R1: mul $[[T0:[0-9]+]], $4, $5 + ; 64R1: sll $[[T0]], $[[T0]], 16 + ; 64R1: sra $2, $[[T0]], 16 + + ; 64R2: mul $[[T0:[0-9]+]], $4, $5 + ; 64R2: seh $2, $[[T0]] + + ; 64R6: mul $[[T0:[0-9]+]], $4, $5 + ; 64R6: seh $2, $[[T0]] + %r = mul i16 %a, %b + ret i16 %r +} + +define signext i32 @mul_i32(i32 signext %a, i32 signext %b) { +entry: +; ALL-LABEL: mul_i32: + + ; M2: mult $4, $5 + ; M2: mflo $2 + + ; 32R1-R2: mul $2, $4, $5 + ; 32R6: mul $2, $4, $5 + + ; 64R1-R2: mul $2, $4, $5 + ; 64R6: mul $2, $4, $5 + %r = mul i32 %a, %b + ret i32 %r +} + +define signext i64 @mul_i64(i64 signext %a, i64 signext %b) { +entry: +; ALL-LABEL: mul_i64: + + ; M2: mult $4, $7 + ; M2: mflo $[[T0:[0-9]+]] + ; M2: mult $5, $6 + ; M2: mflo $[[T1:[0-9]+]] + ; M2: multu $5, $7 + ; M2: mflo $3 + ; M2: mfhi $4 + ; M2: addu $[[T2:[0-9]+]], $4, $[[T1]] + ; M2: addu $2, $[[T2]], $[[T0]] + + ; 32R1-R2: multu $5, $7 + ; 32R1-R2: mflo $3 + ; 32R1-R2: mfhi $[[T0:[0-9]+]] + ; 32R1-R2: mul $[[T1:[0-9]+]], $4, $7 + ; 32R1-R2: mul $[[T2:[0-9]+]], $5, $6 + ; 32R1-R2: addu $[[T0]], $[[T0]], $[[T2:[0-9]+]] + ; 32R1-R2: addu $2, $[[T0]], $[[T1]] + + ; 32R6: mul $[[T0:[0-9]+]], $5, $6 + ; 32R6: muhu $[[T1:[0-9]+]], $5, $7 + ; 32R6: addu $[[T0]], $[[T1]], $[[T0]] + ; 32R6: mul $[[T2:[0-9]+]], $4, $7 + ; 32R6: addu $2, $[[T0]], $[[T2]] + ; 32R6: mul $3, $5, $7 + + ; M4: dmult $4, $5 + ; M4: mflo $2 + + ; 64R1-R2: dmult $4, $5 + ; 64R1-R2: mflo $2 + + ; 64R6: dmul $2, $4, $5 + + %r = mul i64 %a, %b + ret i64 %r +} diff --git a/test/CodeGen/Mips/llvm-ir/select.ll b/test/CodeGen/Mips/llvm-ir/select.ll new file mode 100644 index 000000000000..736bc579088d --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/select.ll @@ -0,0 +1,702 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=M2 -check-prefix=M2-M3 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=CMOV \ +; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R1 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=CMOV \ +; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-32 +; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=M3 -check-prefix=M2-M3 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64 + +define signext i1 @tst_select_i1_i1(i1 signext %s, + i1 signext %x, i1 signext %y) { +entry: + ; ALL-LABEL: tst_select_i1_i1: + + ; M2-M3: andi $[[T0:[0-9]+]], $4, 1 + ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2-M3: move $5, $6 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: move $2, $5 + + ; CMOV: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV: movn $6, $5, $[[T0]] + ; CMOV: move $2, $6 + + ; SEL: andi $[[T0:[0-9]+]], $4, 1 + ; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]] + ; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]] + ; SEL: or $2, $[[T2]], $[[T1]] + %r = select i1 %s, i1 %x, i1 %y + ret i1 %r +} + +define signext i8 @tst_select_i1_i8(i1 signext %s, + i8 signext %x, i8 signext %y) { +entry: + ; ALL-LABEL: tst_select_i1_i8: + + ; M2-M3: andi $[[T0:[0-9]+]], $4, 1 + ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2-M3: move $5, $6 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: move $2, $5 + + ; CMOV: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV: movn $6, $5, $[[T0]] + ; CMOV: move $2, $6 + + ; SEL: andi $[[T0:[0-9]+]], $4, 1 + ; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]] + ; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]] + ; SEL: or $2, $[[T2]], $[[T1]] + %r = select i1 %s, i8 %x, i8 %y + ret i8 %r +} + +define signext i32 @tst_select_i1_i32(i1 signext %s, + i32 signext %x, i32 signext %y) { +entry: + ; ALL-LABEL: tst_select_i1_i32: + + ; M2-M3: andi $[[T0:[0-9]+]], $4, 1 + ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2-M3: move $5, $6 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: move $2, $5 + + ; CMOV: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV: movn $6, $5, $[[T0]] + ; CMOV: move $2, $6 + + ; SEL: andi $[[T0:[0-9]+]], $4, 1 + ; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]] + ; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]] + ; SEL: or $2, $[[T2]], $[[T1]] + %r = select i1 %s, i32 %x, i32 %y + ret i32 %r +} + +define signext i64 @tst_select_i1_i64(i1 signext %s, + i64 signext %x, i64 signext %y) { +entry: + ; ALL-LABEL: tst_select_i1_i64: + + ; M2: andi $[[T0:[0-9]+]], $4, 1 + ; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M2: nop + ; M2: lw $[[T1:[0-9]+]], 16($sp) + ; M2: $[[BB0]]: + ; FIXME: This branch is redundant + ; M2: bnez $[[T0]], $[[BB1:BB[0-9_]+]] + ; M2: nop + ; M2: lw $[[T2:[0-9]+]], 20($sp) + ; M2: $[[BB1]]: + ; M2: move $2, $[[T1]] + ; M2: jr $ra + ; M2: move $3, $[[T2]] + + ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV-32: lw $2, 16($sp) + ; CMOV-32: movn $2, $6, $[[T0]] + ; CMOV-32: lw $3, 20($sp) + ; CMOV-32: movn $3, $7, $[[T0]] + + ; SEL-32: andi $[[T0:[0-9]+]], $4, 1 + ; SEL-32: selnez $[[T1:[0-9]+]], $6, $[[T0]] + ; SEL-32: lw $[[T2:[0-9]+]], 16($sp) + ; SEL-32: seleqz $[[T3:[0-9]+]], $[[T2]], $[[T0]] + ; SEL-32: or $2, $[[T1]], $[[T3]] + ; SEL-32: selnez $[[T4:[0-9]+]], $7, $[[T0]] + ; SEL-32: lw $[[T5:[0-9]+]], 20($sp) + ; SEL-32: seleqz $[[T6:[0-9]+]], $[[T5]], $[[T0]] + ; SEL-32: or $3, $[[T4]], $[[T6]] + + ; M3: andi $[[T0:[0-9]+]], $4, 1 + ; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M3: nop + ; M3: move $5, $6 + ; M3: $[[BB0]]: + ; M3: jr $ra + ; M3: move $2, $5 + + ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV-64: movn $6, $5, $[[T0]] + ; CMOV-64: move $2, $6 + + ; SEL-64: andi $[[T0:[0-9]+]], $4, 1 + ; FIXME: This shift is redundant + ; SEL-64: sll $[[T0]], $[[T0]], 0 + ; SEL-64: seleqz $[[T1:[0-9]+]], $6, $[[T0]] + ; SEL-64: selnez $[[T0]], $5, $[[T0]] + ; SEL-64: or $2, $[[T0]], $[[T1]] + %r = select i1 %s, i64 %x, i64 %y + ret i64 %r +} + +define float @tst_select_i1_float(i1 signext %s, float %x, float %y) { +entry: + ; ALL-LABEL: tst_select_i1_float: + + ; M2-M3: andi $[[T0:[0-9]+]], $4, 1 + ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: jr $ra + ; M2: mtc1 $6, $f0 + ; M3: mov.s $f13, $f14 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2: mtc1 $5, $f0 + ; M3: mov.s $f0, $f13 + + ; CMOV-32: mtc1 $6, $f0 + ; CMOV-32: mtc1 $5, $f1 + ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV-32: movn.s $f0, $f1, $[[T0]] + + ; SEL-32: mtc1 $5, $[[F0:f[0-9]+]] + ; SEL-32: mtc1 $6, $[[F1:f[0-9]+]] + ; SEL-32: mtc1 $4, $f0 + ; SEL-32: sel.s $f0, $[[F1]], $[[F0]] + + ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV-64: movn.s $f14, $f13, $[[T0]] + ; CMOV-64: mov.s $f0, $f14 + + ; SEL-64: mtc1 $4, $f0 + ; SEL-64: sel.s $f0, $f14, $f13 + %r = select i1 %s, float %x, float %y + ret float %r +} + +define float @tst_select_i1_float_reordered(float %x, float %y, + i1 signext %s) { +entry: + ; ALL-LABEL: tst_select_i1_float_reordered: + + ; M2-M3: andi $[[T0:[0-9]+]], $6, 1 + ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.s $f12, $f14 + ; M3: mov.s $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.s $f0, $f12 + + ; CMOV-32: andi $[[T0:[0-9]+]], $6, 1 + ; CMOV-32: movn.s $f14, $f12, $[[T0]] + ; CMOV-32: mov.s $f0, $f14 + + ; SEL-32: mtc1 $6, $f0 + ; SEL-32: sel.s $f0, $f14, $f12 + + ; CMOV-64: andi $[[T0:[0-9]+]], $6, 1 + ; CMOV-64: movn.s $f13, $f12, $[[T0]] + ; CMOV-64: mov.s $f0, $f13 + + ; SEL-64: mtc1 $6, $f0 + ; SEL-64: sel.s $f0, $f13, $f12 + %r = select i1 %s, float %x, float %y + ret float %r +} + +define double @tst_select_i1_double(i1 signext %s, double %x, double %y) { +entry: + ; ALL-LABEL: tst_select_i1_double: + + ; M2: andi $[[T0:[0-9]+]], $4, 1 + ; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M2: nop + ; M2: ldc1 $f0, 16($sp) + ; M2: jr $ra + ; M2: nop + ; M2: $[[BB0]]: + ; M2: mtc1 $7, $f0 + ; M2: jr $ra + ; M2: mtc1 $6, $f1 + + ; CMOV-32: mtc1 $7, $[[F0:f[0-9]+]] + ; CMOV-32R1: mtc1 $6, $f{{[0-9]+}} + ; CMOV-32R2 mthc1 $6, $[[F0]] + ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV-32: ldc1 $f0, 16($sp) + ; CMOV-32: movn.d $f0, $[[F0]], $[[T0]] + + ; SEL-32: mtc1 $7, $[[F0:f[0-9]+]] + ; SEL-32: mthc1 $6, $[[F0]] + ; SEL-32: ldc1 $[[F1:f[0-9]+]], 16($sp) + ; SEL-32: mtc1 $4, $f0 + ; SEL-32: sel.d $f0, $[[F1]], $[[F0]] + + ; M3: andi $[[T0:[0-9]+]], $4, 1 + ; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M3: nop + ; M3: mov.d $f13, $f14 + ; M3: $[[BB0]]: + ; M3: jr $ra + ; M3: mov.d $f0, $f13 + + ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV-64: movn.d $f14, $f13, $[[T0]] + ; CMOV-64: mov.d $f0, $f14 + + ; SEL-64: mtc1 $4, $f0 + ; SEL-64: sel.d $f0, $f14, $f13 + %r = select i1 %s, double %x, double %y + ret double %r +} + +define double @tst_select_i1_double_reordered(double %x, double %y, + i1 signext %s) { +entry: + ; ALL-LABEL: tst_select_i1_double_reordered: + + ; M2: lw $[[T0:[0-9]+]], 16($sp) + ; M2: andi $[[T1:[0-9]+]], $[[T0]], 1 + ; M2: bnez $[[T1]], $[[BB0:BB[0-9_]+]] + ; M2: nop + ; M2: mov.d $f12, $f14 + ; M2: $[[BB0]]: + ; M2: jr $ra + ; M2: mov.d $f0, $f12 + + ; CMOV-32: lw $[[T0:[0-9]+]], 16($sp) + ; CMOV-32: andi $[[T1:[0-9]+]], $[[T0]], 1 + ; CMOV-32: movn.d $f14, $f12, $[[T1]] + ; CMOV-32: mov.d $f0, $f14 + + ; SEL-32: lw $[[T0:[0-9]+]], 16($sp) + ; SEL-32: mtc1 $[[T0]], $f0 + ; SEL-32: sel.d $f0, $f14, $f12 + + ; M3: andi $[[T0:[0-9]+]], $6, 1 + ; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M3: nop + ; M3: mov.d $f12, $f13 + ; M3: $[[BB0]]: + ; M3: jr $ra + ; M3: mov.d $f0, $f12 + + ; CMOV-64: andi $[[T0:[0-9]+]], $6, 1 + ; CMOV-64: movn.d $f13, $f12, $[[T0]] + ; CMOV-64: mov.d $f0, $f13 + + ; SEL-64: mtc1 $6, $f0 + ; SEL-64: sel.d $f0, $f13, $f12 + %r = select i1 %s, double %x, double %y + ret double %r +} + +define float @tst_select_fcmp_olt_float(float %x, float %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_olt_float: + + ; M2: c.olt.s $f12, $f14 + ; M3: c.olt.s $f12, $f13 + ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.s $f12, $f14 + ; M3: mov.s $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.s $f0, $f12 + + ; CMOV-32: c.olt.s $f12, $f14 + ; CMOV-32: movt.s $f14, $f12, $fcc0 + ; CMOV-32: mov.s $f0, $f14 + + ; SEL-32: cmp.lt.s $f0, $f12, $f14 + ; SEL-32: sel.s $f0, $f14, $f12 + + ; CMOV-64: c.olt.s $f12, $f13 + ; CMOV-64: movt.s $f13, $f12, $fcc0 + ; CMOV-64: mov.s $f0, $f13 + + ; SEL-64: cmp.lt.s $f0, $f12, $f13 + ; SEL-64: sel.s $f0, $f13, $f12 + %s = fcmp olt float %x, %y + %r = select i1 %s, float %x, float %y + ret float %r +} + +define float @tst_select_fcmp_ole_float(float %x, float %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_ole_float: + + ; M2: c.ole.s $f12, $f14 + ; M3: c.ole.s $f12, $f13 + ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.s $f12, $f14 + ; M3: mov.s $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.s $f0, $f12 + + ; CMOV-32: c.ole.s $f12, $f14 + ; CMOV-32: movt.s $f14, $f12, $fcc0 + ; CMOV-32: mov.s $f0, $f14 + + ; SEL-32: cmp.le.s $f0, $f12, $f14 + ; SEL-32: sel.s $f0, $f14, $f12 + + ; CMOV-64: c.ole.s $f12, $f13 + ; CMOV-64: movt.s $f13, $f12, $fcc0 + ; CMOV-64: mov.s $f0, $f13 + + ; SEL-64: cmp.le.s $f0, $f12, $f13 + ; SEL-64: sel.s $f0, $f13, $f12 + %s = fcmp ole float %x, %y + %r = select i1 %s, float %x, float %y + ret float %r +} + +define float @tst_select_fcmp_ogt_float(float %x, float %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_ogt_float: + + ; M2: c.ule.s $f12, $f14 + ; M3: c.ule.s $f12, $f13 + ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.s $f12, $f14 + ; M3: mov.s $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.s $f0, $f12 + + ; CMOV-32: c.ule.s $f12, $f14 + ; CMOV-32: movf.s $f14, $f12, $fcc0 + ; CMOV-32: mov.s $f0, $f14 + + ; SEL-32: cmp.lt.s $f0, $f14, $f12 + ; SEL-32: sel.s $f0, $f14, $f12 + + ; CMOV-64: c.ule.s $f12, $f13 + ; CMOV-64: movf.s $f13, $f12, $fcc0 + ; CMOV-64: mov.s $f0, $f13 + + ; SEL-64: cmp.lt.s $f0, $f13, $f12 + ; SEL-64: sel.s $f0, $f13, $f12 + %s = fcmp ogt float %x, %y + %r = select i1 %s, float %x, float %y + ret float %r +} + +define float @tst_select_fcmp_oge_float(float %x, float %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_oge_float: + + ; M2: c.ult.s $f12, $f14 + ; M3: c.ult.s $f12, $f13 + ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.s $f12, $f14 + ; M3: mov.s $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.s $f0, $f12 + + ; CMOV-32: c.ult.s $f12, $f14 + ; CMOV-32: movf.s $f14, $f12, $fcc0 + ; CMOV-32: mov.s $f0, $f14 + + ; SEL-32: cmp.le.s $f0, $f14, $f12 + ; SEL-32: sel.s $f0, $f14, $f12 + + ; CMOV-64: c.ult.s $f12, $f13 + ; CMOV-64: movf.s $f13, $f12, $fcc0 + ; CMOV-64: mov.s $f0, $f13 + + ; SEL-64: cmp.le.s $f0, $f13, $f12 + ; SEL-64: sel.s $f0, $f13, $f12 + %s = fcmp oge float %x, %y + %r = select i1 %s, float %x, float %y + ret float %r +} + +define float @tst_select_fcmp_oeq_float(float %x, float %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_oeq_float: + + ; M2: c.eq.s $f12, $f14 + ; M3: c.eq.s $f12, $f13 + ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.s $f12, $f14 + ; M3: mov.s $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.s $f0, $f12 + + ; CMOV-32: c.eq.s $f12, $f14 + ; CMOV-32: movt.s $f14, $f12, $fcc0 + ; CMOV-32: mov.s $f0, $f14 + + ; SEL-32: cmp.eq.s $f0, $f12, $f14 + ; SEL-32: sel.s $f0, $f14, $f12 + + ; CMOV-64: c.eq.s $f12, $f13 + ; CMOV-64: movt.s $f13, $f12, $fcc0 + ; CMOV-64: mov.s $f0, $f13 + + ; SEL-64: cmp.eq.s $f0, $f12, $f13 + ; SEL-64: sel.s $f0, $f13, $f12 + %s = fcmp oeq float %x, %y + %r = select i1 %s, float %x, float %y + ret float %r +} + +define float @tst_select_fcmp_one_float(float %x, float %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_one_float: + + ; M2: c.ueq.s $f12, $f14 + ; M3: c.ueq.s $f12, $f13 + ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.s $f12, $f14 + ; M3: mov.s $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.s $f0, $f12 + + ; CMOV-32: c.ueq.s $f12, $f14 + ; CMOV-32: movf.s $f14, $f12, $fcc0 + ; CMOV-32: mov.s $f0, $f14 + + ; SEL-32: cmp.ueq.s $f0, $f12, $f14 + ; SEL-32: mfc1 $[[T0:[0-9]+]], $f0 + ; SEL-32: not $[[T0]], $[[T0]] + ; SEL-32: mtc1 $[[T0:[0-9]+]], $f0 + ; SEL-32: sel.s $f0, $f14, $f12 + + ; CMOV-64: c.ueq.s $f12, $f13 + ; CMOV-64: movf.s $f13, $f12, $fcc0 + ; CMOV-64: mov.s $f0, $f13 + + ; SEL-64: cmp.ueq.s $f0, $f12, $f13 + ; SEL-64: mfc1 $[[T0:[0-9]+]], $f0 + ; SEL-64: not $[[T0]], $[[T0]] + ; SEL-64: mtc1 $[[T0:[0-9]+]], $f0 + ; SEL-64: sel.s $f0, $f13, $f12 + + %s = fcmp one float %x, %y + %r = select i1 %s, float %x, float %y + ret float %r +} + +define double @tst_select_fcmp_olt_double(double %x, double %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_olt_double: + + ; M2: c.olt.d $f12, $f14 + ; M3: c.olt.d $f12, $f13 + ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.d $f12, $f14 + ; M3: mov.d $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.d $f0, $f12 + + ; CMOV-32: c.olt.d $f12, $f14 + ; CMOV-32: movt.d $f14, $f12, $fcc0 + ; CMOV-32: mov.d $f0, $f14 + + ; SEL-32: cmp.lt.d $f0, $f12, $f14 + ; SEL-32: sel.d $f0, $f14, $f12 + + ; CMOV-64: c.olt.d $f12, $f13 + ; CMOV-64: movt.d $f13, $f12, $fcc0 + ; CMOV-64: mov.d $f0, $f13 + + ; SEL-64: cmp.lt.d $f0, $f12, $f13 + ; SEL-64: sel.d $f0, $f13, $f12 + %s = fcmp olt double %x, %y + %r = select i1 %s, double %x, double %y + ret double %r +} + +define double @tst_select_fcmp_ole_double(double %x, double %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_ole_double: + + ; M2: c.ole.d $f12, $f14 + ; M3: c.ole.d $f12, $f13 + ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.d $f12, $f14 + ; M3: mov.d $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.d $f0, $f12 + + ; CMOV-32: c.ole.d $f12, $f14 + ; CMOV-32: movt.d $f14, $f12, $fcc0 + ; CMOV-32: mov.d $f0, $f14 + + ; SEL-32: cmp.le.d $f0, $f12, $f14 + ; SEL-32: sel.d $f0, $f14, $f12 + + ; CMOV-64: c.ole.d $f12, $f13 + ; CMOV-64: movt.d $f13, $f12, $fcc0 + ; CMOV-64: mov.d $f0, $f13 + + ; SEL-64: cmp.le.d $f0, $f12, $f13 + ; SEL-64: sel.d $f0, $f13, $f12 + %s = fcmp ole double %x, %y + %r = select i1 %s, double %x, double %y + ret double %r +} + +define double @tst_select_fcmp_ogt_double(double %x, double %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_ogt_double: + + ; M2: c.ule.d $f12, $f14 + ; M3: c.ule.d $f12, $f13 + ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.d $f12, $f14 + ; M3: mov.d $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.d $f0, $f12 + + ; CMOV-32: c.ule.d $f12, $f14 + ; CMOV-32: movf.d $f14, $f12, $fcc0 + ; CMOV-32: mov.d $f0, $f14 + + ; SEL-32: cmp.lt.d $f0, $f14, $f12 + ; SEL-32: sel.d $f0, $f14, $f12 + + ; CMOV-64: c.ule.d $f12, $f13 + ; CMOV-64: movf.d $f13, $f12, $fcc0 + ; CMOV-64: mov.d $f0, $f13 + + ; SEL-64: cmp.lt.d $f0, $f13, $f12 + ; SEL-64: sel.d $f0, $f13, $f12 + %s = fcmp ogt double %x, %y + %r = select i1 %s, double %x, double %y + ret double %r +} + +define double @tst_select_fcmp_oge_double(double %x, double %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_oge_double: + + ; M2: c.ult.d $f12, $f14 + ; M3: c.ult.d $f12, $f13 + ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.d $f12, $f14 + ; M3: mov.d $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.d $f0, $f12 + + ; CMOV-32: c.ult.d $f12, $f14 + ; CMOV-32: movf.d $f14, $f12, $fcc0 + ; CMOV-32: mov.d $f0, $f14 + + ; SEL-32: cmp.le.d $f0, $f14, $f12 + ; SEL-32: sel.d $f0, $f14, $f12 + + ; CMOV-64: c.ult.d $f12, $f13 + ; CMOV-64: movf.d $f13, $f12, $fcc0 + ; CMOV-64: mov.d $f0, $f13 + + ; SEL-64: cmp.le.d $f0, $f13, $f12 + ; SEL-64: sel.d $f0, $f13, $f12 + %s = fcmp oge double %x, %y + %r = select i1 %s, double %x, double %y + ret double %r +} + +define double @tst_select_fcmp_oeq_double(double %x, double %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_oeq_double: + + ; M2: c.eq.d $f12, $f14 + ; M3: c.eq.d $f12, $f13 + ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.d $f12, $f14 + ; M3: mov.d $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.d $f0, $f12 + + ; CMOV-32: c.eq.d $f12, $f14 + ; CMOV-32: movt.d $f14, $f12, $fcc0 + ; CMOV-32: mov.d $f0, $f14 + + ; SEL-32: cmp.eq.d $f0, $f12, $f14 + ; SEL-32: sel.d $f0, $f14, $f12 + + ; CMOV-64: c.eq.d $f12, $f13 + ; CMOV-64: movt.d $f13, $f12, $fcc0 + ; CMOV-64: mov.d $f0, $f13 + + ; SEL-64: cmp.eq.d $f0, $f12, $f13 + ; SEL-64: sel.d $f0, $f13, $f12 + %s = fcmp oeq double %x, %y + %r = select i1 %s, double %x, double %y + ret double %r +} + +define double @tst_select_fcmp_one_double(double %x, double %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_one_double: + + ; M2: c.ueq.d $f12, $f14 + ; M3: c.ueq.d $f12, $f13 + ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.d $f12, $f14 + ; M3: mov.d $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.d $f0, $f12 + + ; CMOV-32: c.ueq.d $f12, $f14 + ; CMOV-32: movf.d $f14, $f12, $fcc0 + ; CMOV-32: mov.d $f0, $f14 + + ; SEL-32: cmp.ueq.d $f0, $f12, $f14 + ; SEL-32: mfc1 $[[T0:[0-9]+]], $f0 + ; SEL-32: not $[[T0]], $[[T0]] + ; SEL-32: mtc1 $[[T0:[0-9]+]], $f0 + ; SEL-32: sel.d $f0, $f14, $f12 + + ; CMOV-64: c.ueq.d $f12, $f13 + ; CMOV-64: movf.d $f13, $f12, $fcc0 + ; CMOV-64: mov.d $f0, $f13 + + ; SEL-64: cmp.ueq.d $f0, $f12, $f13 + ; SEL-64: mfc1 $[[T0:[0-9]+]], $f0 + ; SEL-64: not $[[T0]], $[[T0]] + ; SEL-64: mtc1 $[[T0:[0-9]+]], $f0 + ; SEL-64: sel.d $f0, $f13, $f12 + %s = fcmp one double %x, %y + %r = select i1 %s, double %x, double %y + ret double %r +} diff --git a/test/CodeGen/Mips/longbranch.ll b/test/CodeGen/Mips/longbranch.ll index b9b52be01dad..ad0235eb0af4 100644 --- a/test/CodeGen/Mips/longbranch.ll +++ b/test/CodeGen/Mips/longbranch.ll @@ -123,7 +123,7 @@ end: ; MICROMIPS: $[[BB0]]: ; MICROMIPS: lw $[[R1:[0-9]+]], %got(x)($[[GP]]) -; MICROMIPS: addiu $[[R2:[0-9]+]], $zero, 1 +; MICROMIPS: li16 $[[R2:[0-9]+]], 1 ; MICROMIPS: sw $[[R2]], 0($[[R1]]) ; MICROMIPS: $[[BB2]]: ; MICROMIPS: jr $ra diff --git a/test/CodeGen/Mips/mbrsize4a.ll b/test/CodeGen/Mips/mbrsize4a.ll index c80299166ab4..15e1f47ce29e 100644 --- a/test/CodeGen/Mips/mbrsize4a.ll +++ b/test/CodeGen/Mips/mbrsize4a.ll @@ -34,4 +34,4 @@ attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"= attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #2 = { nounwind } -!1 = metadata !{i32 68} +!1 = !{i32 68} diff --git a/test/CodeGen/Mips/micromips-addiu.ll b/test/CodeGen/Mips/micromips-addiu.ll new file mode 100644 index 000000000000..c5bee34028c8 --- /dev/null +++ b/test/CodeGen/Mips/micromips-addiu.ll @@ -0,0 +1,32 @@ +; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \ +; RUN: -relocation-model=pic -O3 < %s | FileCheck %s + +@x = global i32 65504, align 4 +@y = global i32 60929, align 4 +@z = global i32 60929, align 4 +@.str = private unnamed_addr constant [7 x i8] c"%08x \0A\00", align 1 + +define i32 @main() nounwind { +entry: + %0 = load i32* @x, align 4 + %addiu1 = add i32 %0, -7 + %call1 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds + ([7 x i8]* @.str, i32 0, i32 0), i32 %addiu1) + + %1 = load i32* @y, align 4 + %addiu2 = add i32 %1, 55 + %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds + ([7 x i8]* @.str, i32 0, i32 0), i32 %addiu2) + + %2 = load i32* @z, align 4 + %addiu3 = add i32 %2, 24 + %call3 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds + ([7 x i8]* @.str, i32 0, i32 0), i32 %addiu3) + ret i32 0 +} + +declare i32 @printf(i8*, ...) + +; CHECK: addius5 ${{[0-9]+}}, -7 +; CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 55 +; CHECK: addiur2 ${{[2-7]|16|17}}, ${{[2-7]|16|17}}, 24 diff --git a/test/CodeGen/Mips/micromips-andi.ll b/test/CodeGen/Mips/micromips-andi.ll new file mode 100644 index 000000000000..b82d2b09eae4 --- /dev/null +++ b/test/CodeGen/Mips/micromips-andi.ll @@ -0,0 +1,25 @@ +; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \ +; RUN: -relocation-model=pic -O3 < %s | FileCheck %s + +@x = global i32 65504, align 4 +@y = global i32 60929, align 4 +@.str = private unnamed_addr constant [7 x i8] c"%08x \0A\00", align 1 + +define i32 @main() nounwind { +entry: + %0 = load i32* @x, align 4 + %and1 = and i32 %0, 4 + %call1 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds + ([7 x i8]* @.str, i32 0, i32 0), i32 %and1) + + %1 = load i32* @y, align 4 + %and2 = and i32 %1, 5 + %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds + ([7 x i8]* @.str, i32 0, i32 0), i32 %and2) + ret i32 0 +} + +declare i32 @printf(i8*, ...) + +; CHECK: andi16 ${{[2-7]|16|17}}, ${{[2-7]|16|17}} +; CHECK: andi ${{[0-9]+}}, ${{[0-9]+}} diff --git a/test/CodeGen/Mips/micromips-atomic.ll b/test/CodeGen/Mips/micromips-atomic.ll index a50e0b7850c3..82eee4bd84b5 100644 --- a/test/CodeGen/Mips/micromips-atomic.ll +++ b/test/CodeGen/Mips/micromips-atomic.ll @@ -14,5 +14,5 @@ entry: ; CHECK: ll $[[R1:[0-9]+]], 0($[[R0]]) ; CHECK: addu $[[R2:[0-9]+]], $[[R1]], $4 ; CHECK: sc $[[R2]], 0($[[R0]]) -; CHECK: beqz $[[R2]], $[[BB0]] +; CHECK: beqzc $[[R2]], $[[BB0]] } diff --git a/test/CodeGen/Mips/micromips-atomic1.ll b/test/CodeGen/Mips/micromips-atomic1.ll new file mode 100644 index 000000000000..37c3d7682e4f --- /dev/null +++ b/test/CodeGen/Mips/micromips-atomic1.ll @@ -0,0 +1,29 @@ +; RUN: llc -march=mipsel -filetype=obj --disable-machine-licm -mattr=micromips < %s -o - \ +; RUN: | llvm-objdump -no-show-raw-insn -arch mipsel -mcpu=mips32r2 -mattr=micromips -d - \ +; RUN: | FileCheck %s -check-prefix=MICROMIPS + +; Use llvm-objdump to check wheter the encodings of microMIPS atomic instructions are correct. +; While emitting assembly files directly when in microMIPS mode, it is possible to emit a mips32r2 +; instruction instead of microMIPS instruction, and since many mips32r2 and microMIPS +; instructions have identical assembly formats, invalid instruction cannot be detected. + +@y = common global i8 0, align 1 + +define signext i8 @AtomicLoadAdd8(i8 signext %incr) nounwind { +entry: + %0 = atomicrmw add i8* @y, i8 %incr monotonic + ret i8 %0 + +; MICROMIPS: ll ${{[0-9]+}}, 0(${{[0-9]+}}) +; MICROMIPS: sc ${{[0-9]+}}, 0(${{[0-9]+}}) +} + +define signext i8 @AtomicCmpSwap8(i8 signext %oldval, i8 signext %newval) nounwind { +entry: + %pair0 = cmpxchg i8* @y, i8 %oldval, i8 %newval monotonic monotonic + %0 = extractvalue { i8, i1 } %pair0, 0 + ret i8 %0 + +; MICROMIPS: ll ${{[0-9]+}}, 0(${{[0-9]+}}) +; MICROMIPS: sc ${{[0-9]+}}, 0(${{[0-9]+}}) +} diff --git a/test/CodeGen/Mips/micromips-compact-branches.ll b/test/CodeGen/Mips/micromips-compact-branches.ll new file mode 100644 index 000000000000..670f9a05064f --- /dev/null +++ b/test/CodeGen/Mips/micromips-compact-branches.ll @@ -0,0 +1,19 @@ +; RUN: llc %s -march=mipsel -mattr=micromips -filetype=asm -O3 \ +; RUN: -disable-mips-delay-filler -relocation-model=pic -o - | FileCheck %s + +define void @main() nounwind uwtable { +entry: + %x = alloca i32, align 4 + %0 = load i32* %x, align 4 + %cmp = icmp eq i32 %0, 0 + br i1 %cmp, label %if.then, label %if.end + +if.then: + store i32 10, i32* %x, align 4 + br label %if.end + +if.end: + ret void +} + +; CHECK: bnezc diff --git a/test/CodeGen/Mips/micromips-delay-slot-jr.ll b/test/CodeGen/Mips/micromips-delay-slot-jr.ll new file mode 100644 index 000000000000..df593b35e2a6 --- /dev/null +++ b/test/CodeGen/Mips/micromips-delay-slot-jr.ll @@ -0,0 +1,48 @@ +; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \ +; RUN: -relocation-model=static -O2 < %s | FileCheck %s + +@main.L = internal unnamed_addr constant [3 x i8*] [i8* blockaddress(@main, %L1), i8* blockaddress(@main, %L2), i8* null], align 4 +@str = private unnamed_addr constant [2 x i8] c"A\00" +@str2 = private unnamed_addr constant [2 x i8] c"B\00" + +define i32 @main() #0 { +entry: + br label %L1 + +L1: ; preds = %entry, %L1 + %i.0 = phi i32 [ 0, %entry ], [ %inc, %L1 ] + %puts = tail call i32 @puts(i8* getelementptr inbounds ([2 x i8]* @str, i32 0, i32 0)) + %inc = add i32 %i.0, 1 + %arrayidx = getelementptr inbounds [3 x i8*]* @main.L, i32 0, i32 %i.0 + %0 = load i8** %arrayidx, align 4, !tbaa !1 + indirectbr i8* %0, [label %L1, label %L2] + +L2: ; preds = %L1 + %puts2 = tail call i32 @puts(i8* getelementptr inbounds ([2 x i8]* @str2, i32 0, i32 0)) + ret i32 0 +} + +declare i32 @puts(i8* nocapture readonly) #1 + +!1 = !{!2, !2, i64 0} +!2 = !{!"any pointer", !3, i64 0} +!3 = !{!"omnipotent char", !4, i64 0} +!4 = !{!"Simple C/C++ TBAA"} + +; CHECK: jr +; CHECK-NEXT: nop + +%struct.foostruct = type { [3 x float] } +%struct.barstruct = type { %struct.foostruct, float } +@bar_ary = common global [4 x %struct.barstruct] zeroinitializer, align 4 +define float* @spooky(i32 signext %i) #0 { + + %safe = getelementptr inbounds [4 x %struct.barstruct]* @bar_ary, i32 0, i32 %i, i32 1 + store float 1.420000e+02, float* %safe, align 4, !tbaa !1 + ret float* %safe +} + +; CHECK: spooky: +; CHECK: jr $ra +; CHECK-NEXT: nop + diff --git a/test/CodeGen/Mips/micromips-delay-slot.ll b/test/CodeGen/Mips/micromips-delay-slot.ll new file mode 100644 index 000000000000..b5f6c56235bc --- /dev/null +++ b/test/CodeGen/Mips/micromips-delay-slot.ll @@ -0,0 +1,18 @@ +; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \ +; RUN: -relocation-model=static -O2 < %s | FileCheck %s + +; Function Attrs: nounwind +define i32 @foo(i32 signext %a) #0 { +entry: + %a.addr = alloca i32, align 4 + store i32 %a, i32* %a.addr, align 4 + %0 = load i32* %a.addr, align 4 + %shl = shl i32 %0, 2 + %call = call i32 @bar(i32 signext %shl) + ret i32 %call +} + +declare i32 @bar(i32 signext) #1 + +; CHECK: jals +; CHECK-NEXT: sll16 diff --git a/test/CodeGen/Mips/micromips-li.ll b/test/CodeGen/Mips/micromips-li.ll new file mode 100644 index 000000000000..ac315f938251 --- /dev/null +++ b/test/CodeGen/Mips/micromips-li.ll @@ -0,0 +1,18 @@ +; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \ +; RUN: -relocation-model=pic -O3 < %s | FileCheck %s + +@x = external global i32 +@y = external global i32 +@z = external global i32 + +define i32 @main() nounwind { +entry: + store i32 1, i32* @x, align 4 + store i32 2148, i32* @y, align 4 + store i32 33332, i32* @z, align 4 + ret i32 0 +} + +; CHECK: li16 ${{[2-7]|16|17}}, 1 +; CHECK: addiu ${{[0-9]+}}, $zero, 2148 +; CHECK: ori ${{[0-9]+}}, $zero, 33332 diff --git a/test/CodeGen/Mips/micromips-rdhwr-directives.ll b/test/CodeGen/Mips/micromips-rdhwr-directives.ll new file mode 100644 index 000000000000..af40a8796824 --- /dev/null +++ b/test/CodeGen/Mips/micromips-rdhwr-directives.ll @@ -0,0 +1,15 @@ +; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=static < %s \ +; RUN: -mattr=+micromips | FileCheck %s + +@a = external thread_local global i32 + +define i32 @foo() nounwind readonly { +entry: +; CHECK: .set push +; CHECK: .set mips32r2 +; CHECK: rdhwr +; CHECK: .set pop + + %0 = load i32* @a, align 4 + ret i32 %0 +} diff --git a/test/CodeGen/Mips/micromips-shift.ll b/test/CodeGen/Mips/micromips-shift.ll new file mode 100644 index 000000000000..8215010bfc78 --- /dev/null +++ b/test/CodeGen/Mips/micromips-shift.ll @@ -0,0 +1,44 @@ +; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \ +; RUN: -relocation-model=pic -O3 < %s | FileCheck %s + +@a = global i32 10, align 4 +@b = global i32 0, align 4 +@c = global i32 10, align 4 +@d = global i32 0, align 4 + +define i32 @shift_left() nounwind { +entry: + %0 = load i32* @a, align 4 + %shl = shl i32 %0, 4 + store i32 %shl, i32* @b, align 4 + + %1 = load i32* @c, align 4 + %shl1 = shl i32 %1, 10 + store i32 %shl1, i32* @d, align 4 + + ret i32 0 +} + +; CHECK: sll16 ${{[2-7]|16|17}}, ${{[2-7]|16|17}}, {{[0-7]}} +; CHECK: sll ${{[0-9]+}}, ${{[0-9]+}}, {{[0-9]+}} + +@i = global i32 10654, align 4 +@j = global i32 0, align 4 +@m = global i32 10, align 4 +@n = global i32 0, align 4 + +define i32 @shift_right() nounwind { +entry: + %0 = load i32* @i, align 4 + %shr = lshr i32 %0, 4 + store i32 %shr, i32* @j, align 4 + + %1 = load i32* @m, align 4 + %shr1 = lshr i32 %1, 10 + store i32 %shr1, i32* @n, align 4 + + ret i32 0 +} + +; CHECK: srl16 ${{[2-7]|16|17}}, ${{[2-7]|16|17}}, {{[0-7]}} +; CHECK: srl ${{[0-9]+}}, ${{[0-9]+}}, {{[0-9]+}} diff --git a/test/CodeGen/Mips/mips16-hf-attr-2.ll b/test/CodeGen/Mips/mips16-hf-attr-2.ll new file mode 100644 index 000000000000..60c6eaad8f76 --- /dev/null +++ b/test/CodeGen/Mips/mips16-hf-attr-2.ll @@ -0,0 +1,45 @@ +; Check that stubs generation for mips16 hard-float mode does not depend +; on the function 'use-soft-float' attribute's value. +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel \ +; RUN: -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s + +define void @bar_sf() #1 { +; CHECK: bar_sf: +entry: + %call1 = call float @foo(float 1.000000e+00) +; CHECK: lw $3, %call16(foo)($2) +; CHECK-NOT: lw $5, %got(__mips16_call_stub_sf_1)($3) + ret void +} + +define void @bar_hf() #0 { +; CHECK: bar_hf: +entry: + %call1 = call float @foo(float 1.000000e+00) +; CHECK: lw $2, %call16(foo)($3) +; CHECK: lw $5, %got(__mips16_call_stub_sf_1)($3) + ret void +} + +declare float @foo(float) #2 + +attributes #0 = { + nounwind + "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" + "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" + "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" + "unsafe-fp-math"="false" "use-soft-float"="false" +} +attributes #1 = { + nounwind + "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" + "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" + "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" + "unsafe-fp-math"="false" "use-soft-float"="true" +} +attributes #2 = { + "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" + "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" + "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" + "unsafe-fp-math"="false" "use-soft-float"="true" +} diff --git a/test/CodeGen/Mips/mips16-hf-attr.ll b/test/CodeGen/Mips/mips16-hf-attr.ll index d9ad6295bef8..c6ad442fdea2 100644 --- a/test/CodeGen/Mips/mips16-hf-attr.ll +++ b/test/CodeGen/Mips/mips16-hf-attr.ll @@ -3,8 +3,8 @@ ; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel \ ; RUN: -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -define void @bar_sf() #0 { -; CHECK: bar_sf: +define void @bar_hf() #0 { +; CHECK: bar_hf: entry: %call1 = call float @foo(float 1.000000e+00) ; CHECK: lw $2, %call16(foo)($3) @@ -12,12 +12,12 @@ entry: ret void } -define void @bar_hf() #1 { -; CHECK: bar_hf: +define void @bar_sf() #1 { +; CHECK: bar_sf: entry: %call1 = call float @foo(float 1.000000e+00) -; CHECK: lw $2, %call16(foo)($3) -; CHECK: lw $5, %got(__mips16_call_stub_sf_1)($3) +; CHECK: lw $3, %call16(foo)($2) +; CHECK-NOT: lw $5, %got(__mips16_call_stub_sf_1)($3) ret void } diff --git a/test/CodeGen/Mips/mips64-f128.ll b/test/CodeGen/Mips/mips64-f128.ll index f0cbbd08d79a..6987d4ab0734 100644 --- a/test/CodeGen/Mips/mips64-f128.ll +++ b/test/CodeGen/Mips/mips64-f128.ll @@ -545,7 +545,7 @@ entry: ; ALL-LABEL: load_LD_float: ; ALL: ld $[[R0:[0-9]+]], %got_disp(gf1) -; ALL: lw $4, 0($[[R0]]) +; ALL: lwu $4, 0($[[R0]]) ; ALL: ld $25, %call16(__extendsftf2) ; ALL: jalr $25 diff --git a/test/CodeGen/Mips/msa/arithmetic_float.ll b/test/CodeGen/Mips/msa/arithmetic_float.ll index 86e57ac85a3b..9aae284fe535 100644 --- a/test/CodeGen/Mips/msa/arithmetic_float.ll +++ b/test/CodeGen/Mips/msa/arithmetic_float.ll @@ -276,8 +276,8 @@ define void @fexp2_v4f32_2(<4 x float>* %c, <4 x float>* %a) nounwind { ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) %2 = tail call <4 x float> @llvm.exp2.v4f32 (<4 x float> %1) %3 = fmul <4 x float> <float 2.0, float 2.0, float 2.0, float 2.0>, %2 - ; CHECK-DAG: lui [[R3:\$[0-9]+]], 16384 - ; CHECK-DAG: fill.w [[R4:\$w[0-9]+]], [[R3]] + ; CHECK-DAG: ldi.w [[R3:\$w[0-9]+]], 1 + ; CHECK-DAG: ffint_u.w [[R4:\$w[0-9]+]], [[R3]] ; CHECK-DAG: fexp2.w [[R5:\$w[0-9]+]], [[R4]], [[R1]] store <4 x float> %3, <4 x float>* %c ; CHECK-DAG: st.w [[R5]], 0($4) @@ -287,16 +287,14 @@ define void @fexp2_v4f32_2(<4 x float>* %c, <4 x float>* %a) nounwind { } define void @fexp2_v2f64_2(<2 x double>* %c, <2 x double>* %a) nounwind { - ; CHECK: .8byte 4611686018427387904 - ; CHECK-NEXT: .8byte 4611686018427387904 ; CHECK: fexp2_v2f64_2: %1 = load <2 x double>* %a ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) %2 = tail call <2 x double> @llvm.exp2.v2f64 (<2 x double> %1) %3 = fmul <2 x double> <double 2.0, double 2.0>, %2 - ; CHECK-DAG: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($ - ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0([[G_PTR]]) + ; CHECK-DAG: ldi.d [[R2:\$w[0-9]+]], 1 + ; CHECK-DAG: ffint_u.d [[R3:\$w[0-9]+]], [[R2]] ; CHECK-DAG: fexp2.d [[R4:\$w[0-9]+]], [[R3]], [[R1]] store <2 x double> %3, <2 x double>* %c ; CHECK-DAG: st.d [[R4]], 0($4) diff --git a/test/CodeGen/Mips/named-register-n32.ll b/test/CodeGen/Mips/named-register-n32.ll new file mode 100644 index 000000000000..1e5f53ac5c9c --- /dev/null +++ b/test/CodeGen/Mips/named-register-n32.ll @@ -0,0 +1,18 @@ +; RUN: llc -march=mips64 -relocation-model=static -mattr=+noabicalls,-n64,+n32 < %s | FileCheck %s + +define i32* @get_gp() { +entry: + %0 = call i64 @llvm.read_register.i64(metadata !0) + %1 = trunc i64 %0 to i32 + %2 = inttoptr i32 %1 to i32* + ret i32* %2 +} + +; CHECK-LABEL: get_gp: +; CHECK: sll $2, $gp, 0 + +declare i64 @llvm.read_register.i64(metadata) + +!llvm.named.register.$28 = !{!0} + +!0 = !{!"$28"} diff --git a/test/CodeGen/Mips/named-register-n64.ll b/test/CodeGen/Mips/named-register-n64.ll new file mode 100644 index 000000000000..31987726169e --- /dev/null +++ b/test/CodeGen/Mips/named-register-n64.ll @@ -0,0 +1,17 @@ +; RUN: llc -march=mips64 -relocation-model=static -mattr=+noabicalls < %s | FileCheck %s + +define i32* @get_gp() { +entry: + %0 = call i64 @llvm.read_register.i64(metadata !0) + %1 = inttoptr i64 %0 to i32* + ret i32* %1 +} + +; CHECK-LABEL: get_gp: +; CHECK: move $2, $gp + +declare i64 @llvm.read_register.i64(metadata) + +!llvm.named.register.$28 = !{!0} + +!0 = !{!"$28"} diff --git a/test/CodeGen/Mips/named-register-o32.ll b/test/CodeGen/Mips/named-register-o32.ll new file mode 100644 index 000000000000..0890c66283c3 --- /dev/null +++ b/test/CodeGen/Mips/named-register-o32.ll @@ -0,0 +1,17 @@ +; RUN: llc -march=mips -relocation-model=static -mattr=+noabicalls < %s | FileCheck %s + +define i32* @get_gp() { +entry: + %0 = call i32 @llvm.read_register.i32(metadata !0) + %1 = inttoptr i32 %0 to i32* + ret i32* %1 +} + +; CHECK-LABEL: get_gp: +; CHECK: move $2, $gp + +declare i32 @llvm.read_register.i32(metadata) + +!llvm.named.register.$28 = !{!0} + +!0 = !{!"$28"} diff --git a/test/CodeGen/Mips/nomips16.ll b/test/CodeGen/Mips/nomips16.ll index 0affb16ac7c2..5f7d74e41979 100644 --- a/test/CodeGen/Mips/nomips16.ll +++ b/test/CodeGen/Mips/nomips16.ll @@ -33,6 +33,6 @@ entry: ; CHECK: .end nofoo -attributes #0 = { nounwind "less-precise-fpmad"="false" "mips16" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" } -attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "nomips16" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "mips16" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "nomips16" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/Mips/octeon.ll b/test/CodeGen/Mips/octeon.ll index d5ff9bdf3608..9d82b74f5b7e 100644 --- a/test/CodeGen/Mips/octeon.ll +++ b/test/CodeGen/Mips/octeon.ll @@ -27,3 +27,69 @@ entry: %res = mul i64 %a, %b ret i64 %res } + +define i64 @cmpeq(i64 %a, i64 %b) nounwind { +entry: +; OCTEON-LABEL: cmpeq: +; OCTEON: jr $ra +; OCTEON: seq $2, $4, $5 +; MIPS64-LABEL: cmpeq: +; MIPS64: xor $1, $4, $5 +; MIPS64: sltiu $1, $1, 1 +; MIPS64: dsll $1, $1, 32 +; MIPS64: jr $ra +; MIPS64: dsrl $2, $1, 32 + %res = icmp eq i64 %a, %b + %res2 = zext i1 %res to i64 + ret i64 %res2 +} + +define i64 @cmpeqi(i64 %a) nounwind { +entry: +; OCTEON-LABEL: cmpeqi: +; OCTEON: jr $ra +; OCTEON: seqi $2, $4, 42 +; MIPS64-LABEL: cmpeqi: +; MIPS64: daddiu $1, $zero, 42 +; MIPS64: xor $1, $4, $1 +; MIPS64: sltiu $1, $1, 1 +; MIPS64: dsll $1, $1, 32 +; MIPS64: jr $ra +; MIPS64: dsrl $2, $1, 32 + %res = icmp eq i64 %a, 42 + %res2 = zext i1 %res to i64 + ret i64 %res2 +} + +define i64 @cmpne(i64 %a, i64 %b) nounwind { +entry: +; OCTEON-LABEL: cmpne: +; OCTEON: jr $ra +; OCTEON: sne $2, $4, $5 +; MIPS64-LABEL: cmpne: +; MIPS64: xor $1, $4, $5 +; MIPS64: sltu $1, $zero, $1 +; MIPS64: dsll $1, $1, 32 +; MIPS64: jr $ra +; MIPS64: dsrl $2, $1, 32 + %res = icmp ne i64 %a, %b + %res2 = zext i1 %res to i64 + ret i64 %res2 +} + +define i64 @cmpnei(i64 %a) nounwind { +entry: +; OCTEON-LABEL: cmpnei: +; OCTEON: jr $ra +; OCTEON: snei $2, $4, 42 +; MIPS64-LABEL: cmpnei: +; MIPS64: daddiu $1, $zero, 42 +; MIPS64: xor $1, $4, $1 +; MIPS64: sltu $1, $zero, $1 +; MIPS64: dsll $1, $1, 32 +; MIPS64: jr $ra +; MIPS64: dsrl $2, $1, 32 + %res = icmp ne i64 %a, 42 + %res2 = zext i1 %res to i64 + ret i64 %res2 +} diff --git a/test/CodeGen/Mips/powif64_16.ll b/test/CodeGen/Mips/powif64_16.ll index 48757276bb8c..33ec8c40c610 100644 --- a/test/CodeGen/Mips/powif64_16.ll +++ b/test/CodeGen/Mips/powif64_16.ll @@ -20,7 +20,7 @@ define double @foo_pow_f64(double %y, i32 %p) { attributes #0 = { nounwind optsize "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" } attributes #1 = { nounwind readonly } -!0 = metadata !{metadata !"double", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} -!3 = metadata !{metadata !"int", metadata !1} +!0 = !{!"double", !1} +!1 = !{!"omnipotent char", !2} +!2 = !{!"Simple C/C++ TBAA"} +!3 = !{!"int", !1} diff --git a/test/CodeGen/Mips/prevent-hoisting.ll b/test/CodeGen/Mips/prevent-hoisting.ll index da665c210909..210fe3b0f6d8 100644 --- a/test/CodeGen/Mips/prevent-hoisting.ll +++ b/test/CodeGen/Mips/prevent-hoisting.ll @@ -10,16 +10,19 @@ ; CHECK-LABEL: readLumaCoeff8x8_CABAC -; The check for "addiu" instruction is added so that we can match the correct "b" instruction. +; The check for first "addiu" instruction is added so that we can match the correct "b" instruction. ; CHECK: addiu ${{[0-9]+}}, $zero, -1 ; CHECK: b $[[BB0:BB[0-9_]+]] +; CHECK-NEXT: addiu ${{[0-9]+}}, $zero, 0 -; Check that sll instruction that writes to $1 starts basic block. -; CHECK: {{BB[0-9_#]+}}: +; Check that at the start of a fallthrough block there is a instruction that writes to $1. +; CHECK-NEXT: {{BB[0-9_#]+}}: +; CHECK-NEXT: lw $[[R1:[0-9]+]], %got(assignSE2partition)($[[R2:[0-9]+]]) ; CHECK-NEXT: sll $1, $[[R0:[0-9]+]], 4 -; Check that identical sll instruction starts another basic block. +; Check that identical instructions are at the start of a target block. ; CHECK: [[BB0]]: +; CHECK-NEXT: lw $[[R1]], %got(assignSE2partition)($[[R2]]) ; CHECK-NEXT: sll $1, $[[R0]], 4 diff --git a/test/CodeGen/Mips/seleq.ll b/test/CodeGen/Mips/seleq.ll index 190baad0b1db..9af422fa1bdb 100644 --- a/test/CodeGen/Mips/seleq.ll +++ b/test/CodeGen/Mips/seleq.ll @@ -10,7 +10,7 @@ @z3 = common global i32 0, align 4 @z4 = common global i32 0, align 4 -define void @calc_seleq() nounwind "target-cpu"="mips32" "target-features"="+o32,+mips32" { +define void @calc_seleq() nounwind { entry: %0 = load i32* @a, align 4 %1 = load i32* @b, align 4 diff --git a/test/CodeGen/Mips/small-section-reserve-gp.ll b/test/CodeGen/Mips/small-section-reserve-gp.ll index 03503fb2ae18..cbf0681c78e5 100644 --- a/test/CodeGen/Mips/small-section-reserve-gp.ll +++ b/test/CodeGen/Mips/small-section-reserve-gp.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-sde-elf -march=mipsel -relocation-model=static < %s \ +; RUN: llc -mtriple=mipsel-sde-elf -march=mipsel -relocation-model=static -mattr=+noabicalls -mgpopt < %s \ ; RUN: | FileCheck %s @i = internal unnamed_addr global i32 0, align 4 diff --git a/test/CodeGen/Mips/start-asm-file.ll b/test/CodeGen/Mips/start-asm-file.ll index 88724643166c..9dc501ce10b4 100644 --- a/test/CodeGen/Mips/start-asm-file.ll +++ b/test/CodeGen/Mips/start-asm-file.ll @@ -1,7 +1,4 @@ ; Check the emission of directives at the start of an asm file. -; This test is XFAILED until we fix the emission of '.option pic0' on -; N32. At the moment we check if subtarget is Mips64 when we should be -; checking the Subtarget's ABI. ; ### O32 ABI ### ; RUN: llc -filetype=asm -mtriple mips-unknown-linux -mcpu=mips32 \ |