diff options
Diffstat (limited to 'test/CodeGen')
48 files changed, 567 insertions, 63 deletions
diff --git a/test/CodeGen/ARM/fp16.ll b/test/CodeGen/ARM/fp16.ll new file mode 100644 index 000000000000..c5583b94befd --- /dev/null +++ b/test/CodeGen/ARM/fp16.ll @@ -0,0 +1,32 @@ +; RUN: llc < %s | FileCheck %s +; RUN: llc -mattr=+vfp3,+fp16 < %s | FileCheck --check-prefix=CHECK-FP16 %s +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32" +target triple = "armv7-eabi" + +@x = global i16 12902 +@y = global i16 0 +@z = common global i16 0 + +define arm_aapcs_vfpcc void @foo() nounwind { +; CHECK: foo: +; CHECK-FP6: foo: +entry: + %0 = load i16* @x, align 2 + %1 = load i16* @y, align 2 + %2 = tail call float @llvm.convert.from.fp16(i16 %0) +; CHECK: __gnu_h2f_ieee +; CHECK-FP16: vcvtb.f16.f32 + %3 = tail call float @llvm.convert.from.fp16(i16 %1) +; CHECK: __gnu_h2f_ieee +; CHECK-FP16: vcvtb.f16.f32 + %4 = fadd float %2, %3 + %5 = tail call i16 @llvm.convert.to.fp16(float %4) +; CHECK: __gnu_f2h_ieee +; CHECK-FP16: vcvtb.f32.f16 + store i16 %5, i16* @x, align 2 + ret void +} + +declare float @llvm.convert.from.fp16(i16) nounwind readnone + +declare i16 @llvm.convert.to.fp16(float) nounwind readnone diff --git a/test/CodeGen/ARM/indirectbr.ll b/test/CodeGen/ARM/indirectbr.ll index f05033773bb5..f898060581a9 100644 --- a/test/CodeGen/ARM/indirectbr.ll +++ b/test/CodeGen/ARM/indirectbr.ll @@ -59,6 +59,6 @@ L1: ; preds = %L2, %bb2 store i8* blockaddress(@foo, %L5), i8** @nextaddr, align 4 ret i32 %res.3 } -; ARM: .long L_BA4__foo_L5-(LPC{{.*}}+8) -; THUMB: .long L_BA4__foo_L5-(LPC{{.*}}+4) -; THUMB2: .long L_BA4__foo_L5 +; ARM: .long Ltmp0-(LPC{{.*}}+8) +; THUMB: .long Ltmp0-(LPC{{.*}}+4) +; THUMB2: .long Ltmp0 diff --git a/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll b/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll index a0b1403cf8d1..9c3c804aa754 100644 --- a/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll +++ b/test/CodeGen/Generic/2007-04-13-SwitchLowerBadPhi.ll @@ -1,9 +1,6 @@ ; RUN: llc < %s -O0 ; PR 1323 -; ModuleID = 'test.bc' -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "i686-apple-darwin8" %struct.comp = type { i8*, i32, i8*, [3 x i8], i32 } define void @regbranch() { diff --git a/test/CodeGen/Generic/2007-11-21-UndeadIllegalNode.ll b/test/CodeGen/Generic/2007-11-21-UndeadIllegalNode.ll index e220be6389dc..3090857d9649 100644 --- a/test/CodeGen/Generic/2007-11-21-UndeadIllegalNode.ll +++ b/test/CodeGen/Generic/2007-11-21-UndeadIllegalNode.ll @@ -1,7 +1,5 @@ ; RUN: llc < %s -o - -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" -target triple = "i686-pc-linux-gnu" %struct.RETURN = type { i32, i32 } %struct.ada__finalization__controlled = type { %struct.system__finalization_root__root_controlled } %struct.ada__streams__root_stream_type = type { %struct.ada__tags__dispatch_table* } diff --git a/test/CodeGen/Generic/2007-12-17-InvokeAsm.ll b/test/CodeGen/Generic/2007-12-17-InvokeAsm.ll index bd26481bd306..4cc1e7c181ed 100644 --- a/test/CodeGen/Generic/2007-12-17-InvokeAsm.ll +++ b/test/CodeGen/Generic/2007-12-17-InvokeAsm.ll @@ -1,7 +1,5 @@ ; RUN: llc < %s -enable-eh -target triple = "i686-pc-linux-gnu" - define fastcc void @bc__support__high_resolution_time__initialize_clock_rate() { entry: invoke void asm "rdtsc\0A\09movl %eax, $0\0A\09movl %edx, $1", "=*imr,=*imr,~{dirflag},~{fpsr},~{flags},~{dx},~{ax}"( i32* null, i32* null ) diff --git a/test/CodeGen/Generic/2007-12-31-UnusedSelector.ll b/test/CodeGen/Generic/2007-12-31-UnusedSelector.ll index fc9164f7c4aa..d2e97a477b44 100644 --- a/test/CodeGen/Generic/2007-12-31-UnusedSelector.ll +++ b/test/CodeGen/Generic/2007-12-31-UnusedSelector.ll @@ -1,8 +1,6 @@ ; RUN: llc < %s -enable-eh ; PR1833 -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" -target triple = "i686-pc-linux-gnu" %struct.__class_type_info_pseudo = type { %struct.__type_info_pseudo } %struct.__type_info_pseudo = type { i8*, i8* } @_ZTI2e1 = external constant %struct.__class_type_info_pseudo ; <%struct.__class_type_info_pseudo*> [#uses=1] diff --git a/test/CodeGen/Generic/2008-08-07-PtrToInt-SmallerInt.ll b/test/CodeGen/Generic/2008-08-07-PtrToInt-SmallerInt.ll index 4f95dfe8a730..00ca8c756b42 100644 --- a/test/CodeGen/Generic/2008-08-07-PtrToInt-SmallerInt.ll +++ b/test/CodeGen/Generic/2008-08-07-PtrToInt-SmallerInt.ll @@ -1,7 +1,5 @@ ; RUN: llc < %s ; PR2603 -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" -target triple = "i386-pc-linux-gnu" %struct.A = type { i8 } %struct.B = type { i8, [1 x i8] } @Foo = constant %struct.A { i8 ptrtoint (i8* getelementptr ([1 x i8]* inttoptr (i32 17 to [1 x i8]*), i32 0, i32 -16) to i8) } ; <%struct.A*> [#uses=0] diff --git a/test/CodeGen/Generic/2009-11-16-BadKillsCrash.ll b/test/CodeGen/Generic/2009-11-16-BadKillsCrash.ll index a51c75d62224..22bd4d7e6a41 100644 --- a/test/CodeGen/Generic/2009-11-16-BadKillsCrash.ll +++ b/test/CodeGen/Generic/2009-11-16-BadKillsCrash.ll @@ -1,7 +1,5 @@ ; RUN: llc < %s ; PR5495 -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32" -target triple = "i386-pc-linux-gnu" %"struct.std::__ctype_abstract_base<wchar_t>" = type { %"struct.std::locale::facet" } %"struct.std::basic_ios<char,std::char_traits<char> >" = type { %"struct.std::ios_base", %"struct.std::basic_ostream<char,std::char_traits<char> >"*, i8, i8, %"struct.std::basic_streambuf<char,std::char_traits<char> >"*, %"struct.std::ctype<char>"*, %"struct.std::__ctype_abstract_base<wchar_t>"*, %"struct.std::__ctype_abstract_base<wchar_t>"* } diff --git a/test/CodeGen/Generic/GC/redundant_init.ll b/test/CodeGen/Generic/GC/redundant_init.ll deleted file mode 100644 index 10c70e731052..000000000000 --- a/test/CodeGen/Generic/GC/redundant_init.ll +++ /dev/null @@ -1,17 +0,0 @@ -; RUN: llc < %s -march=x86 | \ -; RUN: ignore grep {movl..0} | count 0 - -%struct.obj = type { i8*, %struct.obj* } - -declare void @g() gc "shadow-stack" - -define void @f(i8* %o) gc "shadow-stack" { -entry: - %root = alloca i8* - call void @llvm.gcroot(i8** %root, i8* null) - store i8* %o, i8** %root - call void @g() - ret void -} - -declare void @llvm.gcroot(i8**, i8*) diff --git a/test/CodeGen/Generic/addr-label.ll b/test/CodeGen/Generic/addr-label.ll new file mode 100644 index 000000000000..51741110e072 --- /dev/null +++ b/test/CodeGen/Generic/addr-label.ll @@ -0,0 +1,58 @@ +; RUN: llc %s -o - + +;; Reference to a label that gets deleted. +define i8* @test1() nounwind { +entry: + ret i8* blockaddress(@test1b, %test_label) +} + +define i32 @test1b() nounwind { +entry: + ret i32 -1 +test_label: + br label %ret +ret: + ret i32 -1 +} + + +;; Issues with referring to a label that gets RAUW'd later. +define i32 @test2a() nounwind { +entry: + %target = bitcast i8* blockaddress(@test2b, %test_label) to i8* + + call i32 @test2b(i8* %target) + + ret i32 0 +} + +define i32 @test2b(i8* %target) nounwind { +entry: + indirectbr i8* %target, [label %test_label] + +test_label: +; assume some code here... + br label %ret + +ret: + ret i32 -1 +} + +; Issues with a BB that gets RAUW'd to another one after references are +; generated. +define void @test3(i8** %P, i8** %Q) nounwind { +entry: + store i8* blockaddress(@test3b, %test_label), i8** %P + store i8* blockaddress(@test3b, %ret), i8** %Q + ret void +} + +define i32 @test3b() nounwind { +entry: + br label %test_label +test_label: + br label %ret +ret: + ret i32 -1 +} + diff --git a/test/CodeGen/PowerPC/2008-10-31-PPCF128Libcalls.ll b/test/CodeGen/PowerPC/2008-10-31-PPCF128Libcalls.ll index 20683b9019e0..8322a8430815 100644 --- a/test/CodeGen/PowerPC/2008-10-31-PPCF128Libcalls.ll +++ b/test/CodeGen/PowerPC/2008-10-31-PPCF128Libcalls.ll @@ -35,3 +35,10 @@ declare ppc_fp128 @"\01_sinl$LDBL128"(ppc_fp128) nounwind readonly declare ppc_fp128 @"\01_cosl$LDBL128"(ppc_fp128) nounwind readonly declare ppc_fp128 @llvm.pow.ppcf128(ppc_fp128, ppc_fp128) nounwind readonly + +declare ppc_fp128 @copysignl(ppc_fp128, ppc_fp128) + +define ppc_fp128 @cs(ppc_fp128 %from, ppc_fp128 %to) { + %tmp = call ppc_fp128 @copysignl(ppc_fp128 %from, ppc_fp128 %to) + ret ppc_fp128 %tmp +} diff --git a/test/CodeGen/PowerPC/indirectbr.ll b/test/CodeGen/PowerPC/indirectbr.ll index 233d923695af..9b76ecc43db9 100644 --- a/test/CodeGen/PowerPC/indirectbr.ll +++ b/test/CodeGen/PowerPC/indirectbr.ll @@ -43,12 +43,12 @@ L2: ; preds = %L3, %bb2 L1: ; preds = %L2, %bb2 %res.3 = phi i32 [ %phitmp, %L2 ], [ 2, %bb2 ] ; <i32> [#uses=1] -; PIC: addis r4, r4, ha16(L_BA4__foo_L5-"L1$pb") -; PIC: li r6, lo16(L_BA4__foo_L5-"L1$pb") +; PIC: addis r4, r4, ha16(Ltmp0-"L1$pb") +; PIC: li r6, lo16(Ltmp0-"L1$pb") ; PIC: add r4, r4, r6 ; PIC: stw r4 -; STATIC: li r5, lo16(L_BA4__foo_L5) -; STATIC: addis r5, r5, ha16(L_BA4__foo_L5) +; STATIC: li r5, lo16(Ltmp0) +; STATIC: addis r5, r5, ha16(Ltmp0) ; STATIC: stw r5 store i8* blockaddress(@foo, %L5), i8** @nextaddr, align 4 ret i32 %res.3 diff --git a/test/CodeGen/PowerPC/ppc-prologue.ll b/test/CodeGen/PowerPC/ppc-prologue.ll index e49dcb82c60d..2ebfd3c319fc 100644 --- a/test/CodeGen/PowerPC/ppc-prologue.ll +++ b/test/CodeGen/PowerPC/ppc-prologue.ll @@ -5,9 +5,9 @@ define i32 @_Z4funci(i32 %a) ssp { ; CHECK-NEXT: stw r31, -4(r1) ; CHECK-NEXT: stw r0, 8(r1) ; CHECK-NEXT: stwu r1, -80(r1) -; CHECK-NEXT: Llabel1: +; CHECK-NEXT: Ltmp0: ; CHECK-NEXT: mr r31, r1 -; CHECK-NEXT: Llabel2: +; CHECK-NEXT: Ltmp1: entry: %a_addr = alloca i32 ; <i32*> [#uses=2] %retval = alloca i32 ; <i32*> [#uses=2] diff --git a/test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll b/test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll new file mode 100644 index 000000000000..71ff68aabebd --- /dev/null +++ b/test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll @@ -0,0 +1,63 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s +; Radar 7459078 +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" + +%0 = type { i32, i32 } +%s1 = type { %s3, i32, %s4, i8*, void (i8*, i8*)*, i8*, i32*, i32*, i32*, i32, i64, [1 x i32] } +%s2 = type { i32 (...)**, %s4 } +%s3 = type { %s2, i32, i32, i32*, [4 x i8], float, %s4, i8*, i8* } +%s4 = type { %s5 } +%s5 = type { i32 } + +; Make sure the cmp is not scheduled before the InlineAsm that clobbers cc. +; CHECK: InlineAsm End +; CHECK: cmp +; CHECK: beq +define arm_apcscc void @test(%s1* %this, i32 %format, i32 %w, i32 %h, i32 %levels, i32* %s, i8* %data, i32* nocapture %rowbytes, void (i8*, i8*)* %release, i8* %info) nounwind { +entry: + %tmp1 = getelementptr inbounds %s1* %this, i32 0, i32 0, i32 0, i32 1, i32 0, i32 0 + volatile store i32 1, i32* %tmp1, align 4 + %tmp12 = getelementptr inbounds %s1* %this, i32 0, i32 1 + store i32 %levels, i32* %tmp12, align 4 + %tmp13 = getelementptr inbounds %s1* %this, i32 0, i32 3 + store i8* %data, i8** %tmp13, align 4 + %tmp14 = getelementptr inbounds %s1* %this, i32 0, i32 4 + store void (i8*, i8*)* %release, void (i8*, i8*)** %tmp14, align 4 + %tmp15 = getelementptr inbounds %s1* %this, i32 0, i32 5 + store i8* %info, i8** %tmp15, align 4 + %tmp16 = getelementptr inbounds %s1* %this, i32 0, i32 6 + store i32* null, i32** %tmp16, align 4 + %tmp17 = getelementptr inbounds %s1* %this, i32 0, i32 7 + store i32* null, i32** %tmp17, align 4 + %tmp19 = getelementptr inbounds %s1* %this, i32 0, i32 10 + store i64 0, i64* %tmp19, align 4 + %tmp20 = getelementptr inbounds %s1* %this, i32 0, i32 0 + tail call arm_apcscc void @f1(%s3* %tmp20, i32* %s) nounwind + %tmp21 = shl i32 %format, 6 + %tmp22 = tail call arm_apcscc zeroext i8 @f2(i32 %format) nounwind + %toBoolnot = icmp eq i8 %tmp22, 0 + %tmp23 = zext i1 %toBoolnot to i32 + %flags.0 = or i32 %tmp23, %tmp21 + %tmp24 = shl i32 %flags.0, 16 + %asmtmp.i.i.i = tail call %0 asm sideeffect "\0A0:\09ldrex $1, [$2]\0A\09orr $1, $1, $3\0A\09strex $0, $1, [$2]\0A\09cmp $0, #0\0A\09bne 0b", "=&r,=&r,r,r,~{memory},~{cc}"(i32* %tmp1, i32 %tmp24) nounwind + %tmp25 = getelementptr inbounds %s1* %this, i32 0, i32 2, i32 0, i32 0 + volatile store i32 1, i32* %tmp25, align 4 + %tmp26 = icmp eq i32 %levels, 0 + br i1 %tmp26, label %return, label %bb4 + +bb4: + %l.09 = phi i32 [ %tmp28, %bb4 ], [ 0, %entry ] + %scevgep = getelementptr %s1* %this, i32 0, i32 11, i32 %l.09 + %scevgep10 = getelementptr i32* %rowbytes, i32 %l.09 + %tmp27 = load i32* %scevgep10, align 4 + store i32 %tmp27, i32* %scevgep, align 4 + %tmp28 = add i32 %l.09, 1 + %exitcond = icmp eq i32 %tmp28, %levels + br i1 %exitcond, label %return, label %bb4 + +return: + ret void +} + +declare arm_apcscc void @f1(%s3*, i32*) +declare arm_apcscc zeroext i8 @f2(i32) diff --git a/test/CodeGen/X86/2004-03-30-Select-Max.ll b/test/CodeGen/X86/2004-03-30-Select-Max.ll index b6631b62118a..c44d10ac5b5a 100644 --- a/test/CodeGen/X86/2004-03-30-Select-Max.ll +++ b/test/CodeGen/X86/2004-03-30-Select-Max.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -march=x86 | not grep {j\[lgbe\]} +; RUN: llc < %s -march=x86 -mcpu=yonah | not grep {j\[lgbe\]} -define i32 @max(i32 %A, i32 %B) { +define i32 @max(i32 %A, i32 %B) nounwind { %gt = icmp sgt i32 %A, %B ; <i1> [#uses=1] %R = select i1 %gt, i32 %A, i32 %B ; <i32> [#uses=1] ret i32 %R diff --git a/test/CodeGen/Generic/2007-02-16-BranchFold.ll b/test/CodeGen/X86/2007-02-16-BranchFold.ll index 6bf5631b4e34..6bf5631b4e34 100644 --- a/test/CodeGen/Generic/2007-02-16-BranchFold.ll +++ b/test/CodeGen/X86/2007-02-16-BranchFold.ll diff --git a/test/CodeGen/Generic/2007-05-05-Personality.ll b/test/CodeGen/X86/2007-05-05-Personality.ll index c92783e5e4eb..c92783e5e4eb 100644 --- a/test/CodeGen/Generic/2007-05-05-Personality.ll +++ b/test/CodeGen/X86/2007-05-05-Personality.ll diff --git a/test/CodeGen/X86/2008-08-05-SpillerBug.ll b/test/CodeGen/X86/2008-08-05-SpillerBug.ll index 4c6493445a90..d9d95b595bee 100644 --- a/test/CodeGen/X86/2008-08-05-SpillerBug.ll +++ b/test/CodeGen/X86/2008-08-05-SpillerBug.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin -disable-fp-elim -stats |& grep asm-printer | grep 55 +; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah -disable-fp-elim -stats |& grep asm-printer | grep 55 ; PR2568 @g_3 = external global i16 ; <i16*> [#uses=1] diff --git a/test/CodeGen/X86/2009-03-13-PHIElimBug.ll b/test/CodeGen/X86/2009-03-13-PHIElimBug.ll index ad7f9f7d1c11..8d426271a194 100644 --- a/test/CodeGen/X86/2009-03-13-PHIElimBug.ll +++ b/test/CodeGen/X86/2009-03-13-PHIElimBug.ll @@ -28,5 +28,5 @@ lpad: ; preds = %cont, %entry } ; CHECK: call{{.*}}f -; CHECK-NEXT: Llabel1: +; CHECK-NEXT: Ltmp0: ; CHECK-NEXT: movl %eax, %esi diff --git a/test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll b/test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll index 11c410173fcb..da493d4910e1 100644 --- a/test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll +++ b/test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll @@ -21,4 +21,4 @@ lpad: ; preds = %cont, %entry } ; CHECK: lpad -; CHECK-NEXT: Llabel +; CHECK-NEXT: Ltmp diff --git a/test/CodeGen/Generic/GC/alloc_loop.ll b/test/CodeGen/X86/GC/alloc_loop.ll index fb78ba2cd10b..fb78ba2cd10b 100644 --- a/test/CodeGen/Generic/GC/alloc_loop.ll +++ b/test/CodeGen/X86/GC/alloc_loop.ll diff --git a/test/CodeGen/Generic/GC/argpromotion.ll b/test/CodeGen/X86/GC/argpromotion.ll index c63ce222b869..c63ce222b869 100644 --- a/test/CodeGen/Generic/GC/argpromotion.ll +++ b/test/CodeGen/X86/GC/argpromotion.ll diff --git a/test/CodeGen/Generic/GC/badreadproto.ll b/test/CodeGen/X86/GC/badreadproto.ll index 4fe90b90833a..4fe90b90833a 100644 --- a/test/CodeGen/Generic/GC/badreadproto.ll +++ b/test/CodeGen/X86/GC/badreadproto.ll diff --git a/test/CodeGen/Generic/GC/badrootproto.ll b/test/CodeGen/X86/GC/badrootproto.ll index ff86d03c646a..ff86d03c646a 100644 --- a/test/CodeGen/Generic/GC/badrootproto.ll +++ b/test/CodeGen/X86/GC/badrootproto.ll diff --git a/test/CodeGen/Generic/GC/badwriteproto.ll b/test/CodeGen/X86/GC/badwriteproto.ll index be81f842672e..be81f842672e 100644 --- a/test/CodeGen/Generic/GC/badwriteproto.ll +++ b/test/CodeGen/X86/GC/badwriteproto.ll diff --git a/test/CodeGen/Generic/GC/deadargelim.ll b/test/CodeGen/X86/GC/deadargelim.ll index 176019020ad4..176019020ad4 100644 --- a/test/CodeGen/Generic/GC/deadargelim.ll +++ b/test/CodeGen/X86/GC/deadargelim.ll diff --git a/test/CodeGen/Generic/GC/dg.exp b/test/CodeGen/X86/GC/dg.exp index f2005891a59a..f2005891a59a 100644 --- a/test/CodeGen/Generic/GC/dg.exp +++ b/test/CodeGen/X86/GC/dg.exp diff --git a/test/CodeGen/Generic/GC/fat.ll b/test/CodeGen/X86/GC/fat.ll index d05ca3da8195..d05ca3da8195 100644 --- a/test/CodeGen/Generic/GC/fat.ll +++ b/test/CodeGen/X86/GC/fat.ll diff --git a/test/CodeGen/Generic/GC/inline.ll b/test/CodeGen/X86/GC/inline.ll index 9da33aef8dd3..9da33aef8dd3 100644 --- a/test/CodeGen/Generic/GC/inline.ll +++ b/test/CodeGen/X86/GC/inline.ll diff --git a/test/CodeGen/Generic/GC/inline2.ll b/test/CodeGen/X86/GC/inline2.ll index 15947056ee39..15947056ee39 100644 --- a/test/CodeGen/Generic/GC/inline2.ll +++ b/test/CodeGen/X86/GC/inline2.ll diff --git a/test/CodeGen/Generic/GC/lower_gcroot.ll b/test/CodeGen/X86/GC/lower_gcroot.ll index c2d418ac50ef..c2d418ac50ef 100644 --- a/test/CodeGen/Generic/GC/lower_gcroot.ll +++ b/test/CodeGen/X86/GC/lower_gcroot.ll diff --git a/test/CodeGen/Generic/GC/outside.ll b/test/CodeGen/X86/GC/outside.ll index 2968c6917ce1..2968c6917ce1 100644 --- a/test/CodeGen/Generic/GC/outside.ll +++ b/test/CodeGen/X86/GC/outside.ll diff --git a/test/CodeGen/Generic/GC/simple_ocaml.ll b/test/CodeGen/X86/GC/simple_ocaml.ll index f765dc029da5..f765dc029da5 100644 --- a/test/CodeGen/Generic/GC/simple_ocaml.ll +++ b/test/CodeGen/X86/GC/simple_ocaml.ll diff --git a/test/CodeGen/X86/clz.ll b/test/CodeGen/X86/clz.ll index 3f27187d44a8..623ac75b5299 100644 --- a/test/CodeGen/X86/clz.ll +++ b/test/CodeGen/X86/clz.ll @@ -1,10 +1,11 @@ -; RUN: llc < %s -march=x86 | grep bsr | count 2 -; RUN: llc < %s -march=x86 | grep bsf -; RUN: llc < %s -march=x86 | grep cmov | count 3 +; RUN: llc < %s -march=x86 -mcpu=yonah | FileCheck %s define i32 @t1(i32 %x) nounwind { %tmp = tail call i32 @llvm.ctlz.i32( i32 %x ) ret i32 %tmp +; CHECK: t1: +; CHECK: bsrl +; CHECK: cmov } declare i32 @llvm.ctlz.i32(i32) nounwind readnone @@ -12,6 +13,9 @@ declare i32 @llvm.ctlz.i32(i32) nounwind readnone define i32 @t2(i32 %x) nounwind { %tmp = tail call i32 @llvm.cttz.i32( i32 %x ) ret i32 %tmp +; CHECK: t2: +; CHECK: bsfl +; CHECK: cmov } declare i32 @llvm.cttz.i32(i32) nounwind readnone @@ -21,6 +25,9 @@ entry: %tmp1 = add i16 %x, %y %tmp2 = tail call i16 @llvm.ctlz.i16( i16 %tmp1 ) ; <i16> [#uses=1] ret i16 %tmp2 +; CHECK: t3: +; CHECK: bsrw +; CHECK: cmov } declare i16 @llvm.ctlz.i16(i16) nounwind readnone diff --git a/test/CodeGen/X86/crash.ll b/test/CodeGen/X86/crash.ll index 1e13046f2acd..4b7c85099389 100644 --- a/test/CodeGen/X86/crash.ll +++ b/test/CodeGen/X86/crash.ll @@ -18,3 +18,77 @@ entry: volatile store i32 %conv19.i, i32* undef ret i32 undef } + +; PR6533 +define void @test2(i1 %x, i32 %y) nounwind { + %land.ext = zext i1 %x to i32 ; <i32> [#uses=1] + %and = and i32 %y, 1 ; <i32> [#uses=1] + %xor = xor i32 %and, %land.ext ; <i32> [#uses=1] + %cmp = icmp eq i32 %xor, 1 ; <i1> [#uses=1] + br i1 %cmp, label %if.end, label %if.then + +if.then: ; preds = %land.end + ret void + +if.end: ; preds = %land.end + ret void +} + +; PR6577 +%pair = type { i64, double } + +define void @test3() { +dependentGraph243.exit: + %subject19 = load %pair* undef ; <%1> [#uses=1] + %0 = extractvalue %pair %subject19, 1 ; <double> [#uses=2] + %1 = select i1 undef, double %0, double undef ; <double> [#uses=1] + %2 = select i1 undef, double %1, double %0 ; <double> [#uses=1] + %3 = insertvalue %pair undef, double %2, 1 ; <%1> [#uses=1] + store %pair %3, %pair* undef + ret void +} + +; PR6605 +define i64 @test4(i8* %P) nounwind ssp { +entry: + %tmp1 = load i8* %P ; <i8> [#uses=3] + %tobool = icmp eq i8 %tmp1, 0 ; <i1> [#uses=1] + %tmp58 = sext i1 %tobool to i8 ; <i8> [#uses=1] + %mul.i = and i8 %tmp58, %tmp1 ; <i8> [#uses=1] + %conv6 = zext i8 %mul.i to i32 ; <i32> [#uses=1] + %cmp = icmp ne i8 %tmp1, 1 ; <i1> [#uses=1] + %conv11 = zext i1 %cmp to i32 ; <i32> [#uses=1] + %call12 = tail call i32 @safe(i32 %conv11) nounwind ; <i32> [#uses=1] + %and = and i32 %conv6, %call12 ; <i32> [#uses=1] + %tobool13 = icmp eq i32 %and, 0 ; <i1> [#uses=1] + br i1 %tobool13, label %if.else, label %return + +if.else: ; preds = %entry + br label %return + +return: ; preds = %if.else, %entry + ret i64 undef +} + +declare i32 @safe(i32) + +; PR6607 +define fastcc void @test5(i32 %FUNC) nounwind { +foo: + %0 = load i8* undef, align 1 ; <i8> [#uses=3] + %1 = sext i8 %0 to i32 ; <i32> [#uses=2] + %2 = zext i8 %0 to i32 ; <i32> [#uses=1] + %tmp1.i5037 = urem i32 %2, 10 ; <i32> [#uses=1] + %tmp.i5038 = icmp ugt i32 %tmp1.i5037, 15 ; <i1> [#uses=1] + %3 = zext i1 %tmp.i5038 to i8 ; <i8> [#uses=1] + %4 = icmp slt i8 %0, %3 ; <i1> [#uses=1] + %5 = add nsw i32 %1, 256 ; <i32> [#uses=1] + %storemerge.i.i57 = select i1 %4, i32 %5, i32 %1 ; <i32> [#uses=1] + %6 = shl i32 %storemerge.i.i57, 16 ; <i32> [#uses=1] + %7 = sdiv i32 %6, -256 ; <i32> [#uses=1] + %8 = trunc i32 %7 to i8 ; <i8> [#uses=1] + store i8 %8, i8* undef, align 1 + ret void +} + + diff --git a/test/CodeGen/X86/gather-addresses.ll b/test/CodeGen/X86/gather-addresses.ll new file mode 100644 index 000000000000..07198386b8ea --- /dev/null +++ b/test/CodeGen/X86/gather-addresses.ll @@ -0,0 +1,39 @@ +; RUN: llc -march=x86-64 < %s | FileCheck %s + +; When doing vector gather-scatter index calculation with 32-bit indices, +; bounce the vector off of cache rather than shuffling each individual +; element out of the index vector. + +; CHECK: pand (%rdx), %xmm0 +; CHECK: movaps %xmm0, -24(%rsp) +; CHECK: movslq -24(%rsp), %rax +; CHECK: movsd (%rdi,%rax,8), %xmm0 +; CHECK: movslq -20(%rsp), %rax +; CHECK: movhpd (%rdi,%rax,8), %xmm0 +; CHECK: movslq -16(%rsp), %rax +; CHECK: movsd (%rdi,%rax,8), %xmm1 +; CHECK: movslq -12(%rsp), %rax +; CHECK: movhpd (%rdi,%rax,8), %xmm1 + +define <4 x double> @foo(double* %p, <4 x i32>* %i, <4 x i32>* %h) nounwind { + %a = load <4 x i32>* %i + %b = load <4 x i32>* %h + %j = and <4 x i32> %a, %b + %d0 = extractelement <4 x i32> %j, i32 0 + %d1 = extractelement <4 x i32> %j, i32 1 + %d2 = extractelement <4 x i32> %j, i32 2 + %d3 = extractelement <4 x i32> %j, i32 3 + %q0 = getelementptr double* %p, i32 %d0 + %q1 = getelementptr double* %p, i32 %d1 + %q2 = getelementptr double* %p, i32 %d2 + %q3 = getelementptr double* %p, i32 %d3 + %r0 = load double* %q0 + %r1 = load double* %q1 + %r2 = load double* %q2 + %r3 = load double* %q3 + %v0 = insertelement <4 x double> undef, double %r0, i32 0 + %v1 = insertelement <4 x double> %v0, double %r1, i32 1 + %v2 = insertelement <4 x double> %v1, double %r2, i32 2 + %v3 = insertelement <4 x double> %v2, double %r3, i32 3 + ret <4 x double> %v3 +} diff --git a/test/CodeGen/X86/ghc-cc.ll b/test/CodeGen/X86/ghc-cc.ll new file mode 100644 index 000000000000..9393cf5a7383 --- /dev/null +++ b/test/CodeGen/X86/ghc-cc.ll @@ -0,0 +1,45 @@ +; RUN: llc < %s -tailcallopt -mtriple=i686-linux-gnu | FileCheck %s + +; Test the GHC call convention works (x86-32) + +@base = external global i32 ; assigned to register: EBX +@sp = external global i32 ; assigned to register: EBP +@hp = external global i32 ; assigned to register: EDI +@r1 = external global i32 ; assigned to register: ESI + +define void @zap(i32 %a, i32 %b) nounwind { +entry: + ; CHECK: movl {{[0-9]*}}(%esp), %ebx + ; CHECK-NEXT: movl {{[0-9]*}}(%esp), %ebp + ; CHECK-NEXT: call addtwo + %0 = call cc 10 i32 @addtwo(i32 %a, i32 %b) + ; CHECK: call foo + call void @foo() nounwind + ret void +} + +define cc 10 i32 @addtwo(i32 %x, i32 %y) nounwind { +entry: + ; CHECK: leal (%ebx,%ebp), %eax + %0 = add i32 %x, %y + ; CHECK-NEXT: ret + ret i32 %0 +} + +define cc 10 void @foo() nounwind { +entry: + ; CHECK: movl base, %ebx + ; CHECK-NEXT: movl sp, %ebp + ; CHECK-NEXT: movl hp, %edi + ; CHECK-NEXT: movl r1, %esi + %0 = load i32* @r1 + %1 = load i32* @hp + %2 = load i32* @sp + %3 = load i32* @base + ; CHECK: jmp bar + tail call cc 10 void @bar( i32 %3, i32 %2, i32 %1, i32 %0 ) nounwind + ret void +} + +declare cc 10 void @bar(i32, i32, i32, i32) + diff --git a/test/CodeGen/X86/ghc-cc64.ll b/test/CodeGen/X86/ghc-cc64.ll new file mode 100644 index 000000000000..fcf7e1797ad8 --- /dev/null +++ b/test/CodeGen/X86/ghc-cc64.ll @@ -0,0 +1,86 @@ +; RUN: llc < %s -tailcallopt -mtriple=x86_64-linux-gnu | FileCheck %s + +; Check the GHC call convention works (x86-64) + +@base = external global i64 ; assigned to register: R13 +@sp = external global i64 ; assigned to register: RBP +@hp = external global i64 ; assigned to register: R12 +@r1 = external global i64 ; assigned to register: RBX +@r2 = external global i64 ; assigned to register: R14 +@r3 = external global i64 ; assigned to register: RSI +@r4 = external global i64 ; assigned to register: RDI +@r5 = external global i64 ; assigned to register: R8 +@r6 = external global i64 ; assigned to register: R9 +@splim = external global i64 ; assigned to register: R15 + +@f1 = external global float ; assigned to register: XMM1 +@f2 = external global float ; assigned to register: XMM2 +@f3 = external global float ; assigned to register: XMM3 +@f4 = external global float ; assigned to register: XMM4 +@d1 = external global double ; assigned to register: XMM5 +@d2 = external global double ; assigned to register: XMM6 + +define void @zap(i64 %a, i64 %b) nounwind { +entry: + ; CHECK: movq %rdi, %r13 + ; CHECK-NEXT: movq %rsi, %rbp + ; CHECK-NEXT: callq addtwo + %0 = call cc 10 i64 @addtwo(i64 %a, i64 %b) + ; CHECK: callq foo + call void @foo() nounwind + ret void +} + +define cc 10 i64 @addtwo(i64 %x, i64 %y) nounwind { +entry: + ; CHECK: leaq (%r13,%rbp), %rax + %0 = add i64 %x, %y + ; CHECK-NEXT: ret + ret i64 %0 +} + +define cc 10 void @foo() nounwind { +entry: + ; CHECK: movq base(%rip), %r13 + ; CHECK-NEXT: movq sp(%rip), %rbp + ; CHECK-NEXT: movq hp(%rip), %r12 + ; CHECK-NEXT: movq r1(%rip), %rbx + ; CHECK-NEXT: movq r2(%rip), %r14 + ; CHECK-NEXT: movq r3(%rip), %rsi + ; CHECK-NEXT: movq r4(%rip), %rdi + ; CHECK-NEXT: movq r5(%rip), %r8 + ; CHECK-NEXT: movq r6(%rip), %r9 + ; CHECK-NEXT: movq splim(%rip), %r15 + ; CHECK-NEXT: movss f1(%rip), %xmm1 + ; CHECK-NEXT: movss f2(%rip), %xmm2 + ; CHECK-NEXT: movss f3(%rip), %xmm3 + ; CHECK-NEXT: movss f4(%rip), %xmm4 + ; CHECK-NEXT: movsd d1(%rip), %xmm5 + ; CHECK-NEXT: movsd d2(%rip), %xmm6 + %0 = load double* @d2 + %1 = load double* @d1 + %2 = load float* @f4 + %3 = load float* @f3 + %4 = load float* @f2 + %5 = load float* @f1 + %6 = load i64* @splim + %7 = load i64* @r6 + %8 = load i64* @r5 + %9 = load i64* @r4 + %10 = load i64* @r3 + %11 = load i64* @r2 + %12 = load i64* @r1 + %13 = load i64* @hp + %14 = load i64* @sp + %15 = load i64* @base + ; CHECK: jmp bar + tail call cc 10 void @bar( i64 %15, i64 %14, i64 %13, i64 %12, i64 %11, + i64 %10, i64 %9, i64 %8, i64 %7, i64 %6, + float %5, float %4, float %3, float %2, double %1, + double %0 ) nounwind + ret void +} + +declare cc 10 void @bar(i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, + float, float, float, float, double, double) + diff --git a/test/CodeGen/X86/liveness-local-regalloc.ll b/test/CodeGen/X86/liveness-local-regalloc.ll new file mode 100644 index 000000000000..17e65d8f81d9 --- /dev/null +++ b/test/CodeGen/X86/liveness-local-regalloc.ll @@ -0,0 +1,60 @@ +; RUN: llc < %s -O3 -regalloc=local -mtriple=x86_64-apple-darwin10 +; <rdar://problem/7755473> + +%0 = type { i32, i8*, i8*, %1*, i8*, i64, i64, i32, i32, i32, i32, [1024 x i8] } +%1 = type { i8*, i32, i32, i16, i16, %2, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %2, %3*, i32, [3 x i8], [1 x i8], %2, i32, i64 } +%2 = type { i8*, i32 } +%3 = type opaque + +declare fastcc i32 @func(%0*, i32, i32) nounwind ssp + +define fastcc void @func2(%0* %arg, i32 %arg1) nounwind ssp { +bb: + br label %.exit3 + +.exit3: ; preds = %.exit3, %bb + switch i32 undef, label %.exit3 [ + i32 -1, label %.loopexit + i32 37, label %bb2 + ] + +bb2: ; preds = %bb5, %bb3, %.exit3 + br i1 undef, label %bb3, label %bb5 + +bb3: ; preds = %bb2 + switch i32 undef, label %infloop [ + i32 125, label %.loopexit + i32 -1, label %bb4 + i32 37, label %bb2 + ] + +bb4: ; preds = %bb3 + %tmp = add nsw i32 undef, 1 ; <i32> [#uses=1] + br label %.loopexit + +bb5: ; preds = %bb2 + switch i32 undef, label %infloop1 [ + i32 -1, label %.loopexit + i32 37, label %bb2 + ] + +.loopexit: ; preds = %bb5, %bb4, %bb3, %.exit3 + %.04 = phi i32 [ %tmp, %bb4 ], [ undef, %bb3 ], [ undef, %.exit3 ], [ undef, %bb5 ] ; <i32> [#uses=2] + br i1 undef, label %bb8, label %bb6 + +bb6: ; preds = %.loopexit + %tmp7 = tail call fastcc i32 @func(%0* %arg, i32 %.04, i32 undef) nounwind ssp ; <i32> [#uses=0] + ret void + +bb8: ; preds = %.loopexit + %tmp9 = sext i32 %.04 to i64 ; <i64> [#uses=1] + %tmp10 = getelementptr inbounds %0* %arg, i64 0, i32 11, i64 %tmp9 ; <i8*> [#uses=1] + store i8 0, i8* %tmp10, align 1 + ret void + +infloop: ; preds = %infloop, %bb3 + br label %infloop + +infloop1: ; preds = %infloop1, %bb5 + br label %infloop1 +} diff --git a/test/CodeGen/X86/object-size.ll b/test/CodeGen/X86/object-size.ll index eed3cfc85136..bbe6b2341e58 100644 --- a/test/CodeGen/X86/object-size.ll +++ b/test/CodeGen/X86/object-size.ll @@ -12,7 +12,7 @@ entry: %tmp = load i8** @p ; <i8*> [#uses=1] %0 = call i64 @llvm.objectsize.i64(i8* %tmp, i1 0) ; <i64> [#uses=1] %cmp = icmp ne i64 %0, -1 ; <i1> [#uses=1] -; X64: movq $-1, %rax +; X64: movabsq $-1, %rax ; X64: cmpq $-1, %rax br i1 %cmp, label %cond.true, label %cond.false diff --git a/test/CodeGen/X86/personality.ll b/test/CodeGen/X86/personality.ll index ce57e8fce6f2..5acf04cc06c1 100644 --- a/test/CodeGen/X86/personality.ll +++ b/test/CodeGen/X86/personality.ll @@ -39,7 +39,7 @@ declare void @__gxx_personality_v0() declare void @__cxa_end_catch() ; X64: Leh_frame_common_begin: -; X64: .long (___gxx_personality_v0@GOTPCREL)+4 +; X64: .long ___gxx_personality_v0@GOTPCREL+4 ; X32: Leh_frame_common_begin: ; X32: .long L___gxx_personality_v0$non_lazy_ptr- diff --git a/test/CodeGen/X86/phys_subreg_coalesce-3.ll b/test/CodeGen/X86/phys_subreg_coalesce-3.ll new file mode 100644 index 000000000000..f23669ed9a4a --- /dev/null +++ b/test/CodeGen/X86/phys_subreg_coalesce-3.ll @@ -0,0 +1,35 @@ +; RUN: llc < %s -mtriple=i386-apple-darwin | FileCheck %s +; rdar://5571034 + +define void @foo(i32* nocapture %quadrant, i32* nocapture %ptr, i32 %bbSize, i32 %bbStart, i32 %shifts) nounwind ssp { +; CHECK: foo: +entry: + %j.03 = add i32 %bbSize, -1 ; <i32> [#uses=2] + %0 = icmp sgt i32 %j.03, -1 ; <i1> [#uses=1] + br i1 %0, label %bb.nph, label %return + +bb.nph: ; preds = %entry + %tmp9 = add i32 %bbStart, %bbSize ; <i32> [#uses=1] + %tmp10 = add i32 %tmp9, -1 ; <i32> [#uses=1] + br label %bb + +bb: ; preds = %bb, %bb.nph +; CHECK: %bb +; CHECK-NOT: movb {{.*}}l, %cl +; CHECK: sarl %cl + %indvar = phi i32 [ 0, %bb.nph ], [ %indvar.next, %bb ] ; <i32> [#uses=3] + %j.06 = sub i32 %j.03, %indvar ; <i32> [#uses=1] + %tmp11 = sub i32 %tmp10, %indvar ; <i32> [#uses=1] + %scevgep = getelementptr i32* %ptr, i32 %tmp11 ; <i32*> [#uses=1] + %1 = load i32* %scevgep, align 4 ; <i32> [#uses=1] + %2 = ashr i32 %j.06, %shifts ; <i32> [#uses=1] + %3 = and i32 %2, 65535 ; <i32> [#uses=1] + %4 = getelementptr inbounds i32* %quadrant, i32 %1 ; <i32*> [#uses=1] + store i32 %3, i32* %4, align 4 + %indvar.next = add i32 %indvar, 1 ; <i32> [#uses=2] + %exitcond = icmp eq i32 %indvar.next, %bbSize ; <i1> [#uses=1] + br i1 %exitcond, label %return, label %bb + +return: ; preds = %bb, %entry + ret void +} diff --git a/test/CodeGen/X86/pic.ll b/test/CodeGen/X86/pic.ll index d3c28a055aee..e997233a5194 100644 --- a/test/CodeGen/X86/pic.ll +++ b/test/CodeGen/X86/pic.ll @@ -15,7 +15,7 @@ entry: ; LINUX: call .L1$pb ; LINUX-NEXT: .L1$pb: ; LINUX-NEXT: popl -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.Lpicbaseref1-.L1$pb), +; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L1$pb), ; LINUX: movl dst@GOT(%eax), ; LINUX: movl ptr@GOT(%eax), ; LINUX: movl src@GOT(%eax), @@ -37,7 +37,7 @@ entry: ; LINUX: call .L2$pb ; LINUX-NEXT: .L2$pb: ; LINUX-NEXT: popl -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.Lpicbaseref2-.L2$pb), %eax +; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L2$pb), %eax ; LINUX: movl dst2@GOT(%eax), ; LINUX: movl ptr2@GOT(%eax), ; LINUX: movl src2@GOT(%eax), @@ -57,7 +57,7 @@ entry: ; LINUX-NEXT: call .L3$pb ; LINUX-NEXT: .L3$pb: ; LINUX-NEXT: popl %ebx -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.Lpicbaseref3-.L3$pb), %ebx +; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L3$pb), %ebx ; LINUX: movl $40, (%esp) ; LINUX: call malloc@PLT ; LINUX: addl $8, %esp @@ -78,7 +78,7 @@ entry: ; LINUX: call .L4$pb ; LINUX-NEXT: .L4$pb: ; LINUX: popl -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.Lpicbaseref4-.L4$pb), +; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L4$pb), ; LINUX: movl pfoo@GOT(%esi), ; LINUX: call afoo@PLT ; LINUX: call * @@ -93,7 +93,7 @@ entry: ; LINUX: test5: ; LINUX: call .L5$pb ; LINUX: popl %ebx -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.Lpicbaseref5-.L5$pb), %ebx +; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L5$pb), %ebx ; LINUX: call foo@PLT } @@ -115,7 +115,7 @@ entry: ; LINUX: call .L6$pb ; LINUX-NEXT: .L6$pb: ; LINUX-NEXT: popl %eax -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.Lpicbaseref6-.L6$pb), %eax +; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L6$pb), %eax ; LINUX: leal dst6@GOTOFF(%eax), %ecx ; LINUX: movl %ecx, ptr6@GOTOFF(%eax) ; LINUX: movl src6@GOTOFF(%eax), %ecx @@ -136,7 +136,7 @@ entry: ; LINUX: test7: ; LINUX: call .L7$pb ; LINUX: .L7$pb: -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.Lpicbaseref7-.L7$pb), +; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L7$pb), ; LINUX: fldl .LCPI7_0@GOTOFF( } @@ -188,7 +188,7 @@ bb12: ; LINUX: test8: ; LINUX: call .L8$pb ; LINUX: .L8$pb: -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.Lpicbaseref8-.L8$pb), +; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L8$pb), ; LINUX: addl .LJTI8_0@GOTOFF( ; LINUX: jmpl * diff --git a/test/CodeGen/X86/tailcall-largecode.ll b/test/CodeGen/X86/tailcall-largecode.ll index 8ddc4054ca88..c7070f2abd25 100644 --- a/test/CodeGen/X86/tailcall-largecode.ll +++ b/test/CodeGen/X86/tailcall-largecode.ll @@ -20,7 +20,7 @@ define fastcc i32 @indirect_manyargs(i32(i32,i32,i32,i32,i32,i32,i32)* %target) ; CHECK: subq $8, %rsp ; Put the call target into R11, which won't be clobbered while restoring ; callee-saved registers and won't be used for passing arguments. -; CHECK: movq %rdi, %r11 +; CHECK: movq %rdi, %rax ; Pass the stack argument. ; CHECK: movl $7, 16(%rsp) ; Pass the register arguments, in the right registers. @@ -33,7 +33,7 @@ define fastcc i32 @indirect_manyargs(i32(i32,i32,i32,i32,i32,i32,i32)* %target) ; Adjust the stack to "return". ; CHECK: addq $8, %rsp ; And tail-call to the target. -; CHECK: jmpq *%r11 # TAILCALL +; CHECK: jmpq *%rax # TAILCALL %res = tail call fastcc i32 %target(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7) ret i32 %res @@ -60,11 +60,11 @@ define fastcc i32 @direct_manyargs() { ; the jmp instruction. Put it into R11, which won't be clobbered ; while restoring callee-saved registers and won't be used for passing ; arguments. -; CHECK: movabsq $manyargs_callee, %r11 +; CHECK: movabsq $manyargs_callee, %rax ; Adjust the stack to "return". ; CHECK: addq $8, %rsp ; And tail-call to the target. -; CHECK: jmpq *%r11 # TAILCALL +; CHECK: jmpq *%rax # TAILCALL %res = tail call fastcc i32 @manyargs_callee(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7) ret i32 %res diff --git a/test/CodeGen/X86/tailcallfp2.ll b/test/CodeGen/X86/tailcallfp2.ll index 3841f518976b..4ec127f81ac7 100644 --- a/test/CodeGen/X86/tailcallfp2.ll +++ b/test/CodeGen/X86/tailcallfp2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -tailcallopt | grep {jmp} | grep {\\*%eax} +; RUN: llc < %s -march=x86 -tailcallopt | grep {jmp} | grep {\\*%edx} declare i32 @putchar(i32) diff --git a/test/CodeGen/XCore/addsub64.ll b/test/CodeGen/XCore/addsub64.ll index 0432e5e712e6..d06248022e31 100644 --- a/test/CodeGen/XCore/addsub64.ll +++ b/test/CodeGen/XCore/addsub64.ll @@ -42,3 +42,18 @@ entry: ; CHECK: maccs: ; CHECK: maccs r1, r0, r3, r2 ; CHECK-NEXT: retsp 0 + +define i64 @lmul(i32 %a, i32 %b, i32 %c, i32 %d) { +entry: + %0 = zext i32 %a to i64 + %1 = zext i32 %b to i64 + %2 = zext i32 %c to i64 + %3 = zext i32 %d to i64 + %4 = mul i64 %1, %0 + %5 = add i64 %4, %2 + %6 = add i64 %5, %3 + ret i64 %6 +} +; CHECK: lmul: +; CHECK: lmul r1, r0, r1, r0, r2, r3 +; CHECK-NEXT: retsp 0 diff --git a/test/CodeGen/XCore/indirectbr.ll b/test/CodeGen/XCore/indirectbr.ll index a8f00cc497fc..92690029cd0e 100644 --- a/test/CodeGen/XCore/indirectbr.ll +++ b/test/CodeGen/XCore/indirectbr.ll @@ -38,7 +38,7 @@ L2: ; preds = %L3, %bb2 L1: ; preds = %L2, %bb2 %res.3 = phi i32 [ %phitmp, %L2 ], [ 2, %bb2 ] ; <i32> [#uses=1] -; CHECK: ldap r11, .LBA3_foo_L5 +; CHECK: ldap r11, .Ltmp0 ; CHECK: stw r11, dp[nextaddr] store i8* blockaddress(@foo, %L5), i8** @nextaddr, align 4 ret i32 %res.3 diff --git a/test/CodeGen/XCore/mul64.ll b/test/CodeGen/XCore/mul64.ll index 329e214d1d23..1dc94712507e 100644 --- a/test/CodeGen/XCore/mul64.ll +++ b/test/CodeGen/XCore/mul64.ll @@ -37,3 +37,16 @@ entry: ; CHECK-NEXT: mul r0, r0, r3 ; CHECK-NEXT: lmul r0, r1, r1, r2, r11, r0 ; CHECK-NEXT: mov r0, r4 + +define i64 @mul64_2(i64 %a, i32 %b) { +entry: + %0 = zext i32 %b to i64 + %1 = mul i64 %a, %0 + ret i64 %1 +} +; CHECK: mul64_2: +; CHECK: ldc r3, 0 +; CHECK-NEXT: lmul r3, r0, r0, r2, r3, r3 +; CHECK-NEXT: mul r1, r1, r2 +; CHECK-NEXT: add r1, r3, r1 +; CHECK-NEXT: retsp 0 |