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* Move all sources from the llvm project into contrib/llvm-project.Dimitry Andric2019-12-2076-23272/+0
| | | | | | | | | | | | | This uses the new layout of the upstream repository, which was recently migrated to GitHub, and converted into a "monorepo". That is, most of the earlier separate sub-projects with their own branches and tags were consolidated into one top-level directory, and are now branched and tagged together. Updating the vendor area to match this layout is next. Notes: svn path=/head/; revision=355940
* Merge commit a751f557d from llvm git (by Simon Atanasyan):Dimitry Andric2019-11-211-2/+5
| | | | | | | | | | | | | | | | [mips] Set macros for Octeon+ CPU This is one of the upstream changes needed for adding support for the OCTEON+ CPU type, so that we can test Clang builds using the most commonly available FreeBSD/mips64 reference platform, the Edge Router Lite. Requested by: kevans MFC after: 1 month X-MFC-With: r353358 Notes: svn path=/head/; revision=354985
* Merge commit 0d14656b9 from llvm git (by Simon Atanasyan):Dimitry Andric2019-11-211-0/+3
| | | | | | | | | | | | | | | | [mips] Set __OCTEON__ macros This is one of the upstream changes needed for adding support for the OCTEON+ CPU type, so that we can test Clang builds using the most commonly available FreeBSD/mips64 reference platform, the Edge Router Lite. Requested by: kevans MFC after: 1 month X-MFC-With: r353358 Notes: svn path=/head/; revision=354984
* Merge commit e578d0fd2 from llvm git (by Simon Atanasyan):Dimitry Andric2019-11-211-1/+1
| | | | | | | | | | | | | | | | [mips] Fix `__mips_isa_rev` macros value for Octeon CPU This is one of the upstream changes needed for adding support for the OCTEON+ CPU type, so that we can test Clang builds using the most commonly available FreeBSD/mips64 reference platform, the Edge Router Lite. Requested by: kevans MFC after: 1 month X-MFC-With: r353358 Notes: svn path=/head/; revision=354983
* Merge commit 3552d3e0f from llvm git (by Simon Atanasyan):Dimitry Andric2019-11-212-1/+4
| | | | | | | | | | | | | | | | [mips] Add `octeon+` to the list of CPUs accepted by the driver This is one of the upstream changes needed for adding support for the OCTEON+ CPU type, so that we can test Clang builds using the most commonly available FreeBSD/mips64 reference platform, the Edge Router Lite. Requested by: kevans MFC after: 1 month X-MFC-With: r353358 Notes: svn path=/head/; revision=354982
* Merge commit f596f4507 from llvm git (by Sam Elliott):Dimitry Andric2019-11-071-6/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [RISCV] Add Custom Parser for Atomic Memory Operands Summary: GCC Accepts both (reg) and 0(reg) for atomic instruction memory operands. These instructions do not allow for an offset in their encoding, so in the latter case, the 0 is silently dropped. Due to how we have structured the RISCVAsmParser, the easiest way to add support for parsing this offset is to add a custom AsmOperand and parser. This parser drops all the parens, and just keeps the register. This commit also adds a custom printer for these operands, which matches the GCC canonical printer, printing both `(a0)` and `0(a0)` as `(a0)`. Reviewers: asb, lewis-revill Reviewed By: asb Subscribers: s.egerton, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, jfb, PkmX, jocewei, psnobl, benna, Jim, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65205 llvm-svn: 367553 Merge commit f596f4507 from llvm git (by Sam Elliott): [RISCV] Add FreeBSD targets Reviewers: asb Reviewed By: asb Subscribers: simoncook, s.egerton, lenary, psnobl, benna, mhorne, emaste, kito-cheng, shiva0217, rogfer01, rkruppe, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D57795 Patch by James Clarke (jrtc27) llvm-svn: 367557 Merge commit f596f4507 from llvm git (by Hsiangkai Wang): [DebugInfo] Generate fixups as emitting DWARF .debug_frame/.eh_frame. It is necessary to generate fixups in .debug_frame or .eh_frame as relaxation is enabled due to the address delta may be changed after relaxation. There is an opcode with 6-bits data in debug frame encoding. So, we also need 6-bits fixup types. Differential Revision: https://reviews.llvm.org/D58335 llvm-svn: 366524 Merge commit f596f4507 from llvm git (by Hsiangkai Wang): [DebugInfo] Some fields do not need relocations even relax is enabled. In debug frame information, some fields, e.g., Length in CIE/FDE and Offset in FDE are attributes to describe the structure of CIE/FDE. They are not related to the relaxed code. However, these attributes are symbol differences. So, in current design, these attributes will be filled as zero and LLVM generates relocations for them. We only need to generate relocations for symbols in executable sections. So, if the symbols are not located in executable sections, we still evaluate their values under relaxation. Differential Revision: https://reviews.llvm.org/D61584 llvm-svn: 366531 Merge commit f596f4507 from llvm git (by Alex Bradbury): [RISCV] Don't force absolute FK_Data_X fixups to relocs The current behavior of shouldForceRelocation forces relocations for the majority of fixups when relaxation is enabled. This makes sense for fixups which incorporate symbols but is unnecessary for simple data fixups where the fixup target is already resolved to an absolute value. Differential Revision: https://reviews.llvm.org/D63404 Patch by Edward Jones. llvm-svn: 369257 Merge commit f596f4507 from llvm git (by Alex Bradbury): [RISCV] Implement getExprForFDESymbol to ensure RISCV_32_PCREL is used for the FDE location Follow binutils in using RISCV_32_PCREL for the FDE initial location. As explained in the relevant binutils commit <https://github.com/riscv/riscv-binutils-gdb/commit/a6cbf936e3dce68114d28cdf60d510a3f78a6d40>, the ADD/SUB pair of relocations is problematic in the presence of linker relaxation. This patch has the same end goal as D64715 but includes test changes and avoids adding a new global VariantKind to MCExpr.h (preferring RISCVMCExpr VKs like the rest of the RISC-V backend). Differential Revision: https://reviews.llvm.org/D66419 llvm-svn: 369375 This series of merges will permit riscv64 kernels and riscv64sf worlds to build with clang instead of gcc (but still using the bfd linker). Requested by: jhb Obtained from: https://github.com/freebsd/freebsd/compare/master...bsdjhb:riscv_clang MFC after: 1 month X-MFC-With: r353358 Notes: svn path=/head/; revision=354469
* Pull in r372186 from upstream llvm trunk (by Eli Friedman):Dimitry Andric2019-10-251-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [ARM] VFPv2 only supports 16 D registers. r361845 changed the way we handle "D16" vs. "D32" targets; there used to be a negative "d16" which removed instructions from the instruction set, and now there's a "d32" feature which adds instructions to the instruction set. This is good, but there was an oversight in the implementation: the behavior of VFPv2 was changed. In particular, the "vfp2" feature was changed to imply "d32". This is wrong: VFPv2 only supports 16 D registers. In practice, this means if you specify -mfpu=vfpv2, the compiler will generate illegal instructions. This patch gets rid of "vfp2d16" and "vfp2d16sp", and fixes "vfp2" and "vfp2sp" so they don't imply "d32". Differential Revision: https://reviews.llvm.org/D67375 Pull in r372187 from upstream clang trunk (by Eli Friedman): [ARM] Update clang for removal of vfp2d16 and vfp2d16sp Matching fix for https://reviews.llvm.org/D67375 (r372186). Differential Revision: https://reviews.llvm.org/D67467 This should fix clang generating invalid opcodes for floating point operations on armv6. Requested by: mmel MFC after: 3 days Notes: svn path=/head/; revision=354097
* Pull in r371066 from upstream clang trunk (by Justin Hibbits):Dimitry Andric2019-09-192-1/+10
| | | | | | | | | | | | | | | | | Add -m(no)-spe to clang Summary: r337347 added support for the Signal Processing Engine (SPE) to LLVM. This follows that up with the clang side. This adds -mspe and -mno-spe, to match GCC. Subscribers: nemanjai, kbarton, cfe-commits Differential Revision: https://reviews.llvm.org/D49754 Notes: svn path=/projects/clang900-import/; revision=352539
* Merge llvm, clang, compiler-rt, libc++, libunwind, lld, lldb, and openmpDimitry Andric2019-09-191-1/+1
| | | | | | | release 9.0.0 r372316, and update version numbers. Notes: svn path=/projects/clang900-import/; revision=352536
* Merge llvm, clang, compiler-rt, libc++, libunwind, lld, lldb, and openmpDimitry Andric2019-09-022-0/+18
| | | | | | | release_90 branch r370514, and update version numbers. Notes: svn path=/projects/clang900-import/; revision=351722
* Merge llvm, clang, compiler-rt, libc++, libunwind, lld, lldb, and openmpDimitry Andric2019-09-027-17/+37
| | | | | | | release_90 branch r369369, and update version numbers. Notes: svn path=/projects/clang900-import/; revision=351708
* Merge clang trunk r366426, resolve conflicts, and update FREEBSD-Xlist.Dimitry Andric2019-08-2176-827/+1675
| | | | Notes: svn path=/projects/clang900-import/; revision=351350
* Merge llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmpDimitry Andric2019-07-201-1/+1
| | | | | | | | | | | | | | 8.0.1 final release r366581. The only functional change is a fix for a mismerge of upstream r360816, which properly restores the r2 register when unwinding on PowerPC64 (See https://reviews.freebsd.org/D20337). Relnotes: yes PR: 236062 MFC after: 3 days X-MFC-With: r349004 Notes: svn path=/head/; revision=350177
* Upgrade our copies of clang, llvm, lld, lldb, compiler-rt, libc++,Dimitry Andric2019-06-121-1/+1
| | | | | | | | | | | libunwind and openmp to the upstream release_80 branch r363030 (effectively, 8.0.1 rc2). The 8.0.1 release should follow this within a week or so. MFC after: 2 weeks Notes: svn path=/head/; revision=349004
* Merge llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmpDimitry Andric2019-03-201-1/+1
| | | | | | | | | | | | | | | | | | | 8.0.0 final release r356365. There were no functional changes since the most recent merge, of 8.0.0 rc5. Release notes for llvm, clang, lld and libc++ 8.0.0 are now available: https://llvm.org/releases/8.0.0/docs/ReleaseNotes.html https://llvm.org/releases/8.0.0/tools/clang/docs/ReleaseNotes.html https://llvm.org/releases/8.0.0/tools/lld/docs/ReleaseNotes.html https://llvm.org/releases/8.0.0/projects/libcxx/docs/ReleaseNotes.html PR: 236062 MFC after: 1 month X-MFC-With: r344779 Notes: svn path=/head/; revision=345345
* Merge llvm, clang, compiler-rt, libc++, lld, and lldb release_80 branchDimitry Andric2019-02-151-1/+7
| | | | | | | r354130, resolve conflicts, and bump version numbers. Notes: svn path=/projects/clang800-import/; revision=344177
* Merge llvm, clang, compiler-rt, libc++, lld, and lldb release_80 branchDimitry Andric2019-02-057-33/+48
| | | | | | | r353167, resolve conflicts, and bump version numbers. Notes: svn path=/projects/clang800-import/; revision=343806
* Merge clang release_80 branch r351543, and resolve conflicts.Dimitry Andric2019-01-221-1/+1
| | | | Notes: svn path=/projects/clang800-import/; revision=343314
* Merge clang trunk r351319, resolve conflicts, and update FREEBSD-Xlist.Dimitry Andric2019-01-2039-2728/+948
| | | | Notes: svn path=/projects/clang800-import/; revision=343214
* Update clang, llvm, lld, lldb, compiler-rt and libc++ version number toDimitry Andric2018-12-151-1/+1
| | | | | | | | | | | | | 7.0.1 release r349250. There were no functional changes since the 7.0.1 rc3 import. PR: 230240, 230355 Relnotes: yes MFC after: 2 months X-MFC-With: r341825 Notes: svn path=/head/; revision=342123
* Merge llvm, clang, lld, lldb, compiler-rt and libc++ release_70 branchDimitry Andric2018-11-041-1/+1
| | | | | | | | | | r346007 (effectively 7.0.1 rc2), resolve conflicts, and bump version numbers. PR: 230240, 230355 Notes: svn path=/projects/clang700-import/; revision=340125
* Merge llvm, clang, lld, lldb, compiler-rt and libc++ 7.0.0 releaseDimitry Andric2018-09-171-1/+1
| | | | | | | | | r342383, and bump version numbers. PR: 230240, 230355 Notes: svn path=/projects/clang700-import/; revision=338730
* For now, revert upstream clang r323281 (by Wei Mi):Dimitry Andric2018-08-171-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Adjust MaxAtomicInlineWidth for i386/i486 targets. This is to fix the bug reported in https://bugs.llvm.org/show_bug.cgi?id=34347#c6. Currently, all MaxAtomicInlineWidth of x86-32 targets are set to 64. However, i386 doesn't support any cmpxchg related instructions. i486 only supports cmpxchg. So in this patch MaxAtomicInlineWidth is reset as follows: For i386, the MaxAtomicInlineWidth should be 0 because no cmpxchg is supported. For i486, the MaxAtomicInlineWidth should be 32 because it supports cmpxchg. For others 32 bits x86 cpu, the MaxAtomicInlineWidth should be 64 because of cmpxchg8b. Differential Revision: https://reviews.llvm.org/D42154 This should fix buildworld on i386, because of our system libraries missing __atomic_load_8, and possibly other 64 bit atomic functions, for that architecture. We should really fix that at some point, but since we have been actually using cmpxchg8b for years now, it does not seem to matter much... Notes: svn path=/projects/clang700-import/; revision=337979
* Merge clang release_70 branch r338892, and resolve conflicts.Dimitry Andric2018-08-041-1/+1
| | | | Notes: svn path=/projects/clang700-import/; revision=337310
* Merge clang trunk r338150 (just before the 7.0.0 branch point), andDimitry Andric2018-08-0213-91/+95
| | | | | | | resolve conflicts. Notes: svn path=/projects/clang700-import/; revision=337150
* Merge clang trunk r338150, and resolve conflicts.Dimitry Andric2018-07-3157-1037/+2219
| | | | Notes: svn path=/projects/clang700-import/; revision=336979
* Upgrade our copies of clang, llvm, lld, lldb, compiler-rt and libc++ toDimitry Andric2018-06-293-3/+40
| | | | | | | | | | 6.0.1 release (upstream r335540). Relnotes: yes MFC after: 2 weeks Notes: svn path=/head/; revision=335799
* Recommit r332501, with an additional upstream fix for "Cannot lowerDimitry Andric2018-04-202-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EFLAGS copy that lives out of a basic block!" errors on i386. Pull in r325446 from upstream clang trunk (by me): [X86] Add 'sahf' CPU feature to frontend Summary: Make clang accept `-msahf` (and `-mno-sahf`) flags to activate the `+sahf` feature for the backend, for bug 36028 (Incorrect use of pushf/popf enables/disables interrupts on amd64 kernels). This was originally submitted in bug 36037 by Jonathan Looney <jonlooney@gmail.com>. As described there, GCC also uses `-msahf` for this feature, and the backend already recognizes the `+sahf` feature. All that is needed is to teach clang to pass this on to the backend. The mapping of feature support onto CPUs may not be complete; rather, it was chosen to match LLVM's idea of which CPUs support this feature (see lib/Target/X86/X86.td). I also updated the affected test case (CodeGen/attr-target-x86.c) to match the emitted output. Reviewers: craig.topper, coby, efriedma, rsmith Reviewed By: craig.topper Subscribers: emaste, cfe-commits Differential Revision: https://reviews.llvm.org/D43394 Pull in r328944 from upstream llvm trunk (by Chandler Carruth): [x86] Expose more of the condition conversion routines in the public API for X86's instruction information. I've now got a second patch under review that needs these same APIs. This bit is nicely orthogonal and obvious, so landing it. NFC. Pull in r329414 from upstream llvm trunk (by Craig Topper): [X86] Merge itineraries for CLC, CMC, and STC. These are very simple flag setting instructions that appear to only be a single uop. They're unlikely to need this separation. Pull in r329657 from upstream llvm trunk (by Chandler Carruth): [x86] Introduce a pass to begin more systematically fixing PR36028 and similar issues. The key idea is to lower COPY nodes populating EFLAGS by scanning the uses of EFLAGS and introducing dedicated code to preserve the necessary state in a GPR. In the vast majority of cases, these uses are cmovCC and jCC instructions. For such cases, we can very easily save and restore the necessary information by simply inserting a setCC into a GPR where the original flags are live, and then testing that GPR directly to feed the cmov or conditional branch. However, things are a bit more tricky if arithmetic is using the flags. This patch handles the vast majority of cases that seem to come up in practice: adc, adcx, adox, rcl, and rcr; all without taking advantage of partially preserved EFLAGS as LLVM doesn't currently model that at all. There are a large number of operations that techinaclly observe EFLAGS currently but shouldn't in this case -- they typically are using DF. Currently, they will not be handled by this approach. However, I have never seen this issue come up in practice. It is already pretty rare to have these patterns come up in practical code with LLVM. I had to resort to writing MIR tests to cover most of the logic in this pass already. I suspect even with its current amount of coverage of arithmetic users of EFLAGS it will be a significant improvement over the current use of pushf/popf. It will also produce substantially faster code in most of the common patterns. This patch also removes all of the old lowering for EFLAGS copies, and the hack that forced us to use a frame pointer when EFLAGS copies were found anywhere in a function so that the dynamic stack adjustment wasn't a problem. None of this is needed as we now lower all of these copies directly in MI and without require stack adjustments. Lots of thanks to Reid who came up with several aspects of this approach, and Craig who helped me work out a couple of things tripping me up while working on this. Differential Revision: https://reviews.llvm.org/D45146 Pull in r329673 from upstream llvm trunk (by Chandler Carruth): [x86] Model the direction flag (DF) separately from the rest of EFLAGS. This cleans up a number of operations that only claimed te use EFLAGS due to using DF. But no instructions which we think of us setting EFLAGS actually modify DF (other than things like popf) and so this needlessly creates uses of EFLAGS that aren't really there. In fact, DF is so restrictive it is pretty easy to model. Only STD, CLD, and the whole-flags writes (WRFLAGS and POPF) need to model this. I've also somewhat cleaned up some of the flag management instruction definitions to be in the correct .td file. Adding this extra register also uncovered a failure to use the correct datatype to hold X86 registers, and I've corrected that as necessary here. Differential Revision: https://reviews.llvm.org/D45154 Pull in r330264 from upstream llvm trunk (by Chandler Carruth): [x86] Fix PR37100 by teaching the EFLAGS copy lowering to rewrite uses across basic blocks in the limited cases where it is very straight forward to do so. This will also be useful for other places where we do some limited EFLAGS propagation across CFG edges and need to handle copy rewrites afterward. I think this is rapidly approaching the maximum we can and should be doing here. Everything else begins to require either heroic analysis to prove how to do PHI insertion manually, or somehow managing arbitrary PHI-ing of EFLAGS with general PHI insertion. Neither of these seem at all promising so if those cases come up, we'll almost certainly need to rewrite the parts of LLVM that produce those patterns. We do now require dominator trees in order to reliably diagnose patterns that would require PHI nodes. This is a bit unfortunate but it seems better than the completely mysterious crash we would get otherwise. Differential Revision: https://reviews.llvm.org/D45673 Together, these should ensure clang does not use pushf/popf sequences to save and restore flags, avoiding problems with unrelated flags (such as the interrupt flag) being restored unexpectedly. Requested by: jtl PR: 225330 MFC after: 1 week Notes: svn path=/head/; revision=332833
* Revert r332501 for now, as it can cause build failures on i386.Dimitry Andric2018-04-142-12/+0
| | | | | | | | | | Reported upstream as <https://bugs.llvm.org/show_bug.cgi?id=37133>. Reported by: emaste, ci.freebsd.org PR: 225330 Notes: svn path=/head/; revision=332503
* Pull in r325446 from upstream clang trunk (by me):Dimitry Andric2018-04-142-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [X86] Add 'sahf' CPU feature to frontend Summary: Make clang accept `-msahf` (and `-mno-sahf`) flags to activate the `+sahf` feature for the backend, for bug 36028 (Incorrect use of pushf/popf enables/disables interrupts on amd64 kernels). This was originally submitted in bug 36037 by Jonathan Looney <jonlooney@gmail.com>. As described there, GCC also uses `-msahf` for this feature, and the backend already recognizes the `+sahf` feature. All that is needed is to teach clang to pass this on to the backend. The mapping of feature support onto CPUs may not be complete; rather, it was chosen to match LLVM's idea of which CPUs support this feature (see lib/Target/X86/X86.td). I also updated the affected test case (CodeGen/attr-target-x86.c) to match the emitted output. Reviewers: craig.topper, coby, efriedma, rsmith Reviewed By: craig.topper Subscribers: emaste, cfe-commits Differential Revision: https://reviews.llvm.org/D43394 Pull in r328944 from upstream llvm trunk (by Chandler Carruth): [x86] Expose more of the condition conversion routines in the public API for X86's instruction information. I've now got a second patch under review that needs these same APIs. This bit is nicely orthogonal and obvious, so landing it. NFC. Pull in r329414 from upstream llvm trunk (by Craig Topper): [X86] Merge itineraries for CLC, CMC, and STC. These are very simple flag setting instructions that appear to only be a single uop. They're unlikely to need this separation. Pull in r329657 from upstream llvm trunk (by Chandler Carruth): [x86] Introduce a pass to begin more systematically fixing PR36028 and similar issues. The key idea is to lower COPY nodes populating EFLAGS by scanning the uses of EFLAGS and introducing dedicated code to preserve the necessary state in a GPR. In the vast majority of cases, these uses are cmovCC and jCC instructions. For such cases, we can very easily save and restore the necessary information by simply inserting a setCC into a GPR where the original flags are live, and then testing that GPR directly to feed the cmov or conditional branch. However, things are a bit more tricky if arithmetic is using the flags. This patch handles the vast majority of cases that seem to come up in practice: adc, adcx, adox, rcl, and rcr; all without taking advantage of partially preserved EFLAGS as LLVM doesn't currently model that at all. There are a large number of operations that techinaclly observe EFLAGS currently but shouldn't in this case -- they typically are using DF. Currently, they will not be handled by this approach. However, I have never seen this issue come up in practice. It is already pretty rare to have these patterns come up in practical code with LLVM. I had to resort to writing MIR tests to cover most of the logic in this pass already. I suspect even with its current amount of coverage of arithmetic users of EFLAGS it will be a significant improvement over the current use of pushf/popf. It will also produce substantially faster code in most of the common patterns. This patch also removes all of the old lowering for EFLAGS copies, and the hack that forced us to use a frame pointer when EFLAGS copies were found anywhere in a function so that the dynamic stack adjustment wasn't a problem. None of this is needed as we now lower all of these copies directly in MI and without require stack adjustments. Lots of thanks to Reid who came up with several aspects of this approach, and Craig who helped me work out a couple of things tripping me up while working on this. Differential Revision: https://reviews.llvm.org/D45146 Pull in r329673 from upstream llvm trunk (by Chandler Carruth): [x86] Model the direction flag (DF) separately from the rest of EFLAGS. This cleans up a number of operations that only claimed te use EFLAGS due to using DF. But no instructions which we think of us setting EFLAGS actually modify DF (other than things like popf) and so this needlessly creates uses of EFLAGS that aren't really there. In fact, DF is so restrictive it is pretty easy to model. Only STD, CLD, and the whole-flags writes (WRFLAGS and POPF) need to model this. I've also somewhat cleaned up some of the flag management instruction definitions to be in the correct .td file. Adding this extra register also uncovered a failure to use the correct datatype to hold X86 registers, and I've corrected that as necessary here. Differential Revision: https://reviews.llvm.org/D45154 Together, these should ensure clang does not use pushf/popf sequences to save and restore flags, avoiding problems with unrelated flags (such as the interrupt flag) being restored unexpectedly. Requested by: jtl PR: 225330 MFC after: 1 week Notes: svn path=/head/; revision=332501
* Upgrade our copies of clang, llvm, lld, lldb, compiler-rt and libc++ toDimitry Andric2018-03-041-1/+1
| | | | | | | | | | | | | | | | | 6.0.0 release (upstream r326565). Release notes for llvm, clang and lld will be available here soon: <http://releases.llvm.org/6.0.0/docs/ReleaseNotes.html> <http://releases.llvm.org/6.0.0/tools/clang/docs/ReleaseNotes.html> <http://releases.llvm.org/6.0.0/tools/lld/docs/ReleaseNotes.html> Relnotes: yes MFC after: 3 months X-MFC-With: r327952 PR: 224669 Notes: svn path=/head/; revision=330384
* Upgrade our copies of clang, llvm, lld, lldb, compiler-rt and libc++ toDimitry Andric2018-02-251-1/+2
| | | | | | | | | | | 6.0.0 (branches/release_60 r325932). This corresponds to 6.0.0 rc3. MFC after: 3 months X-MFC-With: r327952 PR: 224669 Notes: svn path=/head/; revision=329983
* Upgrade our copies of clang, llvm, lld, lldb, compiler-rt and libc++ toDimitry Andric2018-02-022-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 6.0.0 (branches/release_60 r324090). This introduces retpoline support, with the -mretpoline flag. The upstream initial commit message (r323155 by Chandler Carruth) contains quite a bit of explanation. Quoting: Introduce the "retpoline" x86 mitigation technique for variant #2 of the speculative execution vulnerabilities disclosed today, specifically identified by CVE-2017-5715, "Branch Target Injection", and is one of the two halves to Spectre. Summary: First, we need to explain the core of the vulnerability. Note that this is a very incomplete description, please see the Project Zero blog post for details: https://googleprojectzero.blogspot.com/2018/01/reading-privileged-memory-with-side.html The basis for branch target injection is to direct speculative execution of the processor to some "gadget" of executable code by poisoning the prediction of indirect branches with the address of that gadget. The gadget in turn contains an operation that provides a side channel for reading data. Most commonly, this will look like a load of secret data followed by a branch on the loaded value and then a load of some predictable cache line. The attacker then uses timing of the processors cache to determine which direction the branch took *in the speculative execution*, and in turn what one bit of the loaded value was. Due to the nature of these timing side channels and the branch predictor on Intel processors, this allows an attacker to leak data only accessible to a privileged domain (like the kernel) back into an unprivileged domain. The goal is simple: avoid generating code which contains an indirect branch that could have its prediction poisoned by an attacker. In many cases, the compiler can simply use directed conditional branches and a small search tree. LLVM already has support for lowering switches in this way and the first step of this patch is to disable jump-table lowering of switches and introduce a pass to rewrite explicit indirectbr sequences into a switch over integers. However, there is no fully general alternative to indirect calls. We introduce a new construct we call a "retpoline" to implement indirect calls in a non-speculatable way. It can be thought of loosely as a trampoline for indirect calls which uses the RET instruction on x86. Further, we arrange for a specific call->ret sequence which ensures the processor predicts the return to go to a controlled, known location. The retpoline then "smashes" the return address pushed onto the stack by the call with the desired target of the original indirect call. The result is a predicted return to the next instruction after a call (which can be used to trap speculative execution within an infinite loop) and an actual indirect branch to an arbitrary address. On 64-bit x86 ABIs, this is especially easily done in the compiler by using a guaranteed scratch register to pass the target into this device. For 32-bit ABIs there isn't a guaranteed scratch register and so several different retpoline variants are introduced to use a scratch register if one is available in the calling convention and to otherwise use direct stack push/pop sequences to pass the target address. This "retpoline" mitigation is fully described in the following blog post: https://support.google.com/faqs/answer/7625886 We also support a target feature that disables emission of the retpoline thunk by the compiler to allow for custom thunks if users want them. These are particularly useful in environments like kernels that routinely do hot-patching on boot and want to hot-patch their thunk to different code sequences. They can write this custom thunk and use `-mretpoline-external-thunk` *in addition* to `-mretpoline`. In this case, on x86-64 thu thunk names must be: ``` __llvm_external_retpoline_r11 ``` or on 32-bit: ``` __llvm_external_retpoline_eax __llvm_external_retpoline_ecx __llvm_external_retpoline_edx __llvm_external_retpoline_push ``` And the target of the retpoline is passed in the named register, or in the case of the `push` suffix on the top of the stack via a `pushl` instruction. There is one other important source of indirect branches in x86 ELF binaries: the PLT. These patches also include support for LLD to generate PLT entries that perform a retpoline-style indirection. The only other indirect branches remaining that we are aware of are from precompiled runtimes (such as crt0.o and similar). The ones we have found are not really attackable, and so we have not focused on them here, but eventually these runtimes should also be replicated for retpoline-ed configurations for completeness. For kernels or other freestanding or fully static executables, the compiler switch `-mretpoline` is sufficient to fully mitigate this particular attack. For dynamic executables, you must compile *all* libraries with `-mretpoline` and additionally link the dynamic executable and all shared libraries with LLD and pass `-z retpolineplt` (or use similar functionality from some other linker). We strongly recommend also using `-z now` as non-lazy binding allows the retpoline-mitigated PLT to be substantially smaller. When manually apply similar transformations to `-mretpoline` to the Linux kernel we observed very small performance hits to applications running typic al workloads, and relatively minor hits (approximately 2%) even for extremely syscall-heavy applications. This is largely due to the small number of indirect branches that occur in performance sensitive paths of the kernel. When using these patches on statically linked applications, especially C++ applications, you should expect to see a much more dramatic performance hit. For microbenchmarks that are switch, indirect-, or virtual-call heavy we have seen overheads ranging from 10% to 50%. However, real-world workloads exhibit substantially lower performance impact. Notably, techniques such as PGO and ThinLTO dramatically reduce the impact of hot indirect calls (by speculatively promoting them to direct calls) and allow optimized search trees to be used to lower switches. If you need to deploy these techniques in C++ applications, we *strongly* recommend that you ensure all hot call targets are statically linked (avoiding PLT indirection) and use both PGO and ThinLTO. Well tuned servers using all of these techniques saw 5% - 10% overhead from the use of retpoline. We will add detailed documentation covering these components in subsequent patches, but wanted to make the core functionality available as soon as possible. Happy for more code review, but we'd really like to get these patches landed and backported ASAP for obvious reasons. We're planning to backport this to both 6.0 and 5.0 release streams and get a 5.0 release with just this cherry picked ASAP for distros and vendors. This patch is the work of a number of people over the past month: Eric, Reid, Rui, and myself. I'm mailing it out as a single commit due to the time sensitive nature of landing this and the need to backport it. Huge thanks to everyone who helped out here, and everyone at Intel who helped out in discussions about how to craft this. Also, credit goes to Paul Turner (at Google, but not an LLVM contributor) for much of the underlying retpoline design. Reviewers: echristo, rnk, ruiu, craig.topper, DavidKreitzer Subscribers: sanjoy, emaste, mcrosier, mgorny, mehdi_amini, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D41723 MFC after: 3 months X-MFC-With: r327952 PR: 224669 Notes: svn path=/head/; revision=328817
* Pull in r322245 from upstream clang trunk (by Craig Topper):Dimitry Andric2018-01-281-1/+5
| | | | | | | | | | | | | | | | [X86] Make -mavx512f imply -mfma and -mf16c in the frontend like it does in the backend. Similarly, make -mno-fma and -mno-f16c imply -mno-avx512f. Withou this "-mno-sse -mavx512f" ends up with avx512f being enabled in the frontend but disabled in the backend. Reported by: pawel PR: 225488 Notes: svn path=/head/; revision=328513
* Merge llvm, clang, lld, lldb, compiler-rt and libc++ release_60 r321788,Dimitry Andric2018-01-062-6/+3
| | | | | | | update build glue and version numbers. Notes: svn path=/projects/clang600-import/; revision=327657
* Merge llvm, clang, lld, lldb, compiler-rt and libc++ trunk r321545,Dimitry Andric2017-12-294-16/+91
| | | | | | | | update build glue and version numbers, add new intrinsics headers, and update OptionalObsoleteFiles.inc. Notes: svn path=/projects/clang600-import/; revision=327330
* Merge clang trunk r321414 to contrib/llvm.Dimitry Andric2017-12-245-7/+19
| | | | Notes: svn path=/projects/clang600-import/; revision=327135
* Merge clang trunk r321017 to contrib/llvm/tools/clang.Dimitry Andric2017-12-2062-9608/+11300
| | | | Notes: svn path=/projects/clang600-import/; revision=327024
* Upgrade our copies of clang, llvm, lld, lldb, compiler-rt and libc++ toDimitry Andric2017-12-161-1/+1
| | | | | | | | | | 5.0.1 release (upstream r320880). Relnotes: yes MFC after: 2 weeks Notes: svn path=/head/; revision=326909
* Upgrade our copies of clang, llvm, lldb and libc++ to r319231 from theDimitry Andric2017-12-032-4/+9
| | | | | | | | | upstream release_50 branch. This corresponds to 5.0.1 rc2. MFC after: 2 weeks Notes: svn path=/head/; revision=326496
* Upgrade our copies of clang, llvm, lld, lldb, compiler-rt and libc++ toDimitry Andric2017-09-061-1/+1
| | | | | | | | | | | | | | | | 5.0.0 release (upstream r312559). Release notes for llvm, clang and lld will be available here soon: <http://releases.llvm.org/5.0.0/docs/ReleaseNotes.html> <http://releases.llvm.org/5.0.0/tools/clang/docs/ReleaseNotes.html> <http://releases.llvm.org/5.0.0/tools/lld/docs/ReleaseNotes.html> Relnotes: yes MFC after: 1 month X-MFC-with: r321369 Notes: svn path=/head/; revision=323245
* Upgrade our copies of clang, llvm, lld and libc++ to r311219 from theDimitry Andric2017-08-211-1/+7
| | | | | | | | | | upstream release_50 branch. MFC after: 2 months X-MFC-with: r321369 Notes: svn path=/head/; revision=322740
* Upgrade our copies of clang, llvm and libc++ to r310316 from theDimitry Andric2017-08-091-7/+1
| | | | | | | | | | upstream release_50 branch. MFC after: 2 months X-MFC-with: r321369 Notes: svn path=/head/; revision=322320
* Upgrade our copies of clang, llvm, lld and lldb to r309439 from theDimitry Andric2017-07-302-2/+2
| | | | | | | | | | upstream release_50 branch. This is just after upstream's 5.0.0-rc1. MFC after: 2 months X-MFC-with: r321369 Notes: svn path=/head/; revision=321723
* Merge llvm, clang, lld, lldb, compiler-rt and libc++ r308421, and updateDimitry Andric2017-07-193-11/+62
| | | | | | | build glue. Notes: svn path=/projects/clang500-import/; revision=321238
* Merge llvm, clang, lld, lldb, compiler-rt and libc++ r307894, and updateDimitry Andric2017-07-131-51/+68
| | | | | | | build glue. Notes: svn path=/projects/clang500-import/; revision=320970
* Merge llvm, clang, lld, lldb, compiler-rt and libc++ r306956, and updateDimitry Andric2017-07-023-54/+384
| | | | | | | build glue. Notes: svn path=/projects/clang500-import/; revision=320572
* Merge llvm, clang, lld, lldb, compiler-rt and libc++ r306325, and updateDimitry Andric2017-06-274-32/+76
| | | | | | | build glue. Notes: svn path=/projects/clang500-import/; revision=320397
* Merge llvm, clang, lld, lldb, compiler-rt and libc++ r305145, and updateDimitry Andric2017-06-102-5/+69
| | | | | | | build glue. Notes: svn path=/projects/clang500-import/; revision=319799
* Merge llvm, clang, lld, lldb, compiler-rt and libc++ r304659, and updateDimitry Andric2017-06-034-4/+24
| | | | | | | build glue. Notes: svn path=/projects/clang500-import/; revision=319547
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