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* riscv: remove more riscv64sf supportBrooks Davis2024-03-211-8/+0
| | | | | | | | | | Remove a few more bits of riscv64sf support in libc and libm. Reduce floating point ABI checks to requiring double hard float. Reviewed by: imp, jhb Fixes: 1ca12bd927d7 Remove the riscv64sf architecture. Differential Revision: https://reviews.freebsd.org/D44334
* Remove $FreeBSD$: two-line .h patternWarner Losh2023-08-161-2/+0
| | | | Remove /^\s*\*\n \*\s+\$FreeBSD\$$\n/
* Replace SOFTFLOAT with __riscv_float_abi_*.Brooks Davis2018-04-191-1/+1
| | | | | | | | | | | | | | | | | | With SOFTFLOAT, libc and libm were built correctly, but any program including fenv.h itself assumed it was on a hardfloat systen and emitted inline fpu instructions for fedisableexcept() and friends. Unlike r315424 which did this for MIPS, I've used riscv_float_abi_soft and riscv_float_abi_double macros as appropriate rather than using __riscv_float_abi_soft exclusively. This ensures that attempts to use an unsupported hardfloat ABI will fail. Reviewed by: br Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D10039 Notes: svn path=/head/; revision=332792
* Add full softfloat and hardfloat support for RISC-V.Ruslan Bukin2016-11-161-0/+11
| | | | | | | | | | | Hardfloat is now default (use riscv64sf as TARGET_ARCH for softfloat). Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D8529 Notes: svn path=/head/; revision=308731
* Add fenv.c for RISC-V. Copied from MIPS.Ruslan Bukin2016-01-261-0/+52
Notes: svn path=/head/; revision=294833
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