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* Move the mptable.h under x86/include/.Attilio Rao2010-11-091-146/+0
| | | | | | | | Sponsored by: Sandvine Incorporated MFC after: 14 days Notes: svn path=/head/; revision=215051
* guard function decls with _KERNEL so user code can include this fileSam Leffler2006-03-011-1/+2
| | | | Notes: svn path=/head/; revision=156130
* Begin all license/copyright comments with /*-Warner Losh2005-01-051-1/+1
| | | | Notes: svn path=/head/; revision=139731
* Convert a couple of pointers to integers for source compatability withPeter Wemm2003-11-141-4/+4
| | | | | | | amd64. Notes: svn path=/head/; revision=122711
* Add the MP Table APIC enumerator. This code uses the BIOS MP Table toJohn Baldwin2003-11-031-2764/+45
| | | | | | | | enumerate I/O APICs as well as local APICs. It also provides Host-PCI and PCI-PCI bridge drivers to use the MP Table to route PCI interrupts. Notes: svn path=/head/; revision=121991
* Always export r_gdt and r_idt and give them extern declarations inJohn Baldwin2003-10-301-3/+0
| | | | | | | machine/segments.h. Notes: svn path=/head/; revision=121754
* A few whitespace and comment tweaks.John Baldwin2003-10-241-6/+3
| | | | Notes: svn path=/head/; revision=121481
* Commit Bosko's patch to clean up the PSE/PG_G initialization to andPeter Wemm2003-10-011-8/+2
| | | | | | | | | | | | | | | | | | | | | | | | avoid problems with some Pentium 4 cpus and some older PPro/Pentium2 cpus. There are several problems, some documented in Intel errata. This patch: 1) moves the kernel to the second page in the PSE case. There is an errata that says that you Must Not point a 4MB page at physical address zero on older cpus. We avoided bugs here due to sheer luck. 2) sets up PSE page tables right from the start in locore, rather than trying to switch from 4K to 4M (or 2M) pages part way through the boot sequence at the same time that we're messing with PG_G. For some reason, the pmap work over the last 18 months seems to tickle the problems, and the PAE infrastructure changes disturb the cpu bugs even more. A couple of people have reported a problem with APM bios calls during boot. I'll work with people to get this resolved. Obtained from: bmilekic Notes: svn path=/head/; revision=120654
* Remove an XXX comment by using the per CPU mask added after this commentJohn Baldwin2003-09-101-2/+1
| | | | | | | was added. Notes: svn path=/head/; revision=119941
* Fix copyright comment & FBSDID style nits.David E. O'Brien2003-08-251-2/+1
| | | | | | | Requested by: bde Notes: svn path=/head/; revision=119452
* Halted CPU's should not accumulate time.Paul Saab2003-08-121-6/+6
| | | | | | | Reviewed by: jhb Notes: svn path=/head/; revision=118832
* Use macros from apic.h to when writing to the ICR to send IPIs to startupJohn Baldwin2003-07-231-5/+12
| | | | | | | | | APs rather than magic numbers. Tested by: scottl Notes: svn path=/head/; revision=117928
* Protect lint(1) from a #error.Mark Murray2003-07-101-0/+2
| | | | Notes: svn path=/head/; revision=117385
* unifdef -DLAZY_SWITCH and start to tidy up the associated glue.Peter Wemm2003-07-101-3/+0
| | | | Notes: svn path=/head/; revision=117372
* - Construct a cpu topology map for Hyper Threading systems so that ULE mayJeff Roberson2003-06-281-0/+31
| | | | | | | take advantage of them. Notes: svn path=/head/; revision=117006
* Use __FBSDID().David E. O'Brien2003-06-021-1/+3
| | | | Notes: svn path=/head/; revision=115683
* Initialize logical_cpus_mask when the logical CPUs are enumerated inAlan Cox2003-05-151-2/+5
| | | | | | | | | | | the mptable. (Previously, logical_cpus_mask was only initialized if the hyperthreading fixup was executed.) Approved by: re (jhb) Reviewed by: ps Notes: svn path=/head/; revision=115016
* Commit a partial lazy thread switch mechanism for i386. it isn't as lazyPeter Wemm2003-04-021-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | as it could be and can do with some more cleanup. Currently its under options LAZY_SWITCH. What this does is avoid %cr3 reloads for short context switches that do not involve another user process. ie: we can take an interrupt, switch to a kthread and return to the user without explicitly flushing the tlb. However, this isn't as exciting as it could be, the interrupt overhead is still high and too much blocks on Giant still. There are some debug sysctls, for stats and for an on/off switch. The main problem with doing this has been "what if the process that you're running on exits while we're borrowing its address space?" - in this case we use an IPI to give it a kick when we're about to reclaim the pmap. Its not compiled in unless you add the LAZY_SWITCH option. I want to fix a few more things and get some more feedback before turning it on by default. This is NOT a replacement for Bosko's lazy interrupt stuff. This was more meant for the kthread case, while his was for interrupts. Mine helps a little for interrupts, but his helps a lot more. The stats are enabled with options SWTCH_OPTIM_STATS - this has been a pseudo-option for years, I just added a bunch of stuff to it. One non-trivial change was to select a new thread before calling cpu_switch() in the first place. This allows us to catch the silly case of doing a cpu_switch() to the current process. This happens uncomfortably often. This simplifies a bit of the asm code in cpu_switch (no longer have to call choosethread() in the middle). This has been implemented on i386 and (thanks to jake) sparc64. The others will come soon. This is actually seperate to the lazy switch stuff. Glanced at by: jake, jhb Notes: svn path=/head/; revision=112993
* Nuke options HTT infavor of machdep.hlt_logical_cpus tunable/sysctl.Paul Saab2003-03-261-21/+88
| | | | | | | | | | | | | | | | | This keeps the logical cpu's halted in the idle loop. By default the logical cpu's are halted at startup. It is also possible to halt any cpu in the idle loop now using machdep.hlt_cpus. Examples of how to use this: machdep.hlt_cpus=1 halt cpu0 machdep.hlt_cpus=2 halt cpu1 machdep.hlt_cpus=4 halt cpu2 machdep.hlt_cpus=3 halt cpu0,cpu1 Reviewed by: jhb, peter Notes: svn path=/head/; revision=112687
* - Add vm_paddr_t, a physical address type. This is required for systemsJake Burkholder2003-03-251-1/+1
| | | | | | | | | | | | | | | | | | where physical addresses larger than virtual addresses, such as i386s with PAE. - Use this to represent physical addresses in the MI vm system and in the i386 pmap code. This also changes the paddr parameter to d_mmap_t. - Fix printf formats to handle physical addresses >4G in the i386 memory detection code, and due to kvtop returning vm_paddr_t instead of u_long. Note that this is a name change only; vm_paddr_t is still the same as vm_offset_t on all currently supported platforms. Sponsored by: DARPA, Network Associates Laboratories Discussed with: re, phk (cdevsw change) Notes: svn path=/head/; revision=112569
* Wrap the hyperthreading support code with the HTT kernel option.John Baldwin2003-03-041-0/+21
| | | | | | | | | Hyperthreading support is now off unless the HTT option is added. MFC-after: 3 days Notes: svn path=/head/; revision=111878
* The mpbiosreason variable does not used for pc98.Yoshihiro Takahashi2003-02-241-0/+2
| | | | Notes: svn path=/head/; revision=111428
* Allow machines with one CPU and a valid mp table to boot an SMP kernel.Tor Egge2003-02-231-0/+2
| | | | Notes: svn path=/head/; revision=111382
* Back out M_* changes, per decision of the TRB.Warner Losh2003-02-191-4/+4
| | | | | | | Approved by: trb Notes: svn path=/head/; revision=111119
* Remove #include <sys/dkstat.h>Poul-Henning Kamp2003-02-161-1/+0
| | | | Notes: svn path=/head/; revision=111002
* Split statclock into statclock and profclock, and made the method for drivingJake Burkholder2003-02-031-10/+9
| | | | | | | | | | | | | | | | statclock based on profhz when profiling is enabled MD, since most platforms don't use this anyway. This removes the need for statclock_process, whose only purpose was to subdivide profhz, and gets the profiling clock running outside of sched_lock on platforms that implement suswintr. Also changed the interface for starting and stopping the profiling clock to do just that, instead of changing the rate of statclock, since they can now be separate. Reviewed by: jhb, tmm Tested on: i386, sparc64 Notes: svn path=/head/; revision=110296
* Reversion of commit by Davidxu plus fixes since applied.Julian Elischer2003-02-011-1/+2
| | | | | | | | | | | I'm not convinced there is anything major wrong with the patch but them's the rules.. I am using my "David's mentor" hat to revert this as he's offline for a while. Notes: svn path=/head/; revision=110190
* Fix KSE related patch.Julian Elischer2003-01-261-2/+1
| | | | | | | | Make it compile for the SMP case.. statclock_process() has changed prototypes. Notes: svn path=/head/; revision=109898
* - Move enable_sse()'s prototype to machine/md_var.h.John Baldwin2003-01-221-2/+0
| | | | | | | | | | | - Sort definition of cpu_* variables appropriately. - Move cpu_fxsr out of the magic non-BSS set of variables and stick it in the BSS along with hw_instruction_sse (make the latter static as well). Submitted by: bde (partially) Notes: svn path=/head/; revision=109700
* Rename cpuid_cpuinfo to cpu_procinfo. bde requested that I rename thisJohn Baldwin2003-01-221-1/+1
| | | | | | | | | | variable to something in the cpu_* namespace since that's what all the other cpuid variables were named and cpu_procinfo is what I came up with. Requested by: bde Notes: svn path=/head/; revision=109696
* Remove M_TRYWAIT/M_WAITOK/M_WAIT. Callers should use 0.Alfred Perlstein2003-01-211-4/+4
| | | | | | | Merge M_NOWAIT/M_DONTWAIT into a single flag M_NOWAIT. Notes: svn path=/head/; revision=109623
* Enumerate logical hyperthread CPUs manually if they aren't already listedJohn Baldwin2003-01-081-0/+80
| | | | | | | | | | | | | | | | | | | in the mptable. The way this works is that we determine if the system has hyperthreading and how many logical CPU's should be in each physical CPU by using the information returned by cpuid. During the first pass of the mptable, we build a bitmask of the APIC IDs of the CPUs listed in the mptable. We then scan that bitmask to see if the CPUs are already listed by the mptable, or if there are any APIC IDs already in use that would conflict with the APIC IDs of the logical CPUs. If that test succeeds, then we fixup the count of application processors. Later on during the second pass of the mptable we create fake processor entries for logical CPUs and add them to the system. We only need this type of fixup hack when using the mptable to enumerate CPUs. The ACPI MADT table properly enumerates all logical CPUs. Notes: svn path=/head/; revision=108914
* Be consistent about functions being static.Poul-Henning Kamp2002-10-161-1/+1
| | | | | | | Spotted by: FlexeLint. Notes: svn path=/head/; revision=105216
* Turn back on the "SMP: AP CPU #N Launched!" message on normal boots.David E. O'Brien2002-09-301-2/+1
| | | | | | | | Peter's rev 1.189 should fix the lost console on SCSI-based systems due to this message. Notes: svn path=/head/; revision=104215
* Only print out the "SMP: AP CPU #N Launched!" message on verbose boots.David E. O'Brien2002-09-301-4/+4
| | | | | | | The kernel printf() isn't race-free Notes: svn path=/head/; revision=104175
* OK, I have had it with losing my console because the AP's print their "I amPeter Wemm2002-08-281-5/+12
| | | | | | | | | alive!" message right as the scsi probe messages happen. This is a bit nasty, but it seems to work. At the point that we unlock the AP's, briefly wait till they are all done while we hold the console on their behalf. Notes: svn path=/head/; revision=102543
* Revive backed out pmap related changes from Feb 2002. The highlights are:Peter Wemm2002-07-121-22/+230
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - It actually works this time, honest! - Fine grained TLB shootdowns for SMP on i386. IPI's are very expensive, so try and optimize things where possible. - Introduce ranged shootdowns that can be done as a single IPI. - PG_G support for i386 - Specific-cpu targeted shootdowns. For example, there is no sense in globally purging the TLB cache for where we are stealing a page from the local unshared process on the local cpu. Use pm_active to track this. - Add some instrumentation for the tlb shootdown code. - Rip out SMP code from <machine/cpufunc.h> - Try and fix some very bogus PG_G and PG_PS interactions that were bad enough to cause vm86 bios calls to break. vm86 depended on our existing bugs and this was the cause of the VESA panics last time. - Fix the silly one-line error that caused the 'panic: bad pte' last time. - Fix a couple of other silly one-line errors that should have caused more pain than they did. Some more work is needed: - pmap_{zero,copy}_page[_idle]. These can be done without IPI's if we have a hook in cpu_switch. - The IPI handlers need some cleanup. I have a bogus %ds load that can be avoided. - APTD handling is rather bogus and appears to be a large source of global TLB IPI shootdowns for no really good reason. I see speedups of between 1.5% and ~4% on buildworlds in a while 1 loop. I expect to see a bigger difference when there is significant pageout activity or the system otherwise has memory shortages. I have backed out a few optimizations that I had been using over the last few days in order to be a little more conservative. I'll revisit these again over the next few days as the dust settles. New option: DISABLE_PG_G - In case I missed something. Notes: svn path=/head/; revision=99862
* Bah, move the invltlb counter to C code and hook a debug sysctl onto it.Peter Wemm2002-07-111-0/+6
| | | | Notes: svn path=/head/; revision=99766
* Fix typo in adjusted panic message.Tor Egge2002-04-171-1/+1
| | | | | | | Submitted by: cokane Notes: svn path=/head/; revision=94967
* Update io_apic_ints array properly when revoking an irq mapping.Tor Egge2002-04-171-2/+2
| | | | | | | | | Adjust panic message. Submitted by: David Xu <bsddiy@yahoo.com> Notes: svn path=/head/; revision=94962
* Change callers of mtx_init() to pass in an appropriate lock type name. InJohn Baldwin2002-04-041-2/+2
| | | | | | | | | | most cases NULL is passed, but in some cases such as network driver locks (which use the MTX_NETWORK_LOCK macro) and UMA zone locks, a name is used. Tested on: i386, alpha, sparc64 Notes: svn path=/head/; revision=93818
* Compromise for critical*()/cpu_critical*() recommit. Cleanup the interruptMatthew Dillon2002-03-271-0/+6
| | | | | | | | | | | | | | | | | | | | | | disablement assumptions in kern_fork.c by adding another API call, cpu_critical_fork_exit(). Cleanup the td_savecrit field by moving it from MI to MD. Temporarily move cpu_critical*() from <arch>/include/cpufunc.h to <arch>/<arch>/critical.c (stage-2 will clean this up). Implement interrupt deferral for i386 that allows interrupts to remain enabled inside critical sections. This also fixes an IPI interlock bug, and requires uses of icu_lock to be enclosed in a true interrupt disablement. This is the stage-1 commit. Stage-2 will occur after stage-1 has stabilized, and will move cpu_critical*() into its own header file(s) + other things. This commit may break non-i386 architectures in trivial ways. This should be temporary. Reviewed by: core Approved by: core Notes: svn path=/head/; revision=93264
* Fixed some style bugs in the removal of __P(()). The main ones wereBruce Evans2002-03-231-5/+5
| | | | | | | | | not removing tabs before "__P((", and not outdenting continuation lines to preserve non-KNF lining up of code with parentheses. Switch to KNF formatting and/or rewrap the whole prototype in some cases. Notes: svn path=/head/; revision=93017
* Remove __P.Alfred Perlstein2002-03-201-5/+5
| | | | Notes: svn path=/head/; revision=92770
* Add needed includes of machine/smp.h, remove nested include in sys/smp.hJake Burkholder2002-03-071-0/+1
| | | | | | | so that inlines in machine/smp.h can use variables declared in sys/smp.h. Notes: svn path=/head/; revision=91778
* Add a new variable mp_maxid. This is used so that per cpu datastructures mayJeff Roberson2002-03-051-1/+4
| | | | | | | | | | | | | | | | be allocated as arrays indexed by the cpu id. Previously the only reliable way to know the max cpu id was through MAXCPU. mp_ncpus isn't useful here because cpu ids may be sparsely mapped, although x86 and alpha do not do this. Also, call cpu_mp_probe much earlier so the max cpu id is known before the VM starts up. This is intended to help support per cpu queues for the new allocator, but may be useful elsewhere. Reviewed by: jake Approved by: jake Notes: svn path=/head/; revision=91673
* Back out all the pmap related stuff I've touched over the last few days.Peter Wemm2002-02-271-193/+18
| | | | | | | | | There is some unresolved badness that has been eluding me, particularly affecting uniprocessor kernels. Turning off PG_G helped (which is a bad sign) but didn't solve it entirely. Userland programs still crashed. Notes: svn path=/head/; revision=91367
* revert last commit temporarily due to whining on the lists.Matthew Dillon2002-02-261-6/+0
| | | | Notes: svn path=/head/; revision=91328
* STAGE-1 of 3 commit - allow (but do not require) interrupts to remainMatthew Dillon2002-02-261-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | enabled in critical sections and streamline critical_enter() and critical_exit(). This commit allows an architecture to leave interrupts enabled inside critical sections if it so wishes. Architectures that do not wish to do this are not effected by this change. This commit implements the feature for the I386 architecture and provides a sysctl, debug.critical_mode, which defaults to 1 (use the feature). For now you can turn the sysctl on and off at any time in order to test the architectural changes or track down bugs. This commit is just the first stage. Some areas of the code, specifically the MACHINE_CRITICAL_ENTER #ifdef'd code, is strictly temporary and will be cleaned up in the STAGE-2 commit when the critical_*() functions are moved entirely into MD files. The following changes have been made: * critical_enter() and critical_exit() for I386 now simply increment and decrement curthread->td_critnest. They no longer disable hard interrupts. When critical_exit() decrements the counter to 0 it effectively calls a routine to deal with whatever interrupts were deferred during the time the code was operating in a critical section. Other architectures are unaffected. * fork_exit() has been conditionalized to remove MD assumptions for the new code. Old code will still use the old MD assumptions in regards to hard interrupt disablement. In STAGE-2 this will be turned into a subroutine call into MD code rather then hardcoded in MI code. The new code places the burden of entering the critical section in the trampoline code where it belongs. * I386: interrupts are now enabled while we are in a critical section. The interrupt vector code has been adjusted to deal with the fact. If it detects that we are in a critical section it currently defers the interrupt by adding the appropriate bit to an interrupt mask. * In order to accomplish the deferral, icu_lock is required. This is i386-specific. Thus icu_lock can only be obtained by mainline i386 code while interrupts are hard disabled. This change has been made. * Because interrupts may or may not be hard disabled during a context switch, cpu_switch() can no longer simply assume that PSL_I will be in a consistent state. Therefore, it now saves and restores eflags. * FAST INTERRUPT PROVISION. Fast interrupts are currently deferred. The intention is to eventually allow them to operate either while we are in a critical section or, if we are able to restrict the use of sched_lock, while we are not holding the sched_lock. * ICU and APIC vector assembly for I386 cleaned up. The ICU code has been cleaned up to match the APIC code in regards to format and macro availability. Additionally, the code has been adjusted to deal with deferred interrupts. * Deferred interrupts use a per-cpu boolean int_pending, and masks ipending, spending, and fpending. Being per-cpu variables it is not currently necessary to lock; bus cycles modifying them. Note that the same mechanism will enable preemption to be incorporated as a true software interrupt without having to further hack up the critical nesting code. * Note: the old critical_enter() code in kern/kern_switch.c is currently #ifdef to be compatible with both the old and new methodology. In STAGE-2 it will be moved entirely to MD code. Performance issues: One of the purposes of this commit is to enhance critical section performance, specifically to greatly reduce bus overhead to allow the critical section code to be used to protect per-cpu caches. These caches, such as Jeff's slab allocator work, can potentially operate very quickly making the effective savings of the new critical section code's performance very significant. The second purpose of this commit is to allow architectures to enable certain interrupts while in a critical section. Specifically, the intention is to eventually allow certain FAST interrupts to operate rather then defer. The third purpose of this commit is to begin to clean up the critical_enter()/critical_exit()/cpu_critical_enter()/ cpu_critical_exit() API which currently has serious cross pollution in MI code (in fork_exit() and ast() for example). The fourth purpose of this commit is to provide a framework that allows kernel-preempting software interrupts to be implemented cleanly. This is currently used for two forward interrupts in I386. Other architectures will have the choice of using this infrastructure or building the functionality directly into critical_enter()/ critical_exit(). Finally, this commit is designed to greatly improve the flexibility of various architectures to manage critical section handling, software interrupts, preemption, and other highly integrated architecture-specific details. Notes: svn path=/head/; revision=91315
* Work-in-progress commit syncing up pmap cleanups that I have been workingPeter Wemm2002-02-251-18/+193
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | on for a while: - fine grained TLB shootdown for SMP on i386 - ranged TLB shootdowns.. eg: specify a range of pages to shoot down with a single IPI, since the IPI is very expensive. Adjust some callers that used to trigger this inside tight loops to do a ranged shootdown at the end instead. - PG_G support for SMP on i386 (options ENABLE_PG_G) - defer PG_G activation till after we decide what we are going to do with PSE and the 4MB pages at the start of the kernel. This should solve some rumored strangeness about stale PG_G entries getting stuck underneath the 4MB pages. - add some instrumentation for the fine TLB shootdown - convert some asm instruction wrappers from functions to inlines. gcc seems to do a fair bit better with this. - [temporarily!] pessimize the tlb shootdown IPI handlers. I will fix this again shortly. This has been working fairly well for me for a while, but I have tweaked it again prior to commit since my last major testing round. The only outstanding problem that I know of is PG_G related, which is why there is an option for it (not on by default for SMP). I have seen a world speedups by a few percent (as much as 4 or 5% in one case) but I have *not* accurately measured this - I am a bit sceptical of these numbers. Notes: svn path=/head/; revision=91260
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