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* arm64: Add CNTPOFF_EL2 op/CR valuesAndrew Turner7 days1-0/+8
| | | | | Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D51376
* arm64: Support mapping a 52-bit physical adddressAndrew Turner2025-01-241-0/+1
| | | | | | | | | | | | When FEAT_LPA2 is enabled the physical address space increases from 48-bits to 52-bits. The top two address bits are moved to the now unused shareability field. Update the kernel to support this new larger address space. Reviewed by: alc, kib Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D46624
* arm64: add HCRX_EL2 registerHarry Moulton2025-01-231-0/+35
| | | | | | | | | | | | HCRX_EL2 is the Extended Hypervisor Configuration Register introduced with FEAT_HCX in ARMv8.7. All fields in this register are used for features in ARMv8.7 and above. Initially zero the register, incase firmware has not properly configured it. Reviewed by: andrew Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D48583 Signed-off-by: Harry Moulton <harry.moulton@arm.com>
* arm64: Add a constant to document the TZ bit in CPTR_EL2 without VHEJohn Baldwin2024-12-061-0/+1
| | | | | | Reviewed by: emaste Sponsored by: AFRL, DARPA Differential Revision: https://reviews.freebsd.org/D47882
* arm64: Don't trap SVE to EL2Andrew Turner2024-09-301-1/+2
| | | | | | | | | As with floating point instructions don't trap SVE instructions to the hypervisor. This lets us handle then in the kernel. Reviewed by: imp (earlier version) Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D43303
* arm64: Add CPTR_TRAP_ALL and use it in vmmAndrew Turner2024-09-111-0/+2
| | | | | | | | Add a new macro that enables all CPTR_EL2 traps. This helps ensure we trap all extensions we don't support. Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D46516
* arm64: Add CPTR_E2H_TTAAndrew Turner2024-09-111-1/+2
| | | | | | | | The TTA field moves depending on the HCR_EL2.E2H field. Add a macro to hold the E2H == 1 case. Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D46515
* arm64: Add E2H to CPTR_EL2 register valuesAndrew Turner2024-09-111-1/+1
| | | | | | | | Rename register fields that are only valid when HCR_EL2.E2H == 1. Some fields move around depending on the value of the E2H field. Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D46514
* arm64: Adjust the indentation of CPTR_EL2 valuesAndrew Turner2024-09-111-6/+6
| | | | | | Reviewed by: emaste Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D46513
* arm64: add additional MDCR_EL2 fieldsZachary Leaf2024-09-091-0/+30
| | | | | | | | | Monitor Debug Configuration Register provides EL2 configuration options for self-hosted debug and the Performance Monitors Extension. Reviewed by: andrew Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D46191
* arm64: Make shareability attributes dynamicAndrew Turner2024-09-051-0/+2
| | | | | | | | | | When LPA2 is enabled the shareability attribute in the page table are replaces with output address bits. To support a larger physical address space make this attribute dynamic so we only set it when appropriate. Reviewed by: alc, kib Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D46394
* arm64/vmm: Teach the vtimer about VHEAndrew Turner2024-08-201-0/+4
| | | | | | | | | Teach the virtual timer about the cnthctl_el2 field layout under VHE. As with non-VHE we need to trap the physical timer and not trap the virtual timer. Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D46074
* arm64: Ensure sctlr and pstate are in known statesAndrew Turner2024-07-231-0/+4
| | | | | | | | | | | | | | Before entering the kernel exception level ensure sctlr_el2 and sctlr_el1 are in a known state. The EOS flag needs to be set to ensure an eret instruction is a context synchronization event. Set spcr_el1 when entering the kernel from EL1 and use an eret instruction to return to the caller. This ensures the CPU pstate is consistent with the value in spcr_el1 as it is the only way to set it directly. Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D45528
* arm64: Support counter access with E2HAndrew Turner2024-07-231-2/+7
| | | | | | | | | When entering the kernel with the E2H field set the layout of the cnthctl_el2 register changes. Use the correct field locations to enable access to the counter and timer registers from EL1. Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D45529
* arm64: Add a macro to find a VM fault addressAndrew Turner2024-02-211-0/+2
| | | | | | | | | Add a macro to find which bits from far_el2 are needed to be copied to get the full intermediate physical address (IPA). The hpfar_el2 register only contains a 4k aligned fault address. We need to include the lower bits from far_el2 if we need the full faulting IPA.
* arm64: Add the TCR_EL2.PS maskAndrew Turner2024-02-211-0/+1
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* arm64: Add register definitions for MDCR_EL2Mark Johnston2023-12-011-0/+18
| | | | | | | | | This is needed to support the bhyve gdb stub implementation on arm64. Reviewed by: andrew MFC after: 1 week Sponsored by: Innovate UK Differential Revision: https://reviews.freebsd.org/D42867
* sys: Remove $FreeBSD$: two-line .h patternWarner Losh2023-08-161-2/+0
| | | | Remove /^\s*\*\n \*\s+\$FreeBSD\$$\n/
* arm64: set FPEN if we're stuck with HCR_EL2.E2HKyle Evans2023-02-281-0/+4
| | | | | | | | | | On Apple Silicon systems, E2H can't actually be cleared; we're stuck with it. Check it again when we're setting up CPTR_EL2 and set FPEN appropriately to avoid later trapping to EL2 on writes to SIMD registers. Reviewed by: andrew Differential Revision: https://reviews.freebsd.org/D38819
* Add more arm64 hypervisor registersAndrew Turner2022-11-151-1/+29
| | | | | | | These will be used by bhyve. Sponsored by: Innovate UK Sponsored by: The FreeBSD Foundation
* Put the arm64 vttbr_el2 register into a stateAndrew Turner2022-11-151-0/+1
| | | | | | | | | Zero the vttbr_el2 register on each CPU so we can tell if we are running the host or guest kernel from a hypervisor. Obtained from: https://github.com/FreeBSD-UPB/freebsd-src (earlier version) Sponsored by: Innovate UK Sponsored by: The FreeBSD Foundation
* Mark 64-bit arm64 hypervisor registers with ULAndrew Turner2022-10-111-39/+39
| | | | | | | | These are 64-bit. Mark them as unsigned long so we don't rely on undefined behaviour or shift a 32-bit value more than 32 bits. Sponsored by: Innovate UK Sponsored by: The FreeBSD Foundation
* Update the arm64 HCR_EL2 registersAndrew Turner2021-07-141-47/+66
| | | | | | | | | | They are valid as of the ARMv8.7 XML. While here switch to use shifted values as they are easier to compare with values in the Arm Reference Manual. Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D31093
* Update the hypervisor registersAndrew Turner2020-03-061-9/+98
| | | | | | | | | | | - Add more registers needed by bhyve [1] - Move EL2 registers from armreg.h to hypervisor.h - Add the register name to hypervisor.h Obtained from: https://github.com/FreeBSD-UPB/freebsd [1] Notes: svn path=/head/; revision=358703
* Add the ARMv8.3 HCR_EL2 register fields.Andrew Turner2018-11-011-0/+11
| | | | | | | | MFC after: 1 month Sponsored by: DARPA, AFRL Notes: svn path=/head/; revision=340008
* Bring in the start of the arm64 kernel.Andrew Turner2015-04-131-0/+85
This is only the minimum set of files needed to boot in qemu. As such it is missing a few things. The bus_dma code is currently only stub functions with a full implementation from the development tree to follow. The gic driver has been copied as the interrupt framework is different. It is expected the two drivers will be merged by the arm intrng project, however this will need to be imported into the tree and support for arm64 would need to be added. This includes code developed by myself, SemiHalf, Ed Maste, and Robin Randhawa from ARM. This has been funded by the FreeBSD Foundation, with early development by myself in my spare time with assistance from Robin. Differential Revision: https://reviews.freebsd.org/D2199 Reviewed by: emaste, imp Relnotes: yes Sponsored by: The FreeBSD Foundation Notes: svn path=/head/; revision=281494
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