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* arm64: Sort hypervisor.hAndrew Turner2025-10-021-48/+48
* arm64: Rename the MDCR_EL2 macrosAndrew Turner2025-10-021-30/+30
* arm64: Add more counter/timer registersAndrew Turner2025-09-231-0/+32
* arm64/vmm: Clean up enabling guest timer accessAndrew Turner2025-09-231-11/+68
* arm64: Enable EPAN and IESBAndrew Turner2025-09-191-0/+2
* arm64: Read the CPU feature tunables onceAndrew Turner2025-09-191-0/+3
* arm64: Add cpu_feat_disabled for disabled featuresAndrew Turner2025-09-191-1/+4
* arm64: Add the new C1 CPU IDsAndrew Turner2025-09-151-0/+4
* vmm: Suspend the VM before destroying itMark Johnston2025-09-101-0/+1
* arm64: Replace cpu_tlb_flushID in initarmAndrew Turner2025-09-041-0/+2
* arm64: Remove CPU_MATCH_RAWAndrew Turner2025-09-041-3/+0
* arm64: Add a function to check a range of CPU revsAndrew Turner2025-09-041-0/+25
* arm64: Support managing features from loaderAndrew Turner2025-09-041-1/+26
* arm64: Add a sysctl to see if features are enabledAndrew Turner2025-09-041-3/+10
* arm64: Add a macro to create cpu_featAndrew Turner2025-09-041-0/+10
* arm64: Add padding to struct mdprocAndrew Turner2025-09-041-0/+1
* arm64: Make the padding in struct ms_page explicitAndrew Turner2025-09-041-0/+1
* arm64: Support TBI in userspaceAndrew Turner2025-08-084-2/+14
* arm64/vmm: Support reading MPIDR_EL1Andrew Turner2025-08-071-0/+1
* arm64: Use a fixed value for sctlr_el1Andrew Turner2025-07-311-0/+20
* arm64: tidy up Top-Byte-Ignore (TBI) in the kernelHarry Moulton2025-07-311-0/+3
* arm64: Add ADDR_IS_USERAndrew Turner2025-07-311-0/+2
* arm64: Teach CHECK_CPU_FEAT to handle more valuesAndrew Turner2025-07-301-3/+4
* arm64: Add CNTPOFF_EL2 op/CR valuesAndrew Turner2025-07-301-0/+8
* arm64: Rename ID_AA64MMFR0_ECV_CNTHCTLAndrew Turner2025-07-301-1/+1
* vmm: Add support for guest NUMA emulationBojan Novković2025-07-271-0/+5
* arm64: Add AT_HWCAP3 and AT_HWCAP4 supportAndrew Turner2025-06-241-0/+4
* arm64: Add more CPU MIDR valuesAndrew Turner2025-06-231-1/+19
* arm64: Reduce where we decode msr/mrs instructionsAndrew Turner2025-06-232-39/+0
* arm64: Remove the MRS_REG macro and it's usersAndrew Turner2025-06-231-82/+0
* arm64: Use ISS to search for a special registerAndrew Turner2025-06-231-4/+12
* arm64: Remove extract_user_id_fieldAndrew Turner2025-06-231-1/+0
* arm64: Add get_user_regAndrew Turner2025-06-231-0/+1
* runq: Deduce most parameters, remove machine headersOlivier Certner2025-06-181-50/+0
* arm: fix build after _types.h changesBrooks Davis2025-06-121-0/+2
* efi: Include sys/types.h for register_tWarner Losh2025-06-041-0/+2
* arm64: Add a function to restrict the ID registersAndrew Turner2025-06-021-0/+1
* arm64: Add more PMCR_EL0 fieldsAndrew Turner2025-05-271-0/+3
* arm64: Make all the PMCR_EL0 fields 64-bitAndrew Turner2025-05-271-10/+10
* arm64: Sort the PMCR_EL0 fieldsAndrew Turner2025-05-271-5/+5
* arm64: Add the ESR ISS value to struct mrs_user_regAndrew Turner2025-05-121-0/+20
* arm: Switch the timer to the new sys handlerAndrew Turner2025-05-121-0/+1
* arm64: Start splitting out undef sys insn handlingAndrew Turner2025-05-122-0/+5
* arm64: Split out the 32-bit undef handlingAndrew Turner2025-05-121-0/+3
* arm64: Allow building the MSR ISS from raw valuesAndrew Turner2025-05-121-5/+7
* arm64: Remove kernel undef instruction supportAndrew Turner2025-05-121-2/+2
* arm64: Call pmap_bootstrap_dmap from initarmAndrew Turner2025-04-221-1/+2
* efi/metadata: Make a note that efi_map_header isn't standardWarner Losh2025-04-091-3/+8
* arm64: Clean up enabling in-kernel BTIAndrew Turner2025-03-271-1/+2
* vmm: Consolidate code which manages guest memory regionsMark Johnston2025-02-181-32/+2
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