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* sys: Automated cleanup of cdefs and other formattingWarner Losh2023-11-271-1/+0
| | | | | | | | | | | | | | | | Apply the following automated changes to try to eliminate no-longer-needed sys/cdefs.h includes as well as now-empty blank lines in a row. Remove /^#if.*\n#endif.*\n#include\s+<sys/cdefs.h>.*\n/ Remove /\n+#include\s+<sys/cdefs.h>.*\n+#if.*\n#endif.*\n+/ Remove /\n+#if.*\n#endif.*\n+/ Remove /^#if.*\n#endif.*\n/ Remove /\n+#include\s+<sys/cdefs.h>\n#include\s+<sys/types.h>/ Remove /\n+#include\s+<sys/cdefs.h>\n#include\s+<sys/param.h>/ Remove /\n+#include\s+<sys/cdefs.h>\n#include\s+<sys/capsicum.h>/ Sponsored by: Netflix
* sys: Remove $FreeBSD$: one-line .c patternWarner Losh2023-08-161-2/+0
| | | | Remove /^[\s*]*__FBSDID\("\$FreeBSD\$"\);?\s*\n/
* sys: Remove $FreeBSD$: two-line .h patternWarner Losh2023-08-161-2/+0
| | | | Remove /^\s*\*\n \*\s+\$FreeBSD\$$\n/
* arm64: Hyper-V: enablement for ARM64 in Hyper-V (Part 3, final)Souradeep Chakrabarti2022-10-271-1/+1
| | | | | | | | | | | | This is the last part for ARM64 Hyper-V enablement. This includes commone files and make file changes to enable the ARM64 FreeBSD guest on Hyper-V. With this patch, it should be able to build the ARM64 image and install it on Hyper-V. Reviewed by: emaste, andrew, whu Tested by: Souradeep Chakrabarti <schakrabarti@microsoft.com> Sponsored by: Microsoft Differential Revision: https://reviews.freebsd.org/D36744
* Change "compiled" to "assembled"Warner Losh2021-06-111-1/+1
| | | | | | | | | Assembly files are assembled, not compiled. Submitted by: github user gAlfonso-bit Pull Request: https://github.com/freebsd/freebsd-src/pull/474 Sponsored by: Netflix
* hyperv: Fix vmbus after the i386 4/4 splitMark Johnston2021-06-081-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | The vmbus ISR needs to live in a trampoline. Dynamically allocating a trampoline at driver initialization time poses some difficulties due to the fact that the KENTER macro assumes that the offset relative to tramp_idleptd is fixed at static link time. Another problem is that native_lapic_ipi_alloc() uses setidt(), which assumes a fixed trampoline offset. Rather than fight this, move the Hyper-V ISR to i386/exception.s. Add a new HYPERV kernel option to make this optional, and configure it by default on i386. This is sufficient to make use of vmbus(4) after the 4/4 split. Note that vmbus cannot be loaded dynamically and both the HYPERV option and device must be configured together. I think this is not too onerous a requirement, since vmbus(4) was previously non-functional. Reported by: Harry Schmalzbauer <freebsd@omnilan.de> Tested by: Harry Schmalzbauer <freebsd@omnilan.de> Reviewed by: whu, kib MFC after: 2 weeks Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D30577
* x86: remove gcov kernel supportKonstantin Belousov2021-04-021-2/+0
| | | | | | Reviewed by: jhb Sponsored by: The FreeBSD Foundation Differential revision: https://reviews.freebsd.org/D29529
* i386 4/4G split.Konstantin Belousov2018-04-131-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The change makes the user and kernel address spaces on i386 independent, giving each almost the full 4G of usable virtual addresses except for one PDE at top used for trampoline and per-CPU trampoline stacks, and system structures that must be always mapped, namely IDT, GDT, common TSS and LDT, and process-private TSS and LDT if allocated. By using 1:1 mapping for the kernel text and data, it appeared possible to eliminate assembler part of the locore.S which bootstraps initial page table and KPTmap. The code is rewritten in C and moved into the pmap_cold(). The comment in vmparam.h explains the KVA layout. There is no PCID mechanism available in protected mode, so each kernel/user switch forth and back completely flushes the TLB, except for the trampoline PTD region. The TLB invalidations for userspace becomes trivial, because IPI handlers switch page tables. On the other hand, context switches no longer need to reload %cr3. copyout(9) was rewritten to use vm_fault_quick_hold(). An issue for new copyout(9) is compatibility with wiring user buffers around sysctl handlers. This explains two kind of locks for copyout ptes and accounting of the vslock() calls. The vm_fault_quick_hold() AKA slow path, is only tried after the 'fast path' failed, which temporary changes mapping to the userspace and copies the data to/from small per-cpu buffer in the trampoline. If a page fault occurs during the copy, it is short-circuit by exception.s to not even reach C code. The change was motivated by the need to implement the Meltdown mitigation, but instead of KPTI the full split is done. The i386 architecture already shows the sizing problems, in particular, it is impossible to link clang and lld with debugging. I expect that the issues due to the virtual address space limits would only exaggerate and the split gives more liveness to the platform. Tested by: pho Discussed with: bde Sponsored by: The FreeBSD Foundation MFC after: 1 month Differential revision: https://reviews.freebsd.org/D14633 Notes: svn path=/head/; revision=332489
* Rename assym.s to assym.incEd Maste2018-03-201-1/+1
| | | | | | | | | | | | assym is only to be included by other .s files, and should never actually be assembled by itself. Reviewed by: imp, bdrewery (earlier) Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D14180 Notes: svn path=/head/; revision=331254
* PTI for amd64.Konstantin Belousov2018-01-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The implementation of the Kernel Page Table Isolation (KPTI) for amd64, first version. It provides a workaround for the 'meltdown' vulnerability. PTI is turned off by default for now, enable with the loader tunable vm.pmap.pti=1. The pmap page table is split into kernel-mode table and user-mode table. Kernel-mode table is identical to the non-PTI table, while usermode table is obtained from kernel table by leaving userspace mappings intact, but only leaving the following parts of the kernel mapped: kernel text (but not modules text) PCPU GDT/IDT/user LDT/task structures IST stacks for NMI and doublefault handlers. Kernel switches to user page table before returning to usermode, and restores full kernel page table on the entry. Initial kernel-mode stack for PTI trampoline is allocated in PCPU, it is only 16 qwords. Kernel entry trampoline switches page tables. then the hardware trap frame is copied to the normal kstack, and execution continues. IST stacks are kept mapped and no trampoline is needed for NMI/doublefault, but of course page table switch is performed. On return to usermode, the trampoline is used again, iret frame is copied to the trampoline stack, page tables are switched and iretq is executed. The case of iretq faulting due to the invalid usermode context is tricky, since the frame for fault is appended to the trampoline frame. Besides copying the fault frame and original (corrupted) frame to kstack, the fault frame must be patched to make it look as if the fault occured on the kstack, see the comment in doret_iret detection code in trap(). Currently kernel pages which are mapped during trampoline operation are identical for all pmaps. They are registered using pmap_pti_add_kva(). Besides initial registrations done during boot, LDT and non-common TSS segments are registered if user requested their use. In principle, they can be installed into kernel page table per pmap with some work. Similarly, PCPU can be hidden from userspace mapping using trampoline PCPU page, but again I do not see much benefits besides complexity. PDPE pages for the kernel half of the user page tables are pre-allocated during boot because we need to know pml4 entries which are copied to the top-level paging structure page, in advance on a new pmap creation. I enforce this to avoid iterating over the all existing pmaps if a new PDPE page is needed for PTI kernel mappings. The iteration is a known problematic operation on i386. The need to flush hidden kernel translations on the switch to user mode make global tables (PG_G) meaningless and even harming, so PG_G use is disabled for PTI case. Our existing use of PCID is incompatible with PTI and is automatically disabled if PTI is enabled. PCID can be forced on only for developer's benefit. MCE is known to be broken, it requires IST stack to operate completely correctly even for non-PTI case, and absolutely needs dedicated IST stack because MCE delivery while trampoline did not switched from PTI stack is fatal. The fix is pending. Reviewed by: markj (partially) Tested by: pho (previous version) Discussed with: jeff, jhb Sponsored by: The FreeBSD Foundation MFC after: 2 weeks Notes: svn path=/head/; revision=328083
* hyperv: Move machine dependent bits into machine dependent files.Sepherosa Ziehau2016-06-061-0/+51
| | | | | | | | | MFC after: 1 week Sponsored by: Microsoft OSTC Differential Revision: https://reviews.freebsd.org/D6701 Notes: svn path=/head/; revision=301483
* hyperv: Rename some cleaned up/almost cleaned up filesSepherosa Ziehau2016-06-011-0/+0
| | | | | | | | MFC after: 1 week Sponsored by: Microsoft OSTC Notes: svn path=/head/; revision=301113
* hyperv/vmbus: Indentation cleanupSepherosa Ziehau2016-05-311-11/+11
| | | | | | | | | | | No functional changes. MFC after: 1 week Sponsored by: Microsoft OSTC Differential Revision: https://reviews.freebsd.org/D6602 Notes: svn path=/head/; revision=301017
* hyperv/vmbus: Rename ISR functionsSepherosa Ziehau2016-05-311-2/+2
| | | | | | | | | MFC after: 1 week Sponsored by: Microsoft OSTC Differential Revision: https://reviews.freebsd.org/D6601 Notes: svn path=/head/; revision=301015
* hyperv: Deprecate HYPERV option by moving Hyper-V IDT vector into vmbusSepherosa Ziehau2016-04-151-0/+49
Submitted by: Jun Su <junsu microsoft com> Reviewed by: jhb, kib, sephe Sponsored by: Microsoft OSTC Differential Revision: https://reviews.freebsd.org/D5910 Notes: svn path=/head/; revision=298022