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* xen: implement early init helper for PVHv2Roger Pau Monné2018-07-192-47/+222
* xen: allow very early initialization of the hypercall pageRoger Pau Monné2018-07-191-41/+53
* xen: remove direct usage of HYPERVISOR_start_infoRoger Pau Monné2018-07-192-23/+100
* Use the existing MSR_BIOS_SIGN on AMD.Mark Johnston2018-07-131-1/+0
* Define the MSR used to fetch the current microcode patch level on AMD.Mark Johnston2018-07-131-0/+1
* Use C99 initializers for instances of struct apic_enumerator.Mark Johnston2018-07-133-15/+15
* Create helper functions for parsing boot args.Warner Losh2018-07-131-16/+1
* Back pcpu zone with domain correct pagesMatt Macy2018-07-061-2/+6
* Create a new macro for static DPCPU data.Andrew Turner2018-07-051-1/+1
* Add a name for the MSR controlling standard extended features report on AMD.Konstantin Belousov2018-07-051-0/+1
* Order the portion of the AMD-specific MSRs names definitions numerically.Konstantin Belousov2018-07-051-4/+4
* xen: obtain vCPU ID from CPUIDRoger Pau Monné2018-06-261-27/+27
* xen: limit the number of hypercall pages to 1Roger Pau Monné2018-06-261-3/+3
* Do not access ISA timer if BIOS reports that there is no legacyKonstantin Belousov2018-06-251-2/+24
* Provide a helper function acpi_get_fadt_bootflags() to fetch the FADTKonstantin Belousov2018-06-253-23/+27
* Untangle configuration ifdefs a little. On x86, msi is optional on pci,Bruce Evans2018-06-101-4/+5
* x86: reorganize code that deals with unexpected NMI-sAndriy Gapon2018-06-072-15/+12
* expand descriptions of x86 panic_on_nmi and kdb_on_nmi sysctlsAndriy Gapon2018-06-071-2/+2
* add support for console resuming, implement it for uart, use on x86Andriy Gapon2018-05-291-0/+7
* fix x86 UP build broken by r334204, TSC resynchronizationAndriy Gapon2018-05-291-14/+6
* re-synchronize TSC-s on SMP systems after resume, if necessaryAndriy Gapon2018-05-251-4/+28
* xen/pvh: allocate dbg_stackRoger Pau Monné2018-05-241-0/+3
* Fix UP build.Konstantin Belousov2018-05-221-2/+0
* Cleanups related to debug exceptions on x86.John Baldwin2018-05-222-1/+11
* Add Intel Spec Store Bypass Disable control.Konstantin Belousov2018-05-213-2/+108
* Add definition for Intel Speculative Store Bypass Disable MSR bitsKonstantin Belousov2018-05-212-0/+4
* Style.Konstantin Belousov2018-05-191-2/+2
* Fix PCID+PTI pmap operations on Xen/HVM.Konstantin Belousov2018-05-191-2/+53
* Fix IBRS handling around MWAIT.Konstantin Belousov2018-05-191-2/+2
* fix a problem with bad performance after wakeup caused by r333321Andriy Gapon2018-05-171-2/+3
* calibrate lapic timer in native_lapic_setupAndriy Gapon2018-05-151-7/+12
* Put the CPU starting on one line.Warner Losh2018-05-071-1/+5
* x86 cpususpend_handler: call wbinvd after setting suspend state bitsAndriy Gapon2018-05-071-9/+26
* Add helper macros to hide some boring repeatable ceremonies to defineKonstantin Belousov2018-05-031-0/+58
* Redo r332918 with the ACPICA API and remove debug.acpi.suspend_deep_bounce.Jung-uk Kim2018-05-031-4/+4
* xen: fix formatting of xen_init_opsRoger Pau Monné2018-05-021-1/+1
* Turn off IBRS on suspend.Konstantin Belousov2018-04-302-1/+14
* Fix spelling: Appolo -> Apollo [1].Konstantin Belousov2018-04-261-2/+6
* Handle Appolo Lake errata APL31.Konstantin Belousov2018-04-261-1/+13
* Some style and minor code improvements for idle selection.Konstantin Belousov2018-04-261-20/+21
* Use CPUID leaf 0x15 to get TSC frequency when the calibration isKonstantin Belousov2018-04-251-9/+30
* Make the sysctl machdep.idle also a tunable.Konstantin Belousov2018-04-241-17/+35
* Extend ap_boot_mtx scope to also cover mca_init().Konstantin Belousov2018-04-241-2/+2
* Ensure that cmci_monitor() is not executed in parallel, since sharedKonstantin Belousov2018-04-241-0/+10
* Use IS_BSP() macro.Konstantin Belousov2018-04-241-1/+1
* Use relaxed atomics to access the monitor line.Konstantin Belousov2018-04-241-25/+27
* add a new ACPI suspend debugging knob, debug.acpi.suspend_deep_bounceAndriy Gapon2018-04-241-0/+4
* Fix two off-by-one errors when allocating MSI and MSI-X interrupts.John Baldwin2018-04-181-2/+2
* cpufreq: Remove error-prone table terminators in favor of automatic sizingConrad Meyer2018-04-141-74/+28
* i386 4/4G split.Konstantin Belousov2018-04-134-14/+36
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