1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
|
//===- RISCVMacroFusion.cpp - RISC-V Macro Fusion -------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
/// \file This file contains the RISC-V implementation of the DAG scheduling
/// mutation to pair instructions back to back.
//
//===----------------------------------------------------------------------===//
//
#include "RISCVMacroFusion.h"
#include "RISCVSubtarget.h"
#include "llvm/CodeGen/MacroFusion.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
using namespace llvm;
static bool checkRegisters(Register FirstDest, const MachineInstr &SecondMI) {
if (!SecondMI.getOperand(1).isReg())
return false;
if (SecondMI.getOperand(1).getReg() != FirstDest)
return false;
// If the input is virtual make sure this is the only user.
if (FirstDest.isVirtual()) {
auto &MRI = SecondMI.getMF()->getRegInfo();
return MRI.hasOneNonDBGUse(FirstDest);
}
return SecondMI.getOperand(0).getReg() == FirstDest;
}
// Fuse load with add:
// add rd, rs1, rs2
// ld rd, 0(rd)
static bool isLDADD(const MachineInstr *FirstMI, const MachineInstr &SecondMI) {
if (SecondMI.getOpcode() != RISCV::LD)
return false;
if (!SecondMI.getOperand(2).isImm())
return false;
if (SecondMI.getOperand(2).getImm() != 0)
return false;
// Given SecondMI, when FirstMI is unspecified, we must return
// if SecondMI may be part of a fused pair at all.
if (!FirstMI)
return true;
if (FirstMI->getOpcode() != RISCV::ADD)
return true;
return checkRegisters(FirstMI->getOperand(0).getReg(), SecondMI);
}
// Fuse zero extension of halfword:
// slli rd, rs1, 48
// srli rd, rd, 48
static bool isZExtH(const MachineInstr *FirstMI, const MachineInstr &SecondMI) {
if (SecondMI.getOpcode() != RISCV::SRLI)
return false;
if (!SecondMI.getOperand(2).isImm())
return false;
if (SecondMI.getOperand(2).getImm() != 48)
return false;
// Given SecondMI, when FirstMI is unspecified, we must return
// if SecondMI may be part of a fused pair at all.
if (!FirstMI)
return true;
if (FirstMI->getOpcode() != RISCV::SLLI)
return false;
if (FirstMI->getOperand(2).getImm() != 48)
return false;
return checkRegisters(FirstMI->getOperand(0).getReg(), SecondMI);
}
// Fuse zero extension of word:
// slli rd, rs1, 32
// srli rd, rd, 32
static bool isZExtW(const MachineInstr *FirstMI, const MachineInstr &SecondMI) {
if (SecondMI.getOpcode() != RISCV::SRLI)
return false;
if (!SecondMI.getOperand(2).isImm())
return false;
if (SecondMI.getOperand(2).getImm() != 32)
return false;
// Given SecondMI, when FirstMI is unspecified, we must return
// if SecondMI may be part of a fused pair at all.
if (!FirstMI)
return true;
if (FirstMI->getOpcode() != RISCV::SLLI)
return false;
if (FirstMI->getOperand(2).getImm() != 32)
return false;
return checkRegisters(FirstMI->getOperand(0).getReg(), SecondMI);
}
// Fuse shifted zero extension of word:
// slli rd, rs1, 32
// srli rd, rd, x
// where 0 <= x < 32
static bool isShiftedZExtW(const MachineInstr *FirstMI,
const MachineInstr &SecondMI) {
if (SecondMI.getOpcode() != RISCV::SRLI)
return false;
if (!SecondMI.getOperand(2).isImm())
return false;
unsigned SRLIImm = SecondMI.getOperand(2).getImm();
if (SRLIImm >= 32)
return false;
// Given SecondMI, when FirstMI is unspecified, we must return
// if SecondMI may be part of a fused pair at all.
if (!FirstMI)
return true;
if (FirstMI->getOpcode() != RISCV::SLLI)
return false;
if (FirstMI->getOperand(2).getImm() != 32)
return false;
return checkRegisters(FirstMI->getOperand(0).getReg(), SecondMI);
}
// Fuse AUIPC followed by ADDI
// auipc rd, imm20
// addi rd, rd, imm12
static bool isAUIPCADDI(const MachineInstr *FirstMI,
const MachineInstr &SecondMI) {
if (SecondMI.getOpcode() != RISCV::ADDI)
return false;
// Assume the 1st instr to be a wildcard if it is unspecified.
if (!FirstMI)
return true;
if (FirstMI->getOpcode() != RISCV::AUIPC)
return false;
return checkRegisters(FirstMI->getOperand(0).getReg(), SecondMI);
}
// Fuse LUI followed by ADDI or ADDIW.
// rd = imm[31:0] which decomposes to
// lui rd, imm[31:12]
// addi(w) rd, rd, imm[11:0]
static bool isLUIADDI(const MachineInstr *FirstMI,
const MachineInstr &SecondMI) {
if (SecondMI.getOpcode() != RISCV::ADDI &&
SecondMI.getOpcode() != RISCV::ADDIW)
return false;
// Assume the 1st instr to be a wildcard if it is unspecified.
if (!FirstMI)
return true;
if (FirstMI->getOpcode() != RISCV::LUI)
return false;
return checkRegisters(FirstMI->getOperand(0).getReg(), SecondMI);
}
static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
const TargetSubtargetInfo &TSI,
const MachineInstr *FirstMI,
const MachineInstr &SecondMI) {
const RISCVSubtarget &ST = static_cast<const RISCVSubtarget &>(TSI);
if (ST.hasLUIADDIFusion() && isLUIADDI(FirstMI, SecondMI))
return true;
if (ST.hasAUIPCADDIFusion() && isAUIPCADDI(FirstMI, SecondMI))
return true;
if (ST.hasZExtHFusion() && isZExtH(FirstMI, SecondMI))
return true;
if (ST.hasZExtWFusion() && isZExtW(FirstMI, SecondMI))
return true;
if (ST.hasShiftedZExtWFusion() && isShiftedZExtW(FirstMI, SecondMI))
return true;
if (ST.hasLDADDFusion() && isLDADD(FirstMI, SecondMI))
return true;
return false;
}
std::unique_ptr<ScheduleDAGMutation> llvm::createRISCVMacroFusionDAGMutation() {
return createMacroFusionDAGMutation(shouldScheduleAdjacent);
}
|
