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* am64: Allow cpu.h to be included from assemblyAndrew Turner2024-05-101-0/+4
| | | | | | Reviewed by: jhibbits, kevans Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D45081
* arm64: Add a CPU reset hook instead of expecting PSCIStephen J. Kiernan2024-04-051-0/+3
| | | | | | | | | | Some SoCs do not include a PSCI for power management and defer it to something else instead. Add a CPU reset hook to account for this, and use it in the psci driver. Reviewed by: andrew Obtained from: Juniper Networks, Inc. Differential Revision: https://reviews.freebsd.org/D44535
* arm64: add CPU part identifiers for Apple M1 and M2Lexi Winter2024-04-051-0/+14
| | | | | | | Part numbers are sourced from Linux (arch/arm64/include/asm/cputype.h). MFC after: 2 weeks Pull Request: https://github.com/freebsd/freebsd-src/pull/1144
* sys: Remove ancient SCCS tags.Warner Losh2023-11-271-2/+0
| | | | | | | | Remove ancient SCCS tags from the tree, automated scripting, with two minor fixup to keep things compiling. All the common forms in the tree were removed with a perl script. Sponsored by: Netflix
* sys: Remove $FreeBSD$: one-line .h patternWarner Losh2023-08-161-1/+0
| | | | Remove /^\s*\*+\s*\$FreeBSD\$.*$\n/
* arm64 lib32: prepare arm64 headers to redirect to armMike Karels2023-07-251-0/+6
| | | | | | | | | | | | | | | | | | | | | | | In order to compile lib32 libraries and other 32-bit code on arm64, <machine/foo.h> needs to be redirected to an arm header rather than arm64 when building with -m32. Ifdef the arm64 headers that are installed in /usr/include/machine and used by user-level software (including references from /usr/include/*.h) so that if __arm__ is defined when including the arm64 version, <arm/foo.h> is included rather than using the rest of the file's contents. Some arm headers had no arm64 equivalent; headers were added just to do the redirection. These files use #error if __arm__ is not defined to guard against confusion. Also add an include/arm Makefile, and modify Makefiles as needed to install everything, including the arm files in /usr/include/arm. fenv.h comes from lib/msun/arm/fenv.h. The new arm64 headers are: acle-compat.h cpuinfo.h sysreg.h Reviewed by: jrtc27, imp Differential Revision: https://reviews.freebsd.org/D40944
* arm64: Add a masked get_kernel_reg()Mark Johnston2023-06-281-0/+1
| | | | | | | | | | | | | | This lets consumers fetch the value of a system register and apply a mask over individual fields. That is, each field in the returned value will be the "smaller" of the two provided by "mask" and the value saved in kern_cpu_desc. This will be used by vmm to sanitize host system register fields. Reviewed by: andrew MFC after: 2 weeks Sponsored by: The FreeBSD Foundation Sponsored by: Klara, Inc. (hardware) Differential Revision: https://reviews.freebsd.org/D40500
* arm64: Malloc the cpu_desc arrayAndrew Turner2023-06-081-0/+2
| | | | | | | | | We only need this during boot. Allocate the array before starting CPUs to reduce the memory usage. Reviewed by: Zach Leaf <zachary.leaf@arm.com> Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D40433
* arm64: Remove duplicated function prototypes for PACMark Johnston2023-03-271-11/+0
| | | | | | No functional change intended. Sponsored by: The FreeBSD Foundation
* Add CPU Ident for Qualcomm Kryo 400 (used in MS Dev Kit)Allan Jude2023-01-181-0/+5
| | | | | | Reviewed by: imp Sponsored by: Klara, Inc. Differential Revision: https://reviews.freebsd.org/D37767
* Add the arch field to the arm64 MIDR macrosAndrew Turner2022-11-151-0/+3
| | | | | | | | | For completeness add accessors for the MIDR field. As the field is always 0xf on arm64 it is unneeded in the current MICR handling, but will be used in the vmm module for bhyve. Obtained from: https://github.com/FreeBSD-UPB/freebsd-src (earlier version) Sponsored by: The FreeBSD Foundation
* Add more Arm CPUs to the arm64 cpu identAndrew Turner2022-10-111-0/+3
| | | | | | These are based on CPUs found in https://github.com/ARM-software/data Sponsored by: The FreeBSD Foundation
* Add more Arm CPU IDsAndrew Turner2022-05-241-0/+11
| | | | | | Add more CPU main ID register values for Arm Cortex and Neoverse CPUs Sponsored by: The FreeBSD Foundation
* Add the Ampere and Fujitsu arm64 implementer IDsD Scott Phillips2022-03-251-0/+2
| | | | | | | Reviewed By: andrew, emaste MFC after: 3 days Sponsored by: Ampere Computing Differential Revision: https://reviews.freebsd.org/D34666
* arm64: Add explicit barrier after address translation instructionD Scott Phillips2022-03-251-1/+2
| | | | | | | | | | | | | | | Following ARMARM sec D5.2.11, which says: > Where an instruction results in an update to a System register, > as is the case with the AT * address translation instructions, > explicit synchronization must be performed before the result is > guaranteed to be visible to subsequent direct reads of the > PAR_EL1. Reviewed By: andrew MFC after: 3 weeks Sponsored by: Ampere Computing Differential Revision: https://reviews.freebsd.org/D34665
* Add NT_ARM_ADDR_MASKAndrew Turner2022-02-221-0/+3
| | | | | | | | | | | This can be used by debuggers to find which bits in a virtual address should be masked off to get a canonical address. This is currently used by the Pointer Authentication Code support to get its mask. It could also be used if we support Top Byte Ignore for the same purpose. Reviewed by: kib Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D34302
* Add arm64 pointer authentication supportAndrew Turner2022-01-121-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pointer authentication allows userspace to add instructions to insert a Pointer Authentication Code (PAC) into a register based on an address and modifier and check if the PAC is correct. If the check fails it will either return an invalid address or fault to the kernel. As many of these instructions are a NOP when disabled and in earlier revisions of the architecture this can be used, for example, to sign the return address before pushing it to the stack making Return-oriented programming (ROP) attack more difficult on hardware that supports them. The kernel manages five 128 bit signing keys: 2 instruction keys, 2 data keys, and a generic key. The instructions then use one of these when signing the registers. Instructions that use the first four store the PAC in the register being signed, however the instructions that use the generic key store the PAC in a separate register. Currently all userspace threads share all the keys within a process with a new set of userspace keys being generated when executing a new process. This means a forked child will share its keys with its parent until it calls an appropriate exec system call. In the kernel we allow the use of one of the instruction keys, the ia key. This will be used to sign return addresses in function calls. Unlike userspace each kernel thread has its own randomly generated. Thread0 has a static key as does the early code on secondary CPUs. This should be safe as there is minimal user interaction with these threads, however we could generate random keys when the Armv8.5 Random number generation instructions are present. Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D31261
* Simplify swi for bus_dma.John Baldwin2021-12-281-1/+0
| | | | | | | | | | | | | | | | | | | | | | | When a DMA request using bounce pages completes, a swi is triggered to schedule pending DMA requests using the just-freed bounce pages. For a long time this bus_dma swi has been tied to a "virtual memory" swi (swi_vm). However, all of the swi_vm implementations are the same and consist of checking a flag (busdma_swi_pending) which is always true and if set calling busdma_swi. I suspect this dates back to the pre-SMPng days and that the intention was for swi_vm to serve as a mux. However, in the current scheme there's no need for the mux. Instead, remove swi_vm and vm_ih. Each bus_dma implementation that uses bounce pages is responsible for creating its own swi (busdma_ih) which it now schedules directly. This swi invokes busdma_swi directly removing the need for busdma_swi_pending. One consequence is that the swi now works on RISC-V which had previously failed to invoke busdma_swi from swi_vm. Reviewed by: imp, kib Sponsored by: Netflix Differential Revision: https://reviews.freebsd.org/D33447
* arm64, riscv: Fix TRAF_PC() to return the PC, not the return address.John Baldwin2021-10-011-1/+1
| | | | | | | Reviewed by: mhorne Obtained from: CheriBSD Sponsored by: DARPA Differential Revision: https://reviews.freebsd.org/D31969
* Add the Apple arm64 implementer IDAndrew Turner2021-08-121-0/+1
| | | | Sponsored by: The FreeBSD Foundation
* Teach the arm64 kernel to identify the Arm AEMAndrew Turner2021-07-271-0/+1
| | | | | | | | The Arm Architecture Envelope Model is a simulator that models the architecture rather than any specific implementation. Add its part ID macro and add it to the list of Arm CPUs we can decode. Sponsored by: The FreeBSD Foundation
* arm64: clean up empty lines in .c and .h filesMateusz Guzik2020-09-011-1/+0
| | | | Notes: svn path=/head/; revision=365069
* Read the CPU 0 arm64 ID registers early in initarmAndrew Turner2020-07-011-1/+2
| | | | | | | | | | We also update the kernel view early in the boot. This will allow the use of the common kernel view in ifunc resolvers. Sponsored by: Innovate UK Notes: svn path=/head/; revision=362845
* Move ID reading signatures to a better headerAndrew Turner2020-07-011-0/+4
| | | | | | | | | | | The functions to read the common user and kernel ID registers should be in cpu.h rather than undefined.h as they are related to CPU details and used by undefined instruction handlers. Sponsored by: Innovate UK Notes: svn path=/head/; revision=362841
* Move the arm64 cache identification to identcpu.cAndrew Turner2020-03-031-0/+1
| | | | | | | | | | | | This allows us to call it on a per-CPU basis and to warn if the details are different across CPUs. While here read the L1 I-Cache type and store this for use later by pmap. Sponsored by: Innovate UK Notes: svn path=/head/; revision=358583
* Add more Arm arm64 CPU identification valuesAndrew Turner2020-01-061-1/+6
| | | | | | | | | | | | | - Add all the Cortex-A CPU ID register values I can find. - Add the Neoverse-N1 ID regiser value [1] - Sort macros by register value. PR: 243065 Submitted by: Ali Saidi <alisaidi AT amazon.com> [1] Sponsored by: DARPA, AFRL (other than [1]) Notes: svn path=/head/; revision=356426
* Identify eMAG CPU used in Ampere Computing systems.Michael Tuexen2019-08-261-0/+3
| | | | | | | | | Reviewed by: emaste@ MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D21314 Notes: svn path=/head/; revision=351511
* arm64: Implement HWCAPEmmanuel Vadot2019-07-201-1/+0
| | | | | | | | | | | | | | Add HWCAP support for arm64. defines are the same as in Linux and a userland program can use elf_aux_info to get the data. We only save the common denominator for all cores in case the big and little cluster have different support (this is known to exists even if we don't support those SoCs in FreeBSD) Differential Revision: https://reviews.freebsd.org/D17137 Notes: svn path=/head/; revision=350166
* Add a KPI for the delay while spinning on a spin lock.John Baldwin2018-11-051-0/+1
| | | | | | | | | | | | | Replace a call to DELAY(1) with a new cpu_lock_delay() KPI. Currently cpu_lock_delay() is defined to DELAY(1) on all platforms. However, platforms with a DELAY() implementation that uses spin locks should implement a custom cpu_lock_delay() doesn't use locks. Reviewed by: kib MFC after: 3 days Notes: svn path=/head/; revision=340164
* ARM64: Add ThunderX2 CPU revision macro. Add ThunderX2 name in identcpu.cWojciech Macek2018-07-091-0/+2
| | | | | | | | | Submitted by: Patryk Duda <pdk@semihalf.com> Obtained from: Semihalf Sponsored by: Cavium Notes: svn path=/head/; revision=336128
* Rename the ThunderX CPU identification macros to include the X. This is theAndrew Turner2018-06-131-7/+7
| | | | | | | | | | name people know the product by, and is consistent with the later SoC ID macros. Sponsored by: DARPA, AFRL Notes: svn path=/head/; revision=335052
* Add more Cavium CPU part numbers.Andrew Turner2018-06-131-1/+7
| | | | | | | | | While here split the lists by vendor. Sponsored by: DARPA, AFRL Notes: svn path=/head/; revision=335051
* Add a framework to install CPU errata on arm64. Each erratum can encodeAndrew Turner2018-01-091-0/+1
| | | | | | | | | | | | | | a mask and value to compare with the Main ID Register. If these match then a function is called to handle the installation of the erratum workaround. No errata are currently handled, however this will change soon in a future commit. MFC after: 1 week Sponsored by: DARPA, AFRL Notes: svn path=/head/; revision=327727
* Add more ARM Ltd parts to the list of knows CPUs.Andrew Turner2017-09-071-0/+4
| | | | | | | Submitted by: Jon Brawn <jon@brawn.org> Notes: svn path=/head/; revision=323266
* Add ARM Cortex A72 to CPU listMarcin Wojtas2017-09-031-0/+1
| | | | | | | | | | | | | | This change is required to properly detect CPUs on Marvell Armada 80x0/70x0 SoC family. Submitted by: Rafal Kozik <rk@semihalf.com> Reviewed by: andrew, cognet (mentor) Approved by: cognet (mentor) Sponsored by: Semihalf Differential Revision: https://reviews.freebsd.org/D12184 Notes: svn path=/head/; revision=323138
* Use the yield instruction in the arm64 cpu_spinwait. This instruction isAndrew Turner2016-04-251-1/+1
| | | | | | | | | a hint to the hardware the software is not performing a task. Sponsored by: ABT Systems Ltd Notes: svn path=/head/; revision=298586
* Use the saved program state register to detect when an exception frame isAndrew Turner2016-03-221-2/+2
| | | | | | | | | | | | from userpsace. Previously we could have triggered a panic by trying to jump to a kernel address from userland as the trap handling code thought we received an ast in kernel mode. Obtained from: ABT Systems Ltd Sponsored by: The FreeBSD Foundation Notes: svn path=/head/; revision=297184
* Decode and print the ID_AA64* registers on boot. These registers holdAndrew Turner2015-12-301-0/+1
| | | | | | | | | | | | | | information on what the core supports. In most cases these will be identical across most CPUs in the SoC, however there may be the case where, with a big.LITTLE setup they may differ. In this case we print the decoded data on all CPUs. Reviewed by: kib Sponsored by: ABT Systems Ltd Differential Revision: https://reviews.freebsd.org/D4725 Notes: svn path=/head/; revision=292954
* Block secondary ITS instances from attaching on ARM64Zbigniew Bodek2015-09-161-0/+2
| | | | | | | | | | | | | | | Currently FreeBSD supports only single PIC controller. Some systems that have more than one (like ThunderX dual-socket) fails to boot. Disable other PICes until proper handling is implemented in the generic interrupt code. Reviewed by: imp Obtained from: Semihalf Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D3682 Notes: svn path=/head/; revision=287884
* Add SMP support to GICv3 and ITS driversZbigniew Bodek2015-08-191-1/+6
| | | | | | | | | | | Introduce supprot for SMP to GICv3 and ITS drivers. Obtained from: Semihalf Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D3299 Notes: svn path=/head/; revision=286919
* Apply erratum for mrs ICC_IAR1_EL1 speculative execution on ThunderXZbigniew Bodek2015-07-311-0/+26
| | | | | | | | | | | | | ERRATUM: 22978, 23154 PASS (rev.): 1.0/1.1 Reviewed by: imp Obtained from: Semihalf Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D3184 Notes: svn path=/head/; revision=286121
* Implement get_cyclecount() on ARM64Zbigniew Bodek2015-07-211-2/+5
| | | | | | | | | | | | Use Vritual Counter register associated with Generic Timer to read the cyclecount. Obtained from: Semihalf Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D3134 Notes: svn path=/head/; revision=285745
* Improve ARM64 CPU_MATCHZbigniew Bodek2015-07-211-4/+11
| | | | | | | | | | | Add a method to identify CPU based on RAW MIDR value. Obtained from: Semihalf Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D3117 Notes: svn path=/head/; revision=285743
* Rework CPU identification on ARM64Zbigniew Bodek2015-07-091-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit reworks the code responsible for identification of the CPUs during runtime. It is necessary to provide a way for workarounds and erratums to be applied only for certain HW versions. The copy of MIDR is now stored in pcpu to provide a fast and convenient way for assambly code to read it (pcpu is used quite often so there is a chance it's inside the cache). The MIDR is also better way of identification than using user-friendly cpu_desc structure, because it can be compiled into comparision of single u32 with only one access to the memory - this is crucial for some erratums which are called from performance-critical places. Changes in cpu_identify makes this function safe to be called on non-boot CPUs. New function CPU_MATCH was implemented which returns boolean value based on mathing masked MIDR with chip identification. Example of usage: printf("is thunder: %d\n", CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK, CPU_IMPL_CAVIUM, CPU_PART_THUNDER, 0, 0)); printf("is generic: %d\n", CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK, CPU_IMPL_ARM, CPU_PART_FOUNDATION, 0, 0)); Reviewed by: andrew Obtained from: Semihalf Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D3030 Notes: svn path=/head/; revision=285311
* Renumber clauses to avoid missing 3Ed Maste2015-03-231-1/+1
| | | | Notes: svn path=/head/; revision=280381
* Add the start of the arm64 machine headers. This is the subset needed toAndrew Turner2015-03-231-0/+104
start getting userland libraries building. Reviewed by: imp Sponsored by: The FreeBSD Foundation Notes: svn path=/head/; revision=280364
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