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* Remove expired ports:Rene Ladan2021-04-071-2/+0
* One more small cleanup, forgotten yesterday.Mathieu Arnold2021-04-071-1/+0
* Remove # $FreeBSD$ from Makefiles.Mathieu Arnold2021-04-061-2/+0
* New port: cad/archimedes: Semiconductor device simulation softwareYuri Victorovich2020-12-101-0/+1
* New port: cad/stm32flash: Flash program for STM32 using the ST serial bootloaderYuri Victorovich2020-11-181-0/+1
* New port: cad/ecpprog: Driver for FTDI based JTAG probes, to program ECP5 FPGAsYuri Victorovich2020-09-161-0/+1
* cad/opensta: Remove because it is now included in OpenRoad (cad/openroad)Yuri Victorovich2020-09-151-1/+0
* New port: cad/openroad: ASIC physical design toolYuri Victorovich2020-09-141-0/+1
* Clean up some thingsTobias Kortkamp2020-08-181-0/+3
* New port: cad/openfpgaloader: Universal utility for programming FPGAYuri Victorovich2020-08-111-0/+1
* New port: cad/horizon-eda: EDA package for printed circuit board designYuri Victorovich2020-08-071-0/+1
* [NEW PORT] cad/py-ezdxf: Create and modify DXF drawingsLoïc Bartoletti2020-07-301-0/+1
* cad/meshlab: Resurrect, update to 2020.05 and take maintainer'shipLoïc Bartoletti2020-07-181-0/+1
* [NEW PORT] cad/ifcopenshell: Open source IFC library and geometry engineLoïc Bartoletti2020-05-231-0/+1
* This is the new, shiny frontend for Cura. Check daid/LegacyCura for theDiane Bruce2020-03-261-0/+1
* Uranium is a Python framework for building 3D printing related applications.Diane Bruce2020-03-251-0/+1
* In preparation for Cura updates add the FDM material databaseDiane Bruce2020-03-251-0/+1
* New port: cad/opensta: Gate level static timing verifierYuri Victorovich2020-03-231-0/+1
* New port: cad/graywolf: Fork of TimberWolf, a placement tool in VLSI designYuri Victorovich2020-03-221-0/+1
* New port: cad/qflow: End-to-end digital synthesis flow for ASIC designsYuri Victorovich2020-03-221-0/+1
* New port: cad/qrouter: Tool to generate metal layers and viasYuri Victorovich2020-03-191-0/+1
* New port: cad/netgen-lvs: Tool for comparing netlists (a process known as LVS)Yuri Victorovich2020-03-191-0/+1
* OpenCTM is a file format, a software library and a tool set for compressionDiane Bruce2020-03-151-0/+1
* Remove expired ports:Rene Ladan2020-03-011-1/+0
* Remove expired ports, all Python-2.7-only:Rene Ladan2020-02-221-1/+0
* New port: cad/veroroute: PCB (printed circuit board) design softwareYuri Victorovich2020-02-021-0/+1
* Remove expired ports:Rene Ladan2020-01-271-1/+0
* sort SUBDIRs.Mathieu Arnold2020-01-241-1/+1
* New port: cad/PrusaSlicerEugene Grosbein2020-01-241-0/+1
* Move cad/elmerfem -> science/elmerfemYuri Victorovich2020-01-151-1/+0
* Remove expired ports:Rene Ladan2020-01-101-1/+0
* Move cad/ujprog -> comms/ujprogYuri Victorovich2020-01-061-1/+0
* New port: cad/ujprog: ULX2S/ULX3S FPGA JTAG programmerYuri Victorovich2020-01-061-0/+1
* New/resurrected port: cad/gerbvKurt Jaeger2020-01-051-0/+1
* New port: cad/cascade-compiler: Just-In-Time Compiler for Verilog from VMware...Yuri Victorovich2020-01-051-0/+1
* Move the port devel/yosys -> cad/yosys, to the proper categoryYuri Victorovich2020-01-041-0/+1
* New port: cad/ktechlab: IDE for microcontrollers and electronicsYuri Victorovich2019-11-271-0/+1
* Re-add cad/oregano: Schematic capture and circuit simulatorYuri Victorovich2019-11-231-0/+1
* New port: cad/librepcb: Schematic and PCB editing softwareYuri Victorovich2019-11-231-0/+1
* New port: cad/caneda: EDA software suite focused on ease of use and portabilityYuri Victorovich2019-11-211-0/+1
* - Resurrect `cad/elmerfem' and update to version 8.4Alexey Dokuchaev2019-11-111-0/+1
* - Chase r517198 and reconnect `cad/brlcad' to the buildAlexey Dokuchaev2019-11-101-0/+1
* cad/fasm: Make PKGBASE uniqueYuri Victorovich2019-10-271-0/+1
* Remove port with duplicate PKGBASEAntoine Brodin2019-10-271-1/+0
* New port: cad/fasm: FPGA assembly (FASM) parser and generatorYuri Victorovich2019-10-271-0/+1
* New port: cad/nvc: VHDL compiler and simulatorYuri Victorovich2019-10-231-0/+1
* Re-add cad/ghdl: GNU VHDL simulatorYuri Victorovich2019-10-231-0/+1
* Remove expired ports:Rene Ladan2019-10-161-3/+0
* Remove expired port:Rene Ladan2019-08-121-1/+0
* New port: cad/digital: Digital logic designer and circuit simulatorYuri Victorovich2019-07-221-0/+1
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